diff --git a/tests/arch/arm/arm_no_multithreading/src/main.c b/tests/arch/arm/arm_no_multithreading/src/main.c
index 75964163b79d2..198d7f8dae0d1 100644
--- a/tests/arch/arm/arm_no_multithreading/src/main.c
+++ b/tests/arch/arm/arm_no_multithreading/src/main.c
@@ -13,6 +13,16 @@
   #error test can only run on Cortex-M MCUs
 #endif
 
+#if defined(CONFIG_ARMV8_1_M_MAINLINE)
+/*
+ * For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
+ * is not implemented, so mask it when validating the value of the FPSCR.
+ */
+#define FPSCR_MASK		(~FPU_FPDSCR_LTPSIZE_Msk)
+#else
+#define FPSCR_MASK		(0xffffffffU)
+#endif
+
 extern K_THREAD_STACK_DEFINE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
 
 static volatile int test_flag;
@@ -58,7 +68,7 @@ void test_main(void)
 			psp, main_stack_base, main_stack_top);
 
 #if defined(CONFIG_FPU)
-	__ASSERT(__get_FPSCR() == 0,
+	__ASSERT((__get_FPSCR() & FPSCR_MASK) == 0,
 		"FPSCR not zero (0x%x)", __get_FPSCR());
 #endif
 
diff --git a/tests/arch/arm/arm_no_multithreading/testcase.yaml b/tests/arch/arm/arm_no_multithreading/testcase.yaml
index 247ff1bc57a4e..294a360b7c414 100644
--- a/tests/arch/arm/arm_no_multithreading/testcase.yaml
+++ b/tests/arch/arm/arm_no_multithreading/testcase.yaml
@@ -6,4 +6,4 @@ tests:
   arch.arm.no_multithreading:
     filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
     platform_allow: qemu_cortex_m0 qemu_cortex_m3 mps2_an385 mps2_an521
-      nrf52840dk_nrf52840 nrf9160dk_nrf9160 nrf51dk_nrf51422
+      mps3_an547 nrf52840dk_nrf52840 nrf9160dk_nrf9160 nrf51dk_nrf51422
diff --git a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
index 58eecac8000ec..4cd9260642249 100644
--- a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
+++ b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
@@ -30,6 +30,16 @@
 #define EXC_RETURN_FTYPE           (0x00000010UL)
 #endif
 
+#if defined(CONFIG_ARMV8_1_M_MAINLINE)
+/*
+ * For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
+ * is not implemented, so mask it when validating the value of the FPSCR.
+ */
+#define FPSCR_MASK		(~FPU_FPDSCR_LTPSIZE_Msk)
+#else
+#define FPSCR_MASK		(0xffffffffU)
+#endif
+
 extern void z_move_thread_to_end_of_prio_q(struct k_thread *thread);
 
 static struct k_thread alt_thread;
@@ -278,7 +288,7 @@ static void alt_thread_entry(void)
 
 
 	/* Verify that the _current_ (alt) thread is initialized with FPSCR cleared. */
-	zassert_true(__get_FPSCR() == 0,
+	zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
 		"(Alt thread) FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
 
 	zassert_true((p_ztest_thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0,
@@ -461,7 +471,7 @@ void test_arm_thread_swap(void)
 		"CONTROL.FPCA is not cleared at initialization: 0x%x\n",
 		__get_CONTROL());
 	/* Verify that the main test thread is initialized with FPSCR cleared. */
-	zassert_true(__get_FPSCR() == 0,
+	zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
 		"FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
 
 	/* Clear the thread's floating-point callee-saved registers' container.