diff --git a/CODEOWNERS b/CODEOWNERS index 4fd2ded37cdd9..0fe7030cf072e 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -38,6 +38,7 @@ /soc/arm/atmel_sam/samv71/ @nandojve /soc/arm/cypress/ @nandojve /soc/arm/bcm*/ @sbranden +/soc/arm/gigadevice/ @nandojve /soc/arm/infineon_xmc/ @parthitce /soc/arm/nxp*/ @mmahadevan108 @dleach02 /soc/arm/nordic_nrf/ @ioannisg @@ -99,6 +100,7 @@ /boards/arm/faze/ @mbittan @simonguinot /boards/arm/frdm*/ @mmahadevan108 @dleach02 /boards/arm/frdm*/doc/ @dleach02 @MeganHansen +/boards/arm/gd32*/ @nandojve /boards/arm/google_*/ @jackrosenthal /boards/arm/hexiwear*/ @mmahadevan108 @dleach02 /boards/arm/hexiwear*/doc/ @dleach02 @MeganHansen @@ -185,6 +187,7 @@ /drivers/debug/ @nashif /drivers/*/*sam4l* @nandojve /drivers/*/*cc13xx_cc26xx* @bwitherspoon +/drivers/*/*gd32* @nandojve /drivers/*/*litex* @mateusz-holenko @kgugala @pgielda /drivers/*/*mcux* @mmahadevan108 @dleach02 /drivers/*/*stm32* @erwango @ABOSTM @FRASTM @@ -393,6 +396,7 @@ /dts/arm/atmel/ @galak /dts/arm/broadcom/ @sbranden /dts/arm/cypress/ @nandojve +/dts/arm/gigadevice/ @nandojve /dts/arm/infineon/ @parthitce /dts/arm64/ @carlocaione /dts/arm64/armv8-r.dtsi @povergoing @@ -441,6 +445,7 @@ /dts/bindings/modem/*hl7800.yaml @LairdCP/zephyr /dts/bindings/serial/ns16550.yaml @dcpleung @nashif /dts/bindings/wifi/*esp-at.yaml @mniestroj +/dts/bindings/*/*gd32* @nandojve /dts/bindings/*/*npcx* @MulinChao @WealianLiao @ChiHuaL /dts/bindings/*/*psoc6* @nandojve /dts/bindings/*/nordic* @anangl @@ -563,6 +568,7 @@ /lib/libc/arcmwdt/ @abrodkin @ruuddw @evgeniy-paltsev /modules/ @nashif /modules/mbedtls/ @ceolin @d3zd3z +/modules/hal_gigadevice/ @nandojve /modules/trusted-firmware-m/ @ioannisg @microbuilder /kernel/device.c @andyross @nashif /kernel/idle.c @andyross @nashif diff --git a/boards/arm/gd32f403z_eval/CMakeLists.txt b/boards/arm/gd32f403z_eval/CMakeLists.txt new file mode 100644 index 0000000000000..159b5bc2592c9 --- /dev/null +++ b/boards/arm/gd32f403z_eval/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/arm/gd32f403z_eval/Kconfig b/boards/arm/gd32f403z_eval/Kconfig new file mode 100644 index 0000000000000..5630f4bbf05eb --- /dev/null +++ b/boards/arm/gd32f403z_eval/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 50 + help + Board initialization priority. diff --git a/boards/arm/gd32f403z_eval/Kconfig.board b/boards/arm/gd32f403z_eval/Kconfig.board new file mode 100644 index 0000000000000..61733d3bf9714 --- /dev/null +++ b/boards/arm/gd32f403z_eval/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F403Z_EVAL + bool "GigaDevice GD32F403Z Evaluation Kit" + depends on SOC_GD32F403Z diff --git a/boards/arm/gd32f403z_eval/Kconfig.defconfig b/boards/arm/gd32f403z_eval/Kconfig.defconfig new file mode 100644 index 0000000000000..39f1df8e53764 --- /dev/null +++ b/boards/arm/gd32f403z_eval/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GD32F403Z_EVAL + +config BOARD + default "gd32f403z_eval" + +endif # BOARD_GD32F403Z_EVAL diff --git a/boards/arm/gd32f403z_eval/board.c b/boards/arm/gd32f403z_eval/board.c new file mode 100644 index 0000000000000..9786e5339e5c0 --- /dev/null +++ b/boards/arm/gd32f403z_eval/board.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021 ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +static int board_init(const struct device *dev) +{ + rcu_periph_clock_enable(RCU_GPIOA); + + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + return 0; +} + +SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/arm/gd32f403z_eval/board.cmake b/boards/arm/gd32f403z_eval/board.cmake new file mode 100644 index 0000000000000..a419a88e5d13c --- /dev/null +++ b/boards/arm/gd32f403z_eval/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.png b/boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.png new file mode 100644 index 0000000000000..3f984b8889dc7 Binary files /dev/null and b/boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.png differ diff --git a/boards/arm/gd32f403z_eval/doc/index.rst b/boards/arm/gd32f403z_eval/doc/index.rst new file mode 100644 index 0000000000000..5273d767cced5 --- /dev/null +++ b/boards/arm/gd32f403z_eval/doc/index.rst @@ -0,0 +1,165 @@ +.. _gd32f403z_eval: + +GigaDevice GD32F403Z-EVAL +######################### + + +Overview +******** + +The GD32F403Z-EVAL board is a hardware platform that enables design and debug +of the GigaDevice F403 Cortex-M4F High Performance MCU. + +The GD32F403ZE features a single-core ARM Cortex-M4F MCU which can run up +to 168-MHz with flash accesses zero wait states, 512kiB of Flash, 96kiB of +SRAM and 112 GPIOs. + +.. image:: img/gd32f403z_eval.png + :width: 800px + :align: center + :alt: gd32f403z_eval + + +Hardware +******** + +- USB interface with mini-USB connector +- 4 user LEDs +- 4 user push buttons +- Reset Button +- CAN port +- ADC connected to a potentiometer +- 2 DAC channels +- GD25Q40 4Mib SPI Flash +- HY27UF081G2A 1GiB NAND Flash +- AT24C02C 2KiB EEPROM +- 3.2 TFT LCD (320x240) +- PCM1770 Stereo DAC with Headphone Amplifier +- Micro-SDHC interface +- GD-Link interface + + - CMSIS-DAP swd debug interface over USB HID. + + +For more information about the GD32F403 SoC and GD32F403Z-Eval board: + +- `GigaDevice Cortex-M4F High Performance SoC Website`_ +- `GD32F403 Datasheet`_ +- `GD32F403 Reference Manual`_ +- `GD32F403Z Eval Schematics`_ +- `GD32 ISP Console`_ + + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling | ++-----------+------------+-----------------------+ + + +Serial Port +=========== + +The GD32F403Z-EVAL board has 5 serial communication ports. The default port +is UART0 at PIN-9 and PIN-10. + +Programming and Debugging +************************* + +Before program your board make sure to configure boot setting and serial port. +The default serial port is USART0. This port uses header JP-5/6 to route +signals between USB VBUS/ID and USART J2. + ++--------+--------+------------+ +| Boot-0 | Boot-1 | Function | ++========+========+============+ +| 1-2 | 1-2 | SRAM | ++--------+--------+------------+ +| 1-2 | 2-3 | Bootloader | ++--------+--------+------------+ +| 2-3 | Any | Flash | ++--------+--------+------------+ + ++------+------+-------------+ +| JP-5 | JP-6 | Function | ++======+======+=============+ +| 1-2 | 1-2 | USART0 / J2 | ++------+------+-------------+ +| 2-3 | 2-3 | USB VBUS/ID | ++------+------+-------------+ +| open | open | Free | ++------+------+-------------+ + +Using GD-Link +============= + +The GD32F403Z-EVAL includes an onboard programmer/debugger (GD-Link) which +allow flash programming and debug over USB. There are also program and debug +headers J1 and J100 that can be used with any ARM compatible tools. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f403z_eval + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f403z_eval + :goals: flash + :compact: + + You should see "Hello World! gd32f403z_eval" in your terminal. + +#. To debug an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f403z_eval + :goals: debug + :compact: + + +.. _GigaDevice Cortex-M4F High Performance SoC Website: + https://www.gigadevice.com/products/microcontrollers/gd32/arm-cortex-m4/high-performance-line/gd32f403-series/ + +.. _GD32F403 Datasheet: + http://www.gd32mcu.com/data/documents/shujushouce/GD32F403xx_Datasheet_Rev1.3.pdf + +.. _GD32F403 Reference Manual: + http://www.gd32mcu.com/data/documents/yingyongbiji/GD32F403_User_Manual_Rev2.4.pdf + +.. _GD32F403Z Eval Schematics: + http://www.gd32mcu.com/download/down/document_id/270/path_type/1 + +.. _GD32 ISP Console: + http://www.gd32mcu.com/download/down/document_id/175/path_type/1 diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.dts b/boards/arm/gd32f403z_eval/gd32f403z_eval.dts new file mode 100644 index 0000000000000..86393b16d60c1 --- /dev/null +++ b/boards/arm/gd32f403z_eval/gd32f403z_eval.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "GigaDevice GD32F403Z Evaluation Kit"; + compatible = "gd,gd32f403z"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + }; +}; + +&usart0 { + status = "okay"; + + current-speed = <115200>; +}; diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml b/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml new file mode 100644 index 0000000000000..0066bc642184f --- /dev/null +++ b/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +identifier: gd32f403z_eval +name: GigaDevice GD32F403Z Evaluation Kit +type: mcu +arch: arm +ram: 96 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig new file mode 100644 index 0000000000000..f5b70d6a48610 --- /dev/null +++ b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_GD32F4=y +CONFIG_SOC_GD32F403Z=y +CONFIG_BOARD_GD32F403Z_EVAL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CORTEX_M_SYSTICK=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32f403z_eval/support/openocd.cfg b/boards/arm/gd32f403z_eval/support/openocd.cfg new file mode 100644 index 0000000000000..a97ad6bbca4de --- /dev/null +++ b/boards/arm/gd32f403z_eval/support/openocd.cfg @@ -0,0 +1,26 @@ +# Copyright (c) 2021 ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME gd32f403ze +set ENDIAN little +set CPUTAPID 0x790007a3 +set FLASH_SIZE 0x80000 + +source [find target/stm32f1x.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 3b9339022d0c2..5bfc1bf927a08 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -44,6 +44,7 @@ zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c) zephyr_library_sources_ifdef(CONFIG_UART_XEC uart_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_UART_NEORV32 uart_neorv32.c) +zephyr_library_sources_ifdef(CONFIG_USART_GD32 usart_gd32.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4cd924c8ebb95..b73fb90abc00a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -165,6 +165,8 @@ source "drivers/serial/Kconfig.rcar" source "drivers/serial/Kconfig.xec" +source "drivers/serial/Kconfig.gd32" + source "drivers/serial/Kconfig.test" source "drivers/serial/Kconfig.neorv32" diff --git a/drivers/serial/Kconfig.gd32 b/drivers/serial/Kconfig.gd32 new file mode 100644 index 0000000000000..4cadbd139cdfb --- /dev/null +++ b/drivers/serial/Kconfig.gd32 @@ -0,0 +1,14 @@ +# Copyright (c) 2021 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +# Workaround for not being able to have commas in macro arguments +DT_COMPAT_GIGADEVICE_GD32_USART := gd,gd32-usart + +config USART_GD32 + bool "GD32 serial driver" + default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_USART)) + depends on SOC_FAMILY_GD32 + select SERIAL_HAS_DRIVER + select USE_GD32_USART + help + This option enables the USART driver for GD32 SoC family. diff --git a/drivers/serial/usart_gd32.c b/drivers/serial/usart_gd32.c new file mode 100644 index 0000000000000..012824a7c202f --- /dev/null +++ b/drivers/serial/usart_gd32.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT gd_gd32_usart + +#include + +struct gd32_usart_config { + uint32_t reg; + uint32_t rcu_periph_clock; +}; + +struct gd32_usart_data { + uint32_t baud_rate; +}; + +static int usart_gd32_init(const struct device *dev) +{ + const struct gd32_usart_config *const cfg = dev->config; + struct gd32_usart_data *const data = dev->data; + + /* NOTE: pins are configured at board_init till pinctrl be available */ + + rcu_periph_clock_enable(cfg->rcu_periph_clock); + usart_deinit(cfg->reg); + usart_baudrate_set(cfg->reg, data->baud_rate); + usart_word_length_set(cfg->reg, USART_WL_8BIT); + usart_parity_config(cfg->reg, USART_PM_NONE); + usart_stop_bit_set(cfg->reg, USART_STB_1BIT); + usart_parity_config(cfg->reg, USART_PM_NONE); + usart_receive_config(cfg->reg, USART_RECEIVE_ENABLE); + usart_transmit_config(cfg->reg, USART_TRANSMIT_ENABLE); + usart_enable(cfg->reg); + + return 0; +} + +static int usart_gd32_poll_in(const struct device *dev, unsigned char *c) +{ + const struct gd32_usart_config *const cfg = dev->config; + uint32_t status; + + status = usart_flag_get(cfg->reg, USART_FLAG_RBNE); + + if (!status) { + return -EPERM; + } + + *c = usart_data_receive(cfg->reg); + + return 0; +} + +static void usart_gd32_poll_out(const struct device *dev, unsigned char c) +{ + const struct gd32_usart_config *const cfg = dev->config; + + usart_data_transmit(cfg->reg, c); + + while (usart_flag_get(cfg->reg, USART_FLAG_TBE) == RESET) { + ; + } +} + +static int usart_gd32_err_check(const struct device *dev) +{ + const struct gd32_usart_config *const cfg = dev->config; + uint32_t status = USART_STAT0(cfg->reg); + int errors = 0; + + if (status & USART_FLAG_ORERR) { + usart_flag_clear(cfg->reg, USART_FLAG_ORERR); + + errors |= UART_ERROR_OVERRUN; + } + + if (status & USART_FLAG_PERR) { + usart_flag_clear(cfg->reg, USART_FLAG_PERR); + + errors |= UART_ERROR_PARITY; + } + + if (status & USART_FLAG_FERR) { + usart_flag_clear(cfg->reg, USART_FLAG_FERR); + + errors |= UART_ERROR_FRAMING; + } + + usart_flag_clear(cfg->reg, USART_FLAG_NERR); + + return errors; +} + +static const struct uart_driver_api usart_gd32_driver_api = { + .poll_in = usart_gd32_poll_in, + .poll_out = usart_gd32_poll_out, + .err_check = usart_gd32_err_check, +}; + +#define GD32_USART_INIT(n) \ + static struct gd32_usart_data usart##n##_gd32_data = { \ + .baud_rate = DT_INST_PROP(n, current_speed), \ + }; \ + static const struct gd32_usart_config usart##n##_gd32_config = { \ + .reg = DT_INST_REG_ADDR(n), \ + .rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \ + }; \ + DEVICE_DT_INST_DEFINE(n, &usart_gd32_init, \ + NULL, \ + &usart##n##_gd32_data, \ + &usart##n##_gd32_config, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + &usart_gd32_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(GD32_USART_INIT) diff --git a/dts/arm/gigadevice/gd32f403.dtsi b/dts/arm/gigadevice/gd32f403.dtsi new file mode 100644 index 0000000000000..c6b81fea778c9 --- /dev/null +++ b/dts/arm/gigadevice/gd32f403.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021, ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + fmc: flash-controller@40022000 { + compatible = "gd,gd32-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40022000 0x400>; + peripheral-id = <6>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + }; + + usart0: usart@40013800 { + compatible = "gd,gd32-usart"; + reg = <0x40013800 0x400>; + rcu-periph-clock = <0x60e>; + status = "disabled"; + label = "usart_0"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/gigadevice/gd32f403zet6.dtsi b/dts/arm/gigadevice/gd32f403zet6.dtsi new file mode 100644 index 0000000000000..c96e65a40794c --- /dev/null +++ b/dts/arm/gigadevice/gd32f403zet6.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(512)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(96)>; + }; + }; +}; diff --git a/dts/bindings/serial/gd,gd32-usart.yaml b/dts/bindings/serial/gd,gd32-usart.yaml new file mode 100644 index 0000000000000..b12eca413276a --- /dev/null +++ b/dts/bindings/serial/gd,gd32-usart.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +description: GigaDevice USART + +compatible: "gd,gd32-usart" + +include: uart-controller.yaml + +properties: + reg: + required: true + + rcu-periph-clock: + type: int + description: Reset Control Unit Peripheral Clock ID + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index cf3c6bc65e751..352177db2902a 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -218,6 +218,7 @@ gaisler Gaisler gardena GARDENA GmbH gateworks Gateworks Corporation gcw Game Consoles Worldwide +gd GigaDevice Semiconductor ge General Electric Company geekbuying GeekBuying gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. diff --git a/modules/Kconfig b/modules/Kconfig index ce46fdd627722..6cf510adcce14 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -46,6 +46,9 @@ comment "Unavailable modules, please install those via the project manifest." # config ZEPHYR__MODULE # bool +comment "hal_gigadevice module not available." + depends on !ZEPHYR_HAL_GIGADEVICE_MODULE + comment "hal_nordic module not available." depends on !ZEPHYR_HAL_NORDIC_MODULE diff --git a/modules/hal_gigadevice/CMakeLists.txt b/modules/hal_gigadevice/CMakeLists.txt new file mode 100644 index 0000000000000..822c2d7ff6b6b --- /dev/null +++ b/modules/hal_gigadevice/CMakeLists.txt @@ -0,0 +1,50 @@ +# Copyright (c) 2021 ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_HAS_GD32_HAL) + +zephyr_library_named(hal_gigadevice) + +if(CONFIG_SOC_SERIES_GD32F403) + set(gd32_soc_uc GD32F403) + set(gd32_soc_lc gd32f403) +endif() + +zephyr_library_compile_definitions(${gd32_soc_uc}) + +set(gd32_soc_dir ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_uc}) +set(gd32_cmsis_dir ${gd32_soc_dir}/CMSIS/GD/${gd32_soc_uc}) +set(gd32_std_dir ${gd32_soc_dir}/standard_peripheral) +set(gd32_std_src_dir ${gd32_std_dir}/Source) + +# Global includes to be used outside hal_gigadevice +zephyr_include_directories(${gd32_cmsis_dir}/Include) +zephyr_include_directories(${gd32_std_dir}/Include) + +zephyr_library_sources(${gd32_cmsis_dir}/Source/system_${gd32_soc_lc}.c) + +zephyr_library_sources_ifdef(CONFIG_USE_GD32_ADC ${gd32_std_src_dir}/${gd32_soc_lc}_adc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_BKP ${gd32_std_src_dir}/${gd32_soc_lc}_bkp.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_CAN ${gd32_std_src_dir}/${gd32_soc_lc}_can.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC ${gd32_std_src_dir}/${gd32_soc_lc}_crc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC ${gd32_std_src_dir}/${gd32_soc_lc}_ctc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC ${gd32_std_src_dir}/${gd32_soc_lc}_dac.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG ${gd32_std_src_dir}/${gd32_soc_lc}_dbg.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA ${gd32_std_src_dir}/${gd32_soc_lc}_dma.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC ${gd32_std_src_dir}/${gd32_soc_lc}_exmc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI ${gd32_std_src_dir}/${gd32_soc_lc}_exti.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC ${gd32_std_src_dir}/${gd32_soc_lc}_fmc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_fwdgt.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO ${gd32_std_src_dir}/${gd32_soc_lc}_gpio.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C ${gd32_std_src_dir}/${gd32_soc_lc}_i2c.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC ${gd32_std_src_dir}/${gd32_soc_lc}_misc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU ${gd32_std_src_dir}/${gd32_soc_lc}_pmu.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU ${gd32_std_src_dir}/${gd32_soc_lc}_rcu.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC ${gd32_std_src_dir}/${gd32_soc_lc}_rtc.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO ${gd32_std_src_dir}/${gd32_soc_lc}_sdio.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI ${gd32_std_src_dir}/${gd32_soc_lc}_spi.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${gd32_soc_lc}_timer.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${gd32_soc_lc}_usart.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_wwdgt.c) + +endif() diff --git a/modules/hal_gigadevice/Kconfig b/modules/hal_gigadevice/Kconfig new file mode 100644 index 0000000000000..d82fef6629ea3 --- /dev/null +++ b/modules/hal_gigadevice/Kconfig @@ -0,0 +1,183 @@ +# Copyright (c) 2021 ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 + +config ZEPHYR_HAL_GIGADEVICE_MODULE + bool + +config HAS_GD32_HAL + bool + select HAS_CMSIS_CORE if SOC_FAMILY_GD32_ARM + +if HAS_GD32_HAL + +config USE_GD32_ADC + bool + help + Enable GD32 Analog-to-Digital Converter (ADC) HAL module driver + +config USE_GD32_BKP + bool + help + Enable GD32 Backup Registers (BKP) HAL module driver + +config USE_GD32_CAN + bool + help + Enable GD32 Controller Area Network (CAN) HAL module driver + +config USE_GD32_CMP + bool + help + Enable GD32 Comparator (CMP) HAL module driver + +config USE_GD32_CRC + bool + help + Enable GD32 Cyclic redundancy check calculation unit (CRC) HAL + module driver + +config USE_GD32_CTC + bool + help + Enable GD32 Clock Trim Controller (CTC) HAL module driver + +config USE_GD32_DAC + bool + help + Enable GD32 Digital-to-Analog Converter (DAC) HAL module driver + +config USE_GD32_DBG + bool + help + Enable GD32 Debug (DBG) HAL module driver + +config USE_GD32_DMA + bool + help + Enable GD32 Direct Memory Access controller (DMA) HAL module driver + +config USE_GD32_ECLIC + bool + help + Enable GD32 Enhancement Core-Local Interrupt Controller (ECLIC) HAL + module driver + +config USE_GD32_ENET + bool + help + Enable GD32 Ethernet (ENET) HAL module driver + +config USE_GD32_EXMC + bool + help + Enable GD32 External Memory Controller (EXMC) HAL module driver + +config USE_GD32_EXTI + bool + help + Enable GD32 Interrupt/Event controller (EXTI) HAL module driver + +config USE_GD32_FMC + bool + help + Enable GD32 Flash Memory Controller (FMC) HAL module driver + +config USE_GD32_FWDGT + bool + help + Enable GD32 Free Watchdog Timer (FWDGT) HAL module driver + +config USE_GD32_GPIO + bool + default y + help + Enable GD32 General-purpose and Alternate-Function I/Os + (GPIO and AFIO) HAL module driver + +config USE_GD32_I2C + bool + help + Enable GD32 Inter-Integrated Circuit Interface (I2C) HAL module driver + +config USE_GD32_MISC + bool + help + Enable GD32 System Utilities (MISC) HAL module driver + +config USE_GD32_PMU + bool + help + Enable GD32 Power Management Unit (PMU) HAL module driver + +config USE_GD32_RCU + bool + default y + help + Enable GD32 Reset and Clock Unit (RCU) HAL module driver + +config USE_GD32_RTC + bool + help + Enable GD32 Real-Time Clock (RTC) HAL module driver + +config USE_GD32_SDIO + bool + help + Enable GD32 Secure Digital Input/Output interface (SDIO) HAL module + driver + +config USE_GD32_SPI + bool + help + Enable GD32 Serial Peripheral Interface(SPI) HAL module driver + +config USE_GD32_SQPI + bool + help + Enable GD32 Serial/Quad Parallel Interface (SQPI) HAL module driver + +config USE_GD32_SHRTIMER + bool + help + Enable GD32 Super High-Resolution Timer (SHRTIMER) HAL module driver + +config USE_GD32_TIMER + bool + help + Enable GD32 Timer (TIMER) HAL module driver + +config USE_GD32_TMU + bool + help + Enable GD32 Trigonometric Math Unit (TMU) HAL module driver + +config USE_GD32_USART + bool + help + Enable GD32 Universal Synchronous/Asynchronous Receiver/Transmitter + (USART) HAL module driver + +config USE_GD32_USBD + bool + help + Enable GD32 Universal Serial Bus full-speed Device interface (USBD) + HAL module driver + +config USE_GD32_USBFS + bool + help + Enable GD32 Universal Serial Bus on-the-go Full-Speed (USBFS) HAL + module driver + +config USE_GD32_USBHS + bool + help + Enable GD32 Universal Serial Bus High-Speed interface (USBHS) HAL + module driver + +config USE_GD32_WWDGT + bool + help + Enable GD32 Window Watchdog Timer (WWDGT) HAL module driver + +endif # HAS_GD32_HAL diff --git a/soc/arm/gigadevice/CMakeLists.txt b/soc/arm/gigadevice/CMakeLists.txt new file mode 100644 index 0000000000000..6c5e7b454f67f --- /dev/null +++ b/soc/arm/gigadevice/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/gigadevice/Kconfig b/soc/arm/gigadevice/Kconfig new file mode 100644 index 0000000000000..332ff7e824a7b --- /dev/null +++ b/soc/arm/gigadevice/Kconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_GD32 + bool + select HAS_GD32_HAL + select BUILD_OUTPUT_HEX + +config SOC_FAMILY + string + default "gigadevice" + depends on SOC_FAMILY_GD32 + +config SOC_FAMILY_GD32_ARM + bool + select SOC_FAMILY_GD32 + +if SOC_FAMILY_GD32_ARM + +source "soc/arm/gigadevice/*/Kconfig.soc" + +endif # SOC_FAMILY_GD32_ARM diff --git a/soc/arm/gigadevice/Kconfig.defconfig b/soc/arm/gigadevice/Kconfig.defconfig new file mode 100644 index 0000000000000..1a17f737aec90 --- /dev/null +++ b/soc/arm/gigadevice/Kconfig.defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/gigadevice/*/Kconfig.defconfig.series" diff --git a/soc/arm/gigadevice/Kconfig.soc b/soc/arm/gigadevice/Kconfig.soc new file mode 100644 index 0000000000000..897238ff3fbec --- /dev/null +++ b/soc/arm/gigadevice/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/gigadevice/*/Kconfig.series" diff --git a/soc/arm/gigadevice/gd32f4/CMakeLists.txt b/soc/arm/gigadevice/gd32f4/CMakeLists.txt new file mode 100644 index 0000000000000..0003b5a9de275 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403 b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403 new file mode 100644 index 0000000000000..0f06ef7072555 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403 @@ -0,0 +1,21 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GD32F403R || SOC_GD32F403V || SOC_GD32F403Z + +config SOC + default "gd32f403r" if SOC_GD32F403R + default "gd32f403v" if SOC_GD32F403V + default "gd32f403z" if SOC_GD32F403Z + +config SOC_SERIES_GD32F403 + bool + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 168000000 + +config NUM_IRQS + default 68 + +endif diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series new file mode 100644 index 0000000000000..3e93f44e43aac --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F4 + +source "soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f4*" + +config SOC_SERIES + default "gd32f4" + +endif # SOC_SERIES_GD32F4 diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.series b/soc/arm/gigadevice/gd32f4/Kconfig.series new file mode 100644 index 0000000000000..8f15ecdaa8259 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.series @@ -0,0 +1,14 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F4 + bool "GigaDevice GD32F4xxx series Cortex-M4F MCU" + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select SOC_FAMILY_GD32_ARM + help + Enable support for GigaDevice GD32F4xxx MCU series diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.soc b/soc/arm/gigadevice/gd32f4/Kconfig.soc new file mode 100644 index 0000000000000..cc23f5f862c38 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.soc @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "GigaDevice GD32F4xx MCU Selection" + depends on SOC_SERIES_GD32F4 + + config SOC_GD32F403R + bool "gd32f403r" + + config SOC_GD32F403V + bool "gd32f403v" + + config SOC_GD32F403Z + bool "gd32f403z" + +endchoice diff --git a/soc/arm/gigadevice/gd32f4/linker.ld b/soc/arm/gigadevice/gd32f4/linker.ld new file mode 100644 index 0000000000000..975945d6cb102 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/gigadevice/gd32f4/soc.c b/soc/arm/gigadevice/gd32f4/soc.c new file mode 100644 index 0000000000000..09eaaaefbd368 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/soc.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief GD32 MCU series initialization code + * + * This module provides routines to initialize and support board-level + * hardware for the GigaDevice GD32 SoC. + */ + +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int gigadevice_gd32_soc_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + SystemInit(); + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(gigadevice_gd32_soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/gigadevice/gd32f4/soc.h b/soc/arm/gigadevice/gd32f4/soc.h new file mode 100644 index 0000000000000..9fb29d9be2db3 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/soc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros + * + * This header file is used to specify and describe board-level aspects + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifndef _ASMLANGUAGE + +/* Add include for DTS generated information */ +#include + +#if defined(CONFIG_SOC_SERIES_GD32F403) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/west.yml b/west.yml index 8ea80cf00fa2e..6a12abda924cc 100644 --- a/west.yml +++ b/west.yml @@ -72,6 +72,11 @@ manifest: west-commands: west/west-commands.yml groups: - hal + - name: hal_gigadevice + revision: ce323de9655972a545cbdddda813c1576d85d5d1 + path: modules/hal/gigadevice + groups: + - hal - name: hal_infineon revision: f1fa8241f8786198ba41155413243de36ed878a5 path: modules/hal/infineon