diff --git a/boards/arm/gd32f450i_eval/CMakeLists.txt b/boards/arm/gd32f450i_eval/CMakeLists.txt new file mode 100644 index 0000000000000..159b5bc2592c9 --- /dev/null +++ b/boards/arm/gd32f450i_eval/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/arm/gd32f450i_eval/Kconfig b/boards/arm/gd32f450i_eval/Kconfig new file mode 100644 index 0000000000000..5630f4bbf05eb --- /dev/null +++ b/boards/arm/gd32f450i_eval/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 50 + help + Board initialization priority. diff --git a/boards/arm/gd32f450i_eval/Kconfig.board b/boards/arm/gd32f450i_eval/Kconfig.board new file mode 100644 index 0000000000000..427e2a9c206f6 --- /dev/null +++ b/boards/arm/gd32f450i_eval/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450I_EVAL + bool "GigaDevice GD32F450I Evaluation Kit" + depends on SOC_GD32F450I diff --git a/boards/arm/gd32f450i_eval/Kconfig.defconfig b/boards/arm/gd32f450i_eval/Kconfig.defconfig new file mode 100644 index 0000000000000..f235800929033 --- /dev/null +++ b/boards/arm/gd32f450i_eval/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GD32F450I_EVAL + +config BOARD + default "gd32f450i_eval" + +endif # BOARD_GD32F450I_EVAL diff --git a/boards/arm/gd32f450i_eval/board.c b/boards/arm/gd32f450i_eval/board.c new file mode 100644 index 0000000000000..c8e621555839d --- /dev/null +++ b/boards/arm/gd32f450i_eval/board.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +/** Initialize the board's hardware through GD32 HAL */ +static int board_init(const struct device *dev) +{ + /* Enable GPIOA clock for PA9, PA10 */ + rcu_periph_clock_enable(RCU_GPIOA); + + /* Pin AF definition can be found in datasheet Device overview section */ + gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9); + gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_10); + + /* Configure USART0 Tx as alternate function push-pull */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + + /* Configure USART0 Rx as alternate function push-pull */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_10); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + return 0; +} + +SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/arm/gd32f450i_eval/board.cmake b/boards/arm/gd32f450i_eval/board.cmake new file mode 100644 index 0000000000000..e3f7c54ba24a9 --- /dev/null +++ b/boards/arm/gd32f450i_eval/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=GD32F450IK") +board_runner_args(jlink "--iface=JTAG") +board_runner_args(jlink "--speed=4000") +board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") +board_runner_args(jlink "--tool-opt=-autoconnect 1") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png b/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png new file mode 100644 index 0000000000000..ff41f9da936f6 Binary files /dev/null and b/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png differ diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.dts b/boards/arm/gd32f450i_eval/gd32f450i_eval.dts new file mode 100644 index 0000000000000..52da6774f18e7 --- /dev/null +++ b/boards/arm/gd32f450i_eval/gd32f450i_eval.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "GigaDevice GD32F450I Evaluation Kit"; + compatible = "gd,gd32f450i"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + }; +}; + +&usart0 { + status = "okay"; + + current-speed = <115200>; +}; diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml b/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml new file mode 100644 index 0000000000000..d6d2a6b45e303 --- /dev/null +++ b/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: gd32f450i_eval +name: GigaDevice GD32F450I Evaluation Kit +type: mcu +arch: arm +ram: 256 +flash: 3072 +toolchain: + - zephyr + - gnuarmemb + - xtools diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig new file mode 100644 index 0000000000000..e5a9f21699d04 --- /dev/null +++ b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_GD32F4=y +CONFIG_SOC_GD32F450I=y +CONFIG_BOARD_GD32F450I_EVAL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CORTEX_M_SYSTICK=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/dts/arm/gigadevice/gd32f405.dtsi b/dts/arm/gigadevice/gd32f405.dtsi new file mode 100644 index 0000000000000..3007ed04ef634 --- /dev/null +++ b/dts/arm/gigadevice/gd32f405.dtsi @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + fmc: flash-controller@40023c00 { + compatible = "gd,gd32-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40023c00 0x400>; + peripheral-id = <6>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + }; + + usart0: usart@40011000 { + compatible = "gd,gd32-usart"; + reg = <0x40011000 0x400>; + interrupts = <37 0>; + rcu-periph-clock = <0x1104>; + status = "disabled"; + label = "usart_0"; + }; + + usart1: usart@40004400 { + compatible = "gd,gd32-usart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + rcu-periph-clock = <0x1011>; + status = "disabled"; + label = "usart_1"; + }; + + usart2: usart@40004800 { + compatible = "gd,gd32-usart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + rcu-periph-clock = <0x1012>; + status = "disabled"; + label = "usart_2"; + }; + + uart3: usart@40004c00 { + compatible = "gd,gd32-usart"; + reg = <0x40004c00 0x400>; + interrupts = <52 0>; + rcu-periph-clock = <0x1013>; + status = "disabled"; + label = "uart_3"; + }; + + uart4: usart@40005000 { + compatible = "gd,gd32-usart"; + reg = <0x40005000 0x400>; + interrupts = <52 0>; + rcu-periph-clock = <0x1014>; + status = "disabled"; + label = "uart_4"; + }; + + usart5: usart@40011400 { + compatible = "gd,gd32-usart"; + reg = <0x40011400 0x400>; + interrupts = <71 0>; + rcu-periph-clock = <0x1105>; + status = "disabled"; + label = "usart_5"; + }; + + uart6: usart@40007800 { + compatible = "gd,gd32-usart"; + reg = <0x40007800 0x400>; + interrupts = <82 0>; + rcu-periph-clock = <0x101e>; + status = "disabled"; + label = "uart_6"; + }; + + uart7: usart@40007c00 { + compatible = "gd,gd32-usart"; + reg = <0x40007c00 0x400>; + interrupts = <83 0>; + rcu-periph-clock = <0x101f>; + status = "disabled"; + label = "uart_7"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/gigadevice/gd32f405vgt6.dtsi b/dts/arm/gigadevice/gd32f405vgt6.dtsi new file mode 100644 index 0000000000000..de9f109f46d0c --- /dev/null +++ b/dts/arm/gigadevice/gd32f405vgt6.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40023c00 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(1024)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(192)>; + }; + }; +}; diff --git a/dts/arm/gigadevice/gd32f407.dtsi b/dts/arm/gigadevice/gd32f407.dtsi new file mode 100644 index 0000000000000..6d5762f71ac61 --- /dev/null +++ b/dts/arm/gigadevice/gd32f407.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/gigadevice/gd32f450.dtsi b/dts/arm/gigadevice/gd32f450.dtsi new file mode 100644 index 0000000000000..6d5762f71ac61 --- /dev/null +++ b/dts/arm/gigadevice/gd32f450.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/gigadevice/gd32f450ikh6.dtsi b/dts/arm/gigadevice/gd32f450ikh6.dtsi new file mode 100644 index 0000000000000..6a738a2a34cff --- /dev/null +++ b/dts/arm/gigadevice/gd32f450ikh6.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40023c00 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(3072)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(256)>; + }; + }; +}; diff --git a/modules/hal_gigadevice/CMakeLists.txt b/modules/hal_gigadevice/CMakeLists.txt index 822c2d7ff6b6b..03bd4bae239bf 100644 --- a/modules/hal_gigadevice/CMakeLists.txt +++ b/modules/hal_gigadevice/CMakeLists.txt @@ -5,12 +5,27 @@ if(CONFIG_HAS_GD32_HAL) zephyr_library_named(hal_gigadevice) -if(CONFIG_SOC_SERIES_GD32F403) - set(gd32_soc_uc GD32F403) - set(gd32_soc_lc gd32f403) +if(CONFIG_SOC_SERIES_GD32F4) + if(CONFIG_SOC_SERIES_GD32F403) + set(gd32_soc_df GD32F403) + set(gd32_soc_uc GD32F403) + set(gd32_soc_lc gd32f403) + elseif(CONFIG_SOC_SERIES_GD32F405) + set(gd32_soc_df GD32F405) + set(gd32_soc_uc GD32F4XX) + set(gd32_soc_lc gd32f4xx) + elseif(CONFIG_SOC_SERIES_GD32F407) + set(gd32_soc_df GD32F407) + set(gd32_soc_uc GD32F4XX) + set(gd32_soc_lc gd32f4xx) + elseif(CONFIG_SOC_SERIES_GD32F450) + set(gd32_soc_df GD32F450) + set(gd32_soc_uc GD32F4XX) + set(gd32_soc_lc gd32f4xx) + endif() endif() -zephyr_library_compile_definitions(${gd32_soc_uc}) +zephyr_compile_definitions(${gd32_soc_df}) set(gd32_soc_dir ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_uc}) set(gd32_cmsis_dir ${gd32_soc_dir}/CMSIS/GD/${gd32_soc_uc}) @@ -30,20 +45,27 @@ zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC ${gd32_std_src_dir}/${gd32_so zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC ${gd32_std_src_dir}/${gd32_soc_lc}_ctc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC ${gd32_std_src_dir}/${gd32_soc_lc}_dac.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG ${gd32_std_src_dir}/${gd32_soc_lc}_dbg.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_DCI ${gd32_std_src_dir}/${gd32_soc_lc}_dci.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA ${gd32_std_src_dir}/${gd32_soc_lc}_dma.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_ENET ${gd32_std_src_dir}/${gd32_soc_lc}_enet.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC ${gd32_std_src_dir}/${gd32_soc_lc}_exmc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI ${gd32_std_src_dir}/${gd32_soc_lc}_exti.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC ${gd32_std_src_dir}/${gd32_soc_lc}_fmc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_fwdgt.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO ${gd32_std_src_dir}/${gd32_soc_lc}_gpio.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C ${gd32_std_src_dir}/${gd32_soc_lc}_i2c.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_IPA ${gd32_std_src_dir}/${gd32_soc_lc}_ipa.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_IREF ${gd32_std_src_dir}/${gd32_soc_lc}_iref.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC ${gd32_std_src_dir}/${gd32_soc_lc}_misc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU ${gd32_std_src_dir}/${gd32_soc_lc}_pmu.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU ${gd32_std_src_dir}/${gd32_soc_lc}_rcu.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC ${gd32_std_src_dir}/${gd32_soc_lc}_rtc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO ${gd32_std_src_dir}/${gd32_soc_lc}_sdio.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI ${gd32_std_src_dir}/${gd32_soc_lc}_spi.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_SYSCFG ${gd32_std_src_dir}/${gd32_soc_lc}_syscfg.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${gd32_soc_lc}_timer.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_TLI ${gd32_std_src_dir}/${gd32_soc_lc}_tli.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_TRNG ${gd32_std_src_dir}/${gd32_soc_lc}_trng.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${gd32_soc_lc}_usart.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_wwdgt.c) diff --git a/modules/hal_gigadevice/Kconfig b/modules/hal_gigadevice/Kconfig index d82fef6629ea3..57db311e1eca9 100644 --- a/modules/hal_gigadevice/Kconfig +++ b/modules/hal_gigadevice/Kconfig @@ -51,6 +51,11 @@ config USE_GD32_DBG help Enable GD32 Debug (DBG) HAL module driver +config USE_GD32_DCI + bool + help + Enable GD32 Digital camera interface (DCI) HAL module driver + config USE_GD32_DMA bool help @@ -99,6 +104,16 @@ config USE_GD32_I2C help Enable GD32 Inter-Integrated Circuit Interface (I2C) HAL module driver +config USE_GD32_IPA + bool + help + Enable GD32 Image Processing Accelerator (IPA) HAL module driver + +config USE_GD32_IREF + bool + help + Enable GD32 Programmable current reference (IREF) HAL module driver + config USE_GD32_MISC bool help @@ -141,11 +156,21 @@ config USE_GD32_SHRTIMER help Enable GD32 Super High-Resolution Timer (SHRTIMER) HAL module driver +config USE_GD32_SYSCFG + bool + help + Enable GD32 SYSCFG HAL module driver + config USE_GD32_TIMER bool help Enable GD32 Timer (TIMER) HAL module driver +config USE_GD32_TLI + bool + help + Enable GD32 TFT-LCD Interface (TLI) HAL module driver + config USE_GD32_TMU bool help diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f405 b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f405 new file mode 100644 index 0000000000000..f863edf119b2d --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f405 @@ -0,0 +1,21 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GD32F405R || SOC_GD32F405V || SOC_GD32F405Z + +config SOC + default "gd32f405r" if SOC_GD32F405R + default "gd32f405v" if SOC_GD32F405V + default "gd32f405z" if SOC_GD32F405Z + +config SOC_SERIES_GD32F405 + bool + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 168000000 + +config NUM_IRQS + default 82 + +endif diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f407 b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f407 new file mode 100644 index 0000000000000..dc269130f05f7 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f407 @@ -0,0 +1,21 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GD32F407R || SOC_GD32F407V || SOC_GD32F407Z + +config SOC + default "gd32f407r" if SOC_GD32F407R + default "gd32f407v" if SOC_GD32F407V + default "gd32f407z" if SOC_GD32F407Z + +config SOC_SERIES_GD32F407 + bool + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 168000000 + +config NUM_IRQS + default 82 + +endif diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f450 b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f450 new file mode 100644 index 0000000000000..18675f7b70712 --- /dev/null +++ b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f450 @@ -0,0 +1,21 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GD32F450V || SOC_GD32F450Z || SOC_GD32F450I + +config SOC + default "gd32f450v" if SOC_GD32F450V + default "gd32f450z" if SOC_GD32F450Z + default "gd32f450i" if SOC_GD32F450I + +config SOC_SERIES_GD32F450 + bool + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 200000000 + +config NUM_IRQS + default 91 + +endif diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.soc b/soc/arm/gigadevice/gd32f4/Kconfig.soc index cc23f5f862c38..e1401f99c887b 100644 --- a/soc/arm/gigadevice/gd32f4/Kconfig.soc +++ b/soc/arm/gigadevice/gd32f4/Kconfig.soc @@ -1,4 +1,5 @@ # Copyright (c) 2021, ATL Electronics +# Copyright (c) 2021 BrainCo Inc. # SPDX-License-Identifier: Apache-2.0 choice @@ -14,4 +15,31 @@ choice config SOC_GD32F403Z bool "gd32f403z" + config SOC_GD32F405R + bool "gd32f405r" + + config SOC_GD32F405V + bool "gd32f405v" + + config SOC_GD32F405Z + bool "gd32f405z" + + config SOC_GD32F407R + bool "gd32f407r" + + config SOC_GD32F407V + bool "gd32f407v" + + config SOC_GD32F407Z + bool "gd32f407z" + + config SOC_GD32F450V + bool "gd32f450v" + + config SOC_GD32F450Z + bool "gd32f450z" + + config SOC_GD32F450I + bool "gd32f450i" + endchoice diff --git a/soc/arm/gigadevice/gd32f4/soc.h b/soc/arm/gigadevice/gd32f4/soc.h index 9fb29d9be2db3..317c040e78fc7 100644 --- a/soc/arm/gigadevice/gd32f4/soc.h +++ b/soc/arm/gigadevice/gd32f4/soc.h @@ -22,6 +22,10 @@ #if defined(CONFIG_SOC_SERIES_GD32F403) #include +#elif defined(CONFIG_SOC_SERIES_GD32F405) || \ + defined(CONFIG_SOC_SERIES_GD32F407) || \ + defined(CONFIG_SOC_SERIES_GD32F450) +#include #else #error Library does not support the specified device. #endif