diff --git a/boards/arm/gd32f350r_eval/Kconfig.board b/boards/arm/gd32f350r_eval/Kconfig.board new file mode 100644 index 0000000000000..b4fbc6635f7c8 --- /dev/null +++ b/boards/arm/gd32f350r_eval/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F350R_EVAL + bool "GigaDevice GD32F350R Evaluation Kit" + depends on SOC_GD32F350 diff --git a/boards/arm/gd32f350r_eval/Kconfig.defconfig b/boards/arm/gd32f350r_eval/Kconfig.defconfig new file mode 100644 index 0000000000000..1de5675fb9cd1 --- /dev/null +++ b/boards/arm/gd32f350r_eval/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GD32F350R_EVAL + +config BOARD + default "gd32f350r_eval" + +endif # BOARD_GD32F350R_EVAL diff --git a/boards/arm/gd32f350r_eval/board.cmake b/boards/arm/gd32f350r_eval/board.cmake new file mode 100644 index 0000000000000..05d5d4c952cc8 --- /dev/null +++ b/boards/arm/gd32f350r_eval/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(jlink "--device=GD32F350G6" "--iface=SWD" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.png b/boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.png new file mode 100644 index 0000000000000..e8c5de489d47e Binary files /dev/null and b/boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.png differ diff --git a/boards/arm/gd32f350r_eval/doc/index.rst b/boards/arm/gd32f350r_eval/doc/index.rst new file mode 100644 index 0000000000000..157ef7b34fe5a --- /dev/null +++ b/boards/arm/gd32f350r_eval/doc/index.rst @@ -0,0 +1,138 @@ +.. _gd32f350r_eval: + +GigaDevice GD32F350R-EVAL +######################### + +Overview +******** + +The GD32F350R-EVAL board is a hardware platform that enables design and debug +of the GigaDevice F350 Cortex-M4F High Performance MCU. + +The GD32F350RBT6 features a single-core ARM Cortex-M4F MCU which can run up +to 108-MHz with flash accesses zero wait states, 128kB of Flash, 16kB of +SRAM and 55 GPIOs. + +.. image:: img/gd32f350r_eval.png + :align: center + :alt: gd32f350r_eval + +Hardware +******** + +- GD32F350RBT6 MCU +- AT24C02C 2Kb EEPROM +- 4 x User LEDs +- 4 x User Push buttons +- 1 x USART (RS-232 at J2 connector) +- 1 x POT connected to an ADC input +- Headphone interface +- Micro SD Card Interface +- 2.4'' TFT-LCD (36x48) +- GD-Link on board programmer +- J-Link/SWD connector + +For more information about the GD32F350 SoC and GD32F350R-EVAL board: + +- `GigaDevice Cortex-M4F Stretch Performance SoC Website`_ +- `GD32F350xx Datasheet`_ +- `GD32F3x0 User Manual`_ +- `GD32F350R-EVAL User Manual`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v7m-nvic` + * - SYSTICK + - N/A + - N/A + * - USART + - :kconfig:`CONFIG_SERIAL` + - :dtcompatible:`gd,gd32-usart` + * - PINMUX + - :kconfig:`CONFIG_PINCTRL` + - :dtcompatible:`gd,gd32-pinctrl-af` + +Serial Port +=========== + +The GD32F350R-EVAL board has one serial communication port. The default port +is USART0 with TX connected at PA9 and RX at PA10. + +Programming and Debugging +************************* + +Before programming your board make sure to configure boot and serial jumpers as follows: + +- J4: Select 2-3 for both (labeled as ``L``) +- J13: Select 1-2 position (labeled as ``USART``) + +Using GD-Link +============= + +The GD32F350R-EVAL includes an onboard programmer/debugger (GD-Link) which +allows flash programming and debugging over USB. There is also a SWD header +(J3) which can be used with tools like Segger J-Link. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f350r_eval + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. On Linux the + terminal should be something like ``/dev/ttyUSB0``. For example: + + .. code-block:: console + + minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f350r_eval + :goals: flash + :compact: + + You should see "Hello World! gd32f350r_eval" in your terminal. + +#. To debug an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32f350r_eval + :goals: debug + :compact: + +.. _GigaDevice Cortex-M4F Stretch Performance SoC Website: + https://www.gigadevice.com/products/microcontrollers/gd32/arm-cortex-m4/stretch-performance-line/ + +.. _GD32F350xx Datasheet: + http://gd32mcu.com/download/down/document_id/133/path_type/1 + +.. _GD32F3x0 User Manual: + http://gd32mcu.com/download/down/document_id/136/path_type/1 + +.. _GD32F350R-EVAL User Manual: + https://www.tme.com/Document/ff0a3609934053c07d78ef8662781da9/GD32350R-EVAL%20User%20Manual-V1.0.pdf diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi b/boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi new file mode 100644 index 0000000000000..40d1c1514058e --- /dev/null +++ b/boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group1 { + pinmux = , ; + }; + }; +}; diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.dts b/boards/arm/gd32f350r_eval/gd32f350r_eval.dts new file mode 100644 index 0000000000000..1f1e90693aef3 --- /dev/null +++ b/boards/arm/gd32f350r_eval/gd32f350r_eval.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "gd32f350r_eval-pinctrl.dtsi" + +/ { + model = "GigaDevice GD32F350R Evaluation Kit"; + compatible = "gd,gd32f350r-eval"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + }; +}; + +&usart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml b/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml new file mode 100644 index 0000000000000..7386d3e384902 --- /dev/null +++ b/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2021 BrainCO Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: gd32f350r_eval +name: GigaDevice GD32F350R Evaluation Kit +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig b/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig new file mode 100644 index 0000000000000..9397bdbd30d41 --- /dev/null +++ b/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_GD32F3X0=y +CONFIG_SOC_GD32F350=y +CONFIG_BOARD_GD32F350R_EVAL=y + +CONFIG_CORTEX_M_SYSTICK=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32f350r_eval/support/openocd.cfg b/boards/arm/gd32f350r_eval/support/openocd.cfg new file mode 100644 index 0000000000000..8a9690db8109d --- /dev/null +++ b/boards/arm/gd32f350r_eval/support/openocd.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2021, ATL-Electronics +# Copyright (c) 2021, BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/cmsis-dap.cfg] +transport select swd + +set CHIPNAME gd32f350rb +set CPUTAPID 0x790007a3 + +source [find target/stm32f3x.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/drivers/pinctrl/pinctrl_gd32_af.c b/drivers/pinctrl/pinctrl_gd32_af.c index d86b36e2e0ddc..c23c27aeca3a7 100644 --- a/drivers/pinctrl/pinctrl_gd32_af.c +++ b/drivers/pinctrl/pinctrl_gd32_af.c @@ -5,6 +5,7 @@ */ #include +#include BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) && (GD32_PUPD_PULLUP == GPIO_PUPD_PULLUP) && @@ -16,9 +17,15 @@ BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) && "pinctrl output type definitions != HAL definitions"); BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) && +#ifdef CONFIG_SOC_SERIES_GD32F3X0 + (GD32_OSPEED_10MHZ == GPIO_OSPEED_10MHZ) && + (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) && +#else (GD32_OSPEED_25MHZ == GPIO_OSPEED_25MHZ) && (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) && - (GD32_OSPEED_200MHZ == GPIO_OSPEED_200MHZ), + (GD32_OSPEED_200MHZ == GPIO_OSPEED_200MHZ) && +#endif /* CONFIG_SOC_SERIES_GD32F3X0 */ + 1U, "pinctrl output speed definitions != HAL definitions"); /** Utility macro that expands to the GPIO port address if it exists */ diff --git a/drivers/serial/usart_gd32.c b/drivers/serial/usart_gd32.c index 8da839684d926..4797e26f95d17 100644 --- a/drivers/serial/usart_gd32.c +++ b/drivers/serial/usart_gd32.c @@ -8,6 +8,12 @@ #include #include #include +#include + +/* Unify GD32 HAL USART status register name to USART_STAT */ +#ifndef USART_STAT +#define USART_STAT USART_STAT0 +#endif struct gd32_usart_config { uint32_t reg; @@ -120,7 +126,7 @@ static void usart_gd32_poll_out(const struct device *dev, unsigned char c) static int usart_gd32_err_check(const struct device *dev) { const struct gd32_usart_config *const cfg = dev->config; - uint32_t status = USART_STAT0(cfg->reg); + uint32_t status = USART_STAT(cfg->reg); int errors = 0; if (status & USART_FLAG_ORERR) { diff --git a/dts/arm/gigadevice/gd32f3x0/gd32f350g6.dtsi b/dts/arm/gigadevice/gd32f3x0/gd32f350g6.dtsi new file mode 100644 index 0000000000000..a01677ad17700 --- /dev/null +++ b/dts/arm/gigadevice/gd32f3x0/gd32f350g6.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40022000{ + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(32)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(6)>; + }; + }; +}; diff --git a/dts/arm/gigadevice/gd32f3x0/gd32f350rb.dtsi b/dts/arm/gigadevice/gd32f3x0/gd32f350rb.dtsi new file mode 100644 index 0000000000000..f7e34166a6a86 --- /dev/null +++ b/dts/arm/gigadevice/gd32f3x0/gd32f350rb.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40022000{ + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi b/dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi new file mode 100644 index 0000000000000..bb63f6eda1d7e --- /dev/null +++ b/dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + clock-frequency = <108000000>; + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + fmc: flash-controller@40022000 { + compatible = "gd,gd32-flash-controller"; + label = "FMC"; + reg = <0x40022000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + }; + + usart0: usart@40013800 { + compatible = "gd,gd32-usart"; + reg = <0x40013800 0x400>; + interrupts = <27 0>; + rcu-periph-clock = <0x060e>; + status = "disabled"; + label = "USART_0"; + }; + + usart1: usart@40004400 { + compatible = "gd,gd32-usart"; + reg = <0x40004400 0x400>; + interrupts = <28 0>; + rcu-periph-clock = <0x0711>; + status = "disabled"; + label = "USART_1"; + }; + + pinctrl: pin-controller@48000000 { + compatible = "gd,gd32-pinctrl-af"; + reg = <0x48000000 0x1800>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + label = "PINCTRL"; + + gpioa: gpio@48000000 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000000 0x400>; + rcu-periph-clock = <0x511>; + status = "disabled"; + label = "GPIOA"; + }; + + gpiob: gpio@48000400 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000400 0x400>; + rcu-periph-clock = <0x512>; + status = "disabled"; + label = "GPIOB"; + }; + + gpioc: gpio@48000800 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000800 0x400>; + rcu-periph-clock = <0x513>; + status = "disabled"; + label = "GPIOC"; + }; + + gpiod: gpio@48000c00 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + rcu-periph-clock = <0x514>; + status = "disabled"; + label = "GPIOD"; + }; + + gpiof: gpio@48001400 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001400 0x400>; + rcu-periph-clock = <0x516>; + status = "disabled"; + label = "GPIOF"; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/modules/hal_gigadevice/CMakeLists.txt b/modules/hal_gigadevice/CMakeLists.txt index 9315c9b9a35d5..eb929e8aa7493 100644 --- a/modules/hal_gigadevice/CMakeLists.txt +++ b/modules/hal_gigadevice/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources(${gd32_cmsis_dir}/source/system_${CONFIG_SOC_SERIES}.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_ADC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_adc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_BKP ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_bkp.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_CAN ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_can.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_CEC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_cec.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_crc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_ctc.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dac.c) @@ -49,6 +50,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_GD32_SYSCFG ${gd32_std_src_dir}/${CONFIG zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_timer.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_TLI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tli.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_TRNG ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_trng.c) +zephyr_library_sources_ifdef(CONFIG_USE_GD32_TSI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tsi.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_usart.c) zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_wwdgt.c) diff --git a/modules/hal_gigadevice/Kconfig b/modules/hal_gigadevice/Kconfig index 21c60b0ec6009..80b81926740d2 100644 --- a/modules/hal_gigadevice/Kconfig +++ b/modules/hal_gigadevice/Kconfig @@ -35,6 +35,11 @@ config USE_GD32_CAN help Enable GD32 Controller Area Network (CAN) HAL module driver +config USE_GD32_CEC + bool + help + Enable GD32 Consumer Electronics Control (CEC) HAL module driver + config USE_GD32_CMP bool help @@ -191,6 +196,11 @@ config USE_GD32_TRNG help Enable GD32 True Random Number Generator (TRNG) HAL module driver +config USE_GD32_TSI + bool + help + Enable GD32 Touch Sensing Interface (TSI) HAL module driver + config USE_GD32_USART bool help diff --git a/soc/arm/gigadevice/common/pinctrl_soc.h b/soc/arm/gigadevice/common/pinctrl_soc.h index 979a9eb465a55..331986bc0bfc0 100644 --- a/soc/arm/gigadevice/common/pinctrl_soc.h +++ b/soc/arm/gigadevice/common/pinctrl_soc.h @@ -106,12 +106,19 @@ typedef uint32_t pinctrl_soc_pin_t; #ifdef CONFIG_PINCTRL_GD32_AF /** Maximum 2MHz */ #define GD32_OSPEED_2MHZ 0U +#ifdef CONFIG_SOC_SERIES_GD32F3X0 +/** Maximum 10MHz */ +#define GD32_OSPEED_10MHZ 1U +/** Maximum 50MHz */ +#define GD32_OSPEED_50MHZ 3U +#else /** Maximum 25MHz */ #define GD32_OSPEED_25MHZ 1U /** Maximum 50MHz */ #define GD32_OSPEED_50MHZ 2U /** Maximum 200MHz */ #define GD32_OSPEED_200MHZ 3U +#endif /* CONFIG_SOC_SERIES_GD32F3X0 */ #else /** Maximum 10MHz */ #define GD32_OSPEED_10MHZ 0U diff --git a/soc/arm/gigadevice/gd32f3x0/CMakeLists.txt b/soc/arm/gigadevice/gd32f3x0/CMakeLists.txt new file mode 100644 index 0000000000000..012b6cddc94a8 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) diff --git a/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32f350 b/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32f350 new file mode 100644 index 0000000000000..6cd1ca9ec8bed --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32f350 @@ -0,0 +1,11 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC + default "gd32f350" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config NUM_IRQS + default 68 diff --git a/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.series new file mode 100644 index 0000000000000..dc9607f114996 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F3X0 + +source "soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32*" + +config SOC_SERIES + default "gd32f3x0" + +endif # SOC_SERIES_GD32F3X0 diff --git a/soc/arm/gigadevice/gd32f3x0/Kconfig.series b/soc/arm/gigadevice/gd32f3x0/Kconfig.series new file mode 100644 index 0000000000000..19df5f23bf3d3 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/Kconfig.series @@ -0,0 +1,12 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F3X0 + bool "GigaDevice GD32F3X0 series Cortex-M4F MCU" + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select SOC_FAMILY_GD32_ARM + select GD32_HAS_AF_PINMUX + help + Enable support for GigaDevice GD32F3X0 MCU series diff --git a/soc/arm/gigadevice/gd32f3x0/Kconfig.soc b/soc/arm/gigadevice/gd32f3x0/Kconfig.soc new file mode 100644 index 0000000000000..1acbaaf4ae0a4 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "GigaDevice GD32F3X0 MCU Selection" + depends on SOC_SERIES_GD32F3X0 + + config SOC_GD32F350 + bool "gd32f350" +endchoice diff --git a/soc/arm/gigadevice/gd32f3x0/linker.ld b/soc/arm/gigadevice/gd32f3x0/linker.ld new file mode 100644 index 0000000000000..530299298878b --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/linker.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/gigadevice/gd32f3x0/soc.c b/soc/arm/gigadevice/gd32f3x0/soc.c new file mode 100644 index 0000000000000..cbb59de3f7bb9 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/soc.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static int gd32f3x0_init(const struct device *dev) +{ + uint32_t key; + + ARG_UNUSED(dev); + + key = irq_lock(); + + SystemInit(); + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(gd32f3x0_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/gigadevice/gd32f3x0/soc.h b/soc/arm/gigadevice/gd32f3x0/soc.h new file mode 100644 index 0000000000000..9a58f98c4d087 --- /dev/null +++ b/soc/arm/gigadevice/gd32f3x0/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021 BrainCo Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ +#define _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include +#include + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ */ diff --git a/west.yml b/west.yml index 6416383749c8f..905088b437d12 100644 --- a/west.yml +++ b/west.yml @@ -73,7 +73,7 @@ manifest: groups: - hal - name: hal_gigadevice - revision: 749fdd4b9dc9dfc57daac1229a5a669109e14624 + revision: 2eafc9d95b623757df0027dd08ed1b693d3bb770 path: modules/hal/gigadevice groups: - hal