boards: arm: Introduce gd32f350r_eval board

boards/arm/gd32f350r_eval/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GD32F350R_EVAL
+	bool "GigaDevice GD32F350R Evaluation Kit"
+	depends on SOC_GD32F350

boards/arm/gd32f350r_eval/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_GD32F350R_EVAL
+
+config BOARD
+	default "gd32f350r_eval"
+
+endif # BOARD_GD32F350R_EVAL

boards/arm/gd32f350r_eval/board.cmake

@@ -0,0 +1,7 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(jlink "--device=GD32F350G6" "--iface=SWD" "--speed=4000")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/gd32f350r_eval/doc/index.rst

@@ -0,0 +1,138 @@
+.. _gd32f350r_eval:
+
+GigaDevice GD32F350R-EVAL
+#########################
+
+Overview
+********
+
+The GD32F350R-EVAL board is a hardware platform that enables design and debug
+of the GigaDevice F350 Cortex-M4F High Performance MCU.
+
+The GD32F350RBT6 features a single-core ARM Cortex-M4F MCU which can run up
+to 108-MHz with flash accesses zero wait states, 128kB of Flash, 16kB of
+SRAM and 55 GPIOs.
+
+.. image:: img/gd32f350r_eval.png
+     :align: center
+     :alt: gd32f350r_eval
+
+Hardware
+********
+
+- GD32F350RBT6 MCU
+- AT24C02C 2Kb EEPROM
+- 4 x User LEDs
+- 4 x User Push buttons
+- 1 x USART (RS-232 at J2 connector)
+- 1 x POT connected to an ADC input
+- Headphone interface
+- Micro SD Card Interface
+- 2.4'' TFT-LCD (36x48)
+- GD-Link on board programmer
+- J-Link/SWD connector
+
+For more information about the GD32F350 SoC and GD32F350R-EVAL board:
+
+- `GigaDevice Cortex-M4F Stretch Performance SoC Website`_
+- `GD32F350xx Datasheet`_
+- `GD32F3x0 User Manual`_
+- `GD32F350R-EVAL User Manual`_
+
+Supported Features
+==================
+
+The board configuration supports the following hardware features:
+
+.. list-table::
+   :header-rows: 1
+
+   * - Peripheral
+     - Kconfig option
+     - Devicetree compatible
+   * - NVIC
+     - N/A
+     - :dtcompatible:`arm,v7m-nvic`
+   * - SYSTICK
+     - N/A
+     - N/A
+   * - USART
+     - :kconfig:`CONFIG_SERIAL`
+     - :dtcompatible:`gd,gd32-usart`
+   * - PINMUX
+     - :kconfig:`CONFIG_PINCTRL`
+     - :dtcompatible:`gd,gd32-pinctrl-af`
+
+Serial Port
+===========
+
+The GD32F350R-EVAL board has one serial communication port. The default port
+is USART0 with TX connected at PA9 and RX at PA10.
+
+Programming and Debugging
+*************************
+
+Before programming your board make sure to configure boot and serial jumpers as follows:
+
+- J4:  Select 2-3 for both (labeled as ``L``)
+- J13: Select 1-2 position (labeled as ``USART``)
+
+Using GD-Link
+=============
+
+The GD32F350R-EVAL includes an onboard programmer/debugger (GD-Link) which
+allows flash programming and debugging over USB. There is also a SWD header
+(J3) which can be used with tools like Segger J-Link.
+
+#. Build the Zephyr kernel and the :ref:`hello_world` sample application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f350r_eval
+      :goals: build
+      :compact:
+
+#. Run your favorite terminal program to listen for output. On Linux the
+   terminal should be something like ``/dev/ttyUSB0``. For example:
+
+   .. code-block:: console
+
+      minicom -D /dev/ttyUSB0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+      - Speed: 115200
+      - Data: 8 bits
+      - Parity: None
+      - Stop bits: 1
+
+#. To flash an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f350r_eval
+      :goals: flash
+      :compact:
+
+   You should see "Hello World! gd32f350r_eval" in your terminal.
+
+#. To debug an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f350r_eval
+      :goals: debug
+      :compact:
+
+.. _GigaDevice Cortex-M4F Stretch Performance SoC Website:
+   https://www.gigadevice.com/products/microcontrollers/gd32/arm-cortex-m4/stretch-performance-line/
+
+.. _GD32F350xx Datasheet:
+   http://gd32mcu.com/download/down/document_id/133/path_type/1
+
+.. _GD32F3x0 User Manual:
+   http://gd32mcu.com/download/down/document_id/136/path_type/1
+
+.. _GD32F350R-EVAL User Manual:
+   https://www.tme.com/Document/ff0a3609934053c07d78ef8662781da9/GD32350R-EVAL%20User%20Manual-V1.0.pdf

boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/gd32f350r(8-b)xx-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <USART0_TX_PA9>, <USART0_RX_PA10>;
+		};
+	};
+};

boards/arm/gd32f350r_eval/gd32f350r_eval.dts

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <gigadevice/gd32f3x0/gd32f350rb.dtsi>
+#include "gd32f350r_eval-pinctrl.dtsi"
+
+/ {
+	model = "GigaDevice GD32F350R Evaluation Kit";
+	compatible = "gd,gd32f350r-eval";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};

boards/arm/gd32f350r_eval/gd32f350r_eval.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2021 BrainCO Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: gd32f350r_eval
+name: GigaDevice GD32F350R Evaluation Kit
+type: mcu
+arch: arm
+ram: 16
+flash: 128
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools

boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_GD32F3X0=y
+CONFIG_SOC_GD32F350=y
+CONFIG_BOARD_GD32F350R_EVAL=y
+
+CONFIG_CORTEX_M_SYSTICK=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

boards/arm/gd32f350r_eval/support/openocd.cfg

@@ -0,0 +1,24 @@
+# Copyright (c) 2021, ATL-Electronics
+# Copyright (c) 2021, BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+source [find interface/cmsis-dap.cfg]
+transport select swd
+
+set CHIPNAME gd32f350rb
+set CPUTAPID 0x790007a3
+
+source [find target/stm32f3x.cfg]
+
+reset_config trst_and_srst separate
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}

drivers/pinctrl/pinctrl_gd32_af.c

@@ -5,6 +5,7 @@
  */
 
 #include <drivers/pinctrl.h>
+#include <soc.h>
 
 BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) &&
 	     (GD32_PUPD_PULLUP == GPIO_PUPD_PULLUP) &&
@@ -16,9 +17,15 @@ BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) &&
 	     "pinctrl output type definitions != HAL definitions");
 
 BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) &&
+#ifdef CONFIG_SOC_SERIES_GD32F3X0
+	     (GD32_OSPEED_10MHZ == GPIO_OSPEED_10MHZ) &&
+	     (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
+#else
 	     (GD32_OSPEED_25MHZ == GPIO_OSPEED_25MHZ) &&
 	     (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
-	     (GD32_OSPEED_200MHZ == GPIO_OSPEED_200MHZ),
+	     (GD32_OSPEED_200MHZ == GPIO_OSPEED_200MHZ) &&
+#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
+	     1U,
 	     "pinctrl output speed definitions != HAL definitions");
 
 /** Utility macro that expands to the GPIO port address if it exists */

drivers/serial/usart_gd32.c

@@ -8,6 +8,12 @@
 #include <errno.h>
 #include <drivers/pinctrl.h>
 #include <drivers/uart.h>
+#include <soc.h>
+
+/* Unify GD32 HAL USART status register name to USART_STAT */
+#ifndef USART_STAT
+#define USART_STAT USART_STAT0
+#endif
 
 struct gd32_usart_config {
 	uint32_t reg;
@@ -120,7 +126,7 @@ static void usart_gd32_poll_out(const struct device *dev, unsigned char c)
 static int usart_gd32_err_check(const struct device *dev)
 {
 	const struct gd32_usart_config *const cfg = dev->config;
-	uint32_t status = USART_STAT0(cfg->reg);
+	uint32_t status = USART_STAT(cfg->reg);
 	int errors = 0;
 
 	if (status & USART_FLAG_ORERR) {

dts/arm/gigadevice/gd32f3x0/gd32f350g6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000{
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(6)>;
+		};
+	};
+};

dts/arm/gigadevice/gd32f3x0/gd32f350rb.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000{
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(16)>;
+		};
+	};
+};