diff --git a/boards/arm/atsaml21_xpro/Kconfig.board b/boards/arm/atsaml21_xpro/Kconfig.board new file mode 100644 index 0000000000000..a06c9e3d20a33 --- /dev/null +++ b/boards/arm/atsaml21_xpro/Kconfig.board @@ -0,0 +1,8 @@ +# SAM L21 Xplained Pro board configuration + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ATSAML21_XPRO + bool "SAM L21 Xplained Pro" + depends on SOC_PART_NUMBER_SAML21J18B diff --git a/boards/arm/atsaml21_xpro/Kconfig.defconfig b/boards/arm/atsaml21_xpro/Kconfig.defconfig new file mode 100644 index 0000000000000..3c35f327bb20e --- /dev/null +++ b/boards/arm/atsaml21_xpro/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SAM L21 Xplained Pro board configuration + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "atsaml21_xpro" + depends on BOARD_ATSAML21_XPRO diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi b/boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi new file mode 100644 index 0000000000000..eb96b72e3393d --- /dev/null +++ b/boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + tcc0_default: tcc0_default { + group1 { + pinmux = ; + }; + }; + + sercom0_default: sercom0_default { + group1 { + pinmux = , + , + ; + }; + }; + + sercom1_default: sercom1_default { + group1 { + pinmux = , + ; + }; + }; + + sercom2_default: sercom2_default { + group1 { + pinmux = , + ; + }; + }; + + sercom3_default: sercom3_default { + group1 { + pinmux = , + ; + }; + }; + + sercom4_default: sercom4_default { + group1 { + pinmux = , + ; + }; + }; + + sercom5_default: sercom5_default { + group1 { + pinmux = , + , + ; + }; + }; +}; diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.dts b/boards/arm/atsaml21_xpro/atsaml21_xpro.dts new file mode 100644 index 0000000000000..29b5e1494586d --- /dev/null +++ b/boards/arm/atsaml21_xpro/atsaml21_xpro.dts @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "atsaml21_xpro-pinctrl.dtsi" + +/ { + model = "SAM L21 Xplained Pro"; + compatible = "atsaml21,xpro", "atmel,saml21j18b", "atmel,saml21"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portb 10 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 0 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom3_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom4_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; +}; diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml b/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml new file mode 100644 index 0000000000000..d2ec2e2349d6d --- /dev/null +++ b/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +identifier: atsaml21_xpro +name: SAM L21 Xplained Pro +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - usb_cdc + - usb_device + - watchdog diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig b/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig new file mode 100644 index 0000000000000..59ac97485c1de --- /dev/null +++ b/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +CONFIG_SOC_SERIES_SAML21=y +CONFIG_SOC_PART_NUMBER_SAML21J18B=y +CONFIG_BOARD_ATSAML21_XPRO=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SAM0=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_GPIO_SAM0=y +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y diff --git a/boards/arm/atsaml21_xpro/board.cmake b/boards/arm/atsaml21_xpro/board.cmake new file mode 100644 index 0000000000000..45c97a245e7ad --- /dev/null +++ b/boards/arm/atsaml21_xpro/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.png b/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.png new file mode 100644 index 0000000000000..043b328feabcc Binary files /dev/null and b/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.png differ diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.png b/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.png new file mode 100644 index 0000000000000..1f6bd108fe65c Binary files /dev/null and b/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.png differ diff --git a/boards/arm/atsaml21_xpro/doc/index.rst b/boards/arm/atsaml21_xpro/doc/index.rst new file mode 100644 index 0000000000000..783a484448805 --- /dev/null +++ b/boards/arm/atsaml21_xpro/doc/index.rst @@ -0,0 +1,200 @@ + .. _atsaml21_xpro: + +SAM L21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM L21 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM L21 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsaml21-xpro.png + :width: 500px + :align: center + :alt: ATSAML21-XPRO + +Hardware +******** + +- ATSAML21J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The atsaml21_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +``boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig``. + +Pin Mapping +=========== + +The SAM L21 Xplained Pro evaluation kit has 2 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `SAM L21 Family Datasheet`_ and the `SAM L21 +Xplained Pro Schematic`_. + +.. image:: img/atsaml21-xpro-pinout.png + :width: 500px + :align: center + :alt: ATSAML21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 SPI MISO : PA04 +- SERCOM0 SPI MOSI : PA06 +- SERCOM0 SPI SCK : PA07 +- SERCOM1 USART TX : PA18 +- SERCOM1 USART RX : PA19 +- SERCOM2 I2C SDA : PA08 +- SERCOM2 I2C SCL : PA09 +- SERCOM3 USART TX : PA22 +- SERCOM3 USART RX : PA23 +- SERCOM4 USART TX : PB08 +- SERCOM4 USART RX : PB09 +- SERCOM5 SPI MISO : PB16 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- USB DP : PA25 +- USB DM : PA24 +- GPIO SPI CS : PB17 +- GPIO/PWM LED0 : PB10 + +System Clock +============ + +The SAML21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAML21 MCU has six SERCOM based USARTs with two configured as USARTs in +this BSP. SERCOM3 is the default Zephyr console. + +- SERCOM1 115200 8n1 - connected to EXT2 and EXT3 +- SERCOM3 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) +- SERCOM4 115200 8n1 - connected to EXT1 + +PWM +=== + +The SAML21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM0 - connected to EXT1 +- SERCOM5 - connected to EXT2 and EXT3 + +Programming and Debugging +************************* + +The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAML21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsaml21_xpro + :goals: build + :compact: + +#. Connect the SAM L21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsaml21_xpro + :goals: flash + :compact: + + You should see "Hello World! atsaml21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM L21 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAML21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsaml21_xpro/support/openocd.cfg b/boards/arm/atsaml21_xpro/support/openocd.cfg new file mode 100644 index 0000000000000..062a3c50addad --- /dev/null +++ b/boards/arm/atsaml21_xpro/support/openocd.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME at91saml21j18 +set ENDIAN little +set CPUTAPID 0x0bc11477 + +source [find target/at91samdXX.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arm/atsamr34_xpro/Kconfig.board b/boards/arm/atsamr34_xpro/Kconfig.board new file mode 100644 index 0000000000000..d586efcbc7e7a --- /dev/null +++ b/boards/arm/atsamr34_xpro/Kconfig.board @@ -0,0 +1,8 @@ +# SAM R34 Xplained Pro board configuration + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ATSAMR34_XPRO + bool "SAM R34 Xplained Pro" + depends on SOC_PART_NUMBER_SAMR34J18B diff --git a/boards/arm/atsamr34_xpro/Kconfig.defconfig b/boards/arm/atsamr34_xpro/Kconfig.defconfig new file mode 100644 index 0000000000000..e327820655a02 --- /dev/null +++ b/boards/arm/atsamr34_xpro/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SAM R34 Xplained Pro board configuration + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "atsamr34_xpro" + depends on BOARD_ATSAMR34_XPRO diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi b/boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi new file mode 100644 index 0000000000000..cee83fd2c85ed --- /dev/null +++ b/boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + tcc0_default: tcc0_default { + group1 { + pinmux = ; + }; + }; + + sercom0_default: sercom0_default { + group1 { + pinmux = , + ; + }; + }; + + sercom1_default: sercom1_default { + group1 { + pinmux = , + ; + }; + }; + + sercom4_default: sercom4_default { + group1 { + pinmux = , + , + , + ; + }; + }; + + sercom5_default: sercom5_default { + group1 { + pinmux = , + , + ; + }; + }; +}; diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.dts b/boards/arm/atsamr34_xpro/atsamr34_xpro.dts new file mode 100644 index 0000000000000..7620e18022295 --- /dev/null +++ b/boards/arm/atsamr34_xpro/atsamr34_xpro.dts @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "atsamr34_xpro-pinctrl.dtsi" + +/ { + model = "SAM R34 Xplained Pro"; + compatible = "atsamr34,xpro", "atmel,samr34j18b", "atmel,samr34"; + + chosen { + zephyr,console = &sercom0; + zephyr,shell-uart = &sercom0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 19 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 3 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +/* SERCOM4 is used for the internal LoRa radio */ +&sercom4 { + status = "okay"; + + pinctrl-0 = <&sercom4_default>; + pinctrl-names = "default"; +}; +&lora { + tcxo-power-gpios = <&porta 9 GPIO_ACTIVE_HIGH>; /* TCXO_PWR */ + tcxo-power-startup-delay-ms = <5>; + rfi-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ + rfo-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; +}; diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml b/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml new file mode 100644 index 0000000000000..706734e36011b --- /dev/null +++ b/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +identifier: atsamr34_xpro +name: SAM R34 Xplained Pro +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - usb_cdc + - usb_device + - watchdog diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig b/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig new file mode 100644 index 0000000000000..18e081418c0b3 --- /dev/null +++ b/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +CONFIG_SOC_SERIES_SAMR34=y +CONFIG_SOC_PART_NUMBER_SAMR34J18B=y +CONFIG_BOARD_ATSAMR34_XPRO=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SAM0=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_GPIO_SAM0=y +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y diff --git a/boards/arm/atsamr34_xpro/board.cmake b/boards/arm/atsamr34_xpro/board.cmake new file mode 100644 index 0000000000000..45c97a245e7ad --- /dev/null +++ b/boards/arm/atsamr34_xpro/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.png b/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.png new file mode 100644 index 0000000000000..0818688ef96a1 Binary files /dev/null and b/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.png differ diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.png b/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.png new file mode 100644 index 0000000000000..04e06ee89f650 Binary files /dev/null and b/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.png differ diff --git a/boards/arm/atsamr34_xpro/doc/index.rst b/boards/arm/atsamr34_xpro/doc/index.rst new file mode 100644 index 0000000000000..56879c364dfbf --- /dev/null +++ b/boards/arm/atsamr34_xpro/doc/index.rst @@ -0,0 +1,220 @@ + .. _atsamr34_xpro: + +SAM R34 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM R34 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM R34 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP), +including both a SAML21 die, and a Semtech SX1276 LoRa radio die. + +This board is also referred to as DM320111. + +.. image:: img/atsamr34-xpro.png + :width: 500px + :align: center + :alt: ATSAMR34-XPRO + +Hardware +******** + +- ATSAMR34J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The atsamr34_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +The following hardware features are supported by Zephyr, but not yet fully +supported by the SOC: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - LoRa Radio + - on-chip + - Internal SX1276 LoRa Radio + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +``boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig``. + +Pin Mapping +=========== + +The SAM R34 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `SAM R34 Family Datasheet`_ and the `SAM R34 +Xplained Pro Schematic`_. + +.. image:: img/atsamr34-xpro-pinout.png + :width: 500px + :align: center + :alt: ATSAMR34-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 UART TX : PA04 +- SERCOM0 UART RX : PA05 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM4 SPI MISO : PC19 +- SERCOM4 SPI MOSI : PB30 +- SERCOM4 SPI SCK : PC18 +- SERCOM4 GPIO CS : PB31 +- SERCOM5 SPI MISO : PB02 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- SERCOM5 GPIO CS0 : PA23 +- SERCOM5 GPIO CS1 : PA14 +- USB DP : PA25 +- USB DM : PA24 +- GPIO/PWM LED0 : PA19 + +System Clock +============ + +The SAMR34 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMR34 MCU has six SERCOM based USARTs with one configured as USART in +this BSP. SERCOM0 is the default Zephyr console. + +- SERCOM0 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMR34 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM4 - connected to the internal LoRa radio +- SERCOM5 - connected to EXT1 and EXT3 + +Programming and Debugging +************************* + +The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMR34 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsamr34_xpro + :goals: build + :compact: + +#. Connect the SAM R34 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsamr34_xpro + :goals: flash + :compact: + + You should see "Hello World! atsamr34_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/dm320111 + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM R34 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-R34-R35-Low-Power-LoRa-Sub-GHz-SiP-Data-Sheet-DS70005356C.pdf + +.. _SAM R34 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/Secure/en/DeviceDoc/SAMR34_SiP_Reference_Design_Package_V3.0.exe + +.. _Semtech SX1276: + https://www.semtech.com/products/wireless-rf/lora-transceivers/sx1276 diff --git a/boards/arm/atsamr34_xpro/support/openocd.cfg b/boards/arm/atsamr34_xpro/support/openocd.cfg new file mode 100644 index 0000000000000..2e7f31036c7ee --- /dev/null +++ b/boards/arm/atsamr34_xpro/support/openocd.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME at91samr34j18 +set ENDIAN little +set CPUTAPID 0x0bc11477 + +source [find target/at91samdXX.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/drivers/adc/adc_sam0.c b/drivers/adc/adc_sam0.c index 7ea7130b708b2..d09379a384f35 100644 --- a/drivers/adc/adc_sam0.c +++ b/drivers/adc/adc_sam0.c @@ -160,8 +160,16 @@ static int adc_sam0_channel_setup(const struct device *dev, return -EINVAL; } if (adc->REFCTRL.reg != refctrl) { +#ifdef ADC_SAM0_REFERENCE_ENABLE_PROTECTED + adc->CTRLA.bit.ENABLE = 0; + wait_synchronization(adc); +#endif adc->REFCTRL.reg = refctrl; wait_synchronization(adc); +#ifdef ADC_SAM0_REFERENCE_ENABLE_PROTECTED + adc->CTRLA.bit.ENABLE = 1; + wait_synchronization(adc); +#endif #ifdef ADC_SAM0_REFERENCE_GLITCH struct adc_sam0_data *data = dev->data; diff --git a/dts/arm/atmel/saml21.dtsi b/dts/arm/atmel/saml21.dtsi new file mode 100644 index 0000000000000..335ffe1bb2798 --- /dev/null +++ b/dts/arm/atmel/saml21.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + usb0: usb@41000000 { + compatible = "atmel,sam0-usb"; + status = "disabled"; + reg = <0x41000000 0x1000>; + interrupts = <6 0>; + num-bidir-endpoints = <8>; + label = "USB0"; + }; + + dmac: dmac@44000400 { + compatible = "atmel,sam0-dmac"; + reg = <0x44000400 0x50>; + interrupts = <5 0>; + label = "DMA_0"; + #dma-cells = <2>; + }; + + tcc0: tcc@42001400 { + compatible = "atmel,sam0-tcc"; + reg = <0x42001400 0x80>; + interrupts = <14 0>; + label = "TCC_0"; + clocks = <&gclk 25>, <&mclk 0x1c 5>; + clock-names = "GCLK", "MCLK"; + + channels = <4>; + counter-size = <24>; + }; + + tcc1: tcc@42001800 { + compatible = "atmel,sam0-tcc"; + reg = <0x42001800 0x80>; + interrupts = <15 0>; + label = "TCC_1"; + clocks = <&gclk 25>, <&mclk 0x1c 6>; + clock-names = "GCLK", "MCLK"; + + channels = <4>; + counter-size = <24>; + }; + + tcc2: tcc@42001c00 { + compatible = "atmel,sam0-tcc"; + reg = <0x42001C00 0x80>; + interrupts = <16 0>; + label = "TCC_2"; + clocks = <&gclk 26>, <&mclk 0x1c 7>; + clock-names = "GCLK", "MCLK"; + + channels = <2>; + counter-size = <16>; + }; + }; +}; + +&dac { + interrupts = <24 0>; + clocks = <&gclk 32>, <&mclk 0x1c 12>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom0 { + interrupts = <8 0>; + clocks = <&gclk 18>, <&mclk 0x1c 0>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom1 { + interrupts = <9 0>; + clocks = <&gclk 19>, <&mclk 0x1c 1>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom2 { + interrupts = <10 0>; + clocks = <&gclk 20>, <&mclk 0x1c 2>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom3 { + interrupts = <11 0>; + clocks = <&gclk 21>, <&mclk 0x1c 3>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom4 { + interrupts = <12 0>; + clocks = <&gclk 22>, <&mclk 0x1c 4>; + clock-names = "GCLK", "MCLK"; +}; + +&sercom5 { + interrupts = <13 0>; + clocks = <&gclk 24>, <&mclk 0x20 1>; + clock-names = "GCLK", "MCLK"; +}; + +&tc4 { + interrupts = <21 0>; + clocks = <&gclk 29>, <&mclk 0x20 2>; + clock-names = "GCLK", "MCLK"; +}; + +&adc { + interrupts = <22 0>; + interrupt-names = "resrdy"; + clocks = <&gclk 30>, <&mclk 0x20 3>; + clock-names = "GCLK", "MCLK"; +}; diff --git a/dts/arm/atmel/saml2x.dtsi b/dts/arm/atmel/saml2x.dtsi new file mode 100644 index 0000000000000..808372bdeda2b --- /dev/null +++ b/dts/arm/atmel/saml2x.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + watchdog0 = &wdog; + }; + + chosen { + zephyr,flash-controller = &nvmctrl; + zephyr,entropy = &trng; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m0+"; + reg = <0>; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x8000>; + }; + + id: device_id@80a00c { + compatible = "atmel,sam0-id"; + reg = <0x0080A00C 0x4>, + <0x0080A040 0x4>, + <0x0080A044 0x4>, + <0x0080A048 0x4>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + compatible = "atmel,sam0-nvmctrl"; + label = "FLASH_CTRL"; + reg = <0x41004000 0x22>; + interrupts = <4 0>; + lock-regions = <16>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + reg = <0 0x40000>; + write-block-size = <4>; + }; + }; + + pm: pm@40000400 { + compatible = "atmel,saml2x-pm"; + reg = <0x40000400 0x400>; + interrupts = <0 0>; + #clock-cells = <2>; + }; + + mclk: mclk@40000400 { + compatible = "atmel,saml2x-mclk"; + reg = <0x40000400 0x400>; + #clock-cells = <2>; + }; + + gclk: gclk@40001800 { + compatible = "atmel,saml2x-gclk"; + reg = <0x40001800 0x400>; + #clock-cells = <1>; + }; + + dmac: dmac@44000400 { + compatible = "atmel,sam0-dmac"; + reg = <0x44000400 0x400>; + interrupts = <5 0>; + label = "DMA_0"; + #dma-cells = <2>; + }; + + eic: eic@40002400 { + compatible = "atmel,sam0-eic"; + reg = <0x40002400 0x24>; + interrupts = <3 0>; + label = "EIC"; + }; + + wdog: watchdog@40001c00 { + compatible = "atmel,sam0-watchdog"; + reg = <0x40001c00 0x0c>; + interrupts = <1 0>; + label = "WATCHDOG_0"; + }; + + sercom0: sercom@42000000 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000000 0x40>; + status = "disabled"; + label = "SERCOM0"; + }; + + sercom1: sercom@42000400 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000400 0x40>; + status = "disabled"; + label = "SERCOM1"; + }; + + sercom2: sercom@42000800 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000800 0x40>; + status = "disabled"; + label = "SERCOM2"; + }; + + sercom3: sercom@42000c00 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000C00 0x40>; + status = "disabled"; + label = "SERCOM3"; + }; + + sercom4: sercom@42001000 { + compatible = "atmel,sam0-sercom"; + reg = <0x42001000 0x40>; + status = "disabled"; + label = "SERCOM4"; + }; + + sercom5: sercom@43000400 { + compatible = "atmel,sam0-sercom"; + reg = <0x43000400 0x40>; + status = "disabled"; + label = "SERCOM5"; + }; + + tc4: tc@43000800 { + compatible = "atmel,sam0-tc32"; + reg = <0x43000800 0x34>; + label = "TIMER_4"; + }; + + pinctrl: pinctrl@40002800 { + compatible = "atmel,sam0-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40002800 0x40002800 0x100>; + + porta: gpio@40002800 { + compatible = "atmel,sam0-gpio"; + reg = <0x40002800 0x80>; + label = "PORTA"; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + + }; + + portb: gpio@40002880 { + compatible = "atmel,sam0-gpio"; + reg = <0x40002880 0x80>; + label = "PORTB"; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + }; + }; + + rtc: rtc@40002000 { + compatible = "atmel,sam0-rtc"; + reg = <0x40002000 0x1c>; + interrupts = <2 0>; + clock-generator = <0>; + status = "disabled"; + label = "RTC"; + }; + + adc: adc@43000c00 { + compatible = "atmel,sam0-adc"; + reg = <0x43000c00 0x30>; + label = "ADC_0"; + + /* + * 16 MHz max, so clock it with the + * 48 MHz DFLL / 2 / 2 = 12 MHz + */ + gclk = <3>; + prescaler = <2>; + #io-channel-cells = <1>; + }; + + dac: dac@42003000 { + compatible = "atmel,sam0-dac"; + status = "disabled"; + reg = <0x42003000 0x1a>; + label = "DAC_0"; + #io-channel-cells = <0>; + }; + + trng: random@42003800 { + compatible = "atmel,sam-trng"; + reg = <0x42003800 0x24>; + peripheral-id = <0>; + interrupts = <27 0>; + label = "ENTROPY_0"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/atmel/samr34.dtsi b/dts/arm/atmel/samr34.dtsi new file mode 100644 index 0000000000000..05b1378769c5c --- /dev/null +++ b/dts/arm/atmel/samr34.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "saml21.dtsi" + +/ { + aliases { + lora0 = &lora; + }; + + soc { + pinctrl@40002800 { + ranges = <0x40002800 0x40002800 0x180>; + + portc: gpio@40002900 { + compatible = "atmel,sam0-gpio"; + reg = <0x40002900 0x80>; + label = "PORTC"; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + }; + }; + }; +}; + +/delete-node/ &dac; + +&sercom4 { + /* SERCOM4 is used to interface with the internal LoRa radio */ + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + lora: sx1276@0 { + compatible = "semtech,sx1276"; + reg = <0>; + label = "SX1276"; + reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; /* nRST */ + dio-gpios = + <&portb 16 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 */ + <&porta 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 */ + <&porta 12 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 */ + <&portb 17 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 */ + <&porta 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 */ + <&portb 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 */ + spi-max-frequency = ; + }; +}; diff --git a/dts/arm/atmel/samr35.dtsi b/dts/arm/atmel/samr35.dtsi new file mode 100644 index 0000000000000..6bf772b71bb91 --- /dev/null +++ b/dts/arm/atmel/samr35.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/delete-node/ &usb0; diff --git a/dts/bindings/clock/atmel,saml2x-gclk.yaml b/dts/bindings/clock/atmel,saml2x-gclk.yaml new file mode 100644 index 0000000000000..9adcb5322065f --- /dev/null +++ b/dts/bindings/clock/atmel,saml2x-gclk.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAML2x Generic Clock Controller (GCLK) + +compatible: "atmel,saml2x-gclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - periph_ch diff --git a/dts/bindings/clock/atmel,saml2x-mclk.yaml b/dts/bindings/clock/atmel,saml2x-mclk.yaml new file mode 100644 index 0000000000000..e2a4eefcc8189 --- /dev/null +++ b/dts/bindings/clock/atmel,saml2x-mclk.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAML2x Generic Clock Controller (MCLK) + +compatible: "atmel,saml2x-mclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - offset + - bit diff --git a/samples/drivers/adc/boards/atsaml21_xpro.overlay b/samples/drivers/adc/boards/atsaml21_xpro.overlay new file mode 100644 index 0000000000000..94e70414f3a0f --- /dev/null +++ b/samples/drivers/adc/boards/atsaml21_xpro.overlay @@ -0,0 +1,39 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Argentum Systems Ltd. + */ + +#include + +/ { + zephyr,user { + /* EXT-1, pin 3 ADC(+) */ + io-channels = <&adc 13>; + }; +}; + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = ; + }; + }; +}; + +&adc { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + + channel@13 { + reg = <13>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = <13>; + }; +}; diff --git a/samples/drivers/adc/boards/atsamr34_xpro.overlay b/samples/drivers/adc/boards/atsamr34_xpro.overlay new file mode 100644 index 0000000000000..5bb568b683a2d --- /dev/null +++ b/samples/drivers/adc/boards/atsamr34_xpro.overlay @@ -0,0 +1,39 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Argentum Systems Ltd. + */ + +#include + +/ { + zephyr,user { + /* EXT-1, pin 3 ADC(+) */ + io-channels = <&adc 6>; + }; +}; + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = ; + }; + }; +}; + +&adc { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + + channel@6 { + reg = <6>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = <6>; + }; +}; diff --git a/soc/arm/atmel_sam0/Kconfig b/soc/arm/atmel_sam0/Kconfig index 52545825ce39c..e8e704fee30b7 100644 --- a/soc/arm/atmel_sam0/Kconfig +++ b/soc/arm/atmel_sam0/Kconfig @@ -13,6 +13,7 @@ config SOC_FAMILY string default "atmel_sam0" +source "soc/arm/atmel_sam0/common/Kconfig.saml2x" source "soc/arm/atmel_sam0/common/Kconfig.samd2x" source "soc/arm/atmel_sam0/common/Kconfig.samd5x" source "soc/arm/atmel_sam0/*/Kconfig.soc" diff --git a/soc/arm/atmel_sam0/common/CMakeLists.txt b/soc/arm/atmel_sam0/common/CMakeLists.txt index 832a0e464eddb..4c2583792b1d3 100644 --- a/soc/arm/atmel_sam0/common/CMakeLists.txt +++ b/soc/arm/atmel_sam0/common/CMakeLists.txt @@ -10,6 +10,9 @@ zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAML21 soc_saml2x.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR34 soc_saml2x.c soc_samr34.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR35 soc_saml2x.c soc_samr34.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD51 soc_samd5x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME51 soc_samd5x.c) diff --git a/soc/arm/atmel_sam0/common/Kconfig.saml2x b/soc/arm/atmel_sam0/common/Kconfig.saml2x new file mode 100644 index 0000000000000..ae310e0789e19 --- /dev/null +++ b/soc/arm/atmel_sam0/common/Kconfig.saml2x @@ -0,0 +1,74 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 + +config SOC_ATMEL_SAML_DEBUG_PAUSE + bool "Insert a pause at boot, to allow a debugger to attach" + default y + help + Issues have been observed while attempting to attach a debugger. + These can be mitigated by inserting a small delay during the early boot + sequence, before the system clock is configured. + + If you ever intend to attach a debugger, say y. + If you are confident that you will never attach a debugger to the + resulting binary, or require the best possible boot time, say n. + +config SOC_ATMEL_SAML_OSC32K + bool "Internal 32.768 kHz RC oscillator" + help + Eable the internal 32.768 kHz RC oscillator at startup. + This can then be selected as the main clock reference for the SOC. + +config SOC_ATMEL_SAML_XOSC32K + bool "External 32.768 kHz clock source" + help + Enable the external 32.768 kHz cloud source at startup. + This can then be selected as the main clock reference for the SOC. + +config SOC_ATMEL_SAML_XOSC32K_CRYSTAL + bool "External 32.768 kHz clock is a crystal oscillator" + depends on SOC_ATMEL_SAML_XOSC32K + default y + help + Enable the crystal oscillator (if disabled, expect a clock signal on + XIN32). + +config SOC_ATMEL_SAML_OSC16M + bool "Internal 16 MHz RC oscillator" + help + Enable the internal 16 MHz RC oscillator at startup. + This can then be selected as the main clock reference for the SOC. + +# NOTE: XOSC is not currently supported + + +choice + prompt "Main clock reference" + default SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + help + Selects the clock that will be used for the DFLL48M's reference. + Main clocks, such as the CPU and AHB clocks will be derived from + DFLL48M configured for 48 MHz. + +config SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + bool "OPENLOOP" + help + Note, this mode can only be used with an LDO regulator. + +config SOC_ATMEL_SAML_OSC32K_AS_MAIN + bool "OSC32K" + depends on SOC_ATMEL_SAML_OSC32K + +config SOC_ATMEL_SAML_XOSC32K_AS_MAIN + bool "XOSC32K" + depends on SOC_ATMEL_SAML_XOSC32K + +config SOC_ATMEL_SAML_OSC16M_AS_MAIN + bool "OSC16M" + depends on SOC_ATMEL_SAML_OSC16M + +endchoice + +endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/arm/atmel_sam0/common/soc_saml2x.c new file mode 100644 index 0000000000000..3ba38392f96bf --- /dev/null +++ b/soc/arm/atmel_sam0/common/soc_saml2x.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAML MCU series initialization code + */ + +#include +#include +#include +#include +#include +#include + +/* the SAML21 currently operates only in Performance Level 2... sleep + * and low-power operation are not currently supported by the BSP + * + * the CPU clock will be configured to 48 MHz, and run via DFLL48M. + * + * Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN + * + * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz + * GCLK Gen 1 -> DFLL48M (variable) + * GCLK Gen 2 -> USB @ 48 MHz + * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral) + */ + +static inline void gclk_reset(void) +{ + GCLK->CTRLA.bit.SWRST = 1; + while (GCLK->SYNCBUSY.bit.SWRST) { + } + + /* by default, OSC16M will be enabled at 4 MHz, and the CPU will + * run from it. to permit initialization, the CPU is temporarily + * clocked from OSCULP32K, and OSC16M is disabled + */ + GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val; + OSCCTRL->OSC16MCTRL.bit.ENABLE = 0; +} + +#if !CONFIG_SOC_ATMEL_SAML_OSC32K +#define osc32k_init() +#else +static inline void osc32k_init(void) +{ + uint32_t cal; + + /* OSC32KCAL is in NVMCTRL_OTP5[12:6] */ + cal = *((uint32_t *)NVMCTRL_OTP5); + cal >>= 6; + cal &= (1 << 7) - 1; + + OSC32KCTRL->OSC32K.reg = 0 + | OSC32KCTRL_OSC32K_CALIB(cal) + | OSC32KCTRL_OSC32K_STARTUP(0x5) /* 34 cycles / ~1.038ms */ + | !OSC32KCTRL_OSC32K_ONDEMAND + | OSC32KCTRL_OSC32K_RUNSTDBY + | OSC32KCTRL_OSC32K_EN32K + | OSC32KCTRL_OSC32K_ENABLE; + + /* wait for ready */ + while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) { + } +} +#endif + +#if !CONFIG_SOC_ATMEL_SAML_XOSC32K +#define xosc32k_init() +#else +static inline void xosc32k_init(void) +{ + OSC32KCTRL->XOSC32K.reg = 0 + | OSC32KCTRL_XOSC32K_STARTUP(0x1) /* 4096 cycles / ~0.13s */ + | !OSC32KCTRL_XOSC32K_ONDEMAND + | OSC32KCTRL_XOSC32K_RUNSTDBY + | OSC32KCTRL_XOSC32K_EN32K +#if CONFIG_SOC_ATMEL_SAML_XOSC32K_CRYSTAL + | OSC32KCTRL_XOSC32K_XTALEN +#endif + | OSC32KCTRL_XOSC32K_ENABLE; + + /* wait for ready */ + while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) { + } +} +#endif + +#if !CONFIG_SOC_ATMEL_SAML_OSC16M +#define osc16m_init() +#else +static inline void osc16m_init(void) +{ + OSCCTRL->OSC16MCTRL.reg = 0 + | !OSCCTRL_OSC16MCTRL_ONDEMAND + | OSCCTRL_OSC16MCTRL_RUNSTDBY + | OSCCTRL_OSC16MCTRL_FSEL_16 + | OSCCTRL_OSC16MCTRL_ENABLE; + + /* wait for ready */ + while (!OSCCTRL->STATUS.bit.OSC16MRDY) { + } +} +#endif + +/* TODO: use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC ?? */ +static inline void dfll48m_init(void) +{ + uint32_t cal; + + /* setup the reference clock (if any) */ + GCLK->GENCTRL[1].reg = 0 +#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN + | GCLK_GENCTRL_SRC_OSC32K +#elif CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN + | GCLK_GENCTRL_SRC_XOSC32K +#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN + /* configure Fout = Fin / 2^(DIV+1) = 31.25 kHz + * Fgclk_dfll48m_ref max is 33 kHz + */ + | GCLK_GENCTRL_DIV(8) + | GCLK_GENCTRL_DIVSEL + | GCLK_GENCTRL_SRC_OSC16M +#endif +#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + | GCLK_GENCTRL_RUNSTDBY + | GCLK_GENCTRL_GENEN +#endif + ; + +#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + /* configure and enable the generator & peripheral channel */ + GCLK->PCHCTRL[0].reg = 0 + | GCLK_PCHCTRL_CHEN + | GCLK_PCHCTRL_GEN_GCLK1; +#endif + + /* --- */ + + /* if the target frequency is 48 MHz, then the calibration value can be used to + * decrease the time until the coarse lock is acquired. this is loaded from + * NVMCTRL_OTP5[31:26] + */ + cal = *((uint32_t *)NVMCTRL_OTP5); + cal >>= 26; + cal &= (1 << 6) - 1; + + OSCCTRL->DFLLCTRL.reg = 0 + | OSCCTRL_DFLLCTRL_QLDIS + | !OSCCTRL_DFLLCTRL_ONDEMAND + | OSCCTRL_DFLLCTRL_RUNSTDBY +#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + | OSCCTRL_DFLLCTRL_MODE +#endif + ; + + OSCCTRL->DFLLVAL.reg = 0 + | OSCCTRL_DFLLVAL_COARSE(cal) + | OSCCTRL_DFLLVAL_FINE(512) /* use 50% */ + ; + + OSCCTRL->DFLLMUL.reg = 0 + /* use 25% of maximum value for the coarse and fine step + * ... I couldn't find details on the inner workings of the DFLL, or any + * example values for these - I have seen others using ~50%. hopefully these + * values will provide a good balance between startup time and overshoot + */ + | OSCCTRL_DFLLMUL_CSTEP(16) + | OSCCTRL_DFLLMUL_FSTEP(256) +#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN || CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN + /* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */ + | OSCCTRL_DFLLMUL_MUL(1465) +#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN + /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 + * a small value can make the DFLL unstable, hence not using the + * 16 MHz source directly + */ + | OSCCTRL_DFLLMUL_MUL(1536) +#endif + ; + + /* --- */ + + /* enable */ + while (!OSCCTRL->STATUS.bit.DFLLRDY) { + } + OSCCTRL->DFLLCTRL.bit.ENABLE = 1; + +#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN + /* wait for ready... note in open loop mode, we won't get a lock */ + while (!OSCCTRL->STATUS.bit.DFLLLCKC || !OSCCTRL->STATUS.bit.DFLLLCKF) { + } +#endif +} + +static inline void flash_waitstates_init(void) +{ + /* PL2, >= 2.7v, 48MHz = 2 wait states */ + NVMCTRL->CTRLB.bit.RWS = 2; +} + +static inline void pm_init(void) +{ + PM->PLCFG.bit.PLDIS = 0; + PM->PLCFG.bit.PLSEL = 2; +} + +static inline void gclk_main_configure(void) +{ + /* finally, switch the CPU over to run from DFLL48M */ + GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val; +} + +#if !CONFIG_ADC_SAM0 +#define gclk_adc_configure() +#else +static inline void gclk_adc_configure(void) +{ + GCLK->GENCTRL[3].reg = 0 + | GCLK_GENCTRL_SRC_DFLL48M + | GCLK_GENCTRL_DIV(2) + | GCLK_GENCTRL_GENEN; +} +#endif + +#if CONFIG_SOC_ATMEL_SAML_DEBUG_PAUSE +static inline void pause_for_debug(void) +{ + /* for some reason, when attempting to flash / debug the target, the operations + * will time out... I suspect this is due to clock configuration, so instead of + * doing this immediately, we defer startup for a while to permit the debugger + * to jump in and interrupt us. ick + */ + for (uint32_t i = 0; i < 10000; i += 1) { + __asm__ volatile ("nop\n"); + } +} +#else +static inline void pause_for_debug(void) {} +#endif + +static int atmel_saml_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + pause_for_debug(); + + gclk_reset(); + osc32k_init(); + xosc32k_init(); + osc16m_init(); + dfll48m_init(); + flash_waitstates_init(); + pm_init(); + gclk_main_configure(); + gclk_adc_configure(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(atmel_saml_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam0/common/soc_samr34.c b/soc/arm/atmel_sam0/common/soc_samr34.c new file mode 100644 index 0000000000000..2fbe25ad62d78 --- /dev/null +++ b/soc/arm/atmel_sam0/common/soc_samr34.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#if !(ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_spi) && CONFIG_SPI_SAM0) +/* When the radio is not in use, it's important that #CS is set high, to avoid + * unexpected behavior and increased current consumption... see Chapter 10 of + * DS70005356C. We also hold the radio in reset. + */ +static int soc_pinconf_init(const struct device *dev) +{ + const struct device *portb = DEVICE_DT_GET(DT_NODELABEL(portb)); + + ARG_UNUSED(dev); + + if (!device_is_ready(portb)) { + return -ENODEV; + } + + gpio_pin_configure(portb, 31, GPIO_OUTPUT_HIGH); + gpio_pin_configure(portb, 15, GPIO_OUTPUT_LOW); + + return 0; +} + +SYS_INIT(soc_pinconf_init, PRE_KERNEL_2, 0); +#endif diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series new file mode 100644 index 0000000000000..23bfcb70262e7 --- /dev/null +++ b/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series @@ -0,0 +1,31 @@ +# Atmel SAML MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAML21 + +config SOC_SERIES + default "saml21" + +config SOC_PART_NUMBER + default "saml21e15b" if SOC_PART_NUMBER_SAML21E15B + default "saml21e16b" if SOC_PART_NUMBER_SAML21E16B + default "saml21e17b" if SOC_PART_NUMBER_SAML21E17B + default "saml21e18b" if SOC_PART_NUMBER_SAML21E18B + default "saml21g16b" if SOC_PART_NUMBER_SAML21G16B + default "saml21g17b" if SOC_PART_NUMBER_SAML21G17B + default "saml21g18b" if SOC_PART_NUMBER_SAML21G18B + default "saml21j16b" if SOC_PART_NUMBER_SAML21J16B + default "saml21j17b" if SOC_PART_NUMBER_SAML21J17B + default "saml21j17bu" if SOC_PART_NUMBER_SAML21J17BU + default "saml21j18b" if SOC_PART_NUMBER_SAML21J18B + default "saml21j18bu" if SOC_PART_NUMBER_SAML21J18BU + +config NUM_IRQS + default 29 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_SERIES_SAML21 diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.series new file mode 100644 index 0000000000000..57ec9b5558eeb --- /dev/null +++ b/soc/arm/atmel_sam0/saml21/Kconfig.series @@ -0,0 +1,15 @@ +# Atmel SAML21 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAML21 + bool "Atmel SAML21 MCU" + select ARM + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_SAM0 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select ASF + help + Enable support for Atmel SAML21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.soc b/soc/arm/atmel_sam0/saml21/Kconfig.soc new file mode 100644 index 0000000000000..f6ab97367a93d --- /dev/null +++ b/soc/arm/atmel_sam0/saml21/Kconfig.soc @@ -0,0 +1,46 @@ +# Atmel SAML MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAML21 MCU Selection" + depends on SOC_SERIES_SAML21 + +config SOC_PART_NUMBER_SAML21E15B + bool "SAML21E15B" + +config SOC_PART_NUMBER_SAML21E16B + bool "SAML21E16B" + +config SOC_PART_NUMBER_SAML21E17B + bool "SAML21E17B" + +config SOC_PART_NUMBER_SAML21E18B + bool "SAML21E18B" + +config SOC_PART_NUMBER_SAML21G16B + bool "SAML21G16B" + +config SOC_PART_NUMBER_SAML21G17B + bool "SAML21G17B" + +config SOC_PART_NUMBER_SAML21G18B + bool "SAML21G18B" + +config SOC_PART_NUMBER_SAML21J16B + bool "SAML21J16B" + +config SOC_PART_NUMBER_SAML21J17B + bool "SAML21J17B" + +config SOC_PART_NUMBER_SAML21J17BU + bool "SAML21J17BU" + +config SOC_PART_NUMBER_SAML21J18B + bool "SAML21J18B" + +config SOC_PART_NUMBER_SAML21J18BU + bool "SAML21J18BU" + +endchoice diff --git a/soc/arm/atmel_sam0/saml21/linker.ld b/soc/arm/atmel_sam0/saml21/linker.ld new file mode 100644 index 0000000000000..5fc02a3533f93 --- /dev/null +++ b/soc/arm/atmel_sam0/saml21/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam0/saml21/soc.h b/soc/arm/atmel_sam0/saml21/soc.h new file mode 100644 index 0000000000000..de6b80dee6107 --- /dev/null +++ b/soc/arm/atmel_sam0/saml21/soc.h @@ -0,0 +1,76 @@ +/* Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ATMEL_SAML_SOC_H_ +#define _ATMEL_SAML_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#if defined(CONFIG_SOC_PART_NUMBER_SAML21E15B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E16B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E17B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E18B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G16B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G17B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G18B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J16B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17BU) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18BU) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _ATMEL_SAML_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series new file mode 100644 index 0000000000000..96ca593b5a9df --- /dev/null +++ b/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series @@ -0,0 +1,22 @@ +# Atmel SAML MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR34 + +config SOC_SERIES + default "samr34" + +config SOC_PART_NUMBER + default "samr34j16b" if SOC_PART_NUMBER_SAMR34J16B + default "samr34j17b" if SOC_PART_NUMBER_SAMR34J17B + default "samr34j18b" if SOC_PART_NUMBER_SAMR34J18B + +config NUM_IRQS + default 23 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_SERIES_SAMR34 diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.series new file mode 100644 index 0000000000000..8e6de6c6fa8bd --- /dev/null +++ b/soc/arm/atmel_sam0/samr34/Kconfig.series @@ -0,0 +1,15 @@ +# Atmel SAMR34 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR34 + bool "Atmel SAMR34 MCU" + select ARM + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_SAM0 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select ASF + help + Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.soc b/soc/arm/atmel_sam0/samr34/Kconfig.soc new file mode 100644 index 0000000000000..088d56b710913 --- /dev/null +++ b/soc/arm/atmel_sam0/samr34/Kconfig.soc @@ -0,0 +1,19 @@ +# Atmel SAMR MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAMR34 MCU Selection" + depends on SOC_SERIES_SAMR34 + +config SOC_PART_NUMBER_SAMR34J16B + bool "SAMR34J16B" + +config SOC_PART_NUMBER_SAMR34J17B + bool "SAMR34J17B" + +config SOC_PART_NUMBER_SAMR34J18B + bool "SAMR34J18B" + +endchoice diff --git a/soc/arm/atmel_sam0/samr34/linker.ld b/soc/arm/atmel_sam0/samr34/linker.ld new file mode 100644 index 0000000000000..5fc02a3533f93 --- /dev/null +++ b/soc/arm/atmel_sam0/samr34/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam0/samr34/soc.h b/soc/arm/atmel_sam0/samr34/soc.h new file mode 100644 index 0000000000000..2da117cf14e57 --- /dev/null +++ b/soc/arm/atmel_sam0/samr34/soc.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ATMEL_SAMR_SOC_H_ +#define _ATMEL_SAMR_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_PART_NUMBER_SAMR34J16B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J17B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series new file mode 100644 index 0000000000000..edc7636d96d6a --- /dev/null +++ b/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series @@ -0,0 +1,22 @@ +# Atmel SAML MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR35 + +config SOC_SERIES + default "samr35" + +config SOC_PART_NUMBER + default "samr35j16b" if SOC_PART_NUMBER_SAMR35J16B + default "samr35j17b" if SOC_PART_NUMBER_SAMR35J17B + default "samr35j18b" if SOC_PART_NUMBER_SAMR35J18B + +config NUM_IRQS + default 23 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.series new file mode 100644 index 0000000000000..cc6aef2200fe2 --- /dev/null +++ b/soc/arm/atmel_sam0/samr35/Kconfig.series @@ -0,0 +1,15 @@ +# Atmel SAMR35 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR35 + bool "Atmel SAMR35 MCU" + select ARM + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_SAM0 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select ASF + help + Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.soc b/soc/arm/atmel_sam0/samr35/Kconfig.soc new file mode 100644 index 0000000000000..ceb95243806ee --- /dev/null +++ b/soc/arm/atmel_sam0/samr35/Kconfig.soc @@ -0,0 +1,19 @@ +# Atmel SAMR MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAM35 MCU Selection" + depends on SOC_SERIES_SAMR35 + +config SOC_PART_NUMBER_SAMR35J16B + bool "SAMR35J16B" + +config SOC_PART_NUMBER_SAMR35J17B + bool "SAMR35J17B" + +config SOC_PART_NUMBER_SAMR35J18B + bool "SAMR35J18B" + +endchoice diff --git a/soc/arm/atmel_sam0/samr35/linker.ld b/soc/arm/atmel_sam0/samr35/linker.ld new file mode 100644 index 0000000000000..5fc02a3533f93 --- /dev/null +++ b/soc/arm/atmel_sam0/samr35/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam0/samr35/soc.h b/soc/arm/atmel_sam0/samr35/soc.h new file mode 100644 index 0000000000000..db3fd85b865b0 --- /dev/null +++ b/soc/arm/atmel_sam0/samr35/soc.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ATMEL_SAMR_SOC_H_ +#define _ATMEL_SAMR_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_PART_NUMBER_SAMR35J16B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J17B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay new file mode 100644 index 0000000000000..42c6b298e8b6f --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Argentum Systems Ltd. + */ + +&dmac { + status = "okay"; +}; + +&sercom1 { + /* internally loop-back Tx and Rx on PAD0 */ + rxpo = <0>; + txpo = <0>; + + /* configure DMA channels for async operation */ + dmas = <&dmac 0 0x03>, <&dmac 1 0x04>; + dma-names = "rx", "tx"; +}; + +&sercom3 { + /* configure DMA channels for async operation */ + dmas = <&dmac 10 0x07>, <&dmac 11 0x08>; + dma-names = "rx", "tx"; +}; + +&sercom4 { + status = "disabled"; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay new file mode 100644 index 0000000000000..0e7a6c43b62e0 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay @@ -0,0 +1,40 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Argentum Systems Ltd. + */ + +&dmac { + status = "okay"; +}; + +&sercom0 { + /* configure DMA channels for async operation */ + dmas = <&dmac 0 0x01>, <&dmac 1 0x02>; + dma-names = "rx", "tx"; +}; + +&pinctrl { + sercom2_default: sercom2_default { + group1 { + pinmux = ; + }; + }; +}; +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + + /* internally loop-back Tx and Rx on PAD0 */ + rxpo = <0>; + txpo = <0>; + + /* configure DMA channels for async operation */ + dmas = <&dmac 0 0x05>, <&dmac 1 0x06>; + dma-names = "rx", "tx"; + + /* PAD0 must be configured to allow working loop-back */ + pinctrl-0 = <&sercom2_default>; + pinctrl-names = "default"; +}; diff --git a/tests/drivers/uart/uart_async_api/src/test_uart.h b/tests/drivers/uart/uart_async_api/src/test_uart.h index 5e943a5a94677..a73266fda8c3b 100644 --- a/tests/drivers/uart/uart_async_api/src/test_uart.h +++ b/tests/drivers/uart/uart_async_api/src/test_uart.h @@ -32,6 +32,10 @@ #define UART_DEVICE_DEV DT_NODELABEL(sercom1) #elif defined(CONFIG_BOARD_ATSAMR21_XPRO) #define UART_DEVICE_DEV DT_NODELABEL(sercom3) +#elif defined(CONFIG_BOARD_ATSAML21_XPRO) +#define UART_DEVICE_NAME DT_NODELABEL(sercom1) +#elif defined(CONFIG_BOARD_ATSAMR34_XPRO) +#define UART_DEVICE_NAME DT_NODELABEL(sercom2) #elif defined(CONFIG_BOARD_ATSAME54_XPRO) #define UART_DEVICE_DEV DT_NODELABEL(sercom1) #elif defined(CONFIG_BOARD_NUCLEO_F103RB) || \ diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index c7d1a066f0cec..1da2779776949 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -2,7 +2,7 @@ common: platform_exclude: seeeduino_xiao serpente arduino_nano_33_iot atsamr21_xpro adafruit_itsybitsy_m4_express atsame54_xpro atsamd21_xpro adafruit_trinket_m0 arduino_nano_33_iot arduino_zero atsamd21_xpro adafruit_feather_m0_basic_proto - arduino_mkrzero + arduino_mkrzero atsaml21_xpro atsamr34_xpro tests: drivers.uart.async_api: