From fd1d721f9e6c808524169b7fb525da4975d7d4bf Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 14:53:09 +0800 Subject: [PATCH 01/10] dts: pinctrl: add dts binding for nxp mcux rt1xxx add dts binding dedicated for mcux iomuxc settings Signed-off-by: Hake Huang --- dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml diff --git a/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml new file mode 100644 index 0000000000000..b679a7d6a1d1d --- /dev/null +++ b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml @@ -0,0 +1,122 @@ +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree, + + +compatible: "nxp,mcux-rt-pinctrl" + +include: + - name: base.yaml + - name: pincfg-node-group.yaml + child-binding: + property-allowlist: + drive-open-drain + +properties: + reg: + required: true + +properties: + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 + +child-binding: + description: | + MCUX RT pin controller pin configuration state nodes. + child-binding: + description: | + MCUX RT pin controller pin configuration group. + properties: + pinmux: + required: true + type: array + description: | + An array of pins sharing the same group properties. The pins should + be defined using pre-defined macros. + nxp,mcux_hys: + required: false + type: boolean + description: | + Hyst. Enable Field + nxp,mcux_pus: + required: false + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + description: | + 00 PUS_0_100K_Ohm_Pull_Down — 100K Ohm Pull Down + 01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up + 10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up + 11 PUS_3_22K_Ohm_Pull_Up — 22K Ohm Pull Up + nxp,mcux_pue: + required: false + type: int + default: 0 + enum: + - 0 + - 1 + description: | + 0 PUE_0_Keeper — Keeper + 1 PUE_1_Pull — Pull + nxp,mcux_pke: + required: false + type: boolean + description: | + 0 PKE_0_Pull_Keeper_Disabled — Pull/Keeper Disabled + 1 PKE_1_Pull_Keeper_Enabled — Pull/Keeper Enabled + nxp,mcux_speed: + required: false + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + description: | + 00 SPEED_0_low_50MHz_ — low(50MHz) + 01 SPEED_1_medium_100MHz_ — medium(100MHz) + 10 SPEED_2_medium_100MHz_ — medium(100MHz) + 11 SPEED_3_max_200MHz_ — max(200MHz) + nxp,mcux_dse: + required: false + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + description: | + 000 DSE_0_output_driver_disabled_ — output driver disabled + 001 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ — R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 010 DSE_2_R0_2 — R0/2 + 011 DSE_3_R0_3 — R0/3 + 100 DSE_4_R0_4 — R0/4 + 101 DSE_5_R0_5 — R0/5 + 110 DSE_6_R0_6 — R0/6 + 111 DSE_7_R0_7 — R0/7 + nxp,mcux_sre: + required: false + type: int + default: 0 + enum: + - 0 + - 1 + description: | + 0 SRE_0_Slow_Slew_Rate — Slow Slew Rate + 1 SRE_1_Fast_Slew_Rate — Fast Slew Rate From c04d9cf44845c4ae8bf0f4c3e6664c882c2b6192 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 14:53:57 +0800 Subject: [PATCH 02/10] dts: binding: add pinctrl node to sai and lpuart enable pinctrl in i2s and lpuart driver dts Signed-off-by: Hake Huang --- dts/bindings/i2s/nxp,mcux-i2s.yaml | 2 +- dts/bindings/serial/nxp,kinetis-lpuart.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml index c68cd9f41b078..d5b06daf2a719 100644 --- a/dts/bindings/i2s/nxp,mcux-i2s.yaml +++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml @@ -5,7 +5,7 @@ description: NXP mcux SAI-I2S controller compatible: "nxp,mcux-i2s" -include: [i2s-controller.yaml] +include: [i2s-controller.yaml, pinctrl-device.yaml] properties: reg: diff --git a/dts/bindings/serial/nxp,kinetis-lpuart.yaml b/dts/bindings/serial/nxp,kinetis-lpuart.yaml index afcde99e06441..11b859871dd98 100644 --- a/dts/bindings/serial/nxp,kinetis-lpuart.yaml +++ b/dts/bindings/serial/nxp,kinetis-lpuart.yaml @@ -2,7 +2,7 @@ description: Kinetis LPUART compatible: "nxp,kinetis-lpuart" -include: uart-controller.yaml +include: [uart-controller.yaml, pinctrl-device.yaml] properties: reg: From ea665e210d81468cfdd4a353796cb35138539d1f Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 14:55:49 +0800 Subject: [PATCH 03/10] soc: kconfig: pinctrl select in rt1xxx series select pinctrl by default in rt series Signed-off-by: Hake Huang --- soc/arm/nxp_imx/rt/Kconfig.soc | 1 + soc/arm/nxp_imx/rt/pinctrl_soc.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 soc/arm/nxp_imx/rt/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index c974878fb9db3..5e9c43c5e0d12 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -229,6 +229,7 @@ config SOC_MIMXRT1062 select HAS_MCUX_EDMA select HAS_MCUX_FLEXCAN select HAS_MCUX_I2S + select PINCTRL config SOC_MIMXRT1064 bool "SOC_MIMXRT1064" diff --git a/soc/arm/nxp_imx/rt/pinctrl_soc.h b/soc/arm/nxp_imx/rt/pinctrl_soc.h new file mode 100644 index 0000000000000..c127f5ec19b6d --- /dev/null +++ b/soc/arm/nxp_imx/rt/pinctrl_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */ From 989f621b5fb44c525eee89d9631c01625371547f Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 14:56:38 +0800 Subject: [PATCH 04/10] dts: binding: add pinctrl binding header files add pinctrl_soc required headers Signed-off-by: Hake Huang Signed-off-by: Daniel DeGrasse --- dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml | 10 ++- .../pinctrl/pinctrl_soc_mcux_rt_common.h | 80 +++++++++++++++++++ include/dt-bindings/pinctrl/mcux_rt-pinctrl.h | 15 ++++ 3 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h create mode 100644 include/dt-bindings/pinctrl/mcux_rt-pinctrl.h diff --git a/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml index b679a7d6a1d1d..1ea4939986dfa 100644 --- a/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml @@ -2,8 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree, - + The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree compatible: "nxp,mcux-rt-pinctrl" @@ -12,7 +11,7 @@ include: - name: pincfg-node-group.yaml child-binding: property-allowlist: - drive-open-drain + - drive-open-drain properties: reg: @@ -39,6 +38,11 @@ child-binding: description: | An array of pins sharing the same group properties. The pins should be defined using pre-defined macros. + nxp,mcux_input: + required: false + type: boolean + description: | + Force input on nxp,mcux_hys: required: false type: boolean diff --git a/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h b/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h new file mode 100644 index 0000000000000..d03f86d18edee --- /dev/null +++ b/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_ +#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pinmux { + uint32_t mux_register; + uint32_t mux_mode; + uint32_t input_register; + uint32_t input_daisy; + uint32_t config_register; + uint32_t input_on_field; +}; + +typedef struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; +} pinctrl_soc_pin_t; + +#define MCUX_RT_HYS_SHIFT 16 +#define MCUX_RT_PUS_SHIFT 14 +#define MCUX_RT_PUE_SHIFT 13 +#define MCUX_RT_PKE_SHIFT 12 +#define MCUX_RT_ODE_SHIFT 11 +#define MCUX_RT_SPEED_SHIFT 6 +#define MCUX_RT_DSE_SHIFT 3 +#define MCUX_RT_SRE_SHIFT 0 + +#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, nxp_mcux_hys) << MCUX_RT_HYS_SHIFT) | \ + (DT_ENUM_IDX(node_id, nxp_mcux_pus) << MCUX_RT_PUS_SHIFT) | \ + (DT_PROP(node_id, nxp_mcux_pue) << MCUX_RT_PUE_SHIFT) | \ + (DT_PROP(node_id, nxp_mcux_pke) << MCUX_RT_PKE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \ + (DT_ENUM_IDX(node_id, nxp_mcux_speed) << MCUX_RT_SPEED_SHIFT) |\ + (DT_ENUM_IDX(node_id, nxp_mcux_dse) << MCUX_RT_DSE_SHIFT) | \ + (DT_ENUM_IDX(node_id, nxp_mcux_sre) << MCUX_RT_SRE_SHIFT)) + +#define Z_PINCTRL_PIN_INIT(node_id) \ + { .pinmux.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .pinmux.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .pinmux.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .pinmux.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + .pinmux.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .pinmux.input_on_field = DT_PROP(node_id, nxp_mcux_input), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id), \ + }, + + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)} + +/** + * @brief Define all the states for the given node identifier. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_STATES_DEFINE(node_id) \ + static const struct pinctrl_state \ + Z_PINCTRL_STATES_NAME(node_id)[] = { \ + UTIL_LISTIFY(DT_NUM_PINCTRL_STATES(node_id), \ + Z_PINCTRL_STATE_INIT, node_id) \ + }; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_ */ diff --git a/include/dt-bindings/pinctrl/mcux_rt-pinctrl.h b/include/dt-bindings/pinctrl/mcux_rt-pinctrl.h new file mode 100644 index 0000000000000..0ba87c783b1b7 --- /dev/null +++ b/include/dt-bindings/pinctrl/mcux_rt-pinctrl.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCUX_RT_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCUX_RT_PINCTRL_H_ + + + +/** + * @brief MCUX RT specific PIN configuration flag + */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCUX_RT_PINCTRL_H_ */ From 0b53d91f24efaaa6bbb0cb12e57975cfcc7eaaa6 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 14:57:44 +0800 Subject: [PATCH 05/10] dts: pinctrl: add pinctrl and gpr for rt1xxx add dtsi settings for rt series dtsi use gpr to replace pinmux nxp iomuxc has gpr which has more settings than mux and io settings current solution is to export gpr separately and access then directly Signed-off-by: Hake Huang Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_rt.dtsi | 7 ++++--- dts/arm/nxp/nxp_rt1160_cm4.dtsi | 7 +++++++ dts/arm/nxp/nxp_rt1160_cm7.dtsi | 7 +++++++ dts/arm/nxp/nxp_rt1170_cm4.dtsi | 7 +++++++ dts/arm/nxp/nxp_rt1170_cm7.dtsi | 7 +++++++ 5 files changed, 32 insertions(+), 3 deletions(-) diff --git a/dts/arm/nxp/nxp_rt.dtsi b/dts/arm/nxp/nxp_rt.dtsi index fe0bc45c5ebfd..77ec4b61e155c 100644 --- a/dts/arm/nxp/nxp_rt.dtsi +++ b/dts/arm/nxp/nxp_rt.dtsi @@ -231,9 +231,10 @@ status = "disabled"; }; - iomuxc: iomuxc@401f8000 { + pinctrl: pinctrl@401f8000 { + compatible = "nxp,mcux-rt-pinctrl"; reg = <0x401f8000 0x4000>; - label = "PINMUX_0"; + status = "disabled"; }; lcdif: display-controller@402b8000 { @@ -728,7 +729,7 @@ }; iomuxcgpr: iomuxcgpr@400ac000 { - compatible = "nxp,imx-pinmux"; + compatible = "nxp,imx-gpr"; reg = <0x400AC000 0x4000>; label = "IOMUX_GPR"; #pinmux-cells = <2>; diff --git a/dts/arm/nxp/nxp_rt1160_cm4.dtsi b/dts/arm/nxp/nxp_rt1160_cm4.dtsi index c54c71f323b23..b87664963f8db 100644 --- a/dts/arm/nxp/nxp_rt1160_cm4.dtsi +++ b/dts/arm/nxp/nxp_rt1160_cm4.dtsi @@ -71,6 +71,13 @@ <16 0>; }; + iomuxcgpr_lpsr: iomuxcgpr@40c08000 { + compatible = "nxp,imx-gpr"; + reg = <0x40c94000 0x4000>; + label = "IOMUX_GPR"; + #pinmux-cells = <2>; + }; + }; }; diff --git a/dts/arm/nxp/nxp_rt1160_cm7.dtsi b/dts/arm/nxp/nxp_rt1160_cm7.dtsi index a589db0c54389..b42f141c4f1ef 100644 --- a/dts/arm/nxp/nxp_rt1160_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt1160_cm7.dtsi @@ -77,6 +77,13 @@ <12 0>, <13 0>, <14 0>, <15 0>, <16 0>; }; + + iomuxcgpr: iomuxcgpr@40c94000 { + compatible = "nxp,imx-gpr"; + reg = <0x40c94000 0x4000>; + label = "IOMUX_GPR"; + #pinmux-cells = <2>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi index ab131cf8b8102..686d4d1359815 100644 --- a/dts/arm/nxp/nxp_rt1170_cm4.dtsi +++ b/dts/arm/nxp/nxp_rt1170_cm4.dtsi @@ -71,6 +71,13 @@ <12 0>, <13 0>, <14 0>, <15 0>, <16 0>; }; + + iomuxcgpr_lpsr: iomuxcgpr@40c08000 { + compatible = "nxp,imx-gpr"; + reg = <0x40c94000 0x4000>; + label = "IOMUX_GPR"; + #pinmux-cells = <2>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi index 33e794450f03d..7b5890c55edb0 100644 --- a/dts/arm/nxp/nxp_rt1170_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt1170_cm7.dtsi @@ -79,6 +79,13 @@ <12 0>, <13 0>, <14 0>, <15 0>, <16 0>; }; + + iomuxcgpr: iomuxcgpr@40c94000 { + compatible = "nxp,imx-gpr"; + reg = <0x40c94000 0x4000>; + label = "IOMUX_GPR"; + #pinmux-cells = <2>; + }; }; }; From 1645f64650068186608e7a56fecec36f3fb53ab6 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 15:00:28 +0800 Subject: [PATCH 06/10] board: pinctrl: board configs in rt1xxx enable pin control in board level Signed-off-by: Hake Huang Signed-off-by: Daniel DeGrasse --- .../mimxrt1050_evk_qspi_defconfig | 1 + .../mimxrt1060_evk-pinctrl.dtsi | 61 +++++++++++++++++++ boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts | 9 +++ boards/arm/mimxrt1060_evk/pinmux.c | 30 --------- 4 files changed, 71 insertions(+), 30 deletions(-) create mode 100644 boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig index c009123dc1f94..1b883e4d5855e 100644 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig +++ b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig @@ -13,3 +13,4 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINMUX=y diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi new file mode 100644 index 0000000000000..e2447dd9e6c23 --- /dev/null +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + sai1_default: sai1_default { + IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { + pinmux = <0x401F8120 0x3 0x401F858C 0x1 0x401F8310>; + nxp,mcux_input; + nxp,mcux_dse = <6>; + nxp,mcux_speed = <2>; + nxp,mcux_pke; + }; + IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 { + pinmux = <0x401F812C 0x3 0x401F8594 0x1 0x401F831C>; + nxp,mcux_input; + nxp,mcux_dse = <6>; + nxp,mcux_speed = <2>; + nxp,mcux_pke; + }; + IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 { + pinmux = <0x401F8130 0x3 0 0 0x401F8320>; + nxp,mcux_input; + nxp,mcux_dse = <6>; + nxp,mcux_speed = <2>; + nxp,mcux_pke; + }; + IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { + pinmux = <0x401F8134 0x3 0x401F85A8 0x1 0x401F8324>; + nxp,mcux_input; + nxp,mcux_dse = <6>; + nxp,mcux_speed = <2>; + nxp,mcux_pke; + }; + IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { + pinmux = <0x401F8138 0x3 0x401F85AC 0x1 0x401F8328>; + nxp,mcux_input; + nxp,mcux_dse = <6>; + nxp,mcux_speed = <2>; + nxp,mcux_pke; + }; + }; + lpuart1_default: lpuart1_default { + IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401F80EC 0x2 0 0 0x401F82DC>; + nxp,mcux_speed = <2>; + nxp,mcux_dse = <6>; + nxp,mcux_pke; + }; + IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401F80F0 0x2 0 0 0x401F82E0>; + nxp,mcux_speed = <2>; + nxp,mcux_dse = <6>; + nxp,mcux_pke; + }; + }; + status = "okay"; +}; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts index 7446bf6573f0f..463ee9ccd7346 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "mimxrt1060_evk-pinctrl.dtsi" / { model = "NXP MIMXRT1060-EVK board"; @@ -164,6 +165,8 @@ arduino_serial: &lpuart3 {}; &lpuart1 { status = "okay"; current-speed = <115200>; + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; }; &enet { @@ -218,6 +221,8 @@ zephyr_udc0: &usb1 { &sai1 { status = "okay"; + pinctrl-0 = <&sai1_default>; + pinctrl-names = "default"; }; /* Enable GPT for use as a hardware timer. This disables Cortex Systick. @@ -226,3 +231,7 @@ zephyr_udc0: &usb1 { &gpt_hw_timer { status = "okay"; }; + +&iomuxcgpr { + status = "okay"; +}; diff --git a/boards/arm/mimxrt1060_evk/pinmux.c b/boards/arm/mimxrt1060_evk/pinmux.c index f10da0714cf46..c2454fd6250fd 100644 --- a/boards/arm/mimxrt1060_evk/pinmux.c +++ b/boards/arm/mimxrt1060_evk/pinmux.c @@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev) IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL - /* LPUART1 TX/RX */ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, - IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_DSE(6)); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, - IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_DSE(6)); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL /* LPUART3 TX/RX */ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0); @@ -388,20 +372,6 @@ static int mimxrt1060_evk_init(const struct device *dev) IOMUXC_SW_PAD_CTL_PAD_DSE(6)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u); -#endif - return 0; } From 7bac9f7cee93666e6d18bf86fcf73adc29b0f971 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 15:01:27 +0800 Subject: [PATCH 07/10] drivers: pinctrl: add mcux_rt pinctrl driver add pinctrl driver for rt1xxx Signed-off-by: Hake Huang --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.mcux | 9 ++++++ drivers/pinctrl/pinctrl_mcux_rt.c | 46 +++++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.mcux create mode 100644 drivers/pinctrl/pinctrl_mcux_rt.c diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 9fc433f8d3896..6255f6744550b 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -7,3 +7,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f4e84142a7147..ae1268aa141ef 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -32,5 +32,6 @@ config PINCTRL_DYNAMIC source "drivers/pinctrl/Kconfig.gd32" source "drivers/pinctrl/Kconfig.nrf" source "drivers/pinctrl/Kconfig.stm32" +source "drivers/pinctrl/Kconfig.mcux" endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.mcux b/drivers/pinctrl/Kconfig.mcux new file mode 100644 index 0000000000000..57bc52f955be4 --- /dev/null +++ b/drivers/pinctrl/Kconfig.mcux @@ -0,0 +1,9 @@ +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_MCUX_RT + bool "Pin controller driver for MCUX RT1xxx MCUs" + depends on SOC_SERIES_IMX_RT + default y + help + Enable pin controller driver for NXP RT series MCUs diff --git a/drivers/pinctrl/pinctrl_mcux_rt.c b/drivers/pinctrl/pinctrl_mcux_rt.c new file mode 100644 index 0000000000000..64880871644fa --- /dev/null +++ b/drivers/pinctrl/pinctrl_mcux_rt.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, + uintptr_t reg) +{ + uint8_t i; + + /* configure all pins */ + for (i = 0U; i < pin_cnt; i++) { + uint32_t mux_register = pins[i].pinmux.mux_register; + uint32_t mux_mode = pins[i].pinmux.mux_mode; + uint32_t input_register = pins[i].pinmux.input_register; + uint32_t input_daisy = pins[i].pinmux.input_daisy; + uint32_t config_register = pins[i].pinmux.config_register; + uint32_t input_on_field = pins[i].pinmux.input_on_field; + uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; + + IOMUXC_SetPinMux(mux_register, mux_mode, input_register, + input_daisy, config_register, input_on_field); + IOMUXC_SetPinConfig(mux_register, mux_mode, input_register, + input_daisy, config_register, pin_ctrl_flags); + } + + return 0; +} + +static int mcux_pinctrl_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + return 0; +} + +SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); From 302fdfc4fc418fc72d1f806bfc4b6e239dd158bf Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 15:01:58 +0800 Subject: [PATCH 08/10] driver: lpuart: add pinctrl support in mcux lpuart enable pinctrl in lpuart Signed-off-by: Hake Huang --- drivers/serial/uart_mcux_lpuart.c | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index 34b01effa86cf..051e7844e9fdd 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -13,10 +13,16 @@ #include #include #include +#ifdef CONFIG_PINCTRL +#include +#endif struct mcux_lpuart_config { LPUART_Type *base; const struct device *clock_dev; +#ifdef CONFIG_PINCTRL + const struct pinctrl_dev_config *pinctrl; +#endif clock_control_subsys_t clock_subsys; uint32_t baud_rate; uint8_t flow_ctrl; @@ -353,6 +359,10 @@ static int mcux_lpuart_init(const struct device *dev) const struct mcux_lpuart_config *config = dev->config; struct mcux_lpuart_data *data = dev->data; struct uart_config *uart_api_config = &data->uart_config; +#ifdef CONFIG_PINCTRL + int err; + uint8_t state = 0; +#endif uart_api_config->baudrate = config->baud_rate; uart_api_config->parity = UART_CFG_PARITY_NONE; @@ -362,6 +372,12 @@ static int mcux_lpuart_init(const struct device *dev) /* set initial configuration */ mcux_lpuart_configure_init(dev, uart_api_config); +#ifdef CONFIG_PINCTRL + err = pinctrl_apply_state(config->pinctrl, state); + if (err < 0) { + return err; + } +#endif #ifdef CONFIG_UART_INTERRUPT_DRIVEN config->irq_config_func(dev); @@ -425,10 +441,13 @@ static const struct uart_driver_api mcux_lpuart_driver_api = { LPUART_MCUX_DECLARE_CFG(n, LPUART_MCUX_IRQ_CFG_FUNC_INIT) #endif +#if CONFIG_PINCTRL + #define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT) \ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = { \ .base = (LPUART_Type *) DT_INST_REG_ADDR(n), \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ .baud_rate = DT_INST_PROP(n, current_speed), \ .flow_ctrl = DT_INST_PROP(n, hw_flow_control) ? \ @@ -440,6 +459,8 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = { \ \ static struct mcux_lpuart_data mcux_lpuart_##n##_data; \ \ + PINCTRL_DT_INST_DEFINE(n) \ + \ static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\ \ DEVICE_DT_INST_DEFINE(n, \ @@ -456,3 +477,37 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = { \ LPUART_MCUX_INIT_CFG(n); DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT) +#else + +#define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT) \ +static const struct mcux_lpuart_config mcux_lpuart_##n##_config = { \ + .base = (LPUART_Type *) DT_INST_REG_ADDR(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ + .baud_rate = DT_INST_PROP(n, current_speed), \ + .flow_ctrl = DT_INST_PROP(n, hw_flow_control) ? \ + UART_CFG_FLOW_CTRL_RTS_CTS : UART_CFG_FLOW_CTRL_NONE,\ + IRQ_FUNC_INIT \ +} + +#define LPUART_MCUX_INIT(n) \ + \ + static struct mcux_lpuart_data mcux_lpuart_##n##_data; \ + \ + static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\ + \ + DEVICE_DT_INST_DEFINE(n, \ + &mcux_lpuart_init, \ + NULL, \ + &mcux_lpuart_##n##_data, \ + &mcux_lpuart_##n##_config, \ + PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, \ + &mcux_lpuart_driver_api); \ + \ + LPUART_MCUX_CONFIG_FUNC(n) \ + \ + LPUART_MCUX_INIT_CFG(n); + +DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT) +#endif From 3251af65df14eeb64bef5d0778fa972cda9eae59 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 15:02:25 +0800 Subject: [PATCH 09/10] driver: sai: add pinctrl support in mcux sai enable i2s pinctrl Signed-off-by: Hake Huang --- drivers/i2s/i2s_mcux_sai.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c index 87e00ca76b50a..227e4df76a16a 100644 --- a/drivers/i2s/i2s_mcux_sai.c +++ b/drivers/i2s/i2s_mcux_sai.c @@ -16,8 +16,8 @@ #include #include #include - #include +#include #include #include #include @@ -78,6 +78,7 @@ struct i2s_mcux_config { uint32_t tx_channel; clock_control_subsys_t clk_sub_sys; const struct device *ccm_dev; + const struct pinctrl_dev_config *pinctrl; void (*irq_connect)(const struct device *dev); bool rx_sync_mode; bool tx_sync_mode; @@ -328,7 +329,6 @@ static void enable_mclk_direction(const struct device *dev, bool dir) const struct i2s_mcux_config *dev_cfg = dev->config; uint32_t offset = dev_cfg->mclk_pin_offset; uint32_t mask = dev_cfg->mclk_pin_mask; - uint32_t value = 0; uint32_t *gpr = (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset; if (dir) { @@ -336,7 +336,18 @@ static void enable_mclk_direction(const struct device *dev, bool dir) } else { *gpr &= ~mask; } +} + +static void mcux_rt_sai_pin_init(void) +{ + int err; + uint8_t state = 0; + err = pinctrl_apply_state(dev_cfg->pinctrl, state); + if (err < 0) { + LOG_ERR("mclk pinctrl setup failed (%d)", err); + return err; + } } static void get_mclk_rate(const struct device *dev, uint32_t *mclk) @@ -1034,6 +1045,9 @@ static int i2s_mcux_initialize(const struct device *dev) /* register ISR */ dev_cfg->irq_connect(dev); + /* pinctrl */ + mcux_rt_sai_pin_init(); + /*clock configuration*/ audio_clock_settings(dev); @@ -1085,6 +1099,8 @@ static const struct i2s_driver_api i2s_mcux_driver_api = { #define I2S_MCUX_INIT(i2s_id) \ static void i2s_irq_connect_##i2s_id(const struct device *dev); \ \ + PINCTRL_DT_INST_DEFINE(i2s_id) \ + \ static const struct i2s_mcux_config i2s_##i2s_id##_config = { \ .base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \ .clk_src = \ @@ -1116,6 +1132,7 @@ static const struct i2s_driver_api i2s_mcux_driver_api = { .clk_sub_sys = (clock_control_subsys_t) \ DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \ .ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)), \ + .pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id), \ .irq_connect = i2s_irq_connect_##i2s_id, \ .tx_sync_mode = \ DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \ From 3531337ccf047e806a4d5093a7414b4209c53db8 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 24 Dec 2021 15:15:10 +0800 Subject: [PATCH 10/10] dts: binding: rename pinmux to gpr rename pinmux to gpr different from pinmux and io settings gpr will do more IO settings. Signed-off-by: Hake Huang --- dts/bindings/pinctrl/{nxp,imx-pinmux.yaml => nxp,imx-gpr.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename dts/bindings/pinctrl/{nxp,imx-pinmux.yaml => nxp,imx-gpr.yaml} (88%) diff --git a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml b/dts/bindings/pinctrl/nxp,imx-gpr.yaml similarity index 88% rename from dts/bindings/pinctrl/nxp,imx-pinmux.yaml rename to dts/bindings/pinctrl/nxp,imx-gpr.yaml index 66c1ed3a0dfeb..cac8908f65562 100644 --- a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml +++ b/dts/bindings/pinctrl/nxp,imx-gpr.yaml @@ -3,7 +3,7 @@ description: i.MX IOMUXC node -compatible: "nxp,imx-pinmux" +compatible: "nxp,imx-gpr" include: base.yaml