diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi
new file mode 100644
index 0000000000000..5e035ff46c025
--- /dev/null
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2022, NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated by rt_cfg_utils.py on 2022-01-19
+ */
+
+#include <nxp/nxp_imx/rt/mimxrt1062-pinctrl.dtsi>
+
+&IOMUXC_GPIO_AD_B0_12_LPUART1_TX {
+	bias-bus-hold;
+	input-enable;
+};
+
+&IOMUXC_GPIO_AD_B0_13_LPUART1_RX {
+	bias-bus-hold;
+};
+
+&IOMUXC_GPIO_AD_B1_09_SAI1_MCLK {
+	bias-bus-hold;
+	input-enable;
+};
+
+&IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 {
+	bias-bus-hold;
+	input-enable;
+};
+
+&IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 {
+	bias-bus-hold;
+	input-enable;
+};
+
+&IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK {
+	bias-bus-hold;
+	input-enable;
+};
+
+&IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC {
+	bias-bus-hold;
+	input-enable;
+};
+
diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
index 7446bf6573f0f..6a48f248c3b94 100644
--- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_rt1060.dtsi>
+#include "mimxrt1060_evk-pinctrl.dtsi"
 
 / {
 	model = "NXP MIMXRT1060-EVK board";
@@ -164,6 +165,8 @@ arduino_serial: &lpuart3 {};
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&IOMUXC_GPIO_AD_B0_12_LPUART1_TX &IOMUXC_GPIO_AD_B0_13_LPUART1_RX>;
+	pinctrl-names = "default";
 };
 
 &enet {
@@ -218,6 +221,12 @@ zephyr_udc0: &usb1 {
 
 &sai1 {
 	status = "okay";
+	pinctrl-0 = <&IOMUXC_GPIO_B0_13_SAI1_MCLK
+					&IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00
+					&IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00
+					&IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK
+					&IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC>;
+	pinctrl-names = "default";
 };
 
 /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
@@ -226,3 +235,11 @@ zephyr_udc0: &usb1 {
 &gpt_hw_timer {
 	status = "okay";
 };
+
+&iomuxcgpr {
+	status = "okay";
+};
+
+&pinctrl {
+	status = "okay";
+};
diff --git a/boards/arm/mimxrt1060_evk/pinmux.c b/boards/arm/mimxrt1060_evk/pinmux.c
index f10da0714cf46..c2454fd6250fd 100644
--- a/boards/arm/mimxrt1060_evk/pinmux.c
+++ b/boards/arm/mimxrt1060_evk/pinmux.c
@@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
-	/* LPUART1 TX/RX */
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-#endif
-
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
 	/* LPUART3 TX/RX */
 	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
@@ -388,20 +372,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u);
-#endif
-
 	return 0;
 }
 
diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c
index 9a75718c4d842..530b1ba93c4ee 100644
--- a/drivers/i2s/i2s_mcux_sai.c
+++ b/drivers/i2s/i2s_mcux_sai.c
@@ -16,8 +16,8 @@
 #include <device.h>
 #include <init.h>
 #include <drivers/dma.h>
-
 #include <drivers/i2s.h>
+#include <drivers/pinctrl.h>
 #include <drivers/clock_control.h>
 #include <dt-bindings/clock/imx_ccm.h>
 #include <soc.h>
@@ -78,6 +78,7 @@ struct i2s_mcux_config {
 	uint32_t tx_channel;
 	clock_control_subsys_t clk_sub_sys;
 	const struct device *ccm_dev;
+	const struct pinctrl_dev_config *pinctrl;
 	void (*irq_connect)(const struct device *dev);
 	bool rx_sync_mode;
 	bool tx_sync_mode;
@@ -328,7 +329,6 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
 	const struct i2s_mcux_config *dev_cfg = dev->config;
 	uint32_t offset = dev_cfg->mclk_pin_offset;
 	uint32_t mask = dev_cfg->mclk_pin_mask;
-	uint32_t value = 0;
 	uint32_t *gpr =  (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset;
 
 	if (dir) {
@@ -336,7 +336,17 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
 	} else {
 		*gpr &= ~mask;
 	}
+}
+
+static void mcux_rt_sai_pin_init(void)
+{
+	int err;
 
+	err = pinctrl_apply_state(dev_cfg->pinctrl, PINCTRL_STATE_DEFAULT);
+	if (err < 0) {
+		LOG_ERR("mclk pinctrl setup failed (%d)", err);
+		return err;
+	}
 }
 
 static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
@@ -989,6 +999,9 @@ static int i2s_mcux_initialize(const struct device *dev)
 	/* register ISR */
 	dev_cfg->irq_connect(dev);
 
+	/* pinctrl */
+	mcux_rt_sai_pin_init();
+
 	/*clock configuration*/
 	audio_clock_settings(dev);
 
@@ -1040,6 +1053,8 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 #define I2S_MCUX_INIT(i2s_id)						\
 	static void i2s_irq_connect_##i2s_id(const struct device *dev); \
 									\
+	PINCTRL_DT_INST_DEFINE(i2s_id);					\
+									\
 	static const struct i2s_mcux_config i2s_##i2s_id##_config = {	\
 		.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id),		\
 		.clk_src =						\
@@ -1071,6 +1086,7 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 		.clk_sub_sys =	(clock_control_subsys_t)		\
 			DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name),	\
 		.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)),	\
+		.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id),	\
 		.irq_connect = i2s_irq_connect_##i2s_id,		\
 		.tx_sync_mode =						\
 			   DT_INST_PROP(i2s_id, nxp_tx_sync_mode),	\
diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt
index a14936b479dd8..1ce6cf7b7af2b 100644
--- a/drivers/pinctrl/CMakeLists.txt
+++ b/drivers/pinctrl/CMakeLists.txt
@@ -8,3 +8,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8162329175028..eb7a43e8c5116 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -33,5 +33,6 @@ source "drivers/pinctrl/Kconfig.gd32"
 source "drivers/pinctrl/Kconfig.nrf"
 source "drivers/pinctrl/Kconfig.rcar"
 source "drivers/pinctrl/Kconfig.stm32"
+source "drivers/pinctrl/Kconfig.mcux"
 
 endif # PINCTRL
diff --git a/drivers/pinctrl/Kconfig.mcux b/drivers/pinctrl/Kconfig.mcux
new file mode 100644
index 0000000000000..57bc52f955be4
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.mcux
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_MCUX_RT
+	bool "Pin controller driver for MCUX RT1xxx MCUs"
+	depends on SOC_SERIES_IMX_RT
+	default y
+	help
+	  Enable pin controller driver for NXP RT series MCUs
diff --git a/drivers/pinctrl/pinctrl_mcux_rt.c b/drivers/pinctrl/pinctrl_mcux_rt.c
new file mode 100644
index 0000000000000..5d72381adc1c7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_mcux_rt.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/pinctrl.h>
+#include <soc.h>
+#include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	/* configure all pins */
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		uint32_t mux_register = pins[i].pinmux.mux_register;
+		uint32_t mux_mode = pins[i].pinmux.mux_mode;
+		uint32_t input_register = pins[i].pinmux.input_register;
+		uint32_t input_daisy = pins[i].pinmux.input_daisy;
+		uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
+		volatile uint32_t *config_register = (uint32_t *)pins[i].pinmux.config_register;
+		uint32_t config_val = *config_register;
+
+
+
+		IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
+			input_daisy, (uint32_t)config_register,
+			MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
+
+		if (MCUX_RT_INPUT_SCHMITT_ENABLE(pin_ctrl_flags)) {
+			config_val |= IOMUXC_SW_PAD_CTL_PAD_HYS(1);
+		}
+		if (MCUX_RT_DRIVE_OPEN_DRAIN(pin_ctrl_flags)) {
+			config_val |= IOMUXC_SW_PAD_CTL_PAD_ODE(1);
+		}
+		if (MCUX_RT_BIAS_BUS_HOLD(pin_ctrl_flags)) {
+			/* Set pull keeper select to keeper, and pull keeper enable to 1 */
+			config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1);
+			config_val &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
+		}
+		if (MCUX_RT_BIAS_PULL_DOWN(pin_ctrl_flags)) {
+			/* Set pull keeper select to pull, and pull keeper enable to 1 */
+			config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1);
+			/* Set PUS to 0b00 to select pulldown resistor */
+			config_val &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
+		}
+		if (MCUX_RT_BIAS_PULL_UP(pin_ctrl_flags)) {
+			/* Set pull keeper select to pull, and pull keeper enable to 1 */
+			config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1);
+			/* Set PUS field to selected value */
+			config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) |
+				IOMUXC_SW_PAD_CTL_PAD_PUS(MCUX_RT_BIAS_PULL_UP(pin_ctrl_flags)));
+		}
+		/* Set drive strength field */
+		config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) |
+			IOMUXC_SW_PAD_CTL_PAD_DSE(MCUX_RT_DRIVE_STRENGTH(pin_ctrl_flags)));
+		/* Set speed field */
+		config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) |
+			IOMUXC_SW_PAD_CTL_PAD_SPEED(MCUX_RT_SPEED(pin_ctrl_flags)));
+		/* Set slew rate field */
+		config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) |
+			IOMUXC_SW_PAD_CTL_PAD_SRE(MCUX_RT_SLEW_RATE(pin_ctrl_flags)));
+		/* Write out config value */
+		*config_register = config_val;
+	}
+
+	return 0;
+}
+
+static int mcux_pinctrl_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	return 0;
+}
+
+SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c
index 34b01effa86cf..fd967403051bd 100644
--- a/drivers/serial/uart_mcux_lpuart.c
+++ b/drivers/serial/uart_mcux_lpuart.c
@@ -13,10 +13,16 @@
 #include <device.h>
 #include <drivers/uart.h>
 #include <drivers/clock_control.h>
+#ifdef CONFIG_PINCTRL
+#include <drivers/pinctrl.h>
+#endif
 
 struct mcux_lpuart_config {
 	LPUART_Type *base;
 	const struct device *clock_dev;
+#ifdef CONFIG_PINCTRL
+	const struct pinctrl_dev_config *pinctrl;
+#endif
 	clock_control_subsys_t clock_subsys;
 	uint32_t baud_rate;
 	uint8_t flow_ctrl;
@@ -353,6 +359,9 @@ static int mcux_lpuart_init(const struct device *dev)
 	const struct mcux_lpuart_config *config = dev->config;
 	struct mcux_lpuart_data *data = dev->data;
 	struct uart_config *uart_api_config = &data->uart_config;
+#ifdef CONFIG_PINCTRL
+	int err;
+#endif
 
 	uart_api_config->baudrate = config->baud_rate;
 	uart_api_config->parity = UART_CFG_PARITY_NONE;
@@ -362,6 +371,12 @@ static int mcux_lpuart_init(const struct device *dev)
 
 	/* set initial configuration */
 	mcux_lpuart_configure_init(dev, uart_api_config);
+#ifdef CONFIG_PINCTRL
+	err = pinctrl_apply_state(config->pinctrl, PINCTRL_STATE_DEFAULT);
+	if (err < 0) {
+		return err;
+	}
+#endif
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	config->irq_config_func(dev);
@@ -425,10 +440,13 @@ static const struct uart_driver_api mcux_lpuart_driver_api = {
 	LPUART_MCUX_DECLARE_CFG(n, LPUART_MCUX_IRQ_CFG_FUNC_INIT)
 #endif
 
+#if CONFIG_PINCTRL
+
 #define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT)			\
 static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 	.base = (LPUART_Type *) DT_INST_REG_ADDR(n),			\
 	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+	.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
 	.baud_rate = DT_INST_PROP(n, current_speed),			\
 	.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?	\
@@ -440,6 +458,8 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 									\
 	static struct mcux_lpuart_data mcux_lpuart_##n##_data;		\
 									\
+	PINCTRL_DT_INST_DEFINE(n);					\
+									\
 	static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\
 									\
 	DEVICE_DT_INST_DEFINE(n,					\
@@ -456,3 +476,37 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 	LPUART_MCUX_INIT_CFG(n);
 
 DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT)
+#else
+
+#define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT)			\
+static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
+	.base = (LPUART_Type *) DT_INST_REG_ADDR(n),			\
+	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
+	.baud_rate = DT_INST_PROP(n, current_speed),			\
+	.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?	\
+		UART_CFG_FLOW_CTRL_RTS_CTS : UART_CFG_FLOW_CTRL_NONE,\
+	IRQ_FUNC_INIT							\
+}
+
+#define LPUART_MCUX_INIT(n)						\
+									\
+	static struct mcux_lpuart_data mcux_lpuart_##n##_data;		\
+									\
+	static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\
+									\
+	DEVICE_DT_INST_DEFINE(n,					\
+			    &mcux_lpuart_init,				\
+			    NULL,					\
+			    &mcux_lpuart_##n##_data,			\
+			    &mcux_lpuart_##n##_config,			\
+			    PRE_KERNEL_1,				\
+			    CONFIG_SERIAL_INIT_PRIORITY,		\
+			    &mcux_lpuart_driver_api);			\
+									\
+	LPUART_MCUX_CONFIG_FUNC(n)					\
+									\
+	LPUART_MCUX_INIT_CFG(n);
+
+DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT)
+#endif
diff --git a/dts/arm/nxp/nxp_rt.dtsi b/dts/arm/nxp/nxp_rt.dtsi
index 731041ef0587f..b4e5a94bfa3f5 100644
--- a/dts/arm/nxp/nxp_rt.dtsi
+++ b/dts/arm/nxp/nxp_rt.dtsi
@@ -231,9 +231,10 @@
 			status = "disabled";
 		};
 
-		iomuxc: iomuxc@401f8000 {
+		pinctrl: pinctrl@401f8000 {
+			compatible = "nxp,mcux-rt-pinctrl";
 			reg = <0x401f8000 0x4000>;
-			label = "PINMUX_0";
+			status = "disabled";
 		};
 
 		lcdif: display-controller@402b8000 {
@@ -729,7 +730,7 @@
 		};
 
 		iomuxcgpr: iomuxcgpr@400ac000 {
-			compatible = "nxp,imx-pinmux";
+			compatible = "nxp,imx-gpr";
 			reg = <0x400AC000 0x4000>;
 			label = "IOMUX_GPR";
 			#pinmux-cells = <2>;
diff --git a/dts/arm/nxp/nxp_rt1160_cm4.dtsi b/dts/arm/nxp/nxp_rt1160_cm4.dtsi
index c717eacf22fe9..a8acb75fae2ae 100644
--- a/dts/arm/nxp/nxp_rt1160_cm4.dtsi
+++ b/dts/arm/nxp/nxp_rt1160_cm4.dtsi
@@ -82,6 +82,14 @@
 			nxp,tx-dma-channel = <7>;
 			nxp,rx-dma-channel = <8>;
 		};
+
+		iomuxcgpr_lpsr: iomuxcgpr@40c08000 {
+			compatible = "nxp,imx-gpr";
+			reg = <0x40c94000 0x4000>;
+			label = "IOMUX_GPR";
+			#pinmux-cells = <2>;
+		};
+
 	};
 
 };
diff --git a/dts/arm/nxp/nxp_rt1160_cm7.dtsi b/dts/arm/nxp/nxp_rt1160_cm7.dtsi
index 4e46f2af081bb..d417a6e14ea29 100644
--- a/dts/arm/nxp/nxp_rt1160_cm7.dtsi
+++ b/dts/arm/nxp/nxp_rt1160_cm7.dtsi
@@ -90,6 +90,13 @@
 			nxp,tx-dma-channel = <7>;
 			nxp,rx-dma-channel = <8>;
 		};
+
+		iomuxcgpr: iomuxcgpr@40c94000 {
+			compatible = "nxp,imx-gpr";
+			reg = <0x40c94000 0x4000>;
+			label = "IOMUX_GPR";
+			#pinmux-cells = <2>;
+		};
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
index 3c9402fd88f9a..9fb36f9ee218f 100644
--- a/dts/arm/nxp/nxp_rt1170_cm4.dtsi
+++ b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
@@ -82,6 +82,13 @@
 			nxp,tx-dma-channel = <7>;
 			nxp,rx-dma-channel = <8>;
 		};
+
+		iomuxcgpr_lpsr: iomuxcgpr@40c08000 {
+			compatible = "nxp,imx-gpr";
+			reg = <0x40c94000 0x4000>;
+			label = "IOMUX_GPR";
+			#pinmux-cells = <2>;
+		};
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
index 4484d335b0167..a30a8fe5bb9d9 100644
--- a/dts/arm/nxp/nxp_rt1170_cm7.dtsi
+++ b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
@@ -90,6 +90,13 @@
 			nxp,tx-dma-channel = <7>;
 			nxp,rx-dma-channel = <8>;
 		};
+
+		iomuxcgpr: iomuxcgpr@40c94000 {
+			compatible = "nxp,imx-gpr";
+			reg = <0x40c94000 0x4000>;
+			label = "IOMUX_GPR";
+			#pinmux-cells = <2>;
+		};
 	};
 };
 
diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml
index c68cd9f41b078..b48511575e0a0 100644
--- a/dts/bindings/i2s/nxp,mcux-i2s.yaml
+++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml
@@ -5,7 +5,7 @@ description: NXP mcux SAI-I2S controller
 
 compatible: "nxp,mcux-i2s"
 
-include: [i2s-controller.yaml]
+include: [i2s-controller.yaml, pinctrl-device.yaml]
 
 properties:
     reg:
@@ -64,6 +64,12 @@ properties:
       specifier-space: pinmux
       description: iomux settings
 
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
     nxp,tx-channel:
       type: int
       required: false
diff --git a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml b/dts/bindings/pinctrl/nxp,imx-gpr.yaml
similarity index 88%
rename from dts/bindings/pinctrl/nxp,imx-pinmux.yaml
rename to dts/bindings/pinctrl/nxp,imx-gpr.yaml
index 66c1ed3a0dfeb..cac8908f65562 100644
--- a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml
+++ b/dts/bindings/pinctrl/nxp,imx-gpr.yaml
@@ -3,7 +3,7 @@
 
 description: i.MX IOMUXC node
 
-compatible: "nxp,imx-pinmux"
+compatible: "nxp,imx-gpr"
 
 include: base.yaml
 
diff --git a/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml
new file mode 100644
index 0000000000000..429e2e27c7a8e
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml
@@ -0,0 +1,137 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
+  nodes can be autogenerated using the MCUXpresso config tools combined with
+  the rt_dts_gen.py script in NXP's HAL.
+  Each pinctrl node simply selects the pinmux setting by default, sets all
+  configuration values to reset values for the SOC register. Individual
+  overrides to pinctrl nodes can be applied at the board level.
+
+  for example, here is an override for the GPIO_AD_B0_12 pad:
+
+  &IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL {
+      bias-pull-up = <2>;
+      drive-strength = <7>;
+      nxp,speed = <3>;
+      slew-rate = <1>;
+  }
+
+  This will select GPIO_AD_B0_12 for use as SCL on LPI2C4, and enable
+  the 100K pull up resistor on the pin. It will also increase the slew rate
+  and drive strength to their maximum settings. Note that the soc level pinctrl
+  DTSI file can be examined to find the soc level defaults for this pinmux
+  setting.
+
+  The pinmux property itself is used to make the MUX selection that
+  pinctrl node will apply.
+
+  Here are the affects of each property on the IOMUXC SW_PAD_CTL register:
+
+  input-schmitt-enable: HYS=1
+  drive-open-drain: ODE=1
+  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
+  bias-bus-hold: PKE=1, PUE=0
+  bias-pull-down: PKE=1, PUE=1, PUS=0
+  bias-pull-up: PKE=1, PUE=1, PUS=<prop_value>
+  slew-rate: SRE=<prop_value>
+  drive-strength: DSE=<prop_value>
+  nxp,speed: SPEED=<prop_value>
+
+
+
+compatible: "nxp,mcux-rt-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node.yaml
+      child-binding:
+        property-allowlist:
+          - input-schmitt-enable
+          - drive-open-drain
+          - input-enable
+          - bias-bus-hold
+          - bias-pull-down
+
+properties:
+    reg:
+      required: true
+
+child-binding:
+  description: |
+    MCUX RT pin controller pin configuration node.
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        An array of values defining the configuration register for a given
+        pinmux mode. See fsl_iomuxc.h in the NXP HAL for a list.
+        The array takes the following format:
+        mux_register, mux_value, input_register, input_daisy, config_register
+    drive-strength:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 7
+      description: |
+        Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
+        000 DSE_0_output_driver_disabled_ — output driver disabled
+        001 DSE_1_R0_1 — 157 Ohm impedance @3.3V, 260 Ohm impedance @1.8V
+        010 DSE_2_R0_2 — 78 Ohm @3.3V, 130 Ohm @1.8V
+        011 DSE_3_R0_3 — 53 Ohm @3.3V, 88 Ohm @1.8V
+        100 DSE_4_R0_4 — 39 Ohm @3.3V, 65 Ohm @1.8V
+        101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
+        110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
+        111 DSE_7_R0_7 — 26 Ohm @3.3V, 37 Ohm @1.8V
+    bias-pull-up:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+      description: |
+        Select the value of the pull up resistor present on this pin
+        Corresponds to the PUS field in the IOMUXC peripheral
+        00 Unused- no change will be applied to pin
+        01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
+        10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
+        11 PUS_3_22K_Ohm_Pull_Up — 22K Ohm Pull Up
+    slew-rate:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+      description: |
+        Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
+        0 SRE_0_Slow_Slew_Rate — Slow Slew Rate
+        1 SRE_1_Fast_Slew_Rate — Fast Slew Rate
+    nxp,speed:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+      description: |
+        Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
+        00 SPEED_0_low_50MHz_ — low(50MHz)
+        01 SPEED_1_medium_100MHz_ — medium(100MHz)
+        10 SPEED_2_medium_100MHz_ — medium(100MHz)
+        11 SPEED_3_max_200MHz_ — max(200MHz)
diff --git a/dts/bindings/serial/nxp,kinetis-lpuart.yaml b/dts/bindings/serial/nxp,kinetis-lpuart.yaml
index afcde99e06441..11b859871dd98 100644
--- a/dts/bindings/serial/nxp,kinetis-lpuart.yaml
+++ b/dts/bindings/serial/nxp,kinetis-lpuart.yaml
@@ -2,7 +2,7 @@ description: Kinetis LPUART
 
 compatible: "nxp,kinetis-lpuart"
 
-include: uart-controller.yaml
+include: [uart-controller.yaml, pinctrl-device.yaml]
 
 properties:
     reg:
diff --git a/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h b/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h
new file mode 100644
index 0000000000000..3a3c9e546ee2e
--- /dev/null
+++ b/include/drivers/pinctrl/pinctrl_soc_mcux_rt_common.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_
+#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_
+
+#include <devicetree.h>
+#include <zephyr/types.h>
+#include "fsl_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pinctrl_soc_pinmux {
+	uint32_t mux_register;
+	uint32_t mux_mode;
+	uint32_t input_register;
+	uint32_t input_daisy;
+	uint32_t config_register;
+};
+
+typedef struct pinctrl_soc_pin {
+	struct pinctrl_soc_pinmux pinmux;
+	uint32_t pin_ctrl_flags;
+} pinctrl_soc_pin_t;
+
+#define MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT 0
+#define MCUX_RT_INPUT_SCHMITT_ENABLE(x) ((x >> MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) & 0x1)
+#define MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT 1
+#define MCUX_RT_DRIVE_OPEN_DRAIN(x) ((x >> MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) & 0x1)
+#define MCUX_RT_INPUT_ENABLE_SHIFT 2
+#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
+#define MCUX_RT_BIAS_BUS_HOLD_SHIFT 3
+#define MCUX_RT_BIAS_BUS_HOLD(x) ((x >> MCUX_RT_BIAS_BUS_HOLD_SHIFT) & 0x1)
+#define MCUX_RT_BIAS_PULL_DOWN_SHIFT 4
+#define MCUX_RT_BIAS_PULL_DOWN(x) ((x >> MCUX_RT_BIAS_PULL_DOWN_SHIFT) & 0x1)
+#define MCUX_RT_BIAS_PULL_UP_SHIFT 5
+#define MCUX_RT_BIAS_PULL_UP(x) ((x >> MCUX_RT_BIAS_PULL_UP_SHIFT) & 0x3)
+#define MCUX_RT_DRIVE_STRENGTH_SHIFT 7
+#define MCUX_RT_DRIVE_STRENGTH(x) ((x >> MCUX_RT_DRIVE_STRENGTH_SHIFT) & 0x7)
+#define MCUX_RT_SPEED_SHIFT 10
+#define MCUX_RT_SPEED(x) ((x >> MCUX_RT_SPEED_SHIFT) & 0x3)
+#define MCUX_RT_SLEW_RATE_SHIFT 12
+#define MCUX_RT_SLEW_RATE(x) ((x >> MCUX_RT_SLEW_RATE_SHIFT) & 0x1)
+
+
+#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id)				\
+	 ((DT_PROP(node_id, input_schmitt_enable) << MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) |	\
+	 (DT_PROP(node_id, drive_open_drain) << MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) |	\
+	 (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT) |	\
+	 (DT_PROP(node_id, bias_bus_hold) << MCUX_RT_BIAS_BUS_HOLD_SHIFT) |	\
+	 (DT_PROP(node_id, bias_pull_down) << MCUX_RT_BIAS_PULL_DOWN_SHIFT) |	\
+	 (DT_ENUM_IDX(node_id, drive_strength) << MCUX_RT_DRIVE_STRENGTH_SHIFT) |\
+	 (DT_ENUM_IDX(node_id, bias_pull_up) << MCUX_RT_BIAS_PULL_UP_SHIFT) |	\
+	 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_RT_SLEW_RATE_SHIFT) |	\
+	 (DT_ENUM_IDX(node_id, nxp_speed) << MCUX_RT_SPEED_SHIFT))
+
+#define Z_PINCTRL_PIN_INIT(node_id)				\
+	{ .pinmux.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0),	\
+	  .pinmux.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1),	\
+	  .pinmux.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2),	\
+	  .pinmux.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3),	\
+	  .pinmux.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4),	\
+	  .pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id),	\
+	},
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)		\
+	Z_PINCTRL_PIN_INIT(DT_PROP_BY_IDX(node_id, prop, idx))
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)			\
+	{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_SOC_MCUX_RT_COMMON_H_ */
diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc
index f4e6049fa8cd3..b70543da7cdc2 100644
--- a/soc/arm/nxp_imx/rt/Kconfig.soc
+++ b/soc/arm/nxp_imx/rt/Kconfig.soc
@@ -214,6 +214,7 @@ config SOC_MIMXRT1062
 	select HAS_MCUX_EDMA
 	select HAS_MCUX_FLEXCAN
 	select HAS_MCUX_I2S
+	select PINCTRL
 
 config SOC_MIMXRT1064
 	bool "SOC_MIMXRT1064"
diff --git a/soc/arm/nxp_imx/rt/pinctrl_soc.h b/soc/arm/nxp_imx/rt/pinctrl_soc.h
new file mode 100644
index 0000000000000..c127f5ec19b6d
--- /dev/null
+++ b/soc/arm/nxp_imx/rt/pinctrl_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
+
+#include <drivers/pinctrl/pinctrl_soc_mcux_rt_common.h>
+
+#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */
diff --git a/west.yml b/west.yml
index d492671273f1a..448ab1d2eb2aa 100644
--- a/west.yml
+++ b/west.yml
@@ -98,7 +98,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: aee8eaa8cf4264321c2a816a6d165a3351d1c434
+      revision: pull/132/head
       path: modules/hal/nxp
       groups:
         - hal