diff --git a/boards/arm/sam4s_xplained/doc/index.rst b/boards/arm/sam4s_xplained/doc/index.rst index c8cadafdc66dd..dd1b7d647de52 100644 --- a/boards/arm/sam4s_xplained/doc/index.rst +++ b/boards/arm/sam4s_xplained/doc/index.rst @@ -55,6 +55,8 @@ features: +-----------+------------+-------------------------------------+ | HWINFO | on-chip | Unique device serial number | +-----------+------------+-------------------------------------+ +| SMC | on-chip | memc (PSRAM) | ++-----------+------------+-------------------------------------+ Other hardware features are not currently supported by Zephyr. diff --git a/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi b/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi index 0d60047731eb6..492d31378af76 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi +++ b/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi @@ -41,4 +41,39 @@ ; }; }; + smc_default: smc_default { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; }; diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.dts b/boards/arm/sam4s_xplained/sam4s_xplained.dts index 59f428af41f29..d4b6e938de242 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained.dts +++ b/boards/arm/sam4s_xplained/sam4s_xplained.dts @@ -28,6 +28,20 @@ zephyr,flash = &flash0; }; + sram1: sram@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_K(512)>; + zephyr,memory-region = "SRAM1"; + }; + + sram2: sram@61000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x61000000 DT_SIZE_K(512)>; + zephyr,memory-region = "SRAM2"; + }; + leds { compatible = "gpio-leds"; yellow_led_1: led_1 { @@ -175,3 +189,29 @@ xplained4_spi: &spi0 { xplained4_serial: &uart1 { }; + +&smc { + status = "okay"; + pinctrl-0 = <&smc_default>; + pinctrl-names = "default"; + + is66wv51216dbll@0 { + reg = <0>; + + atmel,smc-write-mode = "nwe"; + atmel,smc-read-mode = "nrd"; + atmel,smc-setup-timing = <1 1 1 1>; + atmel,smc-pulse-timing = <6 6 6 6>; + atmel,smc-cycle-timing = <7 7>; + }; + + is66wv51216dbll@1 { + reg = <1>; + + atmel,smc-write-mode = "nwe"; + atmel,smc-read-mode = "nrd"; + atmel,smc-setup-timing = <1 1 1 1>; + atmel,smc-pulse-timing = <6 6 6 6>; + atmel,smc-cycle-timing = <7 7>; + }; +}; diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.yaml b/boards/arm/sam4s_xplained/sam4s_xplained.yaml index 1714442ebcefe..9c485bc0407bd 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained.yaml +++ b/boards/arm/sam4s_xplained/sam4s_xplained.yaml @@ -8,6 +8,7 @@ toolchain: - xtools supported: - gpio + - memc - spi - watchdog - xplained_gpio diff --git a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig b/boards/arm/sam4s_xplained/sam4s_xplained_defconfig index 5e324e56c7a16..d583b3ba9c85b 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig +++ b/boards/arm/sam4s_xplained/sam4s_xplained_defconfig @@ -12,5 +12,8 @@ CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK=y CONFIG_GPIO=y CONFIG_WDT_DISABLE_AT_BOOT=y +# Enable SMC SRAM +CONFIG_MEMC=y + # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y diff --git a/drivers/memc/CMakeLists.txt b/drivers/memc/CMakeLists.txt index af9400facca8d..020f79168302c 100644 --- a/drivers/memc/CMakeLists.txt +++ b/drivers/memc/CMakeLists.txt @@ -10,6 +10,8 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_NOR_PSRAM memc_stm32_nor_psram.c) zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c) zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_HYPERRAM memc_mcux_flexspi_hyperram.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) zephyr_code_relocate(memc_mcux_flexspi.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) endif() diff --git a/drivers/memc/Kconfig b/drivers/memc/Kconfig index f22dc4e9f2954..5912f7a18582a 100644 --- a/drivers/memc/Kconfig +++ b/drivers/memc/Kconfig @@ -25,4 +25,6 @@ source "drivers/memc/Kconfig.stm32" source "drivers/memc/Kconfig.mcux" +source "drivers/memc/Kconfig.sam" + endif diff --git a/drivers/memc/Kconfig.sam b/drivers/memc/Kconfig.sam new file mode 100644 index 0000000000000..fef4f51040b4c --- /dev/null +++ b/drivers/memc/Kconfig.sam @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Basalte bv +# SPDX-License-Identifier: Apache-2.0 + +config MEMC_SAM_SMC + bool "Atmel Static Memory Controller (SMC)" + default y + depends on DT_HAS_ATMEL_SAM_SMC_ENABLED + help + Enable Atmel Static Memory Controller. diff --git a/drivers/memc/memc_sam_smc.c b/drivers/memc/memc_sam_smc.c new file mode 100644 index 0000000000000..ab3d766105408 --- /dev/null +++ b/drivers/memc/memc_sam_smc.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2022 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT atmel_sam_smc + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(memc_sam, CONFIG_MEMC_LOG_LEVEL); + +struct memc_smc_bank_config { + uint32_t cs; + uint32_t mode; + uint32_t setup_timing; + uint32_t pulse_timing; + uint32_t cycle_timing; +}; + +struct memc_smc_config { + Smc *regs; + uint32_t periph_id; + + size_t banks_len; + const struct memc_smc_bank_config *banks; + + const struct pinctrl_dev_config *pcfg; +}; + +static int memc_smc_init(const struct device *dev) +{ + int ret; + const struct memc_smc_config *cfg = dev->config; + SmcCs_number *bank; + + soc_pmc_peripheral_enable(cfg->periph_id); + + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + for (size_t i = 0U; i < cfg->banks_len; i++) { + if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) { + return -EINVAL; + } + + bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; + + bank->SMC_SETUP = cfg->banks[i].setup_timing; + bank->SMC_PULSE = cfg->banks[i].pulse_timing; + bank->SMC_CYCLE = cfg->banks[i].cycle_timing; + bank->SMC_MODE = cfg->banks[i].mode; + } + + return 0; +} + +#define SETUP_TIMING(node_id) \ + SMC_SETUP_NWE_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 0)) \ + | SMC_SETUP_NCS_WR_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 1)) \ + | SMC_SETUP_NRD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 2)) \ + | SMC_SETUP_NCS_RD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 3)) +#define PULSE_TIMING(node_id) \ + SMC_PULSE_NWE_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 0)) \ + | SMC_PULSE_NCS_WR_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 1)) \ + | SMC_PULSE_NRD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 2)) \ + | SMC_PULSE_NCS_RD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 3)) +#define CYCLE_TIMING(node_id) \ + SMC_CYCLE_NWE_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 0)) \ + | SMC_CYCLE_NRD_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 1)) + +#define BANK_CONFIG(node_id) \ + { \ + .cs = DT_REG_ADDR(node_id), \ + .mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \ + (SMC_MODE_WRITE_MODE), (0)) \ + | COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \ + (SMC_MODE_READ_MODE), (0)), \ + .setup_timing = SETUP_TIMING(node_id), \ + .pulse_timing = PULSE_TIMING(node_id), \ + .cycle_timing = CYCLE_TIMING(node_id), \ + }, + +#define MEMC_SMC_DEFINE(inst) \ + static const struct memc_smc_bank_config smc_bank_config_##inst[] = { \ + DT_INST_FOREACH_CHILD(inst, BANK_CONFIG) \ + }; \ + PINCTRL_DT_INST_DEFINE(inst); \ + static const struct memc_smc_config smc_config_##inst = { \ + .regs = (Smc *)DT_INST_REG_ADDR(inst), \ + .periph_id = DT_INST_PROP(inst, peripheral_id), \ + .banks_len = ARRAY_SIZE(smc_bank_config_##inst), \ + .banks = smc_bank_config_##inst, \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, memc_smc_init, NULL, NULL, \ + &smc_config_##inst, POST_KERNEL, \ + CONFIG_MEMC_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(MEMC_SMC_DEFINE) diff --git a/dts/arm/atmel/sam4e.dtsi b/dts/arm/atmel/sam4e.dtsi index 01d9b41c503d5..1ee52c97ae11a 100644 --- a/dts/arm/atmel/sam4e.dtsi +++ b/dts/arm/atmel/sam4e.dtsi @@ -232,6 +232,15 @@ peripheral-id = <27 28 29>; status = "disabled"; }; + + smc: smc@40060000 { + compatible = "atmel,sam-smc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40060000 0x200>; + peripheral-id = <8>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/atmel/sam4s.dtsi b/dts/arm/atmel/sam4s.dtsi index 308ed966faba6..789a5dcf62350 100644 --- a/dts/arm/atmel/sam4s.dtsi +++ b/dts/arm/atmel/sam4s.dtsi @@ -194,6 +194,15 @@ peripheral-id = <1>; user-nrst; }; + + smc: smc@400e0000 { + compatible = "atmel,sam-smc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400e0000 0x200>; + peripheral-id = <10>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/atmel/sam4sa16c.dtsi b/dts/arm/atmel/sam4sa16c.dtsi new file mode 100644 index 0000000000000..ae96e4b27ada6 --- /dev/null +++ b/dts/arm/atmel/sam4sa16c.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@400e0a00 { + flash0: flash@400000 { + reg = <0x00400000 DT_SIZE_K(1024)>; + }; + }; + + sram0: memory@20100000 { + reg = <0x20100000 DT_SIZE_K(160)>; + }; + }; +}; diff --git a/dts/bindings/memory-controllers/atmel,sam-smc.yaml b/dts/bindings/memory-controllers/atmel,sam-smc.yaml new file mode 100644 index 0000000000000..a755dd2eb0c9e --- /dev/null +++ b/dts/bindings/memory-controllers/atmel,sam-smc.yaml @@ -0,0 +1,152 @@ +# Copyright (c) 2022, Basalte bv +# SPDX-License-Identifier: Apache-2.0 + +description: | + Atmel Static Memory Controller (SMC). + + The SMC allows to interface with static-memory mapped external devices such as + SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. + + The SMC is clocked through the Master Clock (MCK) which is controlled by the + Power Management Controller (PMC). + + The SMC controller can have up to 4 children defining the connected external + memory devices. The reg property is set to the device's Chip Select. + Device Tree example taken from the sam4_xplained board: + + &smc { + status = "okay"; + pinctrl-0 = <&smc_default>; + pinctrl-names = "default"; + + is66wv51216dbll@0 { + reg = <0>; + + atmel,smc-write-mode = "nwe"; + atmel,smc-read-mode = "nrd"; + atmel,smc-setup-timing = <1 1 1 1>; + atmel,smc-pulse-timing = <6 6 6 6>; + atmel,smc-cycle-timing = <7 7>; + }; + }; + + The above example configures a is66wv51216dbll-55 device. The device is a + low power static RAM which uses NWE and NRD signals connected to the WE + and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed) + each MCK cycle will be equivalent to 8ns. Since the memory full cycle is + 55ns, as per specification, it requires atmel,smc-cycle-timing of at least + 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts: + setup, pulse and hold. The setup is used to address the memory. The pulse + is the time used to read/write. The hold is used to release memory. For the + is66wv51216dbll-55 a minimum setup of 5ns (1 cycle) with at least 45ns + (6 cycles) for CPU read/write and no hold time is required. + Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing + should have additional cycles to accommodate for hold values. + + No Hold Time: + cycle-timing (7) = setup (1) + pulse (6) + hold (0) + + With 3 Hold Times: + cycle-timing (10) = setup (1) + pulse (6) + hold (3) + + Finally, in order to make the memory available you will need to define new + memory device/s in DeviceTree: + + sram1: sram@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_K(512)>; + zephyr,memory-region = "SRAM1"; + }; + +compatible: "atmel,sam-smc" + +include: [base.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + "#address-cells": + required: true + const: 1 + + "#size-cells": + required: true + const: 0 + + peripheral-id: + type: int + description: peripheral ID + required: true + +child-binding: + description: | + Child device nodes are representing devices connected to the EBI/SMC bus. + + properties: + reg: + type: int + required: true + description: | + The device's SMC Chip Select number. + Valid range: 0 - 3 + + atmel,smc-write-mode: + type: string + required: true + description: | + Select which signal is used for the write operation, either the chip + select (ncs) or a dedicated write enable pin (nwe). The data is put + on the bus during the pulse and hold steps of that signal. + The internal data buffers are switched to output mode after the NCS_WR + or NWE setup time. + enum: + - "ncs" + - "nwe" + + atmel,smc-read-mode: + type: string + required: true + description: | + Select which signal is used for the read operation, either the chip + select (ncs) or a dedicated output enable pin (nrd). The data is read + from the bus during the pulse and hold steps of that signal. + enum: + - "ncs" + - "nrd" + + atmel,smc-setup-timing: + type: array + required: true + description: | + This value is used to setup memory region (set address). The setup + values is an array of the signals NWE, NCS_WR, NRD and NCS_RD + where each value is configured in terms of MCK cycles. The SMC + controller allows use of setups value of 0 (no delays) when + consecutive reads/writes are used. Each value is encoded in + 6 bits where the highest bit adds an offset of 128 cycles. + The effective value for each element is: 128 x setup[5] + setup[4:0] + + atmel,smc-pulse-timing: + type: array + required: true + description: | + This value is used to effectivelly read/write at memory region (pulse phase). + The pulse value is an array of the signals NWE, NCS_WR, NRD and NCS_RD where + each value is configured in terms of MCK cycles and a value of 0 is forbidden. + Each value is encoded in 7 bits where the highest bit adds an offset of 256 + cycles. The effective value for each element is: 256 x setup[6] + setup[5:0] + + atmel,smc-cycle-timing: + type: array + required: true + description: | + SMC timing configurations in cycles for the total write and read + length respectively. + This value describes the entire write/read operation timing which + is defined as: cycle = setup + pulse + hold + Value has to be greater or equal to setup + pulse timing and + is encoded in 9 bits where the two highest bits are multiplied + with an offset of 256. + Effective value for each element: 256 x cycle[8:7] + cycle[6:0] diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series index ef5aed325e70d..78afd905d6348 100644 --- a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series +++ b/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series @@ -11,6 +11,7 @@ config SOC_SERIES config SOC_PART_NUMBER default "sam4s16c" if SOC_PART_NUMBER_SAM4S16C + default "sam4sa16c" if SOC_PART_NUMBER_SAM4SA16C default "sam4s16b" if SOC_PART_NUMBER_SAM4S16B default "sam4s8c" if SOC_PART_NUMBER_SAM4S8C default "sam4s8b" if SOC_PART_NUMBER_SAM4S8B diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.soc b/soc/arm/atmel_sam/sam4s/Kconfig.soc index 6ad8fe32d3b6d..c8c9dd9e21e4a 100644 --- a/soc/arm/atmel_sam/sam4s/Kconfig.soc +++ b/soc/arm/atmel_sam/sam4s/Kconfig.soc @@ -11,8 +11,8 @@ choice config SOC_PART_NUMBER_SAM4S16C bool "SAM4S16C" - config SOC_PART_NUMBER_SAM4S16C - bool "SAM4S16C" + config SOC_PART_NUMBER_SAM4SA16C + bool "SAM4SA16C" config SOC_PART_NUMBER_SAM4S16B bool "SAM4S16B" diff --git a/soc/arm/atmel_sam/sam4s/soc.h b/soc/arm/atmel_sam/sam4s/soc.h index a0ad721ef3444..e469c3ac19a72 100644 --- a/soc/arm/atmel_sam/sam4s/soc.h +++ b/soc/arm/atmel_sam/sam4s/soc.h @@ -26,6 +26,8 @@ #if defined(CONFIG_SOC_PART_NUMBER_SAM4S16C) #include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM4SA16C) +#include #elif defined(CONFIG_SOC_PART_NUMBER_SAM4S16B) #include #elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8C) diff --git a/tests/drivers/memc/stm32_sdram/CMakeLists.txt b/tests/drivers/memc/ram/CMakeLists.txt similarity index 100% rename from tests/drivers/memc/stm32_sdram/CMakeLists.txt rename to tests/drivers/memc/ram/CMakeLists.txt diff --git a/tests/drivers/memc/stm32_sdram/prj.conf b/tests/drivers/memc/ram/prj.conf similarity index 55% rename from tests/drivers/memc/stm32_sdram/prj.conf rename to tests/drivers/memc/ram/prj.conf index 4aba052c6b423..f4133ef834e56 100644 --- a/tests/drivers/memc/stm32_sdram/prj.conf +++ b/tests/drivers/memc/ram/prj.conf @@ -1,2 +1,3 @@ CONFIG_ZTEST=y CONFIG_MEMC=y +CONFIG_ZTEST_NEW_API=y diff --git a/tests/drivers/memc/ram/src/main.c b/tests/drivers/memc/ram/src/main.c new file mode 100644 index 0000000000000..c067df1352c95 --- /dev/null +++ b/tests/drivers/memc/ram/src/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020, Teslabs Engineering S.L. + * Copyright (c) 2022, Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/** Buffer size. */ +#define BUF_SIZE 64U +#define BUF_DEF(label) static uint32_t buf_##label[BUF_SIZE] \ + Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(label))) + +/** + * @brief Helper function to test RAM r/w. + * + * @param mem RAM memory location to be tested. + */ +static void test_ram_rw(uint32_t *mem) +{ + /* fill memory with number range (0, BUF_SIZE - 1) */ + for (size_t i = 0U; i < BUF_SIZE; i++) { + mem[i] = i; + } + + /* check that memory contains written range */ + for (size_t i = 0U; i < BUF_SIZE; i++) { + zassert_equal(mem[i], i, "Unexpected content"); + } +} + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) +BUF_DEF(sdram1); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay) +BUF_DEF(sdram2); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram1), okay) +BUF_DEF(sram1); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram2), okay) +BUF_DEF(sram2); +#endif + +ZTEST_SUITE(test_ram, NULL, NULL, NULL, NULL, NULL); + +ZTEST(test_ram, test_sdram1) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) + test_ram_rw(buf_sdram1); +#else + ztest_test_skip(); +#endif +} + +ZTEST(test_ram, test_sdram2) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay) + test_ram_rw(buf_sdram2); +#else + ztest_test_skip(); +#endif +} + +ZTEST(test_ram, test_sram1) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram1), okay) + test_ram_rw(buf_sram1); +#else + ztest_test_skip(); +#endif +} + +ZTEST(test_ram, test_sram2) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram2), okay) + test_ram_rw(buf_sram2); +#else + ztest_test_skip(); +#endif +} diff --git a/tests/drivers/memc/ram/testcase.yaml b/tests/drivers/memc/ram/testcase.yaml new file mode 100644 index 0000000000000..4ae0d070f77a5 --- /dev/null +++ b/tests/drivers/memc/ram/testcase.yaml @@ -0,0 +1,12 @@ +tests: + drivers.memc.stm32_sdram: + tags: drivers memc + depends_on: memc + filter: dt_compat_enabled("st,stm32-fmc-sdram") + drivers.memc.smc_sram: + tags: drivers memc + depends_on: memc + filter: dt_compat_enabled("atmel,sam-smc") + platform_allow: sam4s_xplained + integration_platforms: + - sam4s_xplained diff --git a/tests/drivers/memc/stm32_sdram/src/main.c b/tests/drivers/memc/stm32_sdram/src/main.c deleted file mode 100644 index 01a596307f047..0000000000000 --- a/tests/drivers/memc/stm32_sdram/src/main.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2020 Teslabs Engineering S.L. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/** Buffer size. */ -#define BUF_SIZE 64U - -/** - * @brief Helper function to test SDRAM r/w. - * - * @param mem SDRAM memory location to be tested. - */ -static void test_sdram_rw(uint32_t *mem) -{ - /* fill memory with number range (0, BUF_SIZE - 1) */ - for (size_t i = 0U; i < BUF_SIZE; i++) { - mem[i] = i; - } - - /* check that memory contains written range */ - for (size_t i = 0U; i < BUF_SIZE; i++) { - zassert_equal(mem[i], i, "Unexpected content"); - } -} - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) -/** Buffer on SDRAM1. */ -__stm32_sdram1_section uint32_t sdram1[BUF_SIZE]; - -static void test_sdram1_rw(void) -{ - test_sdram_rw(sdram1); -} -#else -static void test_sdram1_rw(void) -{ - ztest_test_skip(); -} -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay) -/** Buffer on SDRAM2. */ -__stm32_sdram2_section uint32_t sdram2[BUF_SIZE]; - -static void test_sdram2_rw(void) -{ - test_sdram_rw(sdram2); -} - -#else -static void test_sdram2_rw(void) -{ - ztest_test_skip(); -} -#endif - -void test_main(void) -{ - ztest_test_suite(stm32_sdram, - ztest_unit_test(test_sdram1_rw), - ztest_unit_test(test_sdram2_rw)); - ztest_run_test_suite(stm32_sdram); -} diff --git a/tests/drivers/memc/stm32_sdram/testcase.yaml b/tests/drivers/memc/stm32_sdram/testcase.yaml deleted file mode 100644 index 47087102086e6..0000000000000 --- a/tests/drivers/memc/stm32_sdram/testcase.yaml +++ /dev/null @@ -1,5 +0,0 @@ -tests: - drivers.memc.stm32_sdram: - tags: drivers memc - depends_on: memc - filter: dt_compat_enabled("st,stm32-fmc-sdram")