diff --git a/boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi b/boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi new file mode 100644 index 0000000000000..6249cc554dfd8 --- /dev/null +++ b/boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi @@ -0,0 +1,67 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK22FN512VLH12/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + ftm0_default: ftm0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart1_default: uart1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/frdm_k22f/frdm_k22f.dts b/boards/arm/frdm_k22f/frdm_k22f.dts index 8945d2675e4dc..216be97bbc4dd 100644 --- a/boards/arm/frdm_k22f/frdm_k22f.dts +++ b/boards/arm/frdm_k22f/frdm_k22f.dts @@ -6,8 +6,9 @@ /dts-v1/; -#include +#include #include +#include "frdm_k22f-pinctrl.dtsi" / { model = "NXP Freedom MK22F board"; @@ -124,7 +125,7 @@ }; arduino_i2c: &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SCL_PTB2 &I2C0_SDA_PTB3>; + pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; fxos8700@1c { @@ -136,18 +137,10 @@ arduino_i2c: &i2c0 { }; }; -&I2C0_SCL_PTB2 { - drive-open-drain; -}; - -&I2C0_SDA_PTB3 { - drive-open-drain; -}; arduino_spi: &spi0 { status = "okay"; - pinctrl-0 = <&SPI0_PCS4_PTC0 &SPI0_SCK_PTD1 - &SPI0_SOUT_PTD2 &SPI0_SIN_PTD3>; + pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; @@ -155,19 +148,19 @@ arduino_spi: &spi0 { status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM0_CH6_PTA1 &FTM0_CH7_PTA2 &FTM0_CH5_PTD5>; + pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; }; &uart1 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART1_RX_PTE1 &UART1_TX_PTE0>; + pinctrl-0 = <&uart1_default>; pinctrl-names = "default"; }; &uart2 { - pinctrl-0 = <&UART2_RX_PTD2 &UART2_TX_PTD3>; + pinctrl-0 = <&uart2_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/frdm_k22f/frdm_k22f_defconfig b/boards/arm/frdm_k22f/frdm_k22f_defconfig index 2a75977de6f1c..ec3700a8e2a6d 100644 --- a/boards/arm/frdm_k22f/frdm_k22f_defconfig +++ b/boards/arm/frdm_k22f/frdm_k22f_defconfig @@ -14,5 +14,6 @@ CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_PINMUX=y +CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/arm/frdm_k22f/pinmux.c b/boards/arm/frdm_k22f/pinmux.c index 1342f91df9d29..8a2209bf34731 100644 --- a/boards/arm/frdm_k22f/pinmux.c +++ b/boards/arm/frdm_k22f/pinmux.c @@ -38,22 +38,6 @@ static int frdm_k22f_pinmux_init(const struct device *dev) __ASSERT_NO_MSG(device_is_ready(porte)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL -#error "No UART0 is used" -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) && CONFIG_SERIAL - /* UART1 RX, TX */ - pinmux_pin_set(porte, 0, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(porte, 1, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) && CONFIG_SERIAL - /* UART2 RX, TX */ - pinmux_pin_set(portd, 2, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portd, 3, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ftm0), nxp_kinetis_ftm_pwm, okay) && CONFIG_PWM /* Red, green, blue LEDs as PWM channels*/ pinmux_pin_set(porta, 1, PORT_PCR_MUX(kPORT_MuxAlt3)); diff --git a/boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi b/boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi new file mode 100644 index 0000000000000..010677c5ed8f7 --- /dev/null +++ b/boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi @@ -0,0 +1,130 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK64FN1M0VLL12/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + enet_default: enet_default { + group0 { + pinmux = ; + drive-strength = "high"; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + drive-open-drain; + bias-pull-up; + slew-rate = "fast"; + }; + group2 { + pinmux = , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + flexcan0_default: flexcan0_default { + group0 { + pinmux = ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + ftm0_default: ftm0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + ftm3_default: ftm3_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + ptp_default: ptp_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart3_default: uart3_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/frdm_k64f/frdm_k64f.dts b/boards/arm/frdm_k64f/frdm_k64f.dts index 90f4368e9dbe9..cc5498644e695 100644 --- a/boards/arm/frdm_k64f/frdm_k64f.dts +++ b/boards/arm/frdm_k64f/frdm_k64f.dts @@ -2,7 +2,8 @@ /dts-v1/; -#include +#include +#include "frdm_k64f-pinctrl.dtsi" / { model = "NXP Freedom MK64F board"; @@ -95,7 +96,7 @@ arduino_serial: &uart3 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART3_RX_PTC16 &UART3_TX_PTC17>; + pinctrl-0 = <&uart3_default>; pinctrl-names = "default"; }; @@ -122,7 +123,7 @@ arduino_serial: &uart3 { arduino_i2c: &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SCL_PTE24 &I2C0_SDA_PTE25>; + pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; fxos8700@1d { @@ -136,7 +137,7 @@ arduino_i2c: &i2c0 { arduino_spi: &spi0 { status = "okay"; - pinctrl-0 = <&SPI0_PCS0_PTD0 &SPI0_SCK_PTD1 &SPI0_SOUT_PTD2 &SPI0_SIN_PTD3>; + pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; @@ -144,7 +145,7 @@ arduino_spi: &spi0 { status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM0_CH0_PTC1>; + pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; }; @@ -152,19 +153,19 @@ arduino_spi: &spi0 { status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM3_CH4_PTC8 &FTM3_CH5_PTC9>; + pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; }; &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTB16 &UART0_TX_PTB17>; + pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; }; &uart2 { - pinctrl-0 = <&UART2_RTS_b_PTD0 &UART2_CTS_b_PTD1 &UART2_RX_PTD2 &UART2_TX_PTD3>; + pinctrl-0 = <&uart2_default>; pinctrl-names = "default"; }; @@ -234,37 +235,23 @@ zephyr_udc0: &usbotg { &enet { status = "okay"; - pinctrl-0 = <&RMII0_RXER_PTA5 &RMII0_RXD1_PTA12 - &RMII0_RXD0_PTA13 &RMII0_CRS_DV_PTA14 - &RMII0_TXEN_PTA15 &RMII0_TXD0_PTA16 - &RMII0_TXD1_PTA17 &RMII0_MDIO_PTB0 - &RMII0_MDC_PTB1>; + pinctrl-0 = <&enet_default>; pinctrl-names = "default"; ptp { /* Be aware that PTC16 and PTC17 are also used for uart3 */ status = "disabled"; - pinctrl-0 = <&ENET0_1588_TMR0_PTC16 &ENET0_1588_TMR1_PTC17 - &ENET0_1588_TMR2_PTC18>; + pinctrl-0 = <&ptp_default>; pinctrl-names = "default"; }; }; -&RMII0_MDIO_PTB0 { - bias-pull-up; - drive-open-drain; -}; - &flexcan0 { status = "okay"; - pinctrl-0 = <&CAN0_TX_PTB18 &CAN0_RX_PTB19>; + pinctrl-0 = <&flexcan0_default>; pinctrl-names = "default"; bus-speed = <125000>; }; -&CAN0_RX_PTB19 { - bias-pull-up; -}; - &edma0 { status = "okay"; }; diff --git a/boards/arm/frdm_k64f/frdm_k64f_defconfig b/boards/arm/frdm_k64f/frdm_k64f_defconfig index ccc33805b16ea..fe9709f583502 100644 --- a/boards/arm/frdm_k64f/frdm_k64f_defconfig +++ b/boards/arm/frdm_k64f/frdm_k64f_defconfig @@ -7,6 +7,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y +CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/frdm_k64f/pinmux.c b/boards/arm/frdm_k64f/pinmux.c index 4a718226f9801..e4f02265bed4a 100644 --- a/boards/arm/frdm_k64f/pinmux.c +++ b/boards/arm/frdm_k64f/pinmux.c @@ -38,26 +38,6 @@ static int frdm_k64f_pinmux_init(const struct device *dev) __ASSERT_NO_MSG(device_is_ready(porte)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL - /* UART0 RX, TX */ - pinmux_pin_set(portb, 16, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portb, 17, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) && CONFIG_SERIAL - /* UART2 RX, TX */ - pinmux_pin_set(portd, 0, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portd, 1, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portd, 2, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portd, 3, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay) && CONFIG_SERIAL - /* UART3 RX, TX */ - pinmux_pin_set(portc, 16, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 17, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(spi0), okay) && CONFIG_SPI /* SPI0 CS0, SCK, SOUT, SIN */ pinmux_pin_set(portd, 0, PORT_PCR_MUX(kPORT_MuxAlt2)); diff --git a/boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi b/boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi new file mode 100644 index 0000000000000..1859bb91ddd18 --- /dev/null +++ b/boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi @@ -0,0 +1,83 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK82FN256VLL15/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + ftm3_default: ftm3_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + i2c3_default: i2c3_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + bias-pull-up; + slew-rate = "fast"; + }; + }; + + lpuart4_default: lpuart4_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi1_default: spi1_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/frdm_k82f/frdm_k82f.dts b/boards/arm/frdm_k82f/frdm_k82f.dts index 8256980d43a6f..1f27d0a1c7fdc 100644 --- a/boards/arm/frdm_k82f/frdm_k82f.dts +++ b/boards/arm/frdm_k82f/frdm_k82f.dts @@ -7,8 +7,9 @@ /dts-v1/; #include -#include +#include #include +#include "frdm_k82f-pinctrl.dtsi" / { model = "NXP Kinetis K82 Freedom Board"; @@ -113,7 +114,7 @@ &adc0 { status = "okay"; - pinctrl-0 = <&ADC0_SE15_PTC1>; + pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; @@ -169,7 +170,7 @@ &i2c3 { status = "okay"; - pinctrl-0 = <&I2C3_SDA_PTA1 &I2C3_SCL_PTA2>; + pinctrl-0 = <&i2c3_default>; pinctrl-names = "default"; fxos8700@1c { @@ -180,17 +181,9 @@ }; }; -&I2C3_SDA_PTA1 { - drive-open-drain; -}; - -&I2C3_SCL_PTA2 { - drive-open-drain; -}; - &lpuart4 { status = "okay"; - pinctrl-0 = <&LPUART4_RX_PTC14 &LPUART4_TX_PTC15>; + pinctrl-0 = <&lpuart4_default>; pinctrl-names = "default"; current-speed = <115200>; }; @@ -199,15 +192,14 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM3_CH4_PTC8 &FTM3_CH5_PTC9 &FTM3_CH6_PTC10>; + pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; }; &spi1 { status = "okay"; - pinctrl-0 = <&SPI1_SCK_PTE1 &SPI1_SOUT_PTE2 - &SPI1_SIN_PTE4 &SPI1_PCS0_PTE5>; + pinctrl-0 = <&spi1_default>; pinctrl-names = "default"; mx25u32: mx25u3235f@0 { @@ -240,20 +232,12 @@ zephyr_udc0: &usbotg { arduino_i2c: &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SDA_PTB3 &I2C0_SCL_PTB2>; + pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; }; -&I2C0_SDA_PTB3 { - drive-open-drain; -}; - -&I2C0_SCL_PTB2 { - drive-open-drain; -}; - arduino_spi: &spi0 { status = "okay"; - pinctrl-0 = <&SPI0_SCK_PTD1 &SPI0_SOUT_PTD2 &SPI0_SIN_PTD3 &SPI0_PCS1_PTD4>; + pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/frdm_k82f/frdm_k82f_defconfig b/boards/arm/frdm_k82f/frdm_k82f_defconfig index 547fa979d2746..4e072b2384b27 100644 --- a/boards/arm/frdm_k82f/frdm_k82f_defconfig +++ b/boards/arm/frdm_k82f/frdm_k82f_defconfig @@ -8,6 +8,7 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_PINMUX=y +CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/arm/frdm_k82f/pinmux.c b/boards/arm/frdm_k82f/pinmux.c index ce7441608881f..606aa5e1e929f 100644 --- a/boards/arm/frdm_k82f/pinmux.c +++ b/boards/arm/frdm_k82f/pinmux.c @@ -77,12 +77,6 @@ static int frdm_k82f_pinmux_init(const struct device *dev) pinmux_pin_set(portd, 4, PORT_PCR_MUX(kPORT_MuxAlt2)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart4), okay) && CONFIG_SERIAL - /* LPUART4 RX, TX */ - pinmux_pin_set(portc, 14, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 15, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(adc0), okay) && CONFIG_ADC /* ADC0_SE15 */ pinmux_pin_set(portc, 1, PORT_PCR_MUX(kPORT_PinDisabledOrAnalog)); diff --git a/boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi b/boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi new file mode 100644 index 0000000000000..925aaf7fafe52 --- /dev/null +++ b/boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi @@ -0,0 +1,39 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MKL25Z128VLK4/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + +}; diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.dts b/boards/arm/frdm_kl25z/frdm_kl25z.dts index aacef5c9b792b..f15690d483c4d 100644 --- a/boards/arm/frdm_kl25z/frdm_kl25z.dts +++ b/boards/arm/frdm_kl25z/frdm_kl25z.dts @@ -2,7 +2,8 @@ /dts-v1/; -#include +#include +#include "frdm_kl25z-pinctrl.dtsi" / { model = "NXP Freedom KL25Z board"; @@ -92,13 +93,13 @@ &adc0 { status = "okay"; - pinctrl-0 = <&ADC0_SE12_PTB2>; + pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SCL_PTE24 &I2C0_SDA_PTE25>; + pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; mma8451q@1d { @@ -110,18 +111,10 @@ }; }; -&I2C0_SCL_PTE24 { - bias-pull-up; -}; - -&I2C0_SDA_PTE25 { - bias-pull-up; -}; - &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTA1 &UART0_TX_PTA2>; + pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig b/boards/arm/frdm_kl25z/frdm_kl25z_defconfig index 5d23d4b22d7c1..9e109926a477e 100644 --- a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig +++ b/boards/arm/frdm_kl25z/frdm_kl25z_defconfig @@ -7,5 +7,6 @@ CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_PINMUX=y +CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/arm/frdm_kl25z/pinmux.c b/boards/arm/frdm_kl25z/pinmux.c index 8ecd70c62a944..d2fb116d9fc07 100644 --- a/boards/arm/frdm_kl25z/pinmux.c +++ b/boards/arm/frdm_kl25z/pinmux.c @@ -38,12 +38,6 @@ static int frdm_kl25z_pinmux_init(const struct device *dev) __ASSERT_NO_MSG(device_is_ready(porte)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL - /* UART0 RX, TX */ - pinmux_pin_set(porta, 1, PORT_PCR_MUX(kPORT_MuxAlt2)); - pinmux_pin_set(porta, 2, PORT_PCR_MUX(kPORT_MuxAlt2)); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) && CONFIG_I2C /* I2C0 SCL, SDA */ pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt5) diff --git a/boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi b/boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi new file mode 100644 index 0000000000000..2377304c5c193 --- /dev/null +++ b/boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi @@ -0,0 +1,71 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MKW41Z512VHT4/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + i2c1_default: i2c1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpuart0_default: lpuart0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + tmp2_default: tmp2_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + tpm0_default: tpm0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + +}; diff --git a/boards/arm/frdm_kw41z/frdm_kw41z.dts b/boards/arm/frdm_kw41z/frdm_kw41z.dts index 60db2110720c2..e2ef4cfdad5ba 100644 --- a/boards/arm/frdm_kw41z/frdm_kw41z.dts +++ b/boards/arm/frdm_kw41z/frdm_kw41z.dts @@ -2,7 +2,8 @@ /dts-v1/; -#include +#include +#include "frdm_kw41z-pinctrl.dtsi" / { model = "NXP Freedom KW41Z board"; @@ -109,13 +110,13 @@ &adc0 { status = "okay"; - pinctrl-0 = <&ADC0_SE3_PTB2>; + pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; &i2c1 { status = "okay"; - pinctrl-0 = <&I2C1_SCL_PTC2 &I2C1_SDA_PTC3>; + pinctrl-0 = <&i2c1_default>; pinctrl-names = "default"; fxos8700@1f { @@ -126,17 +127,9 @@ }; }; -&I2C1_SCL_PTC2 { - bias-pull-up; -}; - -&I2C1_SDA_PTC3 { - bias-pull-up; -}; - &lpuart0 { status = "okay"; - pinctrl-0 = <&UART0_RX_PTC6 &UART0_TX_PTC7>; + pinctrl-0 = <&lpuart0_default>; pinctrl-names = "default"; current-speed = <115200>; }; @@ -151,14 +144,13 @@ &spi0 { status = "okay"; - pinctrl-0 = <&SPI0_SCK_PTC16 &SPI0_SOUT_PTC17 - &SPI0_SIN_PTC18 &SPI0_PCS0_PTC19>; + pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; &tpm0 { status = "okay"; - pinctrl-0 = <&TPM0_CH2_PTC1>; + pinctrl-0 = <&tpm0_default>; pinctrl-names = "default"; }; @@ -168,6 +160,6 @@ &tpm2 { status = "okay"; - pinctrl-0 = <&TPM2_CH1_PTA19 &TPM2_CH0_PTA18>; + pinctrl-0 = <&tmp2_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi b/boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi new file mode 100644 index 0000000000000..255e1df394247 --- /dev/null +++ b/boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi @@ -0,0 +1,60 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK64FN1M0VDC12/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + ftm3_default: ftm3_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + i2c1_default: i2c1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart4_default: uart4_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.dts b/boards/arm/hexiwear_k64/hexiwear_k64.dts index 750d77c3969cc..e1ab79c3a752c 100644 --- a/boards/arm/hexiwear_k64/hexiwear_k64.dts +++ b/boards/arm/hexiwear_k64/hexiwear_k64.dts @@ -2,8 +2,9 @@ /dts-v1/; -#include +#include #include +#include "hexiwear_k64-pinctrl.dtsi" / { model = "Hexiwear K64 board"; @@ -80,13 +81,13 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM3_CH4_PTC8 &FTM3_CH5_PTC9 &FTM3_CH0_PTD0>; + pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; }; &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SCL_PTB0 &I2C0_SDA_PTB1>; + pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; max30101@57 { @@ -97,17 +98,9 @@ }; }; -&I2C0_SCL_PTB0 { - drive-open-drain; -}; - -&I2C0_SDA_PTB1 { - drive-open-drain; -}; - &i2c1 { status = "okay"; - pinctrl-0 = <&I2C1_SCL_PTC10 &I2C1_SDA_PTC11>; + pinctrl-0 = <&i2c1_default>; pinctrl-names = "default"; fxos8700@1e { @@ -127,25 +120,17 @@ }; }; -&I2C1_SCL_PTC10 { - drive-open-drain; -}; - -&I2C1_SDA_PTC11 { - drive-open-drain; -}; - &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTB16 &UART0_TX_PTB17>; + pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; }; &uart4 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART4_RX_PTE25 &UART4_TX_PTE24>; + pinctrl-0 = <&uart4_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig index 5f3c7e633fa27..020ca2b9a857c 100644 --- a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig +++ b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig @@ -9,6 +9,7 @@ CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_PINMUX=y +CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_LOW_POWER=y CONFIG_ARM_MPU=y diff --git a/boards/arm/hexiwear_k64/pinmux.c b/boards/arm/hexiwear_k64/pinmux.c index aa1c8a9593439..d593f7271c6cc 100644 --- a/boards/arm/hexiwear_k64/pinmux.c +++ b/boards/arm/hexiwear_k64/pinmux.c @@ -62,18 +62,6 @@ static int hexiwear_k64_pinmux_init(const struct device *dev) | PORT_PCR_ODE_MASK); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL - /* UART0 RX, TX */ - pinmux_pin_set(portb, 16, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portb, 17, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay) && CONFIG_SERIAL - /* UART4 RX, TX - BLE */ - pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(porte, 25, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - #if defined(CONFIG_MAX30101) && DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) const struct device *gpioa = device_get_binding(DT_LABEL(DT_NODELABEL(gpioa))); diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi b/boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi new file mode 100644 index 0000000000000..7027089321619 --- /dev/null +++ b/boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + lpuart0_default: lpuart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts index 75994a3fcd0ce..2b64e0bafd534 100644 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts +++ b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts @@ -2,7 +2,8 @@ /dts-v1/; -#include +#include +#include "hexiwear_kw40z-pinctrl.dtsi" / { model = "Hexiwear KW40 board"; @@ -21,14 +22,14 @@ &adc0 { status = "okay"; - pinctrl-0 = <&ADC0_SE1_PTB1>; + pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; &lpuart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTC6 &UART0_TX_PTC7>; + pinctrl-0 = <&lpuart0_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi b/boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi new file mode 100644 index 0000000000000..675f200c4cfc0 --- /dev/null +++ b/boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK66FN2M0VMD18/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + enet_default: enet_default { + group0 { + pinmux = , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi1_default: spi1_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/ip_k66f/ip_k66f.dts b/boards/arm/ip_k66f/ip_k66f.dts index d83b19047d310..3eb2e1f60dc35 100644 --- a/boards/arm/ip_k66f/ip_k66f.dts +++ b/boards/arm/ip_k66f/ip_k66f.dts @@ -6,7 +6,9 @@ /dts-v1/; -#include +#include + +#include "ip_k66f-pinctrl.dtsi" / { model = "SEGGER MK66F IP Switch board"; @@ -103,10 +105,7 @@ &enet { status = "okay"; - pinctrl-0 = <&RMII0_RXD1_PTA12 &RMII0_RXD0_PTA13 - &RMII0_CRS_DV_PTA14 &RMII0_TXEN_PTA15 - &RMII0_TXD0_PTA16 &RMII0_TXD1_PTA17 - &ENET_1588_CLKIN_PTE26 /* used for RMII ref clk */>; + pinctrl-0 = <&enet_default>; pinctrl-names = "default"; fixed-link { @@ -117,8 +116,7 @@ &spi1 { status = "okay"; - pinctrl-0 = <&SPI1_PCS0_PTB10 &SPI1_SCK_PTB11 - &SPI1_SOUT_PTB16 &SPI1_SIN_PTB17>; + pinctrl-0 = <&spi1_default>; pinctrl-names = "default"; clock-frequency = <44000000>; diff --git a/boards/arm/ip_k66f/ip_k66f_defconfig b/boards/arm/ip_k66f/ip_k66f_defconfig index 406deae4273d9..891223c055e29 100644 --- a/boards/arm/ip_k66f/ip_k66f_defconfig +++ b/boards/arm/ip_k66f/ip_k66f_defconfig @@ -6,6 +6,7 @@ CONFIG_BOARD_IP_K66F=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_PINMUX=y +CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 CONFIG_OSC_LOW_POWER=y CONFIG_USE_SEGGER_RTT=y diff --git a/boards/arm/rddrone_fmuk66/pinmux.c b/boards/arm/rddrone_fmuk66/pinmux.c index 45e13b6ac092e..755c93c8ed0aa 100644 --- a/boards/arm/rddrone_fmuk66/pinmux.c +++ b/boards/arm/rddrone_fmuk66/pinmux.c @@ -46,32 +46,6 @@ static int rddrone_fmuk66_pinmux_init(const struct device *dev) pinmux_pin_set(portd, 9, PORT_PCR_MUX(kPORT_MuxAlt5)); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL - /* UART0 RX, TX */ - pinmux_pin_set(porta, 1, PORT_PCR_MUX(kPORT_MuxAlt2)); - pinmux_pin_set(porta, 2, PORT_PCR_MUX(kPORT_MuxAlt2)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) && CONFIG_SERIAL - /* UART1 RX, TX */ - pinmux_pin_set(portc, 3, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 4, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) && CONFIG_SERIAL - /* UART1 RX, TX */ - pinmux_pin_set(portd, 2, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portd, 3, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay) && CONFIG_SERIAL - /* UART1 RTS, CTS, RX, TX */ - pinmux_pin_set(porte, 27, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 13, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 14, PORT_PCR_MUX(kPORT_MuxAlt3)); - pinmux_pin_set(portc, 15, PORT_PCR_MUX(kPORT_MuxAlt3)); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan0), okay) && CONFIG_CAN /* CAN0 TX, RX */ pinmux_pin_set(portb, 18, PORT_PCR_MUX(kPORT_MuxAlt2)); diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi b/boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi new file mode 100644 index 0000000000000..49383e232bbbc --- /dev/null +++ b/boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi @@ -0,0 +1,191 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MK66FN2M0VMD18/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + enet_default: enet_default { + group0 { + pinmux = ; + drive-strength = "low"; + drive-open-drain; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = , + , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + flexcan0_default: flexcan0_default { + group0 { + pinmux = ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + flexcan1_default: flexcan1_default { + group0 { + pinmux = ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + ftm0_default: ftm0_default { + group0 { + pinmux = ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + ftm3_default: ftm3_default { + group0 { + pinmux = , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + i2c1_default: i2c1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + lpuart0_default: lpuart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi1_default: spi1_default { + group0 { + pinmux = , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + spi2_default: spi2_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "fast"; + }; + }; + + uart1_default: uart1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + uart4_default: uart4_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts index dcbfcbe660860..022376d687b37 100644 --- a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts @@ -1,13 +1,14 @@ /* - * Copyright (c) 2021, Electromaticus LLC, 2021 NXP + * Copyright (c) 2021, Electromaticus LLC, 2022 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include +#include "rddrone_fmuk66-pinctrl.dtsi" / { model = "NXP RDDRONE FMUK66 board"; @@ -89,7 +90,8 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM0_CH0_PTC1 &FTM0_CH1_PTA4 &FTM0_CH4_PTD4 &FTM0_CH5_PTD5>; + pinctrl-0 = <&ftm0_default>; + pinctrl-names = "default"; }; @@ -98,14 +100,16 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM3_CH3_PTD3 &FTM3_CH4_PTC8 &FTM3_CH5_PTC9 &FTM3_CH6_PTE11 &FTM3_CH7_PTE12>; + pinctrl-0 = <&ftm3_default>; + pinctrl-names = "default"; }; /* LPUART connected to debug header */ &lpuart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&LPUART0_RX_PTD8 &LPUART0_TX_PTD9>; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; }; zephyr_udc0: &usbotg { @@ -117,25 +121,29 @@ zephyr_udc0: &usbotg { &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTA1 &UART0_TX_PTA2>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; }; &uart1 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART1_RX_PTC3 &UART1_TX_PTC4>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; }; &uart2 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART2_RX_PTD2 &UART2_TX_PTD3>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; }; &uart4 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART4_RTS_b_PTE27 &UART4_CTS_b_PTC13 &UART4_RX_PTC14 &UART4_TX_PTC15>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; }; &usbotg { @@ -204,42 +212,29 @@ zephyr_udc0: &usbotg { &enet { status = "okay"; - pinctrl-0 = <&RMII0_RXER_PTA5 &RMII0_RXD1_PTA12 - &RMII0_RXD0_PTA13 &RMII0_CRS_DV_PTA14 - &RMII0_TXEN_PTA15 &RMII0_TXD0_PTA16 - &RMII0_TXD1_PTA17 &RMII0_MDIO_PTB0 - &RMII0_MDC_PTB1>; -}; - -&RMII0_MDIO_PTB0 { - bias-pull-up; - drive-open-drain; + pinctrl-0 = <&enet_default>; + pinctrl-names = "default"; }; &flexcan0 { status = "okay"; - pinctrl-0 = <&CAN0_TX_PTB18 &CAN0_RX_PTB19>; + pinctrl-0 = <&flexcan0_default>; + pinctrl-names = "default"; bus-speed = <125000>; }; -&CAN0_RX_PTB19 { - bias-pull-up; -}; - &flexcan1 { status = "okay"; - pinctrl-0 = <&CAN1_TX_PTC17 &CAN1_RX_PTC16>; + pinctrl-0 = <&flexcan1_default>; + pinctrl-names = "default"; bus-speed = <125000>; }; -&CAN1_RX_PTC16 { - bias-pull-up; -}; - /* external i2c port */ &i2c0 { status = "okay"; - pinctrl-0 = <&I2C0_SCL_PTE24 &I2C0_SDA_PTE25>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; }; /* magnetometer (bmm150), barometer (bmp280), pressure (mpl3115), @@ -247,26 +242,29 @@ zephyr_udc0: &usbotg { */ &i2c1 { status = "okay"; - pinctrl-0 = <&I2C1_SCL_PTC10 &I2C1_SDA_PTC11>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; }; /* f-ram spi port */ &spi0 { status = "okay"; - pinctrl-0 = <&SPI0_PCS2_PTC2 &SPI0_SCK_PTC5 &SPI0_SOUT_PTC6 &SPI0_SIN_PTC7>; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; }; /* flash (w25x40), accel, magneto (fxos8700), gyro (fxas2100) */ &spi1 { status = "okay"; - pinctrl-0 = <&SPI1_PCS0_PTB10 &SPI1_PCS1_PTB9 &SPI1_SCK_PTB11 - &SPI1_SOUT_PTB16 &SPI1_SIN_PTB17>; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; }; /* external spi */ &spi2 { status = "okay"; - pinctrl-0 = <&SPI2_PCS0_PTB20 &SPI2_SCK_PTB21 &SPI2_SOUT_PTB22 &SPI2_SIN_PTB23>; + pinctrl-0 = <&spi2_default>; + pinctrl-names = "default"; }; &edma0 { diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig b/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig index 9f87aeca3042d..759bbd8276488 100644 --- a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig +++ b/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig @@ -7,6 +7,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y +CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=160000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi b/boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi new file mode 100644 index 0000000000000..18e95254b9033 --- /dev/null +++ b/boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi @@ -0,0 +1,123 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MKE18F512VLL16/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + dac0_default: dac0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + flexcan0_default: flexcan0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + ftm0_default: ftm0_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + ftm3_default: ftm3_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpi2c0_default: lpi2c0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpi2c1_default: lpi2c1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpspi0_default: lpspi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpspi1_default: lpspi1_default { + group0 { + pinmux = ; + drive-strength = "low"; + bias-pull-up; + slew-rate = "slow"; + }; + group1 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpuart0_default: lpuart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + sim0_default: sim0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + +}; diff --git a/boards/arm/twr_ke18f/twr_ke18f.dts b/boards/arm/twr_ke18f/twr_ke18f.dts index f2ce5b15bfbaa..82a4b4a6a940c 100644 --- a/boards/arm/twr_ke18f/twr_ke18f.dts +++ b/boards/arm/twr_ke18f/twr_ke18f.dts @@ -6,9 +6,10 @@ /dts-v1/; -#include +#include #include #include +#include "twr_ke18f-pinctrl.dtsi" / { model = "NXP Kinetis KE18 MCU Tower System Module"; @@ -139,7 +140,7 @@ &sim { clkout-source = <1>; clkout-divider = <0>; - pinctrl-0 = <&CLKOUT_PTE10>; + pinctrl-0 = <&sim0_default>; pinctrl-names = "default"; }; @@ -207,7 +208,7 @@ &lpuart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&LPUART0_RX_PTB0 &LPUART0_TX_PTB1>; + pinctrl-0 = <&lpuart0_default>; pinctrl-names = "default"; }; @@ -215,7 +216,7 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM0_CH0_PTD15 &FTM0_CH1_PTD16 &FTM0_CH5_PTB5>; + pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; }; @@ -223,14 +224,13 @@ status = "okay"; compatible = "nxp,kinetis-ftm-pwm"; #pwm-cells = <3>; - pinctrl-0 = <&FTM3_CH4_PTC10 &FTM3_CH5_PTC11 - &FTM3_CH6_PTC12 &FTM3_CH7_PTC13>; + pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; }; &lpi2c0 { status = "okay"; - pinctrl-0 = <&LPI2C0_SDA_PTA2 &LPI2C0_SCL_PTA3>; + pinctrl-0 = <&lpi2c0_default>; pinctrl-names = "default"; fxos8700: fxos8700@1d { @@ -243,34 +243,32 @@ &lpi2c1 { status = "okay"; - pinctrl-0 = <&LPI2C1_SDA_PTD8 &LPI2C1_SCL_PTD9>; + pinctrl-0 = <&lpi2c1_default>; pinctrl-names = "default"; }; &lpspi0 { status = "okay"; - pinctrl-0 = <&LPSPI0_SCK_PTE0 &LPSPI0_SIN_PTE1 - &LPSPI0_SOUT_PTE2 &LPSPI0_PCS2_PTE6>; + pinctrl-0 = <&lpspi0_default>; pinctrl-names = "default"; }; &lpspi1 { status = "okay"; - pinctrl-0 = <&LPSPI1_SCK_PTD0 &LPSPI1_SIN_PTD1 - &LPSPI1_SOUT_PTD2 &LPSPI1_PCS0_PTD3>; + pinctrl-0 = <&lpspi1_default>; pinctrl-names = "default"; }; &dac0 { status = "okay"; - pinctrl-0 = <&DAC0_OUT_PTE9>; + pinctrl-0 = <&dac0_default>; pinctrl-names = "default"; }; &adc0 { status = "okay"; sample-time = <12>; - pinctrl-0 = <&ADC0_SE0_PTA0 &ADC0_SE1_PTA1 &ADC0_SE12_PTC14>; + pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; @@ -281,7 +279,7 @@ &flexcan0 { status = "okay"; bus-speed = <125000>; - pinctrl-0 = <&CAN0_RX_PTE4 &CAN0_TX_PTE5>; + pinctrl-0 = <&flexcan0_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi b/boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi new file mode 100644 index 0000000000000..2495acc5e4103 --- /dev/null +++ b/boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi @@ -0,0 +1,32 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MKV58F1M0VLQ24/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + i2c1_default: i2c1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; + + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m.dts b/boards/arm/twr_kv58f220m/twr_kv58f220m.dts index 85068b1d782ba..87b4bf6654fa5 100644 --- a/boards/arm/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/arm/twr_kv58f220m/twr_kv58f220m.dts @@ -6,7 +6,8 @@ /dts-v1/; -#include +#include +#include "twr_kv58f220m-pinctrl.dtsi" / { model = "NXP Kinetis KV58 MCU Tower System Module"; @@ -131,7 +132,7 @@ &i2c1 { status = "okay"; - pinctrl-0 = <&I2C1_SCL_PTD8 &I2C1_SDA_PTD9>; + pinctrl-0 = <&i2c1_default>; pinctrl-names = "default"; fxos8700@1c { @@ -143,17 +144,9 @@ }; }; -&I2C1_SCL_PTD8 { - drive-open-drain; -}; - -&I2C1_SDA_PTD9 { - drive-open-drain; -}; - &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTB0 &UART0_TX_PTB1>; + pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; }; diff --git a/boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi b/boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi new file mode 100644 index 0000000000000..143c28cff93d5 --- /dev/null +++ b/boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * NOTE: Autogenerated file by kinetis_signal2dts.py + * for MKW24D512VHA5/signal_configuration.xml + * + * Copyright (c) 2022, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + uart0_default: uart0_default { + group0 { + pinmux = , + ; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.dts b/boards/arm/usb_kw24d512/usb_kw24d512.dts index 6041e5d01428b..59597dcd627e6 100644 --- a/boards/arm/usb_kw24d512/usb_kw24d512.dts +++ b/boards/arm/usb_kw24d512/usb_kw24d512.dts @@ -2,7 +2,8 @@ /dts-v1/; -#include +#include +#include "usb_kw24d512-pinctrl.dtsi" / { model = "NXP USB-KW24D512 board"; @@ -59,7 +60,7 @@ &uart0 { status = "okay"; current-speed = <115200>; - pinctrl-0 = <&UART0_RX_PTA1 &UART0_TX_PTA2>; + pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; }; diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 8e3bf4df6d88e..0fd6d21796ff5 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -10,3 +10,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 96adf043b058a..9ae5df91103cc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -35,5 +35,6 @@ source "drivers/pinctrl/Kconfig.nrf" source "drivers/pinctrl/Kconfig.rcar" source "drivers/pinctrl/Kconfig.rpi_pico" source "drivers/pinctrl/Kconfig.stm32" +source "drivers/pinctrl/Kconfig.kinetis" endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.kinetis b/drivers/pinctrl/Kconfig.kinetis new file mode 100644 index 0000000000000..d8265eb05a5d8 --- /dev/null +++ b/drivers/pinctrl/Kconfig.kinetis @@ -0,0 +1,11 @@ +# Copyright (c) 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +DT_COMPAT_NXP_KINETIS_PINCTRL := nxp,kinetis-pinctrl + +config PINCTRL_NXP_KINETIS + bool "Pin controller driver for NXP Kinetis MCUs" + depends on SOC_FAMILY_KINETIS + default $(dt_compat_enabled,$(DT_COMPAT_NXP_KINETIS_PINCTRL)) + help + Enable pin controller driver for NXP Kinetis MCUs diff --git a/drivers/pinctrl/pinctrl_kinetis.c b/drivers/pinctrl/pinctrl_kinetis.c new file mode 100644 index 0000000000000..78df9c4b90e41 --- /dev/null +++ b/drivers/pinctrl/pinctrl_kinetis.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#define DT_DRV_COMPAT nxp_kinetis_pinmux + +#include +#include + +/* Port register addresses. */ +static PORT_Type *ports[] = { + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)), + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)), + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)), +#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 5 + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)), + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)), +#endif +}; + +#define PIN(mux) (((mux) & 0xFC00000) >> 22) +#define PORT(mux) (((mux) & 0xF0000000) >> 28) +#define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK) + +struct pinctrl_mcux_config { + clock_ip_name_t clock_ip_name; +}; + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, + uintptr_t reg) +{ + for (uint8_t i = 0; i < pin_cnt; i++) { + PORT_Type *base = ports[PORT(pins[i])]; + uint8_t pin = PIN(pins[i]); + uint16_t mux = PINCFG(pins[i]); + + base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_KINETIS_PCR_MASK)) | mux; + } + return 0; +} + +/* Kinetis pinmux driver binds to the same DTS nodes, + * and handles clock init. Only bind to these nodes if pinmux driver + * is disabled. + */ +#ifndef CONFIG_PINMUX +static int pinctrl_mcux_init(const struct device *dev) +{ + const struct pinctrl_mcux_config *config = dev->config; + + CLOCK_EnableClock(config->clock_ip_name); + + return 0; +} + +#if DT_NODE_HAS_STATUS(DT_INST(0, nxp_kinetis_ke1xf_sim), okay) +#define INST_DT_CLOCK_IP_NAME(n) \ + DT_REG_ADDR(DT_INST_PHANDLE(n, clocks)) + DT_INST_CLOCKS_CELL(n, name) +#else +#define INST_DT_CLOCK_IP_NAME(n) \ + CLK_GATE_DEFINE(DT_INST_CLOCKS_CELL(n, offset), \ + DT_INST_CLOCKS_CELL(n, bits)) +#endif + +#define PINCTRL_MCUX_INIT(n) \ + static const struct pinctrl_mcux_config pinctrl_mcux_##n##_config = {\ + .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, \ + &pinctrl_mcux_init, \ + NULL, \ + NULL, &pinctrl_mcux_##n##_config, \ + PRE_KERNEL_1, \ + 0, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(PINCTRL_MCUX_INIT) +#endif diff --git a/drivers/serial/uart_mcux.c b/drivers/serial/uart_mcux.c index 0e9ca5c097291..3eba34113e5fe 100644 --- a/drivers/serial/uart_mcux.c +++ b/drivers/serial/uart_mcux.c @@ -13,6 +13,9 @@ #include #include #include +#ifdef CONFIG_PINCTRL +#include +#endif struct uart_mcux_config { UART_Type *base; @@ -21,6 +24,9 @@ struct uart_mcux_config { #ifdef CONFIG_UART_INTERRUPT_DRIVEN void (*irq_config_func)(const struct device *dev); #endif +#ifdef CONFIG_PINCTRL + const struct pinctrl_dev_config *pincfg; +#endif }; struct uart_mcux_data { @@ -314,7 +320,7 @@ static void uart_mcux_isr(const struct device *dev) static int uart_mcux_init(const struct device *dev) { -#ifdef CONFIG_UART_INTERRUPT_DRIVEN +#if defined(CONFIG_PINCTRL) || defined(CONFIG_UART_INTERRUPT_DRIVEN) const struct uart_mcux_config *config = dev->config; #endif struct uart_mcux_data *data = dev->data; @@ -325,6 +331,13 @@ static int uart_mcux_init(const struct device *dev) return err; } +#ifdef CONFIG_PINCTRL + err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (err != 0) { + return err; + } +#endif + #ifdef CONFIG_UART_INTERRUPT_DRIVEN config->irq_config_func(dev); #endif @@ -358,11 +371,20 @@ static const struct uart_driver_api uart_mcux_driver_api = { #endif }; +#ifdef CONFIG_PINCTRL +#define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), +#define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); +#else +#define PINCTRL_DEFINE(n) +#define PINCTRL_INIT(n) +#endif + #define UART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT) \ static const struct uart_mcux_config uart_mcux_##n##_config = { \ .base = (UART_Type *)DT_INST_REG_ADDR(n), \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ + PINCTRL_INIT(n) \ IRQ_FUNC_INIT \ } @@ -394,6 +416,7 @@ static const struct uart_mcux_config uart_mcux_##n##_config = { \ #endif #define UART_MCUX_INIT(n) \ + PINCTRL_DEFINE(n) \ \ static struct uart_mcux_data uart_mcux_##n##_data = { \ .uart_cfg = { \ diff --git a/dts/arm/nxp/MK22FN512VLH12.dtsi b/dts/arm/nxp/MK22FN512VLH12.dtsi deleted file mode 100644 index bfd143c05fab3..0000000000000 --- a/dts/arm/nxp/MK22FN512VLH12.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MK64FN1M0VDC12.dtsi b/dts/arm/nxp/MK64FN1M0VDC12.dtsi deleted file mode 100644 index e853b54490bd1..0000000000000 --- a/dts/arm/nxp/MK64FN1M0VDC12.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MK64FN1M0VLL12.dtsi b/dts/arm/nxp/MK64FN1M0VLL12.dtsi deleted file mode 100644 index 41873007ce87e..0000000000000 --- a/dts/arm/nxp/MK64FN1M0VLL12.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MK66FN2M0VLQ18.dtsi b/dts/arm/nxp/MK66FN2M0VLQ18.dtsi deleted file mode 100644 index dc1c489641fe9..0000000000000 --- a/dts/arm/nxp/MK66FN2M0VLQ18.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Electromaticus LLC, 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MK66FN2M0VMD18.dtsi b/dts/arm/nxp/MK66FN2M0VMD18.dtsi deleted file mode 100644 index 4ee16f21a69c4..0000000000000 --- a/dts/arm/nxp/MK66FN2M0VMD18.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MK82FN256VLL15.dtsi b/dts/arm/nxp/MK82FN256VLL15.dtsi deleted file mode 100644 index 68ef3a7b3229e..0000000000000 --- a/dts/arm/nxp/MK82FN256VLL15.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE14F256VLH16.dtsi b/dts/arm/nxp/MKE14F256VLH16.dtsi deleted file mode 100644 index 531ff9b13872a..0000000000000 --- a/dts/arm/nxp/MKE14F256VLH16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE14F256VLL16.dtsi b/dts/arm/nxp/MKE14F256VLL16.dtsi deleted file mode 100644 index d403c10eb33e2..0000000000000 --- a/dts/arm/nxp/MKE14F256VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE14F512VLH16.dtsi b/dts/arm/nxp/MKE14F512VLH16.dtsi deleted file mode 100644 index 0d84e29040130..0000000000000 --- a/dts/arm/nxp/MKE14F512VLH16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE14F512VLL16.dtsi b/dts/arm/nxp/MKE14F512VLL16.dtsi deleted file mode 100644 index bc61e4aa771b0..0000000000000 --- a/dts/arm/nxp/MKE14F512VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE16F256VLH16.dtsi b/dts/arm/nxp/MKE16F256VLH16.dtsi deleted file mode 100644 index f1834712b397e..0000000000000 --- a/dts/arm/nxp/MKE16F256VLH16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE16F256VLL16.dtsi b/dts/arm/nxp/MKE16F256VLL16.dtsi deleted file mode 100644 index dbaaf70c8a2fc..0000000000000 --- a/dts/arm/nxp/MKE16F256VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include - -#include diff --git a/dts/arm/nxp/MKE16F512VLL16.dtsi b/dts/arm/nxp/MKE16F512VLL16.dtsi deleted file mode 100644 index 0781721cb97b5..0000000000000 --- a/dts/arm/nxp/MKE16F512VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE18F256VLH16.dtsi b/dts/arm/nxp/MKE18F256VLH16.dtsi deleted file mode 100644 index b1a20e30745e5..0000000000000 --- a/dts/arm/nxp/MKE18F256VLH16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE18F256VLL16.dtsi b/dts/arm/nxp/MKE18F256VLL16.dtsi deleted file mode 100644 index afac2ed82d7a6..0000000000000 --- a/dts/arm/nxp/MKE18F256VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE18F512VLH16.dtsi b/dts/arm/nxp/MKE18F512VLH16.dtsi deleted file mode 100644 index e36225875e7f2..0000000000000 --- a/dts/arm/nxp/MKE18F512VLH16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKE18F512VLL16.dtsi b/dts/arm/nxp/MKE18F512VLL16.dtsi deleted file mode 100644 index a2bdca0cae5d6..0000000000000 --- a/dts/arm/nxp/MKE18F512VLL16.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKL25Z128VLK4.dtsi b/dts/arm/nxp/MKL25Z128VLK4.dtsi deleted file mode 100644 index 59f5085fa4250..0000000000000 --- a/dts/arm/nxp/MKL25Z128VLK4.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKV58F1M0VLQ24.dtsi b/dts/arm/nxp/MKV58F1M0VLQ24.dtsi deleted file mode 100644 index 6c4726c49997d..0000000000000 --- a/dts/arm/nxp/MKV58F1M0VLQ24.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKW24D512VHA5.dtsi b/dts/arm/nxp/MKW24D512VHA5.dtsi deleted file mode 100644 index 30f998d8c795d..0000000000000 --- a/dts/arm/nxp/MKW24D512VHA5.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKW40Z160VHT4.dtsi b/dts/arm/nxp/MKW40Z160VHT4.dtsi deleted file mode 100644 index c94326fe8c660..0000000000000 --- a/dts/arm/nxp/MKW40Z160VHT4.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/MKW41Z512VHT4.dtsi b/dts/arm/nxp/MKW41Z512VHT4.dtsi deleted file mode 100644 index fc5bc85962fa5..0000000000000 --- a/dts/arm/nxp/MKW41Z512VHT4.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2021, Linaro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include diff --git a/dts/arm/nxp/nxp_k2x.dtsi b/dts/arm/nxp/nxp_k2x.dtsi index 97b42d8898423..5137b3924a159 100644 --- a/dts/arm/nxp/nxp_k2x.dtsi +++ b/dts/arm/nxp/nxp_k2x.dtsi @@ -51,6 +51,12 @@ reg = <0x20000000 DT_SIZE_K(64)>; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { mcg: clock-controller@40064000 { compatible = "nxp,kinetis-mcg"; diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index bb3aa54f31369..0f2bed876d4c7 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -71,6 +71,14 @@ status = "disabled"; }; + + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + + soc { mpu: mpu@4000d000 { compatible = "nxp,k64f-mpu"; diff --git a/dts/arm/nxp/nxp_k8x.dtsi b/dts/arm/nxp/nxp_k8x.dtsi index ed81d0c1abf34..6059744a4ff59 100644 --- a/dts/arm/nxp/nxp_k8x.dtsi +++ b/dts/arm/nxp/nxp_k8x.dtsi @@ -31,6 +31,12 @@ }; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { mpu: mpu@4000d000 { compatible = "nxp,kinetis-mpu"; diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi index 1906e90cd317a..d45fbb9a9c133 100644 --- a/dts/arm/nxp/nxp_ke1xf.dtsi +++ b/dts/arm/nxp/nxp_ke1xf.dtsi @@ -91,6 +91,12 @@ status = "disabled"; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { edma: dma-controller@40008000 { compatible = "nxp,mcux-edma"; diff --git a/dts/arm/nxp/nxp_kl25z.dtsi b/dts/arm/nxp/nxp_kl25z.dtsi index 97248af2d2673..b967b3d480976 100644 --- a/dts/arm/nxp/nxp_kl25z.dtsi +++ b/dts/arm/nxp/nxp_kl25z.dtsi @@ -28,6 +28,12 @@ reg = <0x1FFFF000 DT_SIZE_K(16)>; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { ftfa: flash-controller@40020000 { compatible = "nxp,kinetis-ftfa"; diff --git a/dts/arm/nxp/nxp_kv5x.dtsi b/dts/arm/nxp/nxp_kv5x.dtsi index 6bd3999ebba62..a91fd2fbd994a 100644 --- a/dts/arm/nxp/nxp_kv5x.dtsi +++ b/dts/arm/nxp/nxp_kv5x.dtsi @@ -26,6 +26,12 @@ }; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { mpu: mpu@4000d000 { compatible = "nxp,kinetis-mpu"; diff --git a/dts/arm/nxp/nxp_kw2xd.dtsi b/dts/arm/nxp/nxp_kw2xd.dtsi index 7313d00901263..f584c30f68e27 100644 --- a/dts/arm/nxp/nxp_kw2xd.dtsi +++ b/dts/arm/nxp/nxp_kw2xd.dtsi @@ -7,6 +7,9 @@ #include #include +/* Include package pinmux file for the spi modem settings */ +#include + / { aliases { watchdog0 = &wdog; @@ -28,6 +31,26 @@ }; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + /* + * KW2XD is a system in package part, so the SPI1 controller is + * connected internally to the modem + */ + spi1_modem: spi1_modem { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + }; + sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(32)>; @@ -169,19 +192,6 @@ compatible = "nxp,kinetis-pinmux"; reg = <0x4004a000 0xd0>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; - - SPI1_PCS0_PTB10: spi1_pcs0_ptb10 { - nxp,kinetis-port-pins = < 10 2 >; - }; - SPI1_SCK_PTB11: spi1_sck_ptb11 { - nxp,kinetis-port-pins = < 11 2 >; - }; - SPI1_SOUT_PTB16: spi1_sout_ptb16 { - nxp,kinetis-port-pins = < 16 2 >; - }; - SPI1_SIN_PTB17: spi1_sin_ptb17 { - nxp,kinetis-port-pins = < 17 2 >; - }; }; portc: pinmux@4004b000 { @@ -278,8 +288,7 @@ #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&SPI1_PCS0_PTB10 &SPI1_SCK_PTB11 - &SPI1_SOUT_PTB16 &SPI1_SIN_PTB17>; + pinctrl-0 = <&spi1_modem>; mcr20a@0 { compatible = "nxp,mcr20a"; diff --git a/dts/arm/nxp/nxp_kw40z.dtsi b/dts/arm/nxp/nxp_kw40z.dtsi index ae5520d440c1c..9d6bd1699016f 100644 --- a/dts/arm/nxp/nxp_kw40z.dtsi +++ b/dts/arm/nxp/nxp_kw40z.dtsi @@ -28,6 +28,12 @@ reg = <0x20000000 DT_SIZE_K(16)>; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { mcg: clock-controller@40064000 { compatible = "nxp,kinetis-mcg"; diff --git a/dts/arm/nxp/nxp_kw41z.dtsi b/dts/arm/nxp/nxp_kw41z.dtsi index 18560dd014ffa..e6d072a21783c 100644 --- a/dts/arm/nxp/nxp_kw41z.dtsi +++ b/dts/arm/nxp/nxp_kw41z.dtsi @@ -33,6 +33,12 @@ reg = <0x20000000 DT_SIZE_K(128)>; }; + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; + soc { mcg: clock-controller@40064000 { compatible = "nxp,kinetis-mcg"; diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml new file mode 100644 index 0000000000000..02bff96bc7a48 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml @@ -0,0 +1,78 @@ +# Copyright (c) 2022, NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + Kinetis pinctrl node. This node will define pin configurations in pin groups, + and has the 'pinctrl' node identifier in the SOC's devicetree. Each group + within the pin configuration defines the pin configuration for a peripheral, + and each numbered subgroup in the pin group defines all the pins for that + peripheral with the same configuration properties. The 'pins' property in + a group selects the pins to be configured, and the remaining properties set + configuration values for those pins. Here is an example group for UART0 pins: + + uart0_default: uart0_default { + group0 { + pins = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + If only the required properties are supplied, the pin configuration register + will be assigned the following values: + PCR_PS=0, + PCR_PE=0, + PCR_ODE=0, + PCR_SRE=, + PCR_DSE=, + PCR_PFE=0 + +compatible: "nxp,kinetis-pinctrl" + +include: + - name: base.yaml + - name: pincfg-node-group.yaml + child-binding: + child-binding: + property-allowlist: + - drive-open-drain + - bias-pull-up + - bias-pull-down + +child-binding: + description: Kinetis pin controller pin group + child-binding: + description: | + Kinetis pin controller pin configuration node + properties: + pinmux: + required: true + type: array + description: | + Pin mux selections for this group. See the soc level pinctrl DTSI file + in NXP's HAL for a defined list of these options + drive-strength: + required: true + type: string + enum: + - "low" + - "high" + description: | + Pin output drive strength. Sets the DSE field in the PORTx_PCRn register. + 0 DSE_0- low drive strength when pin is configured as output + 1 DSE_1- high drive strength when pin is configured as output + slew-rate: + required: true + type: string + enum: + - "slow" + - "fast" + description: | + Pin output slew rate. Sets the SRE field in the PORTx_PCRn register. + 0 SRE_0_slow- slow slew rate when pin is configured as output + 1 SRE_1_fast- fast slew rate when pin is configured as output + nxp,passive-filter: + type: boolean + description: | + Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register. diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml index fc236da138a77..1e4bd804c2e6b 100644 --- a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml +++ b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml @@ -12,28 +12,3 @@ properties: clocks: required: true - -child-binding: - description: | - NXP Kinetis Pin data. A series of child nodes that describe each pin - configuration supported by the SoC. Each node is expected to named as - follows - __pt - - The node will have a matching node label that board dtsi files can - utilized to reference in pinctrl- properties. - - The following is an example for UART0 CTS signal on pin 0, with mux - value of 2. - - uart0_cts_pta0: uart0_cts_pta0 { - nxp,kinetis-port-pins = < 0 2 >; - }; - - properties: - "nxp,kinetis-port-pins": - description: | - The array is expected to have two elements. The first element is the - pin number and the second element is the mux value (i.e. PCR[MUX]). - - type: array - required: true diff --git a/dts/bindings/serial/nxp,kinetis-uart.yaml b/dts/bindings/serial/nxp,kinetis-uart.yaml index ae3ed052e8c7b..56483ecc4ff90 100644 --- a/dts/bindings/serial/nxp,kinetis-uart.yaml +++ b/dts/bindings/serial/nxp,kinetis-uart.yaml @@ -2,7 +2,7 @@ description: Kinetis UART compatible: "nxp,kinetis-uart" -include: uart-controller.yaml +include: [uart-controller.yaml, pinctrl-device.yaml] properties: reg: diff --git a/samples/sensor/mcux_acmp/boards/twr_ke18f.overlay b/samples/sensor/mcux_acmp/boards/twr_ke18f.overlay index 8b2e9a4ccc85f..72f4c0c03de1b 100644 --- a/samples/sensor/mcux_acmp/boards/twr_ke18f.overlay +++ b/samples/sensor/mcux_acmp/boards/twr_ke18f.overlay @@ -4,7 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ +&pinctrl { + cmp2_default: cmp2_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; +}; + &cmp2 { status = "okay"; - pinctrl-0 = <&ADC0_SE12_PTC14>; + pinctrl-0 = <&cmp2_default>; }; diff --git a/soc/arm/nxp_kinetis/CMakeLists.txt b/soc/arm/nxp_kinetis/CMakeLists.txt index 64b24a7cd1bb0..ada536c964b16 100644 --- a/soc/arm/nxp_kinetis/CMakeLists.txt +++ b/soc/arm/nxp_kinetis/CMakeLists.txt @@ -4,6 +4,9 @@ zephyr_sources_ifdef(CONFIG_KINETIS_FLASH_CONFIG flash_configuration.c) add_subdirectory(${SOC_SERIES}) +# This is for access to pinctrl macros +zephyr_include_directories(common) + zephyr_linker_sources_ifdef(CONFIG_KINETIS_FLASH_CONFIG ROM_START SORT_KEY ${CONFIG_KINETIS_FLASH_CONFIG_OFFSET} diff --git a/soc/arm/nxp_kinetis/common/pinctrl_soc.h b/soc/arm/nxp_kinetis/common/pinctrl_soc.h new file mode 100644 index 0000000000000..c542b1f26be14 --- /dev/null +++ b/soc/arm/nxp_kinetis/common/pinctrl_soc.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * @file + * NXP Kinetis SOC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + +/* Kinetis KW/KL series does not support open drain. Define macros to have no effect */ +#if defined(CONFIG_SOC_SERIES_KINETIS_KWX) || \ + defined(CONFIG_SOC_SERIES_KINETIS_KL2X) +#define PORT_PCR_ODE(x) 0x0 +#define PORT_PCR_ODE_MASK 0x0 +#endif + +#define Z_PINCTRL_KINETIS_PINCFG(node_id) \ + (PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \ + PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \ + PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \ + PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \ + PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter))) + +#define Z_PINCTRL_KINETIS_PCR_MASK \ + (PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | \ + PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | \ + PORT_PCR_PS_MASK) + + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ */ diff --git a/tests/drivers/pwm/pwm_loopback/boards/twr_ke18f.overlay b/tests/drivers/pwm/pwm_loopback/boards/twr_ke18f.overlay index 3e7e3f0cf3f3f..e8e6e39133029 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/twr_ke18f.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/twr_ke18f.overlay @@ -6,6 +6,24 @@ #include +&pinctrl { + pwt_default: pwt_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + ftm2_default: ftm2_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; +}; + / { pwm_loopback_0 { compatible = "test-pwm-loopback"; @@ -17,7 +35,7 @@ &pwt { status = "okay"; prescaler = <32>; - pinctrl-0 = <&PWT_IN1_PTE11>; + pinctrl-0 = <&pwt_default>; }; &ftm2 { @@ -25,5 +43,5 @@ compatible = "nxp,kinetis-ftm-pwm"; prescaler = <128>; #pwm-cells = <3>; - pinctrl-0 = <&FTM2_CH6_PTE15>; + pinctrl-0 = <&ftm2_default>; }; diff --git a/west.yml b/west.yml index 0c6360b99db6b..986499bc798bc 100644 --- a/west.yml +++ b/west.yml @@ -98,7 +98,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 9629f15fd80169cc9669e3fbb1260467c3aeb175 + revision: 072bf81d2ffcb764a6c63041cec876cbfb614c6a path: modules/hal/nxp groups: - hal