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@benediktibk benediktibk commented Apr 11, 2022

Make the LSE driving capability of a STM32H7 configurable via devicetree.
Fixes #44737.

Signed-off-by: Benedikt Schmidt [email protected]

@github-actions github-actions bot added area: API Changes to public APIs area: Devicetree area: Devicetree Binding PR modifies or adds a Device Tree binding platform: STM32 ST Micro STM32 labels Apr 11, 2022
@benediktibk
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Tested on a H735.
Reference manual checked for:

  • STM32H723XX
  • STM32H735XX
  • STM32H725XX
  • STM32H7A3XX
  • STM32H7B3XX
  • STM32H743XX
  • STM32H753XX
  • STM32H750XX
  • STM32H745XX
  • STM32H747XX

@FRASTM
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FRASTM commented Apr 12, 2022

@benediktibk thanks for adding this property.
Could it be extended in other stm32 mcus which have that drive feature on their LSE (stm32F0, stm32G4 etc) in a similar way,

@benediktibk
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My results from checking the reference manuals from the already available SoCs in zephyr:

has the feature:

  • stm32f030x4
  • stm32f030x8
  • stm32f030xc
  • stm32f070xb
  • stm32f031x6
  • stm32f051x8
  • stm32f072xb
  • stm32f091xc
  • stm32f098xx
  • stm32f302x8
  • stm32f303x8
  • stm32f303xc
  • stm32f303xe
  • stm32f334x8
  • stm32f373xc
  • stm32u575xx
  • stm32u585xx
  • stm32wb55xx
  • stm32f723xx
  • stm32f745xx
  • stm32f746xx
  • stm32f756xx
  • stm32f767xx
  • stm32f769xx
  • stm32g0b0xx
  • stm32g030xx
  • stm32g050xx
  • stm32g070xx
  • stm32g0b1xx
  • stm32g0c1xx
  • stm32g031xx
  • stm32g041xx
  • stm32g051xx
  • stm32g061xx
  • stm32g071xx
  • stm32g081xx
  • stm32g4a1xx
  • stm32g431rb
  • stm32g441xx
  • stm32g473xx
  • stm32g474re
  • stm32g483xx
  • stm32g484xx
  • stm32g491xx
  • stm32l010xb
  • stm32l011xx
  • stm32l031xx
  • stm32l051xx
  • stm32l071xx
  • stm32l072xx
  • stm32l053xx
  • stm32l073xx
  • stm32l4r5xx
  • stm32l4r9xx
  • stm32l4s5xx
  • stm32l412xx
  • stm32l422xx
  • stm32l432xx
  • stm32l433xx
  • stm32l452xx
  • stm32l462xx
  • stm32l471xx
  • stm32l475xx
  • stm32l476xx
  • stm32l496xx
  • stm32l552xx
  • stm32l562xx
  • stm32wl54xx
  • stm32wl55xx
  • stm32wle4xx
  • stm32wle5xx
  • stm32mp15_m4

does not have the feature:

  • stm32f100xx
  • stm32f103xx
  • stm32f105xc
  • stm32f107xc
  • stm32f205xx
  • stm32f207xx
  • stm32f401xc
  • stm32f401xe
  • stm32f405xx
  • stm32f407xx
  • stm32f415xx
  • stm32f417xx
  • stm32f437xx
  • stm32f427xx
  • stm32f429xx
  • stm32f410xx
  • stm32f411xe
  • stm32f412xx
  • stm32f413xx
  • stm32f446xx
  • stm32f469xx
  • stm32l151x8a
  • stm32l151xb
  • stm32l151xba
  • stm32l151xc
  • stm32l152xc
  • stm32l152xe

Hence, I would continue to add the following bindings, similar to the one of the H7 series:

  • st,stm32f0-lse-clock.yaml
  • st,stm32f3-lse-clock.yaml
  • st,stm32u5-lse-clock.yaml
  • st,stm32wb-lse-clock.yaml
  • st,stm32f7-lse-clock.yaml
  • st,stm32g0-lse-clock.yaml
  • st,stm32g4-lse-clock.yaml
  • st,stm32l0-lse-clock.yaml
  • st,stm32l4-lse-clock.yaml
  • st,stm32l5-lse-clock.yaml
  • st,stm32wl-lse-clock.yaml

Does this sound reasonable to you @FRASTM ?

@benediktibk
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While implementing this I realized that for some SoCs the LSE is not really implemented, at least I couldn't find a call to LL_RCC_LSE_Enable:

  • F0
  • F3
  • F7
  • G0
  • L0

I still went ahead and at least added the properties for them.

And there is one more additional problem, stm32_counter kinda is in conflict with the LSE configuration with the clock control. Seems problematic, but for the moment I kept it as it is.

@benediktibk
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The LPTIM timer as well enables LSE. I feel like only the clock control should enable LSE?

@benediktibk benediktibk force-pushed the add_h7_lse_driving_cap branch 2 times, most recently from 6615cd4 to fb28411 Compare April 13, 2022 12:38
@FRASTM
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FRASTM commented Apr 13, 2022

While implementing this I realized that for some SoCs the LSE is not really implemented, at least I couldn't find a call to LL_RCC_LSE_Enable:

  • F0
  • F3
  • F7
  • G0
  • L0

I still went ahead and at least added the properties for them.

And there is one more additional problem, stm32_counter kinda is in conflict with the LSE configuration with the clock control. Seems problematic, but for the moment I kept it as it is.

Yes, this might change with the coming PR #44312

@FRASTM
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FRASTM commented Apr 13, 2022

@benediktibk thanks for listing all the stm32 and giving that exhaustive view.

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No hard objections on the binding; one suggestion.

@erwango
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erwango commented Apr 20, 2022

The LPTIM timer as well enables LSE. I feel like only the clock control should enable LSE?

This is right. On going proposal for this is #42097.

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One main request.
Also, you'll need to rebase on top of #44312 which will have some impact on your change.

@benediktibk benediktibk force-pushed the add_h7_lse_driving_cap branch 2 times, most recently from 5872d39 to 7539856 Compare April 21, 2022 07:30
@benediktibk benediktibk force-pushed the add_h7_lse_driving_cap branch 2 times, most recently from 3b3b7c9 to 68d9320 Compare April 21, 2022 07:49
@benediktibk benediktibk requested a review from erwango April 21, 2022 08:45
Make the LSE driving capability configurable for the STM32 series.
Fixes zephyrproject-rtos#44737.

Signed-off-by: Benedikt Schmidt <[email protected]>
@benediktibk benediktibk force-pushed the add_h7_lse_driving_cap branch from 68d9320 to 66e112d Compare April 21, 2022 12:23
@benediktibk
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@erwango Anything still missing?

@carlescufi carlescufi merged commit 86469b1 into zephyrproject-rtos:main Apr 29, 2022
@benediktibk benediktibk deleted the add_h7_lse_driving_cap branch March 6, 2023 10:48
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area: API Changes to public APIs area: Boards area: Clock Control area: Devicetree Binding PR modifies or adds a Device Tree binding area: Devicetree area: Timer Timer platform: STM32 ST Micro STM32

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Configurable LSE driving capability on H735

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