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drivers: clock_control: clock_stm32_ll_h7: Make LSE driving configurable #44736

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Merged
merged 1 commit into from
Apr 29, 2022
+65 −12
Merged

drivers: clock_control: clock_stm32_ll_h7: Make LSE driving configurable #44736

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2 changes: 2 additions & 0 deletions drivers/bluetooth/hci/ipm_stm32wb.c
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Original file line number Diff line number Diff line change
Expand Up @@ -397,6 +397,8 @@ static void start_ble_rf(void)
}

#if STM32_LSE_ENABLED
/* Configure driving capability */
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
/* Select LSE clock */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
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3 changes: 3 additions & 0 deletions drivers/clock_control/clock_stm32_ll_h7.c
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Expand Up @@ -473,6 +473,9 @@ static void set_up_fixed_clock_sources(void)
/* Enable backup domain */
LL_PWR_EnableBkUpAccess();

/* Configure driving capability */
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);

/* Enable LSE oscillator */
LL_RCC_LSE_Enable();
while (LL_RCC_LSE_IsReady() != 1) {
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3 changes: 3 additions & 0 deletions drivers/clock_control/clock_stm32_ll_u5.c
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Expand Up @@ -336,6 +336,9 @@ static void set_up_fixed_clock_sources(void)
}
}

/* Configure driving capability */
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);

/* Enable LSE Oscillator */
LL_RCC_LSE_Enable();
/* Wait for LSE ready */
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2 changes: 2 additions & 0 deletions drivers/clock_control/clock_stm32g4.c
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Expand Up @@ -75,6 +75,8 @@ void config_enable_default_clocks(void)
/* Wait for Backup domain access */
}

/* Configure driving capability */
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
/* Enable LSE Oscillator (32.768 kHz) */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
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2 changes: 2 additions & 0 deletions drivers/clock_control/clock_stm32l4_l5_wb_wl.c
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Expand Up @@ -88,6 +88,8 @@ void config_enable_default_clocks(void)
/* Wait for Backup domain access */
}

/* Configure driving capability */
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
/* Enable LSE Oscillator (32.768 kHz) */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
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1 change: 1 addition & 0 deletions drivers/timer/stm32_lptim_timer.c
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Expand Up @@ -279,6 +279,7 @@ static int sys_clock_driver_init(const struct device *dev)

/* enable LSE clock */
LL_RCC_LSE_DisableBypass();
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {
/* Wait for LSE ready */
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3 changes: 2 additions & 1 deletion dts/arm/st/f0/stm32f0.dtsi
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Expand Up @@ -49,8 +49,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/f3/stm32f3.dtsi
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Expand Up @@ -50,8 +50,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/f7/stm32f7.dtsi
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Expand Up @@ -55,8 +55,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/g0/stm32g0.dtsi
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Expand Up @@ -52,8 +52,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/g4/stm32g4.dtsi
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Expand Up @@ -51,8 +51,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/h7/stm32h7.dtsi
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Expand Up @@ -66,8 +66,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/l0/stm32l0.dtsi
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Expand Up @@ -56,8 +56,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/l4/stm32l4.dtsi
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Expand Up @@ -58,8 +58,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/l5/stm32l5.dtsi
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Expand Up @@ -66,8 +66,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/u5/stm32u5.dtsi
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Expand Up @@ -64,8 +64,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/wb/stm32wb.dtsi
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Expand Up @@ -71,8 +71,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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3 changes: 2 additions & 1 deletion dts/arm/st/wl/stm32wl.dtsi
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Expand Up @@ -59,8 +59,9 @@

clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};

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22 changes: 22 additions & 0 deletions dts/bindings/clock/st,stm32-lse-clock.yaml
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@@ -0,0 +1,22 @@
# Copyright (c) 2022, SILA Embedded Solutions GmbH
# SPDX-License-Identifier: Apache-2.0

description: STM32 LSE Clock

compatible: "st,stm32-lse-clock"

include: [fixed-clock.yaml]

properties:
driving-capability:
type: int
required: true
description: |
LSE driving capability, within the range 0 to 3.
0 represents the lowests driving capability, 3
the highest.
enum:
- 0
- 1
- 2
- 3
6 changes: 6 additions & 0 deletions include/zephyr/drivers/clock_control/stm32_clock_control.h
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Expand Up @@ -180,9 +180,15 @@
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
#define STM32_LSE_ENABLED 1
#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
#define STM32_LSE_DRIVING 0
#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
#define STM32_LSE_ENABLED 1
#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
#else
#define STM32_LSE_ENABLED 0
#define STM32_LSE_FREQ 0
#define STM32_LSE_DRIVING 0
#endif

#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
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