[RFC] stm32: clock_control: Enable device clock source selection

boards/arm/nucleo_h723zg/arduino_r3_connector.dtsi

@@ -35,5 +35,5 @@
 };
 
 arduino_i2c: &i2c1 {};
-
+arduino_spi: &spi1 {};
 arduino_serial: &uart8 {};

boards/arm/nucleo_h723zg/doc/index.rst

@@ -107,6 +107,8 @@ features:
 +-------------+------------+-------------------------------------+
 | I2C         | on-chip    | i2c                                 |
 +-------------+------------+-------------------------------------+
+| SPI         | on-chip    | spi                                 |
++-------------+------------+-------------------------------------+
 | PWM         | on-chip    | pwm                                 |
 +-------------+------------+-------------------------------------+
 | ETHERNET    | on-chip    | ethernet                            |
@@ -135,6 +137,7 @@ and a ST morpho connector. Board is configured as follows:
 - LD2 : PB7
 - LD3 : PB14
 - I2C : PB8, PB9
+- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI)
 
 System Clock
 ------------

boards/arm/nucleo_h723zg/nucleo_h723zg.dts

@@ -115,6 +115,13 @@
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+};
+
 &i2c1 {
 	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
 	pinctrl-names = "default";

boards/arm/nucleo_h723zg/nucleo_h723zg.yaml

@@ -11,10 +11,12 @@ flash: 1024
 supported:
   - arduino_gpio
   - arduino_i2c
+  - arduino_spi
   - uart
   - gpio
   - counter
   - i2c
   - pwm
+  - spi
   - netif:eth
   - backup_sram

drivers/clock_control/CMakeLists.txt

@@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR       clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
+  zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c)
 if(CONFIG_SOC_SERIES_STM32MP1X)
   zephyr_library_sources(clock_stm32_ll_mp1.c)
 elseif(CONFIG_SOC_SERIES_STM32H7X)

drivers/clock_control/Kconfig.stm32

@@ -8,7 +8,7 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
 	bool "STM32 Reset & Clock Control"
 	depends on SOC_FAMILY_STM32
 	select USE_STM32_LL_UTILS
-	select USE_STM32_LL_RCC if SOC_SERIES_STM32MP1X
+	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X)
 	help
 	  Enable driver for Reset & Clock Control subsystem found
 	  in STM32 family of MCUs
@@ -17,6 +17,7 @@ if CLOCK_CONTROL_STM32_CUBE
 
 DT_STM32_HSE_CLOCK := $(dt_nodelabel_path,clk_hse)
 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
+DT_COMPAT_ST_MUX_CLOCK := st,stm32-clock-mux
 
 config CLOCK_STM32_HSE_CLOCK
 	int "HSE clock value"
@@ -33,6 +34,15 @@ config CLOCK_STM32_HSE_CLOCK
 	  Note: Device tree configuration is overridden when current symbol is set:
 	  CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
 
+config CLOCK_STM32_MUX
+	bool "STM32 clock mux driver"
+	default $(dt_compat_enabled,$(DT_COMPAT_ST_MUX_CLOCK))
+	help
+	  Enable driver for STM32 clock mux which don't match an
+	  existing clock hardware block but allows to select a clock
+	  for a specific domain. For instance per_ck clock on STM32H7 or
+	  CLK48 clock
+
 # Micro-controller Clock output configuration options
 
 choice