Add support for stm32u5 fdcan #45216

warasilapm · 2022-04-28T16:36:45Z

This addresses #45123 in the near term.

Since the clock configuration on STM32 is set to change with #42097 in the future, this only supports clocking from PLL1Q, which should be sufficient for most applications.

Fixes: #45123

henrikbrixandersen · 2022-04-28T17:11:21Z

Does this pass the CAN driver tests (tests/drivers/can/*)?

warasilapm · 2022-04-28T17:15:45Z

Does this pass the CAN driver tests (tests/drivers/can/*)?

Unfortunately, my development environment is on Windows so I am unable to run tests using twister.

henrikbrixandersen · 2022-04-28T17:18:21Z

Unfortunately, my development environment is on Windows so I am unable to run tests using twister.

You can build and flash the test applications just like any other application and examine the console output. No need for twister.

I am mainly interested in the timing tests as you are introducing a new core CAN clock here. If the timing tests all pass (and the produced bitrate is correct), we know this change is okay.

warasilapm · 2022-04-28T17:40:15Z

Unfortunately, my development environment is on Windows so I am unable to run tests using twister.

You can build and flash the test applications just like any other application and examine the console output. No need for twister.

I am mainly interested in the timing tests as you are introducing a new core CAN clock here. If the timing tests all pass (and the produced bitrate is correct), we know this change is okay.

All of the tests pass (see below). There are two caveats to consider:

Because my board uses the can-transceiver-gpio device to control the standby pin, I have to force CONFIG_CAN_INIT_PRIORITY=80 so it is higher than CONFIG_CAN_TRANSCEIVER_INIT_PRIORITY=70 (the default).
My board's core clock is driven off PLL1R generated from MSIS at 48 MHz as the source for SYSCLK. This means the core clock and the FDCAN clock are ultimately driven off of the same clock source.

As an aside, while the generated timings work on my bench set up, I don't like how large the segments Tq are compared to the SJW (in my case 1). Historically, I've always preferred to keep the total number of Tq to 16, since it allows for a single SJW to cover a large range of clock issues. I can of course manually configure my timing how I please, but is there a reason why the calculator uses so many Tq?

*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
testing on device CAN_1 @ 160000000 Hz
Running test suite can_timing_tests
===================================================================
START - test_set_timing_min
 PASS - test_set_timing_min in 0.1 seconds
===================================================================
START - test_set_timing_max
 PASS - test_set_timing_max in 0.1 seconds
===================================================================
START - test_timing
testing bitrate 20000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 40 OK, sample point error 0.0%
testing bitrate 50000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 16 OK, sample point error 0.0%
testing bitrate 125000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 223, phase_seg2 = 32, prescaler = 5 OK, sample point error 0.0%
testing bitrate 250000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 4 OK, sample point error 0.0%
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 2 OK, sample point error 0.0%
testing bitrate 800000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 159, phase_seg2 = 40, prescaler = 1 OK, sample point error 0.0%
testing bitrate 1000000, sample point 75.0% (valid): prop_seg = 0, phase_seg1 = 119, phase_seg2 = 40, prescaler = 1 OK, sample point error 0.0%
testing bitrate 125000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 143, phase_seg2 = 16, prescaler = 8 OK, sample point error 0.0%
testing bitrate 125000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 255, phase_seg2 = 64, prescaler = 4 OK, sample point error 0.0%
testing bitrate 125000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing in 0.123 seconds
===================================================================
START - test_timing_data
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 27, phase_seg2 = 4, prescaler = 10 OK, sample point error 0.0%
testing bitrate 1000000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 27, phase_seg2 = 4, prescaler = 5 OK, sample point error 0.0%
testing bitrate 500000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 17, phase_seg2 = 2, prescaler = 16 OK, sample point error 0.0%
testing bitrate 500000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 31, phase_seg2 = 8, prescaler = 8 OK, sample point error 0.0%
testing bitrate 500000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing_data in 0.60 seconds
===================================================================
Test suite can_timing_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_api_tests
===================================================================
START - test_get_core_clock
 PASS - test_get_core_clock in 0.1 seconds
===================================================================
START - test_set_state_change_callback
 PASS - test_set_state_change_callback in 0.1 seconds
===================================================================
START - test_set_bitrate_too_high
 PASS - test_set_bitrate_too_high in 0.1 seconds
===================================================================
START - test_set_bitrate
 PASS - test_set_bitrate in 0.1 seconds
===================================================================
START - test_set_loopback
 PASS - test_set_loopback in 0.1 seconds
===================================================================
START - test_send_and_forget
 PASS - test_send_and_forget in 0.1 seconds
===================================================================
START - test_add_filter
 PASS - test_add_filter in 0.1 seconds
===================================================================
START - test_max_std_filters
W: No free standard id filter left
 PASS - test_max_std_filters in 0.4 seconds
===================================================================
START - test_max_ext_filters
W: No free extended id filter left
 PASS - test_max_ext_filters in 0.4 seconds
===================================================================
START - test_receive_timeout
 PASS - test_receive_timeout in 0.101 seconds
===================================================================
START - test_send_callback
 PASS - test_send_callback in 0.1 seconds
===================================================================
START - test_send_receive_std_id
 PASS - test_send_receive_std_id in 0.3 seconds
===================================================================
START - test_send_receive_ext_id
 PASS - test_send_receive_ext_id in 0.4 seconds
===================================================================
START - test_send_receive_std_id_masked
 PASS - test_send_receive_std_id_masked in 0.3 seconds
===================================================================
START - test_send_receive_ext_id_masked
 PASS - test_send_receive_ext_id_masked in 0.4 seconds
===================================================================
START - test_send_receive_msgq
 PASS - test_send_receive_msgq in 0.10 seconds
===================================================================
START - test_send_invalid_dlc
E: data length (12) > max frame data length (8)
 PASS - test_send_invalid_dlc in 0.5 seconds
===================================================================
START - test_send_receive_wrong_id
 PASS - test_send_receive_wrong_id in 0.102 seconds
===================================================================
START - test_recover
 PASS - test_recover in 0.1 seconds
===================================================================
START - test_get_state
 PASS - test_get_state in 0.1 seconds
===================================================================
START - test_filters_preserved_through_mode_change
E: Message RAM access failure
 PASS - test_filters_preserved_through_mode_change in 0.4 seconds
===================================================================
START - test_filters_preserved_through_bitrate_change
 PASS - test_filters_preserved_through_bitrate_change in 0.3 seconds
===================================================================
Test suite can_api_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite canfd_driver
===================================================================
START - test_set_loopback
 PASS - test_set_loopback in 0.1 seconds
===================================================================
START - test_send_receive_classic
 PASS - test_send_receive_classic in 0.1 seconds
===================================================================
START - test_send_receive_fd
 PASS - test_send_receive_fd in 0.2 seconds
===================================================================
START - test_send_receive_mixed
 PASS - test_send_receive_mixed in 0.2 seconds
===================================================================
Test suite canfd_driver succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_stm32_tests
===================================================================
START - test_filter_handling
 PASS - test_filter_handling in 0.101 seconds
===================================================================
Test suite can_stm32_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_utilities_tests
===================================================================
START - test_can_frame_to_zcan_frame
 PASS - test_can_frame_to_zcan_frame in 0.1 seconds
===================================================================
START - test_zcan_frame_to_can_frame
 PASS - test_zcan_frame_to_can_frame in 0.1 seconds
===================================================================
START - test_can_filter_to_zcan_filter
 PASS - test_can_filter_to_zcan_filter in 0.1 seconds
===================================================================
START - test_zcan_filter_to_can_filter
 PASS - test_zcan_filter_to_can_filter in 0.1 seconds
===================================================================
START - test_can_dlc_to_bytes
 PASS - test_can_dlc_to_bytes in 0.1 seconds
===================================================================
START - test_can_bytes_to_dlc
 PASS - test_can_bytes_to_dlc in 0.1 seconds
===================================================================
Test suite can_utilities_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL

henrikbrixandersen · 2022-04-28T19:19:39Z

Because my board uses the can-transceiver-gpio device to control the standby pin, I have to force CONFIG_CAN_INIT_PRIORITY=80 so it is higher than CONFIG_CAN_TRANSCEIVER_INIT_PRIORITY=70 (the default).

Thanks, fixed in #45220

My board's core clock is driven off PLL1R generated from MSIS at 48 MHz as the source for SYSCLK. This means the core clock and the FDCAN clock are ultimately driven off of the same clock source.

As an aside, while the generated timings work on my bench set up, I don't like how large the segments Tq are compared to the SJW (in my case 1). Historically, I've always preferred to keep the total number of Tq to 16, since it allows for a single SJW to cover a large range of clock issues. I can of course manually configure my timing how I please, but is there a reason why the calculator uses so many Tq?

You are right, that does seem rather high. I have just verified on a nucleo_g474re that I get similar results. I will look into improving the algorithm.

*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
testing on device CAN_1 @ 160000000 Hz

The CAN core clock (160MHz) is very high? On the nucleo_g474re using the same driver, I have a core CAN clock of 24MHz.

drivers/can/can_stm32fd.c

warasilapm · 2022-05-03T15:52:25Z

Test suite results running from the 24 MHz HSE clock.

*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_api_tests
===================================================================
START - test_get_core_clock
 PASS - test_get_core_clock in 0.1 seconds
===================================================================
START - test_set_state_change_callback
 PASS - test_set_state_change_callback in 0.1 seconds
===================================================================
START - test_set_bitrate_too_high
 PASS - test_set_bitrate_too_high in 0.1 seconds
===================================================================
START - test_set_bitrate
 PASS - test_set_bitrate in 0.1 seconds
===================================================================
START - test_set_loopback
 PASS - test_set_loopback in 0.1 seconds
===================================================================
START - test_send_and_forget
 PASS - test_send_and_forget in 0.1 seconds
===================================================================
START - test_add_filter
 PASS - test_add_filter in 0.1 seconds
===================================================================
START - test_max_std_filters
W: No free standard id filter left
 PASS - test_max_std_filters in 0.4 seconds
===================================================================
START - test_max_ext_filters
W: No free extended id filter left
 PASS - test_max_ext_filters in 0.4 seconds
===================================================================
START - test_receive_timeout
 PASS - test_receive_timeout in 0.101 seconds
===================================================================
START - test_send_callback
 PASS - test_send_callback in 0.1 seconds
===================================================================
START - test_send_receive_std_id
 PASS - test_send_receive_std_id in 0.3 seconds
===================================================================
START - test_send_receive_ext_id
 PASS - test_send_receive_ext_id in 0.4 seconds
===================================================================
START - test_send_receive_std_id_masked
 PASS - test_send_receive_std_id_masked in 0.3 seconds
===================================================================
START - test_send_receive_ext_id_masked
 PASS - test_send_receive_ext_id_masked in 0.4 seconds
===================================================================
START - test_send_receive_msgq
 PASS - test_send_receive_msgq in 0.10 seconds
===================================================================
START - test_send_invalid_dlc
E: data length (12) > max frame data length (8)
 PASS - test_send_invalid_dlc in 0.5 seconds
===================================================================
START - test_send_receive_wrong_id
 PASS - test_send_receive_wrong_id in 0.102 seconds
===================================================================
START - test_recover
 PASS - test_recover in 0.1 seconds
===================================================================
START - test_get_state
 PASS - test_get_state in 0.1 seconds
===================================================================
START - test_filters_preserved_through_mode_change
E: Message RAM access failure
 PASS - test_filters_preserved_through_mode_change in 0.4 seconds
===================================================================
START - test_filters_preserved_through_bitrate_change
 PASS - test_filters_preserved_through_bitrate_change in 0.3 seconds
===================================================================
Test suite can_api_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
testing on device CAN_1 @ 24000000 Hz
Running test suite can_timing_tests
===================================================================
START - test_set_timing_min
 PASS - test_set_timing_min in 0.1 seconds
===================================================================
START - test_set_timing_max
 PASS - test_set_timing_max in 0.1 seconds
===================================================================
START - test_timing
testing bitrate 20000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 209, phase_seg2 = 30, prescaler = 5 OK, sample point error 0.0%
testing bitrate 50000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 209, phase_seg2 = 30, prescaler = 2 OK, sample point error 0.0%
testing bitrate 125000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 167, phase_seg2 = 24, prescaler = 1 OK, sample point error 0.0%
testing bitrate 250000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 83, phase_seg2 = 12, prescaler = 1 OK, sample point error 0.0%
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 41, phase_seg2 = 6, prescaler = 1 OK, sample point error 0.0%
testing bitrate 800000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 23, phase_seg2 = 6, prescaler = 1 OK, sample point error 0.0%
testing bitrate 1000000, sample point 75.0% (valid): prop_seg = 0, phase_seg1 = 17, phase_seg2 = 6, prescaler = 1 OK, sample point error 0.0%
testing bitrate 125000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 171, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.5%
testing bitrate 125000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 152, phase_seg2 = 39, prescaler = 1 OK, sample point error 0.4%
testing bitrate 125000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing in 0.123 seconds
===================================================================
START - test_timing_data
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 20, phase_seg2 = 3, prescaler = 2 OK, sample point error 0.0%
testing bitrate 1000000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 20, phase_seg2 = 3, prescaler = 1 OK, sample point error 0.0%
testing bitrate 500000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 20, phase_seg2 = 3, prescaler = 2 OK, sample point error 2.5%
testing bitrate 500000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 18, phase_seg2 = 5, prescaler = 2 OK, sample point error 0.9%
testing bitrate 500000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing_data in 0.60 seconds
===================================================================
Test suite can_timing_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite canfd_driver
===================================================================
START - test_set_loopback
 PASS - test_set_loopback in 0.1 seconds
===================================================================
START - test_send_receive_classic
 PASS - test_send_receive_classic in 0.1 seconds
===================================================================
START - test_send_receive_fd
 PASS - test_send_receive_fd in 0.2 seconds
===================================================================
START - test_send_receive_mixed
 PASS - test_send_receive_mixed in 0.2 seconds
===================================================================
Test suite canfd_driver succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_stm32_tests
===================================================================
START - test_filter_handling
 PASS - test_filter_handling in 0.101 seconds
===================================================================
Test suite can_stm32_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build zephyr-v3.0.0-3123-gdacad6ace626  ***
Running test suite can_utilities_tests
===================================================================
START - test_can_frame_to_zcan_frame
 PASS - test_can_frame_to_zcan_frame in 0.1 seconds
===================================================================
START - test_zcan_frame_to_can_frame
 PASS - test_zcan_frame_to_can_frame in 0.1 seconds
===================================================================
START - test_can_filter_to_zcan_filter
 PASS - test_can_filter_to_zcan_filter in 0.1 seconds
===================================================================
START - test_zcan_filter_to_can_filter
 PASS - test_zcan_filter_to_can_filter in 0.1 seconds
===================================================================
START - test_can_dlc_to_bytes
 PASS - test_can_dlc_to_bytes in 0.1 seconds
===================================================================
START - test_can_bytes_to_dlc
 PASS - test_can_bytes_to_dlc in 0.1 seconds
===================================================================
Test suite can_utilities_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL

henrikbrixandersen

Looks good from a CAN point of view. I'll leave the SoC specific stuff to @erwango.

erwango

One tiny comment.
Otherwise, I'd suggest to squash first and third commit for clarity.

drivers/can/can_stm32fd.c

The STM32u% series of processors has a unique set of clock sources for the FDCAN peripheral. This brings the selection in line with the existing can_stm32fd clock selection Kconfigs. This change was tested on a proprietary board using the STM32U5 series which exposes the CAN pins of the SOC using a transciever on a live CAN bus as well as on the nucleo_g474re board from ST in loopback mode. HSE and PLL1Q tests run and all passed. PLL2P is not currently supported by the clock drivers for STM32U5, and as such is currently untested. When this support is added, the driver should be able to use this clock without issue. When changes from zephyrproject-rtos#42097 are merged this fix should be deprecated in favor of using the methods outlined there. Signed-off-by: Peter Maxwell Warasila <[email protected]>

Add support for the fdcan peripheral to the stm32u5 series device tree include. This can be applied here since (at present) all of the stm32u5 series MCUs have an FDCAN peripheral. Signed-off-by: Peter Maxwell Warasila <[email protected]>

erwango · 2022-05-05T07:50:55Z

@henrikbrixandersen, @alexanderwachter mind approving once more ?

In zephyrproject-rtos#45014 the m_can compatible identifier was changed from "m-can-base" to "m_can-base" while zephyrproject-rtos#45216 was being developed. This commit updates the dts for u5 to the latest format. Signed-off-by: Peter Maxwell Warasila <[email protected]>

In #45014 the m_can compatible identifier was changed from "m-can-base" to "m_can-base" while #45216 was being developed. This commit updates the dts for u5 to the latest format. Signed-off-by: Peter Maxwell Warasila <[email protected]>

In zephyrproject-rtos#45014 the m_can compatible identifier was changed from "m-can-base" to "m_can-base" while zephyrproject-rtos#45216 was being developed. This commit updates the dts for u5 to the latest format. Signed-off-by: Peter Maxwell Warasila <[email protected]>

warasilapm requested review from alexanderwachter, erwango and henrikbrixandersen as code owners April 28, 2022 16:36

github-actions bot added area: CAN area: Devicetree platform: STM32 ST Micro STM32 labels Apr 28, 2022

zephyrbot requested review from ABOSTM, FRASTM, gmarull, karstenkoenig and martinjaeger April 28, 2022 16:53

zephyrbot assigned erwango Apr 28, 2022

henrikbrixandersen linked an issue Apr 28, 2022 that may be closed by this pull request

driver: can_stm32fd: STM32U5 series support #45123

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henrikbrixandersen changed the title ~~Add support for stm32u5 fdcan issue45123~~ Add support for stm32u5 fdcan Apr 28, 2022

henrikbrixandersen mentioned this pull request Apr 28, 2022

drivers: can: transceivers are initialized after controllers #45219

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warasilapm dismissed stale reviews from alexanderwachter and henrikbrixandersen via 88edeb9 May 4, 2022 14:27

warasilapm force-pushed the add-support-for-stm32u5-fdcan-issue45123 branch from 393ad3d to 88edeb9 Compare May 4, 2022 14:27

warasilapm added 2 commits May 4, 2022 15:09

dts: arm: st: u5: add fdcan to stm32u5 series

645cbe0

Add support for the fdcan peripheral to the stm32u5 series device tree include. This can be applied here since (at present) all of the stm32u5 series MCUs have an FDCAN peripheral. Signed-off-by: Peter Maxwell Warasila <[email protected]>

warasilapm force-pushed the add-support-for-stm32u5-fdcan-issue45123 branch from 88edeb9 to 645cbe0 Compare May 4, 2022 19:12

warasilapm requested a review from erwango May 4, 2022 19:15

erwango approved these changes May 5, 2022

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MaureenHelm merged commit d875cfc into zephyrproject-rtos:main May 5, 2022

warasilapm deleted the add-support-for-stm32u5-fdcan-issue45123 branch May 6, 2022 21:34

warasilapm mentioned this pull request May 6, 2022

dts: arm: st: u5: update m_can compatible #45444

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