drivers: can: sam: use UPLL clock instead of PLLA clock #45223

henrikbrixandersen · 2022-04-28T20:20:51Z

Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM E70 data sheet.

Signed-off-by: Henrik Brix Andersen [email protected]

henrikbrixandersen · 2022-04-28T20:22:22Z

The can_sam_get_core_clock() function likely needs updating as well to reflect the change in CAN core clock frequency, but I do not have the hardware to test with. @nandojve Any ideas?

nandojve · 2022-04-29T07:18:27Z

Hi @henrikbrixandersen ,
Let me check

nandojve · 2022-05-01T17:04:33Z

Hi @henrikbrixandersen , Let me check

@henrikbrixandersen ,

May you check if below enables UPLLCK at 480 MHz:

diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 77a7fe0cf3..bd0e77c9ae 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c
@@ -177,6 +177,15 @@ static ALWAYS_INLINE void clock_init(void)
                ;
        }
 
+       /* Setup UPLL */
+       PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(0x3Fu);
+                      | CKGR_UCKR_UPLLEN;
+
+       /* Wait for PLL lock */
+       while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {
+               ;
+       }
+
        /*
         * Final setup of the Master Clock
         */

henrikbrixandersen · 2022-05-02T09:22:58Z

May you check if below enables UPLLCK at 480 MHz:

Thanks! I do not have access to the hardware, but perhaps @shaoanxli can check?

shaoanxli · 2022-05-03T02:56:57Z

May you check if below enables UPLLCK at 480 MHz:

Thanks! I do not have access to the hardware, but perhaps @shaoanxli can check?

Is there any good way to get UPLLCK? It seems no register to get the UPLLCK.

From the SAM E70 data sheet, page 277:

And the UPLLCK clock frequency seems to be fixed.

nandojve · 2022-05-03T19:34:29Z

Is there any good way to get UPLLCK?

The below is supposed to work.

diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 77a7fe0cf3..bd0e77c9ae 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c
@@ -177,6 +177,15 @@ static ALWAYS_INLINE void clock_init(void)
                ;
        }
 
+       /* Setup UPLL */
+       PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(0x3Fu);
+                      | CKGR_UCKR_UPLLEN;
+
+       /* Wait for PLL lock */
+       while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {
+               ;
+       }
+
        /*
         * Final setup of the Master Clock
         */

shaoanxli · 2022-05-05T01:21:06Z

The UPLLCK seems to setup successfully , but the test failed , logs and console output shows:

DEBUG   - DEVICE: *** Booting Zephyr OS build zephyr-v3.0.0-3206-gf7171e20b33e  ***
DEBUG   - DEVICE: testing on device CAN_0 @ 150000000 Hz
DEBUG   - DEVICE: Running test suite can_timing_tests
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_set_timing_min
DEBUG   - DEVICE: PASS - test_set_timing_min in 0.1 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_set_timing_max
DEBUG   - DEVICE: PASS - test_set_timing_max in 0.1 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_timing
DEBUG   - DEVICE: testing bitrate 20000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 130, phase_seg2 = 19, prescaler = 50 OK, sample point error 0.2%
DEBUG   - DEVICE: testing bitrate 50000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 15 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 125000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 209, phase_seg2 = 30, prescaler = 5 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 250000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 3 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 130, phase_seg2 = 19, prescaler = 2 OK, sample point error 0.2%
DEBUG   - DEVICE: testing bitrate 800000, sample point 80.0% (valid):
DEBUG   - DEVICE: Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/can/timing/src/main.c:194: test_timing_values: (sp_err >= 0 is false)
DEBUG   - DEVICE: unknown error -22
DEBUG   - DEVICE: FAIL - test_timing in 0.80 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_timing_data
DEBUG   - DEVICE: testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 25, phase_seg2 = 4, prescaler = 10 OK, sample point error 0.9%
DEBUG   - DEVICE: testing bitrate 1000000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 25, phase_seg2 = 4, prescaler = 5 OK, sample point error 0.9%
DEBUG   - DEVICE: testing bitrate 500000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 26, phase_seg2 = 3, prescaler = 10 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 23, phase_seg2 = 6, prescaler = 10 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 100.0% (invalid): OK
DEBUG   - DEVICE: testing bitrate 8000001, sample point 75.0% (invalid): OK
DEBUG   - DEVICE: PASS - test_timing_data in 0.60 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: Test suite can_timing_tests failed.
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: RunID: 52876579eaf0bab6807fb28529187fe9
DEBUG   - DEVICE: PROJECT EXECUTION FAILED

nandojve · 2022-05-05T06:26:55Z

The UPLLCK seems to setup successfully , but the test failed

Hi @shaoanxli,

Let me check!

shaoanxli · 2022-05-05T06:33:35Z

The UPLLCK seems to setup successfully , but the test failed

Hi @shaoanxli,

Let me check!

This error seems to occur here(drivers/can/can_common.c) , when bitrate=800000 :

if (core_clock % (prescaler * bitrate)) {
	/* No integer ts */
	continue;
}

henrikbrixandersen · 2022-05-05T06:56:17Z

The UPLLCK seems to setup successfully , but the test failed , logs and console output shows:
DEBUG   - DEVICE: *** Booting Zephyr OS build zephyr-v3.0.0-3206-gf7171e20b33e  ***
DEBUG   - DEVICE: testing on device CAN_0 @ 150000000 Hz

The can_sam_get_core_clock() function needs to be updated to report the correct clock frequency and you need to use one of the clock dividers recommended by the data sheet (see the linked issue).

Without those changes there are no changes to the CAN timing calculations.

henrikbrixandersen · 2022-05-05T07:52:54Z

@shaoanxli, @nandojve I have tried to incorporate the needed changes as good as I can from studying the datasheet and the suggested code from @nandojve. Please test - both the CAN timing test cases and the actual CAN bitrate as presented on the CAN bus.

@alexanderwachter You wrote the original driver - can you assist in testing?

nandojve · 2022-05-07T16:29:04Z

@shaoanxli, @nandojve I have tried to incorporate the needed changes as good as I can from studying the datasheet and the suggested code from @nandojve. Please test - both the CAN timing test cases and the actual CAN bitrate as presented on the CAN bus.

@alexanderwachter You wrote the original driver - can you assist in testing?

Hi folks,

There is nothing wrong with this patch. You just need select correct divisor at devicetree. With 24 CAN clock will be 20MHz. Please, change it to 6 then clock will be 80MHz. See below result at SAMV71_XULT:

*** Booting Zephyr OS build zephyr-v3.0.0-3510-g9a8162aca685  ***
testing on device CAN_1 @ 80000000 Hz
Running test suite can_timing_tests
===================================================================
START - test_set_timing_min
 PASS - test_set_timing_min in 0.1 seconds
===================================================================
START - test_set_timing_max
 PASS - test_set_timing_max in 0.1 seconds
===================================================================
START - test_timing
testing bitrate 20000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 20 OK, sample point error 0.0%
testing bitrate 50000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 8 OK, sample point error 0.0%
testing bitrate 125000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 4 OK, sample point error 0.0%
testing bitrate 250000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 2 OK, sample point error 0.0%
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
testing bitrate 800000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 79, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
testing bitrate 1000000, sample point 75.0% (valid): prop_seg = 0, phase_seg1 = 59, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
testing bitrate 125000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 143, phase_seg2 = 16, prescaler = 4 OK, sample point error 0.0%
testing bitrate 125000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 255, phase_seg2 = 64, prescaler = 2 OK, sample point error 0.0%
testing bitrate 125000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing in 0.123 seconds
===================================================================
START - test_timing_data
testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 27, phase_seg2 = 4, prescaler = 5 OK, sample point error 0.0%
testing bitrate 1000000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 13, phase_seg2 = 2, prescaler = 5 OK, sample point error 0.0%
testing bitrate 500000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 17, phase_seg2 = 2, prescaler = 8 OK, sample point error 0.0%
testing bitrate 500000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 31, phase_seg2 = 8, prescaler = 4 OK, sample point error 0.0%
testing bitrate 500000, sample point 100.0% (invalid): OK
testing bitrate 8000001, sample point 75.0% (invalid): OK
 PASS - test_timing_data in 0.60 seconds
===================================================================
Test suite can_timing_tests succeeded
===================================================================
PROJECT EXECUTION SUCCESSFUL

BTW, don't forget to add soc: arm: atmel: same70: enable the UPLL clock to samv71.

henrikbrixandersen · 2022-05-07T18:03:04Z

@nandojve Thank you so much for your help on co-authoring and verifying this fix :) I have marked it ready for review.

nandojve · 2022-05-07T18:09:48Z

@nandojve Thank you so much for your help on co-authoring and verifying this fix :) I have marked it ready for review.

Hi @henrikbrixandersen , you are welcome!
BTW, it should be [email protected] in this case. Thank you!

Enable the UTMI PLL (UPLL) clock and add a static definition of its clock frequency. Signed-off-by: Henrik Brix Andersen <[email protected]> Co-authored-by: Gerson Fernando Budke <[email protected]>

Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM E70 data sheet. Move the configuration of the clock prescaler from Kconfig to devicetree and limit it to the values recommended by the SAM E70 datasheet. Fixes: zephyrproject-rtos#45012 Signed-off-by: Henrik Brix Andersen <[email protected]>

Remove unnecessary #address-cells/#size-cells from the CAN devicetree nodes. Signed-off-by: Henrik Brix Andersen <[email protected]>

henrikbrixandersen · 2022-05-07T18:12:04Z

Hi @henrikbrixandersen , you are welcome! BTW, it should be [email protected] in this case. Thank you!

Fixed.

alexanderwachter

Cannot get my hands on the HW at the moment. Did somebody test?

Edit: never mind. Test results were hidden in the APP 🤦‍♂️

shaoanxli · 2022-05-09T01:33:00Z

Cannot get my hands on the HW at the moment. Did somebody test?

Edit: never mind. Test results were hidden in the APP 🤦‍♂️

I tried the test on the HW . The test pass.

DEBUG   - DEVICE: *** Booting Zephyr OS build zephyr-v3.0.0-3507-g6388778fb17d  ***
DEBUG   - DEVICE: testing on device CAN_0 @ 80000000 Hz
DEBUG   - DEVICE: Running test suite can_timing_tests
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_set_timing_min
DEBUG   - DEVICE: PASS - test_set_timing_min in 0.1 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_set_timing_max
DEBUG   - DEVICE: PASS - test_set_timing_max in 0.1 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_timing
DEBUG   - DEVICE: testing bitrate 20000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 20 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 50000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 174, phase_seg2 = 25, prescaler = 8 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 125000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 4 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 250000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 2 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 139, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 800000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 79, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 1000000, sample point 75.0% (valid): prop_seg = 0, phase_seg1 = 59, phase_seg2 = 20, prescaler = 1 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 125000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 143, phase_seg2 = 16, prescaler = 4 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 125000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 255, phase_seg2 = 64, prescaler = 2 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 125000, sample point 100.0% (invalid): OK
DEBUG   - DEVICE: testing bitrate 8000001, sample point 75.0% (invalid): OK
DEBUG   - DEVICE: PASS - test_timing in 0.123 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: START - test_timing_data
DEBUG   - DEVICE: testing bitrate 500000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 27, phase_seg2 = 4, prescaler = 5 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 1000000, sample point 87.5% (valid): prop_seg = 0, phase_seg1 = 13, phase_seg2 = 2, prescaler = 5 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 90.0% (valid): prop_seg = 0, phase_seg1 = 17, phase_seg2 = 2, prescaler = 8 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 80.0% (valid): prop_seg = 0, phase_seg1 = 31, phase_seg2 = 8, prescaler = 4 OK, sample point error 0.0%
DEBUG   - DEVICE: testing bitrate 500000, sample point 100.0% (invalid): OK
DEBUG   - DEVICE: testing bitrate 8000001, sample point 75.0% (invalid): OK
DEBUG   - DEVICE: PASS - test_timing_data in 0.60 seconds
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: Test suite can_timing_tests succeeded
DEBUG   - DEVICE: ===================================================================
DEBUG   - DEVICE: RunID: 63937deb897c652468f6c0e64355cba8
DEBUG   - DEVICE: PROJECT EXECUTION SUCCESSFUL

henrikbrixandersen added bug The issue is a bug, or the PR is fixing a bug platform: Microchip SAM Microchip SAM Platform (formerly Atmel SAM) area: CAN labels Apr 28, 2022

henrikbrixandersen self-assigned this Apr 28, 2022

henrikbrixandersen mentioned this pull request Apr 28, 2022

sam_e70b_xplained: failed to run test case tests/drivers/can/timing/drivers.can.timing #45012

Closed

henrikbrixandersen force-pushed the can_sam_core_clock branch from 80cde34 to e55b155 Compare May 5, 2022 07:50

github-actions bot added area: Devicetree area: Devicetree Binding PR modifies or adds a Device Tree binding labels May 5, 2022

henrikbrixandersen force-pushed the can_sam_core_clock branch from e55b155 to 471b550 Compare May 7, 2022 18:01

henrikbrixandersen marked this pull request as ready for review May 7, 2022 18:02

henrikbrixandersen requested review from alexanderwachter, galak and nandojve as code owners May 7, 2022 18:02

henrikbrixandersen requested review from karstenkoenig and martinjaeger May 7, 2022 18:02

soc: arm: atmel: same70: enable the UPLL clock

13173ac

Enable the UTMI PLL (UPLL) clock and add a static definition of its clock frequency. Signed-off-by: Henrik Brix Andersen <[email protected]> Co-authored-by: Gerson Fernando Budke <[email protected]>

henrikbrixandersen and others added 3 commits May 7, 2022 20:11

soc: arm: atmel: samv71: enable the UPLL clock

31ec2b6

Enable the UTMI PLL (UPLL) clock and add a static definition of its clock frequency. Signed-off-by: Henrik Brix Andersen <[email protected]> Co-authored-by: Gerson Fernando Budke <[email protected]>

dts: arm: atmel: same70: remove unnecessary #address-cells/#size-cells

a20bfae

Remove unnecessary #address-cells/#size-cells from the CAN devicetree nodes. Signed-off-by: Henrik Brix Andersen <[email protected]>

henrikbrixandersen force-pushed the can_sam_core_clock branch from 471b550 to a20bfae Compare May 7, 2022 18:11

nandojve approved these changes May 7, 2022

View reviewed changes

alexanderwachter approved these changes May 8, 2022

View reviewed changes

carlescufi merged commit 302e643 into zephyrproject-rtos:main May 9, 2022

henrikbrixandersen deleted the can_sam_core_clock branch May 9, 2022 15:12

nandojve added this to the v3.1.0 milestone May 26, 2022

drivers: can: sam: use UPLL clock instead of PLLA clock #45223

drivers: can: sam: use UPLL clock instead of PLLA clock #45223

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