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Extend STM32 QSPI with QER (SFDP, DTS), custom quad write opcode, and 1-1-4 read mode #45433

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Merged
merged 14 commits into from
May 13, 2022
Merged

Extend STM32 QSPI with QER (SFDP, DTS), custom quad write opcode, and 1-1-4 read mode #45433

merged 14 commits into from
May 13, 2022

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@GeorgeCGV
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@GeorgeCGV GeorgeCGV commented May 6, 2022

Extends existing STM32 QSPI NOR driver.

Adds:

  • Support every QE requirement - can be specified in DTS. However, SFDP BFP DW15 bypasses the DTS value (if DW15 is present).

  • Add support to specify what quad program (write) opcode is going to be used:

    • PP_1_1_4 (new)
    • PP_1_4_4 (used originally)

    Some flash ICs support a different set of opcodes for programming and reading. The inspiration is taken from the
    nrf_qspi_nor driver, but spi_nor defines are used.

  • Add support for 1-1-4 read mode. The driver auto-detects the fastest supported quad read mode from SFDP BFP

This PR enables STM32 QSPI NOR driver usage with different kinds of QSPI Flash ICs.

Tested using custom H750 board with W25Q128JVSIQ.

Flash test output

[00:00:00.000,000] flash_stm32_qspi: flash_stm32_qspi_init: W25Q128JVSIQ: SFDP v 1.5 AP ff with 1 PH
[00:00:00.000,000] flash_stm32_qspi: flash_stm32_qspi_init: PH0: ff00 rev 1.5: 16 DW @ 80
[00:00:00.000,000] flash_stm32_qspi: W25Q128JVSIQ: 16 MiBy flash
[00:00:00.000,000] flash_stm32_qspi: Quad read mode 4 instr [0x6b] supported
[00:00:00.000,000] flash_stm32_qspi: Quad read mode 7 instr [0xeb] supported
[00:00:00.000,000] flash_stm32_qspi: Quad read mode 7 instr [0xeb] will be used
[00:00:00.000,000] flash_stm32_qspi: QE Requirement mode: 4
[00:00:00.000,000] flash_stm32_qspi: Quad mode enabled

uart:~$ flash test W25Q128JVSIQ 0x0 0x1000 3
Erase OK.
Write OK.
Erase OK.
Write OK.
Erase OK.
Write OK.
Erase-Write test done.

uart:~$ flash erase W25Q128JVSIQ 0x0 0x1000
Erase success.

uart:~$ flash read W25Q128JVSIQ 0x0 0x16
00000000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |........ ........|
00000010: ff ff ff ff ff ff |...... |

uart:~$ flash write W25Q128JVSIQ 0x0 0xAABBCCDD
Write OK.
Verified.

uart:~$ flash read W25Q128JVSIQ 0x0 0x16
00000000: dd cc bb aa ff ff ff ff ff ff ff ff ff ff ff ff |........ ........|
00000010: ff ff ff ff ff ff |...... |

uart:~$

@GeorgeCGV GeorgeCGV force-pushed the stm32_qspi_nor_qe_qmodes branch from da5815e to e491229 Compare May 6, 2022 12:45
@github-actions github-actions bot added area: Devicetree area: Devicetree Binding PR modifies or adds a Device Tree binding platform: STM32 ST Micro STM32 labels May 6, 2022
erwango
erwango reviewed May 6, 2022
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@GeorgeCGV GeorgeCGV force-pushed the stm32_qspi_nor_qe_qmodes branch from dc3502b to ca8104b Compare May 6, 2022 13:02
erwango
erwango requested changes May 6, 2022
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@GeorgeCGV GeorgeCGV force-pushed the stm32_qspi_nor_qe_qmodes branch from ca8104b to 15d6828 Compare May 6, 2022 14:39
@GeorgeCGV GeorgeCGV requested a review from erwango May 6, 2022 14:41
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@GeorgeCGV GeorgeCGV requested a review from erwango May 6, 2022 15:35
@GeorgeCGV GeorgeCGV force-pushed the stm32_qspi_nor_qe_qmodes branch 6 times, most recently from 2249c64 to c7152b0 Compare May 6, 2022 21:22
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GeorgeCGV commented May 6, 2022

erwango
erwango previously approved these changes May 9, 2022
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@erwango erwango requested review from ABOSTM and FRASTM May 9, 2022 07:40
FRASTM
FRASTM reviewed May 13, 2022
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GeorgeCGV added 14 commits May 13, 2022 09:58
@GeorgeCGV
drivers: flash: spi_nor: remove not used QE bit define
619f4e9 
Removes unused QE bit define.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: falsh: spi_nor: add PP_1_1_4 and rename 4PP
67ffd4d 
* Renames 4PP define to PP_1_4_4
* Adds PP_1_1_4 define

That matches linux kernel defines a bit more.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: spi_nor: add SR3 read and write defines
4148940 
Adds Status Register 3 read and write opcode defines.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: jesd216: correct comment mistake
aba7b40 
Corrects type name in the comment for the DW15 QER field.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
dts: bindings: flash_controller: stm32-qspi-nor: add writeoc property
d9cac02 
Adds writeoc property to allow quad write opcode selection.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: minor cleanup
d3238d1 
Removes double line and log output regarding
device initialization.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: support DTS writeoc
7a65dc2 
Adds support for DTS writeoc.

Uses 1-4-4 mode by default (as the original driver).

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: support 1-4-4 and 1-1-4 quad read modes
767fd62 
Adds support for 1-4-4 and 1-1-4 read modes.

SFDP is used to query for available read instructions, then the
fastest one is used.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: move prepare cmd is enable check
90769b3 
Moves IS_ENABLE check from prepare program and read to the caller.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: support DTS quad enable requirements
213ec26 
Adds support for DTS quad_enable_requirements property.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: support SFDP quad enable requirements
283d5fa 
Parses SFDP QER related DW15 to use as the source for QER.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: always include gpio header
8b7b012 
Always include gpio header.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: remove flag_quad_io_en field
8358837 
There is no need in the `flag_quad_io_en` field.
When QE enabling failed, then the driver `init` fails as well.

There is no way to use qspi in quad mode if qe is not enabled.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV
drivers: flash: stm32: qspi: use ternary and asserts in quad prepare
689528b 
Use ternary operation and asserts to reduce the footprint
and code size.

Signed-off-by: Georgij Cernysiov <[email protected]>
@GeorgeCGV GeorgeCGV force-pushed the stm32_qspi_nor_qe_qmodes branch from c7152b0 to 689528b Compare May 13, 2022 08:20
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GeorgeCGV commented May 13, 2022

Rebased, got rid of flag_quad_io_en and switched to the ternary operator and asserts in the quad command preparation.

@GeorgeCGV GeorgeCGV requested a review from FRASTM May 13, 2022 08:31
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A bit of commit number inflation, but I won't be picky this close to the DV freeze.

@erwango erwango added this to the v3.1.0 milestone May 13, 2022
FRASTM
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mbolivar-nordic commented May 13, 2022

@nvlsianpu I'm going to merge this to make it in time for code freeze since the changes to the common SPI NOR header seem quite harmless. If I messed up, I apologize, and we can revert.

@mbolivar-nordic mbolivar-nordic merged commit 4f10178 into zephyrproject-rtos:main May 13, 2022
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GeorgeCGV commented May 13, 2022

@nvlsianpu I'm going to merge this to make it in time for code freeze since the changes to the common SPI NOR header seem quite harmless. If I messed up, I apologize, and we can revert.

  • SPI_NOR_QE_BIT - wasn't used by any existing driver
  • SPI_NOR_CMD_4PP - was used by the STM32 QSPI driver. Therefore, renaming shall be fine
  • RDSR3/WRSR3 - new
  • SPI_NOR_CMD_PP_1_4_4 - new

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@erwango erwango erwango approved these changes

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