diff --git a/boards/arm/stm32f746g_disco/Kconfig.defconfig b/boards/arm/stm32f746g_disco/Kconfig.defconfig
index 0e7cd38b557e0..c77beb992e641 100644
--- a/boards/arm/stm32f746g_disco/Kconfig.defconfig
+++ b/boards/arm/stm32f746g_disco/Kconfig.defconfig
@@ -15,14 +15,29 @@ config NET_L2_ETHERNET
 
 endif # NETWORKING
 
-config I2C
-	default y if KSCAN
+if DISPLAY
+
+config KSCAN
+	default y
+
+# MEMC needs to be enabled in order to store
+# display buffer to external SDRAM connected to FMC
+config MEMC
+	default y
+
+endif # DISPLAY
 
 if KSCAN
 
+config I2C
+	default y
+
 config KSCAN_FT5336
 	default y
 
+config KSCAN_FT5336_INTERRUPT
+	default y
+
 endif # KSCAN
 
 config DISK_DRIVER_SDMMC
diff --git a/boards/arm/stm32f746g_disco/doc/index.rst b/boards/arm/stm32f746g_disco/doc/index.rst
index bf47d2d6e9611..508426a132345 100644
--- a/boards/arm/stm32f746g_disco/doc/index.rst
+++ b/boards/arm/stm32f746g_disco/doc/index.rst
@@ -116,6 +116,10 @@ The Zephyr stm32f746g_disco board configuration supports the following hardware
 +-----------+------------+-------------------------------------+
 | QSPI NOR  | on-chip    | off-chip flash                      |
 +-----------+------------+-------------------------------------+
+| FMC       | on-chip    | memc (SDRAM)                        |
++-----------+------------+-------------------------------------+
+| LTDC      | on-chip    | display                             |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on Zephyr porting.
 
@@ -147,6 +151,22 @@ configured as follows
 - LD1 : PI1
 - USB DM : PA11
 - USB DP : PA12
+- FMC SDRAM :
+
+   - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10
+   - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1
+   - A14/A15 : PG4/PG5
+   - SDNRAS/SDNCAS : PF11/PG15
+   - NBL0/NBL1 : PE0/PE1
+   - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3
+
+- LTDC :
+
+   - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6
+   - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2
+   - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6
+   - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13
+
 
 System Clock
 ============
diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts
index 639762782b13a..9d5d063b9f043 100644
--- a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts
+++ b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts
@@ -20,6 +20,7 @@
 		zephyr,flash = &flash0;
 		zephyr,dtcm = &dtcm;
 		zephyr,flash-controller = &n25q128a1;
+		zephyr,display = &ltdc;
 	};
 
 	leds {
@@ -38,6 +39,13 @@
 		};
 	};
 
+	sdram1: sdram@c0000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0xc0000000 DT_SIZE_M(16)>;
+		zephyr,memory-region = "SDRAM1";
+	};
+
 	aliases {
 		led0 = &green_led_1;
 		sw0 = &user_button;
@@ -185,3 +193,75 @@ zephyr_udc0: &usbotg_fs {
 		};
 	};
 };
+
+&fmc {
+	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
+		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_pc3
+		     &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
+		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
+		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
+		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
+		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
+		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
+		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
+		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
+		     &fmc_d15_pd10>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	sdram {
+		status = "okay";
+		power-up-delay = <100>;
+		num-auto-refresh = <8>;
+		mode-register = <0x220>;
+		/*
+		 * Auto refresh command shall be issued every 15.625 us
+		 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
+		 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
+		 */
+		refresh-rate = <1667>;
+		bank@0 {
+			reg = <0>;
+			st,sdram-control = <STM32_FMC_SDRAM_NC_8
+						STM32_FMC_SDRAM_NR_12
+						STM32_FMC_SDRAM_MWID_16
+						STM32_FMC_SDRAM_NB_4
+						STM32_FMC_SDRAM_CAS_2
+						STM32_FMC_SDRAM_SDCLK_PERIOD_2
+						STM32_FMC_SDRAM_RBURST_ENABLE
+						STM32_FMC_SDRAM_RPIPE_0>;
+			st,sdram-timing = <2 6 4 6 2 2 2>;
+		};
+	};
+};
+
+&ltdc {
+	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
+		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
+		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
+		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
+		     &ltdc_b0_pe4 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
+		     &ltdc_b4_pg12 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
+		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
+	pinctrl-names = "default";
+	disp-on-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
+	ext-sdram = <&sdram1>;
+	status = "okay";
+
+	width = <480>;
+	height = <272>;
+	hsync-pol = <STM32_LTDC_HSPOL_ACTIVE_LOW>;
+	vsync-pol = <STM32_LTDC_VSPOL_ACTIVE_LOW>;
+	de-pol = <STM32_LTDC_DEPOL_ACTIVE_LOW>;
+	pclk-pol = <STM32_LTDC_PCPOL_ACTIVE_LOW>;
+	hsync-duration = <1>;
+	vsync-duration = <10>;
+	hbp-duration = <43>;
+	vbp-duration = <12>;
+	hfp-duration = <8>;
+	vfp-duration = <4>;
+	def-back-color-red = <0xFF>;
+	def-back-color-green = <0xFF>;
+	def-back-color-blue = <0xFF>;
+};
diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml b/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml
index 52aa50abf0599..9c2d49a17b937 100644
--- a/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml
+++ b/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml
@@ -19,3 +19,5 @@ supported:
   - sdhc
   - usb_device
   - kscan:touch
+  - display
+  - memc
diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
index 937cccf6e647c..c9c9c6e91d848 100644
--- a/drivers/display/display_stm32_ltdc.c
+++ b/drivers/display/display_stm32_ltdc.c
@@ -262,9 +262,9 @@ static int stm32_ltdc_init(const struct device *dev)
 #if defined(CONFIG_SOC_SERIES_STM32F7X)
 	LL_RCC_PLLSAI_Disable();
 	LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
-					LL_RCC_PLLM_DIV_8,
-					192,
-					LL_RCC_PLLSAIR_DIV_4,
+					LL_RCC_PLLM_DIV_25,
+					384,
+					LL_RCC_PLLSAIR_DIV_5,
 					LL_RCC_PLLSAIDIVR_DIV_8);
 
 	LL_RCC_PLLSAI_Enable();
diff --git a/dts/arm/st/f4/stm32f429.dtsi b/dts/arm/st/f4/stm32f429.dtsi
index ce2b02f917ccd..ace29fe32e409 100644
--- a/dts/arm/st/f4/stm32f429.dtsi
+++ b/dts/arm/st/f4/stm32f429.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/f4/stm32f427.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/f7/stm32f746.dtsi b/dts/arm/st/f7/stm32f746.dtsi
index 2bd662f14ea82..de22ebf950823 100644
--- a/dts/arm/st/f7/stm32f746.dtsi
+++ b/dts/arm/st/f7/stm32f746.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/f7/stm32f745.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi
index f83633fa5dea9..56b76c1465367 100644
--- a/dts/arm/st/f7/stm32f767.dtsi
+++ b/dts/arm/st/f7/stm32f767.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/f7/stm32f7.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi
index 9d2980f6fe182..3ddd9b6de097f 100644
--- a/dts/arm/st/h7/stm32h723.dtsi
+++ b/dts/arm/st/h7/stm32h723.dtsi
@@ -7,6 +7,7 @@
 
 #include <mem.h>
 #include <st/h7/stm32h7.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi
index 3327dce99d527..2d1d7f4dd4367 100644
--- a/dts/arm/st/h7/stm32h743.dtsi
+++ b/dts/arm/st/h7/stm32h743.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/h7/stm32h7.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi
index fe6cd754e86a5..1289deb7b4fb9 100644
--- a/dts/arm/st/h7/stm32h745.dtsi
+++ b/dts/arm/st/h7/stm32h745.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/h7/stm32h7_dualcore.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi
index bf6bb1e301d25..897989db56b66 100644
--- a/dts/arm/st/h7/stm32h750.dtsi
+++ b/dts/arm/st/h7/stm32h750.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/h7/stm32h7.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi
index 9df866b73e25f..ffbf91987709a 100644
--- a/dts/arm/st/h7/stm32h7a3.dtsi
+++ b/dts/arm/st/h7/stm32h7a3.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <st/h7/stm32h7.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/l4/stm32l4r9.dtsi b/dts/arm/st/l4/stm32l4r9.dtsi
index f79b560236c6f..08b98c7df9b37 100644
--- a/dts/arm/st/l4/stm32l4r9.dtsi
+++ b/dts/arm/st/l4/stm32l4r9.dtsi
@@ -6,6 +6,7 @@
 
 #include <mem.h>
 #include <st/l4/stm32l4r5.dtsi>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	soc {
diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi
index c7953ea5b8578..b9db3c86e1736 100644
--- a/dts/arm/st/mp1/stm32mp157.dtsi
+++ b/dts/arm/st/mp1/stm32mp157.dtsi
@@ -13,6 +13,7 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
+#include <zephyr/dt-bindings/display/stm32_ltdc.h>
 
 / {
 	cpus {
diff --git a/samples/subsys/display/lvgl/boards/stm32f746g_disco.conf b/samples/subsys/display/lvgl/boards/stm32f746g_disco.conf
new file mode 100644
index 0000000000000..d70c016b29f50
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/stm32f746g_disco.conf
@@ -0,0 +1,2 @@
+CONFIG_LV_Z_POINTER_KSCAN=y
+CONFIG_LV_Z_POINTER_KSCAN_DEV_NAME="FT5336"