diff --git a/boards/arm/sam_v71_xult/Kconfig.board b/boards/arm/sam_v71_xult/Kconfig.board index 9ca0469360e4c..2d2d46c7c8cdc 100644 --- a/boards/arm/sam_v71_xult/Kconfig.board +++ b/boards/arm/sam_v71_xult/Kconfig.board @@ -7,3 +7,7 @@ config BOARD_SAM_V71_XULT bool "Atmel SMART SAM V71 Xplained Ultra Board" depends on SOC_PART_NUMBER_SAMV71Q21 || SOC_PART_NUMBER_SAMV71Q21B + +config BOARD_SAM_V70_XULT + bool "Atmel SMART SAM V70 Xplained Ultra Board" + depends on SOC_PART_NUMBER_SAMV70Q20 || SOC_PART_NUMBER_SAMV70Q20B diff --git a/boards/arm/sam_v71_xult/Kconfig.defconfig b/boards/arm/sam_v71_xult/Kconfig.defconfig index 09607a270387e..57d4e4007577e 100644 --- a/boards/arm/sam_v71_xult/Kconfig.defconfig +++ b/boards/arm/sam_v71_xult/Kconfig.defconfig @@ -1,4 +1,4 @@ -# Atmel SMART SAM V71 Xplained Board configuration +# Atmel SMART SAM V70/V71 Xplained Board configuration # Copyright (c) 2019 Gerson Fernando Budke # Copyright (c) 2016 Piotr Mienkowski @@ -44,3 +44,10 @@ config ETH_SAM_GMAC endif # NETWORKING endif # BOARD_SAM_V71_XULT + +if BOARD_SAM_V70_XULT + +config BOARD + default "sam_v70_xult" + +endif # BOARD_SAM_V70_XULT diff --git a/boards/arm/sam_v71_xult/doc/index.rst b/boards/arm/sam_v71_xult/doc/index.rst index ae58e0a21cebc..aaaf3eeb8e455 100644 --- a/boards/arm/sam_v71_xult/doc/index.rst +++ b/boards/arm/sam_v71_xult/doc/index.rst @@ -1,7 +1,7 @@ .. _sam_v71_xplained_ultra: -SAM V71(B) Xplained Ultra -######################### +SAM V70/V71 (B) Xplained Ultra +############################## Overview ******** @@ -10,6 +10,12 @@ The SAM V71 Xplained Ultra evaluation kit is a development platform to evaluate the Atmel SAM V71 series microcontrollers. The current version allows to use both IC variations ATSAMV71Q21A(B). +There are two additional variations of this board, sam_v70_xult and +sam_v70b_xult. While these are not actually manufactured variations, they exist +to test the SAM V70 support. These boards are configured with an ATSAMV70Q20(b) +processor and are functionally identical to the SAM V71 versions, minus +Ethernet. + .. image:: img/sam_v71_xult.jpg :width: 500px :align: center diff --git a/boards/arm/sam_v71_xult/sam_v70_xult.dts b/boards/arm/sam_v71_xult/sam_v70_xult.dts new file mode 100644 index 0000000000000..45bc4f12b9a1b --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70_xult.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2019-2020 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "sam_v7x_xult-pinctrl-common.dtsi" +#include "sam_v7x_xult-common.dtsi" + +/ { + model = "Atmel SAM V70 Xplained Ultra board"; + compatible = "atmel,sam_v70_xult", "atmel,samv70x19", "atmel,samv70"; +}; diff --git a/boards/arm/sam_v71_xult/sam_v70_xult.yaml b/boards/arm/sam_v71_xult/sam_v70_xult.yaml new file mode 100644 index 0000000000000..d00929a328e56 --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70_xult.yaml @@ -0,0 +1,25 @@ +identifier: sam_v70_xult +name: SAM V70 Xplained Ultra +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - gpio + - spi + - watchdog + - usb_device + - pwm + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi + - can + - canfd + - hwinfo diff --git a/boards/arm/sam_v71_xult/sam_v70_xult_defconfig b/boards/arm/sam_v71_xult/sam_v70_xult_defconfig new file mode 100644 index 0000000000000..8f89c7b9a561a --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70_xult_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_SAMV70=y +CONFIG_SOC_PART_NUMBER_SAMV70Q20=y +CONFIG_SOC_ATMEL_SAMV70_EXT_MAINCK=y +CONFIG_SOC_ATMEL_SAMV70_PLLA_MULA=24 +CONFIG_SOC_ATMEL_SAMV70_PLLA_DIVA=1 +CONFIG_ARM_MPU=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_USART_SAM=y +CONFIG_BOARD_SAM_V70_XULT=y +CONFIG_WDT_DISABLE_AT_BOOT=y +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/sam_v71_xult/sam_v70b_xult.dts b/boards/arm/sam_v71_xult/sam_v70b_xult.dts new file mode 100644 index 0000000000000..7efbc63cd2d99 --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70b_xult.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2020 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "sam_v7x_xult-pinctrl-common.dtsi" +#include "sam_v7x_xult-common.dtsi" + +/ { + model = "Atmel SAM V70B Xplained Ultra board"; + compatible = "atmel,sam_v70b_xult", "atmel,samv70q20b", "atmel,samv70b"; +}; diff --git a/boards/arm/sam_v71_xult/sam_v70b_xult.yaml b/boards/arm/sam_v71_xult/sam_v70b_xult.yaml new file mode 100644 index 0000000000000..25551fb88fae6 --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70b_xult.yaml @@ -0,0 +1,25 @@ +identifier: sam_v70b_xult +name: SAM V70 Xplained Ultra (Revision B) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - gpio + - spi + - watchdog + - usb_device + - pwm + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi + - can + - canfd + - hwinfo diff --git a/boards/arm/sam_v71_xult/sam_v70b_xult_defconfig b/boards/arm/sam_v71_xult/sam_v70b_xult_defconfig new file mode 100644 index 0000000000000..c0f73dfaedcdd --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v70b_xult_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_SAMV70=y +CONFIG_SOC_PART_NUMBER_SAMV70Q20B=y +CONFIG_SOC_ATMEL_SAMV70_EXT_MAINCK=y +CONFIG_SOC_ATMEL_SAMV70_PLLA_MULA=24 +CONFIG_SOC_ATMEL_SAMV70_PLLA_DIVA=1 +CONFIG_ARM_MPU=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_USART_SAM=y +CONFIG_BOARD_SAM_V70_XULT=y +CONFIG_WDT_DISABLE_AT_BOOT=y +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi index 2a42d89fc2aa8..5c36d6c52f12e 100644 --- a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi @@ -1,222 +1,3 @@ -/* - * Copyright (c) 2017 Piotr Mienkowski - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2019-2022 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sam_v71_xult-pinctrl.dtsi" - -/ { - aliases { - i2c-0 = &twihs0; - i2c-1 = &twihs2; - led0 = &yellow_led1; - pwm-led0 = &pwm_led0; - pwm-0 = &pwm0; - sw0 = &sw0_user_button; - sw1 = &sw1_user_button; - }; - - chosen { - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,canbus = &can1; - }; - - leds { - compatible = "gpio-leds"; - yellow_led0: led_0 { - gpios = <&pioa 23 GPIO_ACTIVE_LOW>; - label = "User LED 0"; - status = "disabled"; - }; - yellow_led1: led_1 { - gpios = <&pioc 9 GPIO_ACTIVE_LOW>; - label = "User LED 1"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm0 0 PWM_MSEC(20)>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - /* The switch is labeled SW300/301 in the schematic, and - * labeled SW0 on the board, and labeled ERASE User Button - * on docs - */ - sw0_user_button: button_1 { - label = "User Button 0"; - gpios = <&pioa 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - }; - sw1_user_button: button_2 { - label = "User Button 1"; - gpios = <&piob 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - }; - }; - - ext1_header: xplained-pro-connector1 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioc 31 0>, /* AFE1 AD6 */ - <1 0 &pioa 19 0>, /* AFE0 AD8 */ - <2 0 &piob 3 0>, /* RTS0 */ - <3 0 &piob 2 0>, /* CTS0 */ - <4 0 &pioa 0 0>, /* PWMC0_H0 */ - <5 0 &pioc 30 0>, /* TIOB5 */ - <6 0 &piod 28 0>, /* WKUP5 */ - <7 0 &pioa 5 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXT2 */ - <9 0 &pioa 4 0>, /* TWCK0 EXT2 */ - <10 0 &piob 0 0>, /* RXD0 */ - <11 0 &piob 1 0>, /* TXD0 */ - <12 0 &piod 25 0>, /* SPI0(NPCS1) */ - <13 0 &piod 21 0>, /* SPI0(MOSI) EXT2 */ - <14 0 &piod 20 0>, /* SPI0(MISO) EXT2 */ - <15 0 &piod 22 0>; /* SPI0(SCK) EXT2 */ - /* GND */ - /* +3.3V */ - }; - - ext2_header: xplained-pro-connector2 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &piod 30 0>, /* AFE0 AD0 */ - <1 0 &pioc 13 0>, /* AFE1 AD1 */ - <2 0 &pioa 6 0>, /* GPIO */ - <3 0 &piod 11 0>, /* GPIO */ - <4 0 &pioc 19 0>, /* PWMC0_H2 */ - <5 0 &piod 26 0>, /* PWMC0_L2 */ - <6 0 &pioa 2 0>, /* WKUP2 */ - <7 0 &pioa 24 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXT1 */ - <9 0 &pioa 4 0>, /* TWCK0 EXT1 */ - <10 0 &pioa 21 0>, /* RXD1 */ - <11 0 &piob 4 0>, /* TXD1 */ - <12 0 &piod 27 0>, /* SPI0(NPCS3) */ - <13 0 &piod 21 0>, /* SPI0(MOSI) EXT1 */ - <14 0 &piod 20 0>, /* SPI0(MISO) EXT1 */ - <15 0 &piod 22 0>; /* SPI0(SCK) EXT1 */ - /* GND */ - /* +3.3V */ - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &piod 26 0>, /* A0-TD */ - <1 0 &pioc 31 0>, /* A1-AFE1 AD6 y */ - <2 0 &pioa 19 0>, /* A2-AFE0 AD8 y */ - <3 0 &piod 30 0>, /* A3-AFE0 AD0 y */ - <4 0 &pioc 13 0>, /* A4-AFE1 AD1 y */ - <5 0 &pioe 0 0>, /* A5-AFE1 AD11 */ - <6 0 &piod 28 0>, /* D0-URXD3 */ - <7 0 &piod 30 0>, /* D1-UTXD3 */ - <8 0 &pioa 0 0>, /* D2-PWMC0_H0 */ - <9 0 &pioa 6 0>, /* D3-GPIO */ - <10 0 &piod 27 0>, /* D4-SPI0_NPCS3 y */ - <11 0 &piod 11 0>, /* D5-PWMC0_H0 */ - <12 0 &pioc 19 0>, /* D6-PWMC0_H2 */ - <13 0 &pioa 2 0>, /* D7-PWMC0_H1 */ - <14 0 &pioa 5 0>, /* D8-PWMC1_PWML3 */ - <15 0 &pioc 9 0>, /* D9-TIOB7 */ - <16 0 &piod 25 0>, /* D10-SPI0_NPCS1 y */ - <17 0 &piod 21 0>, /* D11-SPI0_MOSI y */ - <18 0 &piod 20 0>, /* D12-SPI0_MISO y */ - <19 0 &piod 22 0>, /* D13-SPI0_SPCK y */ - <20 0 &pioa 3 0>, /* D14-TWD0 y */ - <21 0 &pioa 4 0>; /* D15-TWCK0 y */ - }; -}; - -&cpu0 { - clock-frequency = <300000000>; -}; - -&afec0 { - status = "okay"; - - pinctrl-0 = <&afec0_default>; - pinctrl-names = "default"; -}; - -&afec1 { - status = "okay"; - - pinctrl-0 = <&afec1_default>; - pinctrl-names = "default"; -}; - -&dacc { - status = "okay"; -}; - -&twihs0 { - status = "okay"; - - pinctrl-0 = <&twihs0_default>; - pinctrl-names = "default"; -}; - -&twihs2 { - status = "okay"; - - pinctrl-0 = <&twihs2_default>; - pinctrl-names = "default"; -}; - -&spi0 { - status = "okay"; - - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - - cs-gpios = <&piod 25 GPIO_ACTIVE_LOW>, - <&piod 27 GPIO_ACTIVE_LOW>; -}; - -&usart1 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&usart1_default>; - pinctrl-names = "default"; -}; - -&uart3 { - status = "okay"; - current-speed = <115200>; - - - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; -}; - -&wdt { - status = "okay"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - &gmac { status = "okay"; @@ -237,118 +18,3 @@ zephyr_udc0: &usbhs { pinctrl-0 = <&mdio_default>; pinctrl-names = "default"; }; - -&pwm0 { - status = "okay"; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&pioa { - status = "okay"; -}; - -&piob { - status = "okay"; -}; - -&pioc { - status = "okay"; -}; - -&piod { - status = "okay"; -}; - -&pioe { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The first half of sector 0 (64 kbytes) - * is reserved for the bootloader - */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00010000>; - read-only; - }; - - /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x000e0000>; - }; - - /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ - slot1_partition: partition@100000 { - label = "image-1"; - reg = <0x00100000 0x000e0000>; - }; - - /* Sector 15: scratch (128 kbytes) */ - scratch_partition: partition@1e0000 { - label = "image-scratch"; - reg = <0x001e0000 0x00020000>; - }; - }; -}; - -&ssc { - status = "okay"; - label = "I2S_0"; - - pinctrl-0 = <&ssc_default>; - pinctrl-names = "default"; - - dma-names = "rx", "tx"; - dmas = <&xdmac 22 DMA_PERID_SSC_RX>, <&xdmac 23 DMA_PERID_SSC_TX>; -}; - -&can1 { - status = "okay"; - - pinctrl-0 = <&can1_default>; - pinctrl-names = "default"; - - bus-speed = <125000>; - bus-speed-data = <1000000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -ext1_spi: &spi0 { -}; - -ext1_i2c: &twihs0 { -}; - -ext1_serial: &usart0 { -}; - -ext2_spi: &spi0 { -}; - -ext2_i2c: &twihs0 { -}; - -ext2_serial: &usart1 { -}; - -arduino_spi: &spi0 { -}; - -arduino_i2c: &twihs0 { -}; - -arduino_serial: &uart3 { -}; diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi b/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi index 328d68762f8cd..b7aff842d35ea 100644 --- a/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi +++ b/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi @@ -4,29 +4,9 @@ */ #include +#include "sam_v7x_xult-pinctrl-common.dtsi" &pinctrl { - afec0_default: afec0_default { - group1 { - pinmux = , - ; - }; - }; - - afec1_default: afec1_default { - group1 { - pinmux = , - ; - }; - }; - - can1_default: can1_default { - group1 { - pinmux = , - ; - }; - }; - gmac_rmii: gmac_rmii { group1 { pinmux = , @@ -46,111 +26,4 @@ ; }; }; - - pwm_default: pwm_default { - group1 { - pinmux = , - , - , - ; - }; - }; - - spi0_default: spi0_default { - group1 { - pinmux = , - , - , - , - ; - }; - }; - - ssc_default: ssc_default { - group1 { - pinmux = , - , - , - , - , - ; - }; - }; - - twihs0_default: twihs0_default { - group1 { - pinmux = , - ; - }; - }; - twihs2_default: twihs2_default { - group1 { - pinmux = , - ; - }; - }; - - uart3_default: uart3_default { - group1 { - pinmux = , - ; - }; - }; - uart4_default: uart4_default { - group1 { - pinmux = , - ; - }; - }; - usart0_default: usart0_default { - group1 { - pinmux = , - ; - }; - }; - usart0_hw_ctrl_flow: usart0_hw_ctrl_flow { - group1 { - pinmux = , - ; - bias-pull-up; - }; - group1 { - pinmux = , - ; - }; - }; - usart1_default: usart1_default { - group1 { - pinmux = , - ; - }; - }; - usart1_hw_ctrl_flow: usart1_hw_ctrl_flow { - group1 { - pinmux = , - ; - bias-pull-up; - }; - group1 { - pinmux = , - ; - }; - }; - usart2_default: usart2_default { - group1 { - pinmux = , - ; - }; - }; - usart2_hw_ctrl_flow: usart2_hw_ctrl_flow_clk { - group1 { - pinmux = , - ; - bias-pull-up; - }; - group1 { - pinmux = , - ; - }; - }; }; diff --git a/boards/arm/sam_v71_xult/sam_v71_xult.dts b/boards/arm/sam_v71_xult/sam_v71_xult.dts index 634da676e964d..0802f0dbcd012 100644 --- a/boards/arm/sam_v71_xult/sam_v71_xult.dts +++ b/boards/arm/sam_v71_xult/sam_v71_xult.dts @@ -9,6 +9,8 @@ /dts-v1/; #include +#include "sam_v71_xult-pinctrl.dtsi" +#include "sam_v7x_xult-common.dtsi" #include "sam_v71_xult-common.dtsi" / { diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult.dts b/boards/arm/sam_v71_xult/sam_v71b_xult.dts index 8f16beb951fe1..31ba547ff69a5 100644 --- a/boards/arm/sam_v71_xult/sam_v71b_xult.dts +++ b/boards/arm/sam_v71_xult/sam_v71b_xult.dts @@ -8,6 +8,8 @@ /dts-v1/; #include +#include "sam_v71_xult-pinctrl.dtsi" +#include "sam_v7x_xult-common.dtsi" #include "sam_v71_xult-common.dtsi" / { diff --git a/boards/arm/sam_v71_xult/sam_v7x_xult-common.dtsi b/boards/arm/sam_v71_xult/sam_v7x_xult-common.dtsi new file mode 100644 index 0000000000000..9b14d3625dd54 --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v7x_xult-common.dtsi @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2019-2022 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sam_v7x_xult-pinctrl-common.dtsi" + +/ { + aliases { + i2c-0 = &twihs0; + i2c-1 = &twihs2; + led0 = &yellow_led1; + pwm-led0 = &pwm_led0; + pwm-0 = &pwm0; + sw0 = &sw0_user_button; + sw1 = &sw1_user_button; + }; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &can1; + }; + + leds { + compatible = "gpio-leds"; + yellow_led0: led_0 { + gpios = <&pioa 23 GPIO_ACTIVE_LOW>; + label = "User LED 0"; + status = "disabled"; + }; + yellow_led1: led_1 { + gpios = <&pioc 9 GPIO_ACTIVE_LOW>; + label = "User LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20)>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* The switch is labeled SW300/301 in the schematic, and + * labeled SW0 on the board, and labeled ERASE User Button + * on docs + */ + sw0_user_button: button_1 { + label = "User Button 0"; + gpios = <&pioa 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + }; + sw1_user_button: button_2 { + label = "User Button 1"; + gpios = <&piob 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + }; + }; + + ext1_header: xplained-pro-connector1 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = <0 0 &pioc 31 0>, /* AFE1 AD6 */ + <1 0 &pioa 19 0>, /* AFE0 AD8 */ + <2 0 &piob 3 0>, /* RTS0 */ + <3 0 &piob 2 0>, /* CTS0 */ + <4 0 &pioa 0 0>, /* PWMC0_H0 */ + <5 0 &pioc 30 0>, /* TIOB5 */ + <6 0 &piod 28 0>, /* WKUP5 */ + <7 0 &pioa 5 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXT2 */ + <9 0 &pioa 4 0>, /* TWCK0 EXT2 */ + <10 0 &piob 0 0>, /* RXD0 */ + <11 0 &piob 1 0>, /* TXD0 */ + <12 0 &piod 25 0>, /* SPI0(NPCS1) */ + <13 0 &piod 21 0>, /* SPI0(MOSI) EXT2 */ + <14 0 &piod 20 0>, /* SPI0(MISO) EXT2 */ + <15 0 &piod 22 0>; /* SPI0(SCK) EXT2 */ + /* GND */ + /* +3.3V */ + }; + + ext2_header: xplained-pro-connector2 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = <0 0 &piod 30 0>, /* AFE0 AD0 */ + <1 0 &pioc 13 0>, /* AFE1 AD1 */ + <2 0 &pioa 6 0>, /* GPIO */ + <3 0 &piod 11 0>, /* GPIO */ + <4 0 &pioc 19 0>, /* PWMC0_H2 */ + <5 0 &piod 26 0>, /* PWMC0_L2 */ + <6 0 &pioa 2 0>, /* WKUP2 */ + <7 0 &pioa 24 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXT1 */ + <9 0 &pioa 4 0>, /* TWCK0 EXT1 */ + <10 0 &pioa 21 0>, /* RXD1 */ + <11 0 &piob 4 0>, /* TXD1 */ + <12 0 &piod 27 0>, /* SPI0(NPCS3) */ + <13 0 &piod 21 0>, /* SPI0(MOSI) EXT1 */ + <14 0 &piod 20 0>, /* SPI0(MISO) EXT1 */ + <15 0 &piod 22 0>; /* SPI0(SCK) EXT1 */ + /* GND */ + /* +3.3V */ + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = <0 0 &piod 26 0>, /* A0-TD */ + <1 0 &pioc 31 0>, /* A1-AFE1 AD6 y */ + <2 0 &pioa 19 0>, /* A2-AFE0 AD8 y */ + <3 0 &piod 30 0>, /* A3-AFE0 AD0 y */ + <4 0 &pioc 13 0>, /* A4-AFE1 AD1 y */ + <5 0 &pioe 0 0>, /* A5-AFE1 AD11 */ + <6 0 &piod 28 0>, /* D0-URXD3 */ + <7 0 &piod 30 0>, /* D1-UTXD3 */ + <8 0 &pioa 0 0>, /* D2-PWMC0_H0 */ + <9 0 &pioa 6 0>, /* D3-GPIO */ + <10 0 &piod 27 0>, /* D4-SPI0_NPCS3 y */ + <11 0 &piod 11 0>, /* D5-PWMC0_H0 */ + <12 0 &pioc 19 0>, /* D6-PWMC0_H2 */ + <13 0 &pioa 2 0>, /* D7-PWMC0_H1 */ + <14 0 &pioa 5 0>, /* D8-PWMC1_PWML3 */ + <15 0 &pioc 9 0>, /* D9-TIOB7 */ + <16 0 &piod 25 0>, /* D10-SPI0_NPCS1 y */ + <17 0 &piod 21 0>, /* D11-SPI0_MOSI y */ + <18 0 &piod 20 0>, /* D12-SPI0_MISO y */ + <19 0 &piod 22 0>, /* D13-SPI0_SPCK y */ + <20 0 &pioa 3 0>, /* D14-TWD0 y */ + <21 0 &pioa 4 0>; /* D15-TWCK0 y */ + }; +}; + +&cpu0 { + clock-frequency = <300000000>; +}; + +&afec0 { + status = "okay"; + + pinctrl-0 = <&afec0_default>; + pinctrl-names = "default"; +}; + +&afec1 { + status = "okay"; + + pinctrl-0 = <&afec1_default>; + pinctrl-names = "default"; +}; + +&dacc { + status = "okay"; +}; + +&twihs0 { + status = "okay"; + + pinctrl-0 = <&twihs0_default>; + pinctrl-names = "default"; +}; + +&twihs2 { + status = "okay"; + + pinctrl-0 = <&twihs2_default>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + + cs-gpios = <&piod 25 GPIO_ACTIVE_LOW>, + <&piod 27 GPIO_ACTIVE_LOW>; +}; + +&usart1 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; +}; + +&uart3 { + status = "okay"; + current-speed = <115200>; + + + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; +}; + +&wdt { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&pioa { + status = "okay"; +}; + +&piob { + status = "okay"; +}; + +&pioc { + status = "okay"; +}; + +&piod { + status = "okay"; +}; + +&pioe { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The first half of sector 0 (64 kbytes) + * is reserved for the bootloader + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00010000>; + read-only; + }; + + /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x000e0000>; + }; + + /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x00100000 0x000e0000>; + }; + + /* Sector 15: scratch (128 kbytes) */ + scratch_partition: partition@1e0000 { + label = "image-scratch"; + reg = <0x001e0000 0x00020000>; + }; + }; +}; + +&ssc { + status = "okay"; + label = "I2S_0"; + + pinctrl-0 = <&ssc_default>; + pinctrl-names = "default"; + + dma-names = "rx", "tx"; + dmas = <&xdmac 22 DMA_PERID_SSC_RX>, <&xdmac 23 DMA_PERID_SSC_TX>; +}; + +&can1 { + status = "okay"; + + pinctrl-0 = <&can1_default>; + pinctrl-names = "default"; + + bus-speed = <125000>; + bus-speed-data = <1000000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +ext1_spi: &spi0 { +}; + +ext1_i2c: &twihs0 { +}; + +ext1_serial: &usart0 { +}; + +ext2_spi: &spi0 { +}; + +ext2_i2c: &twihs0 { +}; + +ext2_serial: &usart1 { +}; + +arduino_spi: &spi0 { +}; + +arduino_i2c: &twihs0 { +}; + +arduino_serial: &uart3 { +}; diff --git a/boards/arm/sam_v71_xult/sam_v7x_xult-pinctrl-common.dtsi b/boards/arm/sam_v71_xult/sam_v7x_xult-pinctrl-common.dtsi new file mode 100644 index 0000000000000..7a5cd22176b2f --- /dev/null +++ b/boards/arm/sam_v71_xult/sam_v7x_xult-pinctrl-common.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2022, Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + afec0_default: afec0_default { + group1 { + pinmux = , + ; + }; + }; + + afec1_default: afec1_default { + group1 { + pinmux = , + ; + }; + }; + + can1_default: can1_default { + group1 { + pinmux = , + ; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = , + , + , + ; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , + , + , + , + ; + }; + }; + + ssc_default: ssc_default { + group1 { + pinmux = , + , + , + , + , + ; + }; + }; + + twihs0_default: twihs0_default { + group1 { + pinmux = , + ; + }; + }; + twihs2_default: twihs2_default { + group1 { + pinmux = , + ; + }; + }; + + uart3_default: uart3_default { + group1 { + pinmux = , + ; + }; + }; + uart4_default: uart4_default { + group1 { + pinmux = , + ; + }; + }; + usart0_default: usart0_default { + group1 { + pinmux = , + ; + }; + }; + usart0_hw_ctrl_flow: usart0_hw_ctrl_flow { + group1 { + pinmux = , + ; + bias-pull-up; + }; + group1 { + pinmux = , + ; + }; + }; + usart1_default: usart1_default { + group1 { + pinmux = , + ; + }; + }; + usart1_hw_ctrl_flow: usart1_hw_ctrl_flow { + group1 { + pinmux = , + ; + bias-pull-up; + }; + group1 { + pinmux = , + ; + }; + }; + usart2_default: usart2_default { + group1 { + pinmux = , + ; + }; + }; + usart2_hw_ctrl_flow: usart2_hw_ctrl_flow_clk { + group1 { + pinmux = , + ; + bias-pull-up; + }; + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/drivers/can/Kconfig.sam b/drivers/can/Kconfig.sam index 8952f4d1ae758..6e87920e57337 100644 --- a/drivers/can/Kconfig.sam +++ b/drivers/can/Kconfig.sam @@ -8,3 +8,15 @@ config CAN_SAM bool "Atmel SAM CAN driver" default $(dt_compat_enabled,$(DT_COMPAT_ATMEL_SAM_CAN)) select CAN_MCAN + +if CAN_SAM + +config CAN_MAX_FILTER + int "Maximum number of concurrent active filters" + default 5 + range 1 32 + help + Defines the array size of the callback/msgq pointers. + Must be at least the size of concurrent reads. + +endif # CAN_SAM diff --git a/drivers/ethernet/Kconfig.sam_gmac b/drivers/ethernet/Kconfig.sam_gmac index 8ad091888a794..c54554eff83c8 100644 --- a/drivers/ethernet/Kconfig.sam_gmac +++ b/drivers/ethernet/Kconfig.sam_gmac @@ -5,7 +5,7 @@ menuconfig ETH_SAM_GMAC bool "Atmel SAM Ethernet driver" - depends on SOC_FAMILY_SAM0 || SOC_FAMILY_SAM + depends on (SOC_FAMILY_SAM0 || SOC_FAMILY_SAM) && !SOC_SERIES_SAMV70 select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT select MDIO help diff --git a/drivers/flash/Kconfig.sam b/drivers/flash/Kconfig.sam index dfa6976475148..e895d99fc6e1a 100644 --- a/drivers/flash/Kconfig.sam +++ b/drivers/flash/Kconfig.sam @@ -10,6 +10,6 @@ config SOC_FLASH_SAM select FLASH_HAS_DRIVER_ENABLED select MPU_ALLOW_FLASH_WRITE if ARM_MPU depends on SOC_SERIES_SAME70 || \ - SOC_SERIES_SAMV71 + SOC_SERIES_SAMV71 || SOC_SERIES_SAMV70 help Enable the Atmel SAM series internal flash driver. diff --git a/dts/arm/atmel/samv70.dtsi b/dts/arm/atmel/samv70.dtsi new file mode 100644 index 0000000000000..1b98c7674cbdc --- /dev/null +++ b/dts/arm/atmel/samv70.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "dma_atmel_samv71.h" diff --git a/dts/arm/atmel/samv70b.dtsi b/dts/arm/atmel/samv70b.dtsi new file mode 100644 index 0000000000000..7e43b466a1a52 --- /dev/null +++ b/dts/arm/atmel/samv70b.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "dma_atmel_samv71.h" diff --git a/dts/arm/atmel/samv70n19b.dtsi b/dts/arm/atmel/samv70n19b.dtsi new file mode 100644 index 0000000000000..aa04e2799c025 --- /dev/null +++ b/dts/arm/atmel/samv70n19b.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/atmel/samv70x19.dtsi b/dts/arm/atmel/samv70x19.dtsi new file mode 100644 index 0000000000000..5c5e538b58957 --- /dev/null +++ b/dts/arm/atmel/samv70x19.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20400000 { + reg = <0x20400000 DT_SIZE_K(256)>; + }; + + soc { + flash-controller@400e0c00 { + flash0: flash@400000 { + reg = <0x00400000 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samv70x19b.dtsi b/dts/arm/atmel/samv70x19b.dtsi new file mode 100644 index 0000000000000..5f264a2533426 --- /dev/null +++ b/dts/arm/atmel/samv70x19b.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20400000 { + reg = <0x20400000 DT_SIZE_K(256)>; + }; + + soc { + flash-controller@400e0c00 { + flash0: flash@400000 { + reg = <0x00400000 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samv70x20.dtsi b/dts/arm/atmel/samv70x20.dtsi new file mode 100644 index 0000000000000..a8ca73c4ef552 --- /dev/null +++ b/dts/arm/atmel/samv70x20.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20400000 { + reg = <0x20400000 DT_SIZE_K(384)>; + }; + + soc { + flash-controller@400e0c00 { + flash0: flash@400000 { + reg = <0x00400000 DT_SIZE_K(1024)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samv70x20b.dtsi b/dts/arm/atmel/samv70x20b.dtsi new file mode 100644 index 0000000000000..b80c36c9adaa9 --- /dev/null +++ b/dts/arm/atmel/samv70x20b.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20400000 { + reg = <0x20400000 DT_SIZE_K(384)>; + }; + + soc { + flash-controller@400e0c00 { + flash0: flash@400000 { + reg = <0x00400000 DT_SIZE_K(1024)>; + }; + }; + }; +}; diff --git a/soc/arm/atmel_sam/samv70/CMakeLists.txt b/soc/arm/atmel_sam/samv70/CMakeLists.txt new file mode 100644 index 0000000000000..0ad494174ddca --- /dev/null +++ b/soc/arm/atmel_sam/samv70/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + soc_config.c + ) diff --git a/soc/arm/atmel_sam/samv70/Kconfig.defconfig.series b/soc/arm/atmel_sam/samv70/Kconfig.defconfig.series new file mode 100644 index 0000000000000..503eda839ff4c --- /dev/null +++ b/soc/arm/atmel_sam/samv70/Kconfig.defconfig.series @@ -0,0 +1,71 @@ +# Atmel SAM V70 MCU series configuration options + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMV70 + +config SOC_SERIES + default "samv70" + +config SOC_PART_NUMBER + default "samv70q20" if SOC_PART_NUMBER_SAMV70Q20 + default "samv70q19" if SOC_PART_NUMBER_SAMV70Q19 + default "samv70n20" if SOC_PART_NUMBER_SAMV70N20 + default "samv70n19" if SOC_PART_NUMBER_SAMV70N19 + default "samv70j20" if SOC_PART_NUMBER_SAMV70J20 + default "samv70j19" if SOC_PART_NUMBER_SAMV70J19 + default "samv70q20b" if SOC_PART_NUMBER_SAMV70Q20B + default "samv70q19b" if SOC_PART_NUMBER_SAMV70Q19B + default "samv70n20b" if SOC_PART_NUMBER_SAMV70N20B + default "samv70n19b" if SOC_PART_NUMBER_SAMV70N19B + default "samv70j20b" if SOC_PART_NUMBER_SAMV70J20B + default "samv70j19b" if SOC_PART_NUMBER_SAMV70J19B + +# +# SAM V70 family has in total 71 peripherals capable of generating interrupts +# for the revision A and 74 for the revision B (not all Peripheral Identifiers +# are used). +# +config NUM_IRQS + default 74 if SOC_ATMEL_SAMV70_REVB + default 71 + +# Configure default device drivers. If a feature is supported by more than one +# device driver the default configuration will be placed in the board defconfig +# file. + +config DMA_SAM_XDMAC + default y + depends on DMA + +config ADC_SAM_AFEC + default y + depends on ADC + +config I2C_SAM_TWIHS + default y + depends on I2C + +config I2S_SAM_SSC + default y + depends on I2S + +config USB_DC_SAM_USBHS + default y + depends on USB_DEVICE_DRIVER + +config ENTROPY_SAM_RNG + default y + depends on ENTROPY_GENERATOR + +config SOC_FLASH_SAM + default y + depends on FLASH + +config PWM_SAM + default y + depends on PWM + +endif # SOC_SERIES_SAMV70 diff --git a/soc/arm/atmel_sam/samv70/Kconfig.series b/soc/arm/atmel_sam/samv70/Kconfig.series new file mode 100644 index 0000000000000..b7c15f2153213 --- /dev/null +++ b/soc/arm/atmel_sam/samv70/Kconfig.series @@ -0,0 +1,22 @@ +# Atmel SAM V70 MCU series + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV70 + bool "Atmel SAMV70 MCU" + select ARM + select CPU_CORTEX_M7 + select SOC_FAMILY_SAM + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_CORTEX_M_HAS_CACHE + select CPU_CORTEX_M_HAS_DWT + select ASF + select XIP + select CPU_HAS_ARM_MPU + select HAS_SWO + help + Enable support for Atmel SAM V70 ARM Cortex-M7 Microcontrollers. + Part No.: SAMV70J19, SAMV70J20, SAMV70N19, SAMV70N20, SAMV70Q19, SAMV70Q20, + SAMV70J19B, SAMV70J20B, SAMV70N19B, SAMV70N20B, SAMV70Q19B, SAMV70Q20B diff --git a/soc/arm/atmel_sam/samv70/Kconfig.soc b/soc/arm/atmel_sam/samv70/Kconfig.soc new file mode 100644 index 0000000000000..e2780ca3f875c --- /dev/null +++ b/soc/arm/atmel_sam/samv70/Kconfig.soc @@ -0,0 +1,147 @@ +# Atmel SAM V70 MCU series + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAMV70 MCU Selection" + depends on SOC_SERIES_SAMV70 + + config SOC_PART_NUMBER_SAMV70Q20 + bool "SAMV70Q20" + + config SOC_PART_NUMBER_SAMV70Q19 + bool "SAMV70Q19" + + config SOC_PART_NUMBER_SAMV70N20 + bool "SAMV70N20" + + config SOC_PART_NUMBER_SAMV70N19 + bool "SAMV70N19" + + config SOC_PART_NUMBER_SAMV70J20 + bool "SAMV70J20" + + config SOC_PART_NUMBER_SAMV70J19 + bool "SAMV70J19" + + config SOC_PART_NUMBER_SAMV70Q20B + bool "SAMV70Q20B" + select SOC_ATMEL_SAMV70_REVB + + config SOC_PART_NUMBER_SAMV70Q19B + bool "SAMV70Q19B" + select SOC_ATMEL_SAMV70_REVB + + config SOC_PART_NUMBER_SAMV70N20B + bool "SAMV70N20B" + select SOC_ATMEL_SAMV70_REVB + + config SOC_PART_NUMBER_SAMV70N19B + bool "SAMV70N19B" + select SOC_ATMEL_SAMV70_REVB + + config SOC_PART_NUMBER_SAMV70J20B + bool "SAMV70J20B" + select SOC_ATMEL_SAMV70_REVB + + config SOC_PART_NUMBER_SAMV70J19B + bool "SAMV70J19B" + select SOC_ATMEL_SAMV70_REVB +endchoice + +if SOC_SERIES_SAMV70 + +config SOC_ATMEL_SAMV70_REVB + bool + +config SOC_ATMEL_SAMV70_EXT_SLCK + bool "Use external crystal oscillator for slow clock" + help + Say y if you want to use external 32 kHz crystal + oscillator to drive the slow clock. Note that this + adds a few seconds to boot time, as the crystal + needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. + The slow clock will be driven by the internal fast + RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAMV70_EXT_MAINCK + bool "Use external crystal oscillator for main clock" + help + The main clock is being used to drive the PLL, and + thus driving the processor clock. + + Say y if you want to use external crystal oscillator + to drive the main clock. Note that this adds about + a second to boot time, as the crystal needs to + stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator + running at 12 MHz. + +config SOC_ATMEL_SAMV70_MDIV + int "MDIV" + default 2 + range 1 4 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK): + MCK = HCLK / MDIV + +config SOC_ATMEL_SAMV70_PLLA_MULA + int "PLL MULA" + default 24 + range 1 62 + help + This is the multiplier MULA used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + Setting MULA=0 would disable PLL at boot, this is currently + not supported. + + With default of MULA == 24, and DIVA == 1, + PLL is running at 25 times the main clock frequency. + +config SOC_ATMEL_SAMV70_PLLA_DIVA + int "PLL DIVA" + default 1 + range 1 255 + help + This is the divider DIVA used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + Setting DIVA=0 would disable PLL at boot, this is currently + not supported. + + With default of MULA == 24, and DIVA == 1, + PLL is running at 25 times the main clock frequency. + +config SOC_ATMEL_SAMV70_WAIT_MODE + bool "Go to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAMV70_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order + to achieve this, make CPU go to Wait mode instead of Sleep + mode while using external crystal oscillator for main clock. + +config SOC_ATMEL_SAMV70_DISABLE_ERASE_PIN + bool "Disable ERASE pin" + help + At reset ERASE pin is configured in System IO mode. Asserting the ERASE + pin at '1' will completely erase Flash memory. Setting this option will + switch the pin to general IO mode giving control of the pin to the GPIO + module. + +endif # SOC_SERIES_SAMV70 diff --git a/soc/arm/atmel_sam/samv70/linker.ld b/soc/arm/atmel_sam/samv70/linker.ld new file mode 100644 index 0000000000000..e9411a5f88960 --- /dev/null +++ b/soc/arm/atmel_sam/samv70/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam/samv70/soc.c b/soc/arm/atmel_sam/samv70/soc.c new file mode 100644 index 0000000000000..2b5d986698ce8 --- /dev/null +++ b/soc/arm/atmel_sam/samv70/soc.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM V70 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM V70 MCU. + */ + +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/* Power Manager Controller */ + +/* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ +#define PMC_CKGR_PLLAR_MULA \ + (CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAMV70_PLLA_MULA)) +#define PMC_CKGR_PLLAR_DIVA \ + (CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAMV70_PLLA_DIVA)) + +#if CONFIG_SOC_ATMEL_SAMV70_MDIV == 1 +#define SOC_ATMEL_SAMV70_MDIV PMC_MCKR_MDIV_EQ_PCK +#elif CONFIG_SOC_ATMEL_SAMV70_MDIV == 2 +#define SOC_ATMEL_SAMV70_MDIV PMC_MCKR_MDIV_PCK_DIV2 +#elif CONFIG_SOC_ATMEL_SAMV70_MDIV == 3 +#define SOC_ATMEL_SAMV70_MDIV PMC_MCKR_MDIV_PCK_DIV3 +#elif CONFIG_SOC_ATMEL_SAMV70_MDIV == 4 +#define SOC_ATMEL_SAMV70_MDIV PMC_MCKR_MDIV_PCK_DIV4 +#else +#error "Invalid CONFIG_SOC_ATMEL_SAMV70_MDIV define value" +#endif + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + uint32_t reg_val; + +#ifdef CONFIG_SOC_ATMEL_SAMV70_EXT_SLCK + /* Switch slow clock to the external 32 kHz crystal oscillator */ + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; + + /* Wait for oscillator to be stabilized */ + while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { + ; + } +#endif /* CONFIG_SOC_ATMEL_SAMV70_EXT_SLCK */ + +#ifdef CONFIG_SOC_ATMEL_SAMV70_EXT_MAINCK + /* + * Setup main external crystal oscillator if not already done + * by a previous program i.e. bootloader + */ + + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) { + /* Start the external crystal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + | CKGR_MOR_MOSCXTST(0xFFu) + /* RC OSC must stay on */ + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN; + + /* Wait for oscillator to be stabilized */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { + ; + } + + /* Select the external crystal oscillator as main clock */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCSEL + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN; + + /* Wait for external oscillator to be selected */ + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { + ; + } + } + + /* Turn off RC OSC, not used any longer, to save power */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCSEL + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCXTEN; + + /* Wait for RC OSC to be turned off */ + while (PMC->PMC_SR & PMC_SR_MOSCRCS) { + ; + } + +#ifdef CONFIG_SOC_ATMEL_SAMV70_WAIT_MODE + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG + */ + PMC->PMC_FSMR |= PMC_FSMR_LPM; +#endif +#else + /* Attempt to change main fast RC oscillator frequency */ + + /* + * NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR + * register, should normally be the case here + */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } + + /* Set main fast RC oscillator to 12 MHz */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCRCF_12_MHz + | CKGR_MOR_MOSCRCEN; + + /* Wait for oscillator to be stabilized */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } +#endif /* CONFIG_SOC_ATMEL_SAMV70_EXT_MAINCK */ + + /* + * Setup PLLA + */ + + /* Switch MCK (Master Clock) to the main clock first */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; + + /* Wait for clock selection to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Setup PLLA */ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE + | PMC_CKGR_PLLAR_MULA + | CKGR_PLLAR_PLLACOUNT(0x3Fu) + | PMC_CKGR_PLLAR_DIVA; + + /* + * NOTE: Both MULA and DIVA must be set to a value greater than 0 or + * otherwise PLL will be disabled. In this case we would get stuck in + * the following loop. + */ + + /* Wait for PLL lock */ + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { + ; + } + + /* Setup UPLL */ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(0x3Fu) | CKGR_UCKR_UPLLEN; + + /* Wait for PLL lock */ + while (!(PMC->PMC_SR & PMC_SR_LOCKU)) { + ; + } + + /* + * Final setup of the Master Clock + */ + + /* + * NOTE: PMC_MCKR must not be programmed in a single write operation. + * If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be + * set again. + */ + + /* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk; + PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAMV70_MDIV; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Finally select PLL as Master Clock source */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_samv70_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + SCB_EnableICache(); + + if (!(SCB->CCR & SCB_CCR_DC_Msk)) { + SCB_EnableDCache(); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* Setup system clocks */ + clock_init(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_samv70_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/samv70/soc.h b/soc/arm/atmel_sam/samv70/soc.h new file mode 100644 index 0000000000000..5aed235cbbb83 --- /dev/null +++ b/soc/arm/atmel_sam/samv70/soc.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM V70 MCU. + * + * This file provides register access macros for the Atmel SAM V70 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _ATMEL_SAMV70_SOC_H_ +#define _ATMEL_SAMV70_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined CONFIG_SOC_PART_NUMBER_SAMV70J19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70J20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70N19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70N20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70Q19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70Q20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70J19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70J20B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70N19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70N20B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70Q19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV70Q20B +#include +#else + #error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAMV70_MDIV) + +/** UTMI PLL clock (UPLLCK) Frequency */ +#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) + +#endif /* _ASMLANGUAGE */ + +#include "pwm_fixup.h" + +#endif /* _ATMEL_SAMV70_SOC_H_ */ diff --git a/soc/arm/atmel_sam/samv70/soc_config.c b/soc/arm/atmel_sam/samv70/soc_config.c new file mode 100644 index 0000000000000..bcc214ee18c16 --- /dev/null +++ b/soc/arm/atmel_sam/samv70/soc_config.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM V70 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_samv70_config(const struct device *dev) +{ +#ifdef CONFIG_SOC_ATMEL_SAMV70_DISABLE_ERASE_PIN + /* Disable ERASE function on PB12 pin, this is controlled by Bus + * Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; +#endif + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } + /* Enable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; +#else + /* Disable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; +#endif + + return 0; +} + +SYS_INIT(atmel_samv70_config, PRE_KERNEL_1, 1); diff --git a/west.yml b/west.yml index c4f0afc14260f..e2b685f64f69a 100644 --- a/west.yml +++ b/west.yml @@ -60,7 +60,7 @@ manifest: groups: - hal - name: hal_atmel - revision: 78c5567c05b6b434dd7d98f49156319df4217bac + revision: pull/23/head path: modules/hal/atmel groups: - hal