Skip to content

alternate clock configuration for the stm32 ospi driver #46703

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jul 4, 2022
Merged

alternate clock configuration for the stm32 ospi driver #46703

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
ecc2f8f
drivers: flash: stm32 ospi driver configures peripheral clock
FRASTM Jun 20, 2022
71697fb
dts: arm: stm32u5 octospi clock source
FRASTM Jun 20, 2022
3dc0207
dts: arm: stm32l5 octospi clock source
FRASTM Jun 28, 2022
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
43 changes: 28 additions & 15 deletions drivers/flash/flash_stm32_ospi.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,8 @@ typedef void (*irq_config_func_t)(const struct device *dev);

struct flash_stm32_ospi_config {
OCTOSPI_TypeDef *regs;
struct stm32_pclken pclken;
const struct stm32_pclken *pclken; /* clock subsystem */
size_t pclk_len; /* number of clock subsystems */
irq_config_func_t irq_config;
size_t flash_size;
uint32_t max_frequency;
Expand Down Expand Up @@ -1568,21 +1569,33 @@ static int flash_stm32_ospi_init(const struct device *dev)
return ret;
}

/* Initializes the independent peripherals clock */
__HAL_RCC_OSPI_CONFIG(RCC_OSPICLKSOURCE_SYSCLK); /* */

/* Clock configuration */
if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken) != 0) {
(clock_control_subsys_t) &dev_cfg->pclken[0]) != 0) {
LOG_ERR("Could not enable OSPI clock");
return -EIO;
}

if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken,
&ahb_clock_freq) < 0) {
LOG_ERR("Failed to get AHB clock frequency");
return -EIO;
/* Alternate clock config for peripheral if any */
if (dev_cfg->pclk_len > 1) {
if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken[1],
NULL) != 0) {
LOG_ERR("Could not select OSPI source clock pclk[1]");
return -EIO;
}
if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken[1],
&ahb_clock_freq) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclk[1])");
return -EIO;
}
} else {
if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken[0],
&ahb_clock_freq) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclk[0])");
return -EIO;
}
}

for (; prescaler <= STM32_OSPI_CLOCK_PRESCALER_MAX; prescaler++) {
Expand Down Expand Up @@ -1773,12 +1786,12 @@ static void flash_stm32_ospi_irq_config_func(const struct device *dev);

PINCTRL_DT_DEFINE(STM32_OSPI_NODE);

static const struct stm32_pclken pclken_id[] = STM32_DT_CLOCKS(STM32_OSPI_NODE);

static const struct flash_stm32_ospi_config flash_stm32_ospi_cfg = {
.regs = (OCTOSPI_TypeDef *)DT_REG_ADDR(STM32_OSPI_NODE),
.pclken = {
.enr = DT_CLOCKS_CELL(STM32_OSPI_NODE, bits),
.bus = DT_CLOCKS_CELL(STM32_OSPI_NODE, bus)
},
.pclken = pclken_id,
.pclk_len = DT_NUM_CLOCKS(STM32_OSPI_NODE),
.irq_config = flash_stm32_ospi_irq_config_func,
.flash_size = DT_INST_PROP(0, size) / 8U,
.max_frequency = DT_INST_PROP(0, ospi_max_frequency),
Expand Down
3 changes: 2 additions & 1 deletion dts/arm/st/l5/stm32l5.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -397,7 +397,8 @@
compatible = "st,stm32-ospi";
reg = <0x44021000 0x400>;
interrupts = <76 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>,
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
Expand Down
6 changes: 4 additions & 2 deletions dts/arm/st/u5/stm32u5.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -360,7 +360,8 @@
compatible = "st,stm32-ospi";
reg = <0x420d1400 0x400>;
interrupts = <76 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000010>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000010>,
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
Expand All @@ -371,7 +372,8 @@
compatible = "st,stm32-ospi";
reg = <0x420d2400 0x400>;
interrupts = <120 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000100>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000100>,
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
Expand Down