Add support for NXP S32 CAN driver

boards/arm/s32z270dc2_r52/doc/index.rst

@@ -51,6 +51,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | SWT       | on-chip    | watchdog                            |
 +-----------+------------+-------------------------------------+
+| CANEXCEL  | on-chip    | can                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -128,6 +130,16 @@ single Virtual SI (VSI). The rest of the VSI's shall be assigned to different
 cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to
 configure the Ethernet network controller.
 
+Controller Area Network (CAN)
+=============================
+
+Currently, the CANXL transceiver is not populated in this board. So CAN transceiver
+connection is required for running external traffic. We can use any CAN transceiver,
+which supports CAN 2.0 and CAN FD protocol.
+
+CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is
+not supported as this feature is not available on NXP S32 CANXL HAL.
+
 Programming and Debugging
 *************************
 

boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi

@@ -52,4 +52,26 @@
 			output-enable;
 		};
 	};
+
+	can0_default: can0_default {
+		group1 {
+			pinmux = <PN2_CANXL_0_RX>;
+			input-enable;
+		};
+		group2 {
+			pinmux = <PN1_CANXL_0_TX>;
+			output-enable;
+		};
+	};
+
+	can1_default: can1_default {
+		group1 {
+			pinmux = <PM11_CANXL_1_RX>;
+			input-enable;
+		};
+		group2 {
+			pinmux = <PM10_CANXL_1_TX>;
+			output-enable;
+		};
+	};
 };

boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi

@@ -112,3 +112,28 @@
 	phy-dev = <&phy0>;
 	status = "okay";
 };
+
+&can0 {
+	pinctrl-0 = <&can0_default>;
+	pinctrl-names = "default";
+	clock-frequency = <80000000>;
+	bus-speed = <125000>;
+	sample-point = <875>;
+	sjw = <1>;
+	bus-speed-data = <1000000>;
+	sample-point-data = <875>;
+	sjw-data = <1>;
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-0 = <&can1_default>;
+	pinctrl-names = "default";
+	clock-frequency = <80000000>;
+	bus-speed = <125000>;
+	sample-point = <875>;
+	sjw = <1>;
+	bus-speed-data = <1000000>;
+	sample-point-data = <875>;
+	sjw-data = <1>;
+};

boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts

@@ -16,6 +16,7 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,canbus = &can0;
 	};
 
 	aliases {

boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml

@@ -13,3 +13,4 @@ supported:
   - gpio
   - watchdog
   - netif:eth
+  - can

boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts

@@ -16,6 +16,7 @@
 		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,canbus = &can0;
 	};
 
 	aliases {

boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml

@@ -13,3 +13,4 @@ supported:
   - gpio
   - watchdog
   - netif:eth
+  - can

drivers/can/CMakeLists.txt

@@ -36,5 +36,6 @@ zephyr_library_sources_ifdef(CONFIG_CAN_KVASER_PCI   can_kvaser_pci.c)
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE        can_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_SHELL        can_shell.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL    can_nxp_s32_canxl.c)
 
 add_subdirectory(transceiver)

drivers/can/Kconfig

@@ -99,6 +99,7 @@ source "drivers/can/Kconfig.sja1000"
 source "drivers/can/Kconfig.esp32"
 source "drivers/can/Kconfig.kvaser"
 source "drivers/can/Kconfig.fake"
+source "drivers/can/Kconfig.nxp_s32"
 
 source "drivers/can/transceiver/Kconfig"
 

drivers/can/Kconfig.nxp_s32

@@ -0,0 +1,27 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CAN_NXP_S32_CANXL
+	bool "NXP S32 CANXL driver"
+	default y
+	depends on DT_HAS_NXP_S32_CANXL_ENABLED
+	help
+	  Enable support for NXP S32 CANXL driver.
+
+if CAN_NXP_S32_CANXL
+config CAN_NXP_S32_MAX_RX
+	int "Maximum number of RX descriptors"
+	depends on CAN_NXP_S32_CANXL
+	default 16
+	range 1 128
+	help
+	  Maximum number of RX descriptors.
+
+config CAN_NXP_S32_MAX_TX
+	int "Maximum number of TX descriptors"
+	depends on CAN_NXP_S32_CANXL
+	default 16
+	range 1 128
+	help
+	  Maximum number of TX descriptors.
+endif # CAN_NXP_S32_CANXL