diff --git a/boards/arm/gd32a503v_eval/Kconfig.board b/boards/arm/gd32a503v_eval/Kconfig.board new file mode 100644 index 0000000000000..827b0b4dcb818 --- /dev/null +++ b/boards/arm/gd32a503v_eval/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32A503V_EVAL + bool "GigaDevice GD32A503V-EVAL" + depends on SOC_GD32A503 diff --git a/boards/arm/gd32a503v_eval/Kconfig.defconfig b/boards/arm/gd32a503v_eval/Kconfig.defconfig new file mode 100644 index 0000000000000..7c0c1ad2b7002 --- /dev/null +++ b/boards/arm/gd32a503v_eval/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GD32A503V_EVAL + +config BOARD + default "gd32a503v_eval" + +endif # BOARD_GD32A503V_EVAL diff --git a/boards/arm/gd32a503v_eval/board.cmake b/boards/arm/gd32a503v_eval/board.cmake new file mode 100644 index 0000000000000..d8afe770a086c --- /dev/null +++ b/boards/arm/gd32a503v_eval/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=gd32a503vd" "--tool-opt=--pack=${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${CONFIG_SOC_SERIES}/support/GigaDevice.GD32A50x_DFP.1.0.0.pack") +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) + +board_runner_args(gd32isp "--device=GD32A503VDT3") +include(${ZEPHYR_BASE}/boards/common/gd32isp.board.cmake) diff --git a/boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg b/boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg new file mode 100644 index 0000000000000..b18530d9e39b4 Binary files /dev/null and b/boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg differ diff --git a/boards/arm/gd32a503v_eval/doc/index.rst b/boards/arm/gd32a503v_eval/doc/index.rst new file mode 100644 index 0000000000000..1039faf515fb6 --- /dev/null +++ b/boards/arm/gd32a503v_eval/doc/index.rst @@ -0,0 +1,223 @@ +.. _gd32a503v_eval: + +GigaDevice GD32A503V-EVAL +######################### + + +Overview +******** + +The GD32A503V-EVAL board is a hardware platform that enables design and debug +of the GigaDevice A503 Cortex-M4F High Performance MCU. + +The GD32A503VD features a single-core ARM Cortex-M4F MCU which can run up +to 120-MHz with flash accesses zero wait states, 384kiB of Flash, 48kiB of +SRAM and 88 GPIOs. + +.. image:: img/gd32a503v_eval.jpg + :align: center + :alt: gd32a503v_eval + + +Hardware +******** + +- 2 user LEDs +- 2 user push buttons +- Reset Button +- ADC connected to a potentiometer +- 1 DAC channels +- GD25Q16 2Mib SPI Flash +- AT24C02C 2KiB EEPROM +- CS4344 Stereo DAC with Headphone Amplifier +- GD-Link interface + + - CMSIS-DAP swd debug interface over USB HID. + +- 2 CAN port(support CAN-FD) + +For more information about the GD32A503 SoC and GD32A503V-EVAL board: + +- `GigaDevice Cortex-M33 High Performance SoC Website`_ +- `GD32A503 Datasheet`_ +- `GD32A503 Reference Manual`_ +- `GD32A503V Eval Schematics`_ +- `GD32 ISP Console`_ + + +Supported Features +================== + +The board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - EXTI + - :kconfig:option:`CONFIG_GD32_EXTI` + - :dtcompatible:`gd,gd32-exti` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`gd,gd32-gpio` + * - NVIC + - N/A + - :dtcompatible:`arm,v8m-nvic` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`gd,gd32-pwm` + * - SYSTICK + - N/A + - N/A + * - USART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`gd,gd32-usart` + * - PINMUX + - :kconfig:option:`CONFIG_PINCTRL` + - :dtcompatible:`gd,gd32-pinctrl-af` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`gd,gd32-adc` + * - DAC + - :kconfig:option:`CONFIG_DAC` + - :dtcompatible:`gd,gd32-dac` + * - FMC + - N/A + - :dtcompatible:`gd,gd32-flash-controller` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`gd,gd32-spi` + +Serial Port +=========== + +The GD32A503V-EVAL board has 3 serial communication ports. The default port +is UART0 at PIN-72 and PIN-73. + +Programming and Debugging +************************* + +Before program your board make sure to configure boot setting and serial port. +The default serial port is USART0. + ++--------+--------+------------+ +| Boot-0 | Boot-1 | Function | ++========+========+============+ +| 1-2 | 1-2 | SRAM | ++--------+--------+------------+ +| 1-2 | 2-3 | Bootloader | ++--------+--------+------------+ +| 2-3 | Any | Flash | ++--------+--------+------------+ + +Using GD-Link +============= + +The GD32A503V-EVAL includes an onboard programmer/debugger (GD-Link) which +allow flash programming and debug over USB. There are also program and debug +headers J2 and J100 that can be used with any ARM compatible tools. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32a503v_eval + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32a503v_eval + :goals: flash + :compact: + + You should see "Hello World! gd32a503v_eval" in your terminal. + +#. To debug an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32a503v_eval + :goals: debug + :compact: + + +Using ROM bootloader +==================== + +The GD32A503 MCU have a ROM bootloader which allow flash programming. User +should install `GD32 ISP Console`_ software at some Linux path. The recommended +is :code:`$HOME/.local/bin`. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32a503v_eval + :goals: build + :compact: + +#. Enable board bootloader: + + - Remove boot-0 jumper + - press reset button + +#. To flash an image: + + .. code-block:: console + + west flash -r gd32isp [--port=/dev/ttyUSB0] + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Press reset button + + You should see "Hello World! gd32a503v_eval" in your terminal. + + +.. _GigaDevice Cortex-M33 High Performance SoC Website: + https://www.gigadevice.com.cn/product/mcu/arm-cortex-m33/gd32a503vdt3 + +.. _GD32A503 Datasheet: + https://www.gd32mcu.com/download/down/document_id/401/path_type/1 + +.. _GD32A503 Reference Manual: + https://www.gd32mcu.com/download/down/document_id/402/path_type/1 + +.. _GD32A503V Eval Schematics: + https://www.gd32mcu.com/download/down/document_id/404/path_type/1 + +.. _GD32 ISP Console: + http://www.gd32mcu.com/download/down/document_id/175/path_type/1 diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi b/boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi new file mode 100644 index 0000000000000..4c53fce378064 --- /dev/null +++ b/boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2022 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group1 { + pinmux = , ; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = ; + }; + }; + + dac_default: dac_default { + group1 { + pinmux = ; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , + , + /* Use pinmux to pullup pg10 and pg11. */ + , ; + }; + }; +}; diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval.dts b/boards/arm/gd32a503v_eval/gd32a503v_eval.dts new file mode 100644 index 0000000000000..f5f79267c16fe --- /dev/null +++ b/boards/arm/gd32a503v_eval/gd32a503v_eval.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2022 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "gd32a503v_eval-pinctrl.dtsi" + +/ { + model = "GigaDevice GD32A503V-EVAL"; + compatible = "gd,gd32a503v-eval"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,flash-controller = &fmc; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&gpioc 0 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + led2: led2 { + gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + spi-flash0 = &nor_flash; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&usart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&dac { + status = "okay"; + pinctrl-0 = <&dac_default>; + pinctrl-names = "default"; +}; + +&fwdgt { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + + nor_flash: gd25q16@0 { + compatible ="jedec,spi-nor"; + size = <0x1000000>; + reg = <0>; + spi-max-frequency = <4000000>; + status = "okay"; + jedec-id = [c8 40 15]; + }; +}; diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig b/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig new file mode 100644 index 0000000000000..1bb7621214f74 --- /dev/null +++ b/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_GD32A50X=y +CONFIG_SOC_GD32A503=y +CONFIG_BOARD_GD32A503V_EVAL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32a503v_eval/gd32f450z_eval.yaml b/boards/arm/gd32a503v_eval/gd32f450z_eval.yaml new file mode 100644 index 0000000000000..ea5a264f5b4b0 --- /dev/null +++ b/boards/arm/gd32a503v_eval/gd32f450z_eval.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +identifier: gd32a503v_eval +name: GigaDevice GD32A503V-EVAL +type: mcu +arch: arm +ram: 48 +flash: 384 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - counter + - dac + - dma + - gpio + - pwm + - spi + - uart + - watchdog diff --git a/drivers/adc/adc_gd32.c b/drivers/adc/adc_gd32.c index 66e5c4fa7142e..0a49c7af2e31d 100644 --- a/drivers/adc/adc_gd32.c +++ b/drivers/adc/adc_gd32.c @@ -98,6 +98,20 @@ static const uint32_t table_samp_time[] = { SMP_TIME(71), SMP_TIME(239), }; +#elif defined(CONFIG_SOC_SERIES_GD32A50X) +#define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5 + +static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480}; +static const uint32_t table_samp_time[] = { + SMP_TIME(2), + SMP_TIME(14), + SMP_TIME(27), + SMP_TIME(55), + SMP_TIME(83), + SMP_TIME(111), + SMP_TIME(143), + SMP_TIME(479) +}; #else #define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5 @@ -289,7 +303,8 @@ static int adc_gd32_start_read(const struct device *dev, defined(CONFIG_SOC_SERIES_GD32L23X) ADC_CTL0(cfg->reg) &= ~ADC_CTL0_DRES; ADC_CTL0(cfg->reg) |= CTL0_DRES(resolution_id); -#elif defined(CONFIG_SOC_SERIES_GD32F403) +#elif defined(CONFIG_SOC_SERIES_GD32F403) || \ + defined(CONFIG_SOC_SERIES_GD32A50X) ADC_OVSAMPCTL(cfg->reg) &= ~ADC_OVSAMPCTL_DRES; ADC_OVSAMPCTL(cfg->reg) |= OVSAMPCTL_DRES(resolution_id); #elif defined(CONFIG_SOC_SERIES_GD32VF103) @@ -384,6 +399,11 @@ static int adc_gd32_init(const struct device *dev) ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC; #endif +#ifdef CONFIG_SOC_SERIES_GD32A50X + ADC_CTL1(cfg->reg) |= ADC_CTL1_ETSRC; + ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC; +#endif + /* Enable ADC */ ADC_CTL1(cfg->reg) |= ADC_CTL1_ADCON; diff --git a/drivers/clock_control/clock_control_gd32.c b/drivers/clock_control/clock_control_gd32.c index aef5fd81cbdae..222648d027bde 100644 --- a/drivers/clock_control/clock_control_gd32.c +++ b/drivers/clock_control/clock_control_gd32.c @@ -113,6 +113,7 @@ static int clock_control_gd32_get_rate(const struct device *dev, break; case RCU_APB1EN_OFFSET: #if !defined(CONFIG_SOC_SERIES_GD32VF103) && \ + !defined(CONFIG_SOC_SERIES_GD32A50X) && \ !defined(CONFIG_SOC_SERIES_GD32L23X) case RCU_ADDAPB1EN_OFFSET: #endif diff --git a/drivers/dac/dac_gd32.c b/drivers/dac/dac_gd32.c index fe38c006a4426..d26a8fd2a4931 100644 --- a/drivers/dac/dac_gd32.c +++ b/drivers/dac/dac_gd32.c @@ -20,10 +20,14 @@ LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL); /** - * GD32 DAC HAL use different DAC0 interface for 2 or 1 output channels SoCs. - * Unify the DAC0 interface to DAC0_xx. + * For some gd32 series which only have 1 DAC, their HAL name may not same as others. + * Below definitions help to unify the HAL name. */ -#if DT_INST_PROP(0, num_channels) == 1 +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#define DAC_CTL_DEN0 DAC_CTL_DEN +#define DAC0_R8DH OUT_R8DH +#define DAC0_R12DH OUT_R12DH +#elif defined(CONFIG_SOC_SERIES_GD32F3X0) #define DAC_CTL_DEN0 DAC_CTL_DEN #define DAC0_R8DH DAC_R8DH #define DAC0_R12DH DAC_R12DH diff --git a/drivers/pinctrl/pinctrl_gd32_af.c b/drivers/pinctrl/pinctrl_gd32_af.c index 21c3adf85cafb..eb50d53f59da0 100644 --- a/drivers/pinctrl/pinctrl_gd32_af.c +++ b/drivers/pinctrl/pinctrl_gd32_af.c @@ -21,6 +21,7 @@ BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) && BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) && #if defined(CONFIG_SOC_SERIES_GD32F3X0) || \ + defined(CONFIG_SOC_SERIES_GD32A50X) || \ defined(CONFIG_SOC_SERIES_GD32L23X) (GD32_OSPEED_10MHZ == GPIO_OSPEED_10MHZ) && (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) && diff --git a/drivers/spi/spi_gd32.c b/drivers/spi/spi_gd32.c index a48a0edd6b0db..37c705ed30901 100644 --- a/drivers/spi/spi_gd32.c +++ b/drivers/spi/spi_gd32.c @@ -31,17 +31,6 @@ LOG_MODULE_REGISTER(spi_gd32); #define GD32_SPI_PSC_MAX 0x7U -#if defined(CONFIG_SOC_SERIES_GD32F4XX) || \ - defined(CONFIG_SOC_SERIES_GD32F403) || \ - defined(CONFIG_SOC_SERIES_GD32VF103) || \ - defined(CONFIG_SOC_SERIES_GD32E10X) -#define RCU_APB1EN_OFFSET APB1EN_REG_OFFSET -#elif defined(CONFIG_SOC_SERIES_GD32F3X0) -#define RCU_APB1EN_OFFSET IDX_APB1EN -#else -#error Unknown GD32 soc series -#endif - #ifdef CONFIG_SPI_GD32_DMA enum spi_gd32_dma_direction { diff --git a/dts/arm/gigadevice/gd32a50x/gd32a503vdt3.dtsi b/dts/arm/gigadevice/gd32a50x/gd32a503vdt3.dtsi new file mode 100644 index 0000000000000..674016f5e98f3 --- /dev/null +++ b/dts/arm/gigadevice/gd32a50x/gd32a503vdt3.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2022 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&flash0 { + reg = <0x08000000 DT_SIZE_K(384)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(48)>; +}; diff --git a/dts/arm/gigadevice/gd32a50x/gd32a50x.dtsi b/dts/arm/gigadevice/gd32a50x/gd32a50x.dtsi new file mode 100644 index 0000000000000..87cce2d615d40 --- /dev/null +++ b/dts/arm/gigadevice/gd32a50x/gd32a50x.dtsi @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2022 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = ; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + rcu: reset-clock-controller@40021000 { + compatible = "gd,gd32-rcu"; + reg = <0x40021000 0x400>; + status = "okay"; + + cctl: clock-controller { + compatible = "gd,gd32-cctl"; + #clock-cells = <1>; + status = "okay"; + }; + + rctl: reset-controller { + compatible = "gd,gd32-rctl"; + #reset-cells = <1>; + status = "okay"; + }; + }; + + fmc: flash-controller@40022000 { + compatible = "gd,gd32-flash-controller"; + reg = <0x40022000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash"; + write-block-size = <2>; + max-erase-time-ms = <2578>; + bank0-page-size = ; + bank1-page-size = ; + }; + }; + + usart0: usart@40013800 { + compatible = "gd,gd32-usart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + clocks = <&cctl GD32_CLOCK_USART0>; + resets = <&rctl GD32_RESET_USART0>; + status = "disabled"; + }; + + usart1: usart@40004400 { + compatible = "gd,gd32-usart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + clocks = <&cctl GD32_CLOCK_USART1>; + resets = <&rctl GD32_RESET_USART1>; + status = "disabled"; + }; + + usart2: usart@40004800 { + compatible = "gd,gd32-usart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + clocks = <&cctl GD32_CLOCK_USART2>; + resets = <&rctl GD32_RESET_USART2>; + status = "disabled"; + }; + + dac: dac@40007400 { + compatible = "gd,gd32-dac"; + reg = <0x40007400 0x400>; + clocks = <&cctl GD32_CLOCK_DAC>; + resets = <&rctl GD32_RESET_DAC>; + num-channels = <1>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + i2c0: i2c@40005400 { + compatible = "gd,gd32-i2c"; + reg = <0x40005400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <31 0>, <32 0>; + interrupt-names = "event", "error"; + clocks = <&cctl GD32_CLOCK_I2C0>; + resets = <&rctl GD32_RESET_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@40005800 { + compatible = "gd,gd32-i2c"; + reg = <0x40005800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <33 0>, <34 0>; + interrupt-names = "event", "error"; + clocks = <&cctl GD32_CLOCK_I2C1>; + resets = <&rctl GD32_RESET_I2C1>; + status = "disabled"; + }; + + spi0: spi@40013000 { + compatible = "gd,gd32-spi"; + reg = <0x40013000 0x400>; + interrupts = <35 0>; + clocks = <&cctl GD32_CLOCK_SPI0>; + resets = <&rctl GD32_RESET_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@40003800 { + compatible = "gd,gd32-spi"; + reg = <0x40003800 0x400>; + interrupts = <36 0>; + clocks = <&cctl GD32_CLOCK_SPI1>; + resets = <&rctl GD32_RESET_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + adc0: adc@40012400 { + compatible = "gd,gd32-adc"; + reg = <0x40012400 0x100>; + interrupts = <18 0>; + clocks = <&cctl GD32_CLOCK_ADC0>; + resets = <&rctl GD32_RESET_ADC0>; + channels = <16>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + adc1: adc@40012800 { + compatible = "gd,gd32-adc"; + reg = <0x40012800 0x100>; + interrupts = <18 0>; + clocks = <&cctl GD32_CLOCK_ADC1>; + resets = <&rctl GD32_RESET_ADC1>; + channels = <16>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + syscfg: syscfg@40010000 { + compatible = "gd,gd32-syscfg"; + reg = <0x40010000 0x400>; + clocks = <&cctl GD32_CLOCK_SYSCFG>; + }; + + exti: interrupt-controller@40010400 { + compatible = "gd,gd32-exti"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x40010400 0x400>; + num-lines = <25>; + interrupts = <6 0>, <7 0>, <8 0>, <9 0>, + <10 0>, <41 0>, <40 0>; + interrupt-names = "line0", "line1", "line2", "line3", + "line4", "line5-9", "line10-15"; + status = "okay"; + }; + + fwdgt: watchdog@40003000 { + compatible = "gd,gd32-fwdgt"; + reg = <0x40003000 0x400>; + status = "disabled"; + }; + + wwdgt: watchdog@40002c00 { + compatible = "gd,gd32-wwdgt"; + reg = <0x40002C00 0x400>; + clocks = <&cctl GD32_CLOCK_WWDGT>; + resets = <&rctl GD32_RESET_WWDGT>; + interrupts = <0 0>; + status = "disabled"; + }; + + pinctrl: pin-controller@48000000 { + compatible = "gd,gd32-pinctrl-af"; + reg = <0x48000000 0x1800>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + gpioa: gpio@48000000 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000000 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOA>; + resets = <&rctl GD32_RESET_GPIOA>; + status = "disabled"; + }; + + gpiob: gpio@48000400 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000400 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOB>; + resets = <&rctl GD32_RESET_GPIOB>; + status = "disabled"; + }; + + gpioc: gpio@48000800 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000800 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOC>; + resets = <&rctl GD32_RESET_GPIOC>; + status = "disabled"; + }; + + gpiod: gpio@48000c00 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOD>; + resets = <&rctl GD32_RESET_GPIOD>; + status = "disabled"; + }; + + gpioe: gpio@48001000 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOE>; + resets = <&rctl GD32_RESET_GPIOE>; + status = "disabled"; + }; + + gpiof: gpio@48001400 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001400 0x400>; + clocks = <&cctl GD32_CLOCK_GPIOF>; + resets = <&rctl GD32_RESET_GPIOF>; + status = "disabled"; + }; + }; + + timer0: timer@40012c00 { + compatible = "gd,gd32-timer"; + reg = <0x40012c00 0x400>; + interrupts = <24 0>, <25 0>, <26 0>, <27 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + clocks = <&cctl GD32_CLOCK_TIMER0>; + resets = <&rctl GD32_RESET_TIMER0>; + is-advanced; + channels = <4>; + status = "disabled"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + + timer1: timer@40000000 { + compatible = "gd,gd32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28 0>; + interrupt-names = "global"; + clocks = <&cctl GD32_CLOCK_TIMER1>; + resets = <&rctl GD32_RESET_TIMER1>; + is-32bit; + channels = <4>; + status = "disabled"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + + timer5: timer@40001000 { + compatible = "gd,gd32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54 0>; + interrupt-names = "global"; + clocks = <&cctl GD32_CLOCK_TIMER5>; + resets = <&rctl GD32_RESET_TIMER5>; + channels = <0>; + status = "disabled"; + }; + + timer6: timer@40001400 { + compatible = "gd,gd32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55 0>; + interrupt-names = "global"; + clocks = <&cctl GD32_CLOCK_TIMER6>; + resets = <&rctl GD32_RESET_TIMER6>; + channels = <0>; + status = "disabled"; + }; + + timer7: timer@40013400 { + compatible = "gd,gd32-timer"; + reg = <0x40013400 0x400>; + interrupts = <43 0>, <44 0>, <45 0>, <46 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + clocks = <&cctl GD32_CLOCK_TIMER7>; + resets = <&rctl GD32_RESET_TIMER7>; + is-advanced; + channels = <4>; + status = "disabled"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + + timer19: timer@40015000 { + compatible = "gd,gd32-timer"; + reg = <0x40015000 0x400>; + interrupts = <43 0>; + interrupt-names = "global"; + clocks = <&cctl GD32_CLOCK_TIMER19>; + resets = <&rctl GD32_RESET_TIMER19>; + channels = <2>; + status = "disabled"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + + timer20: timer@40015400 { + compatible = "gd,gd32-timer"; + reg = <0x40015400 0x400>; + interrupts = <44 0>; + interrupt-names = "global"; + clocks = <&cctl GD32_CLOCK_TIMER20>; + resets = <&rctl GD32_RESET_TIMER20>; + channels = <1>; + status = "disabled"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + + dma0: dma@40020000 { + compatible = "gd,gd32-dma"; + reg = <0x40020000 0x400>; + interrupts = <11 0>, <12 0>, <13 0>, <14 0>, + <15 0>, <16 0>, <17 0>, <47 0>; + clocks = <&cctl GD32_CLOCK_DMA0>; + dma-channels = <7>; + gd,mem2mem; + #dma-cells = <2>; + status = "disabled"; + }; + + dma1: dma@40020400 { + compatible = "gd,gd32-dma"; + reg = <0x40020400 0x400>; + interrupts = <56 0>, <57 0>, <58 0>, + <59 0>, <60 0>; + clocks = <&cctl GD32_CLOCK_DMA1>; + dma-channels = <5>; + gd,mem2mem; + #dma-cells = <2>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h b/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h index 9d1d829317918..06b0615651a0c 100644 --- a/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h +++ b/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h @@ -107,6 +107,7 @@ typedef uint32_t pinctrl_soc_pin_t; /** Maximum 2MHz */ #define GD32_OSPEED_2MHZ 0U #if defined(CONFIG_SOC_SERIES_GD32F3X0) || \ + defined(CONFIG_SOC_SERIES_GD32A50X) || \ defined(CONFIG_SOC_SERIES_GD32L23X) /** Maximum 10MHz */ #define GD32_OSPEED_10MHZ 1U diff --git a/include/zephyr/dt-bindings/clock/gd32a50x-clocks.h b/include/zephyr/dt-bindings/clock/gd32a50x-clocks.h new file mode 100644 index 0000000000000..c57efc2d76fc3 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/gd32a50x-clocks.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ + +#include "gd32-clocks-common.h" + +/** + * @name Register offsets + * @{ + */ + +#define GD32_AHBEN_OFFSET 0x14U +#define GD32_APB1EN_OFFSET 0x1CU +#define GD32_APB2EN_OFFSET 0x18U + +/** @} */ + +/** + * @name Clock enable/disable definitions for peripherals + * @{ + */ + +/* AHB peripherals */ +#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) +#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) +#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) +#define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHBEN, 3U) +#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) +#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) +#define GD32_CLOCK_MFCOM GD32_CLOCK_CONFIG(AHBEN, 14U) +#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U) +#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U) +#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U) +#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U) +#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHBEN, 21U) +#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U) + +/* APB1 peripherals */ +#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) +#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) +#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) +#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) +#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) +#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) +#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) +#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) +#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) +#define GD32_CLOCK_BKP GD32_CLOCK_CONFIG(APB1EN, 26U) +#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) +#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) + +/* APB2 peripherals */ +#define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 0U) +#define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APB2EN, 1U) +#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) +#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) +#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) +#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) +#define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) +#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) +#define GD32_CLOCK_TIMER19 GD32_CLOCK_CONFIG(APB2EN, 20U) +#define GD32_CLOCK_TIMER20 GD32_CLOCK_CONFIG(APB2EN, 21U) +#define GD32_CLOCK_TRIGSEL GD32_CLOCK_CONFIG(APB2EN, 29U) +#define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB2EN, 30U) +#define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB2EN, 31U) + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ */ diff --git a/include/zephyr/dt-bindings/reset/gd32a50x.h b/include/zephyr/dt-bindings/reset/gd32a50x.h new file mode 100644 index 0000000000000..40f88c060cdfd --- /dev/null +++ b/include/zephyr/dt-bindings/reset/gd32a50x.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2022 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ + +#include "gd32-common.h" + +/** + * @name Register offsets + * @{ + */ + +#define GD32_AHBRST_OFFSET 0x28U +#define GD32_APB1RST_OFFSET 0x10U +#define GD32_APB2RST_OFFSET 0x0CU + +/** @} */ + +/** + * @name Clock enable/disable definitions for peripherals + * @{ + */ + + +/* AHB peripherals */ +#define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHBRST, 0U) +#define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHBRST, 1U) +#define GD32_RESET_SRAMSP GD32_RESET_CONFIG(AHBRST, 2U) +#define GD32_RESET_DMAMUX GD32_RESET_CONFIG(AHBRST, 3U) +#define GD32_RESET_FMCSP GD32_RESET_CONFIG(AHBRST, 4U) +#define GD32_RESET_CRC GD32_RESET_CONFIG(AHBRST, 6U) +#define GD32_RESET_MFCOM GD32_RESET_CONFIG(AHBRST, 14U) +#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U) +#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U) +#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U) +#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U) +#define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHBRST, 21U) +#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U) + +/* APB1 peripherals */ +#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) +#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) +#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) +#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) +#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) +#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) +#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U) +#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) +#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U) +#define GD32_RESET_BKP GD32_RESET_CONFIG(APB1RST, 26U) +#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U) +#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U) + +/* APB2 peripherals */ +#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 0U) +#define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 1U) +#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) +#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U) +#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) +#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U) +#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) +#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) +#define GD32_RESET_TIMER19 GD32_RESET_CONFIG(APB2RST, 20U) +#define GD32_RESET_TIMER20 GD32_RESET_CONFIG(APB2RST, 21U) +#define GD32_RESET_TRIGSEL GD32_RESET_CONFIG(APB2RST, 29U) +#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB2RST, 30U) +#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB2RST, 31U) + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ */ diff --git a/modules/hal_gigadevice/CMakeLists.txt b/modules/hal_gigadevice/CMakeLists.txt index 3045eaedd63b2..7a4096bc4d2f0 100644 --- a/modules/hal_gigadevice/CMakeLists.txt +++ b/modules/hal_gigadevice/CMakeLists.txt @@ -46,6 +46,11 @@ if(${CONFIG_SOC_SERIES_GD32E50X}) endif() endif() +# GD32A50X series HAL public headers require extra definitions +if(${CONFIG_SOC_SERIES_GD32A50X}) + zephyr_compile_definitions(GD32A50X) +endif() + # Global includes to be used outside hal_gigadevice zephyr_include_directories(${gd32_soc_sys_dir}/include) zephyr_include_directories(${gd32_std_dir}/include) diff --git a/samples/drivers/adc/boards/gd32a503v_eval.overlay b/samples/drivers/adc/boards/gd32a503v_eval.overlay new file mode 100644 index 0000000000000..08af2516f573d --- /dev/null +++ b/samples/drivers/adc/boards/gd32a503v_eval.overlay @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2023 YuLong Yao + */ + +#include + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&adc0 1>; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/samples/drivers/dac/boards/gd32a503v_eval.overlay b/samples/drivers/dac/boards/gd32a503v_eval.overlay new file mode 100644 index 0000000000000..062ee89d0423e --- /dev/null +++ b/samples/drivers/dac/boards/gd32a503v_eval.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2022 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; diff --git a/samples/drivers/jesd216/boards/gd32a503v_eval.conf b/samples/drivers/jesd216/boards/gd32a503v_eval.conf new file mode 100644 index 0000000000000..f66cef2fd8f27 --- /dev/null +++ b/samples/drivers/jesd216/boards/gd32a503v_eval.conf @@ -0,0 +1,7 @@ +# +# Copyright (c) 2022 YuLong Yao +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y diff --git a/samples/drivers/spi_flash/boards/gd32a503v_eval.conf b/samples/drivers/spi_flash/boards/gd32a503v_eval.conf new file mode 100644 index 0000000000000..543d4d301e522 --- /dev/null +++ b/samples/drivers/spi_flash/boards/gd32a503v_eval.conf @@ -0,0 +1,8 @@ +# +# Copyright (c) 2022 YuLong Yao +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SPI_NOR=y diff --git a/soc/arm/gigadevice/gd32a50x/CMakeLists.txt b/soc/arm/gigadevice/gd32a50x/CMakeLists.txt new file mode 100644 index 0000000000000..6691c48964839 --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) diff --git a/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32a503 b/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32a503 new file mode 100644 index 0000000000000..a714d56cb61fd --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32a503 @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC + default "gd32a503" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config NUM_IRQS + default 82 diff --git a/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.series new file mode 100644 index 0000000000000..d9e48ae18c2fa --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32A50X + +source "soc/arm/gigadevice/gd32a50x/Kconfig.defconfig.gd32*" + +config SOC_SERIES + default "gd32a50x" + +endif # SOC_SERIES_GD32A50X diff --git a/soc/arm/gigadevice/gd32a50x/Kconfig.series b/soc/arm/gigadevice/gd32a50x/Kconfig.series new file mode 100644 index 0000000000000..96fc8c1d0af71 --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/Kconfig.series @@ -0,0 +1,15 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32A50X + bool "GigaDevice GD32A50X series Cortex-M33 MCU" + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M33 + select SOC_FAMILY_GD32_ARM + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_40K + select PLATFORM_SPECIFIC_INIT + help + Enable support for GigaDevice GD32A50X MCU series diff --git a/soc/arm/gigadevice/gd32a50x/Kconfig.soc b/soc/arm/gigadevice/gd32a50x/Kconfig.soc new file mode 100644 index 0000000000000..6601c77c11af7 --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "GigaDevice GD32A50X MCU Selection" + depends on SOC_SERIES_GD32A50X + + config SOC_GD32A503 + bool "gd32a503" + +endchoice diff --git a/soc/arm/gigadevice/gd32a50x/gd32_regs.h b/soc/arm/gigadevice/gd32a50x/gd32_regs.h new file mode 100644 index 0000000000000..f89af870d103c --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/gd32_regs.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_ +#define SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_ + +#include + +/* RCU */ +#define RCU_CFG0_OFFSET 0x04U +#define RCU_AHBEN_OFFSET 0x14U +#define RCU_APB1EN_OFFSET 0x1CU +#define RCU_APB2EN_OFFSET 0x18U +#define RCU_CFG1_OFFSET 0x2CU +#define RCU_CFG2_OFFSET 0x30U + +#define RCU_CFG0_AHBPSC_POS 4U +#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS) +#define RCU_CFG0_APB1PSC_POS 8U +#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS) +#define RCU_CFG0_APB2PSC_POS 11U +#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) + +#endif /* SOC_ARM_GIGADEVICE_GD32A50X_GD32_REGS_H_ */ diff --git a/soc/arm/gigadevice/gd32a50x/linker.ld b/soc/arm/gigadevice/gd32a50x/linker.ld new file mode 100644 index 0000000000000..32362bbe6e748 --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/linker.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021 Teslabs Engineering S.L. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/gigadevice/gd32a50x/soc.c b/soc/arm/gigadevice/gd32a50x/soc.c new file mode 100644 index 0000000000000..e20bdfab0cd6a --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/soc.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/* initial ecc memory */ +void z_arm_platform_init(void) +{ + register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram)); + register unsigned r1 __asm("r1") = + DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_sram)); + + for (; r0 < r1; r0 += 4) { + *(unsigned int *)r0 = 0; + } +} + +static int gd32a50x_soc_init(const struct device *dev) +{ + uint32_t key; + + ARG_UNUSED(dev); + + key = irq_lock(); + + SystemInit(); + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(gd32a50x_soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/gigadevice/gd32a50x/soc.h b/soc/arm/gigadevice/gd32a50x/soc.h new file mode 100644 index 0000000000000..8249c4ed7da27 --- /dev/null +++ b/soc/arm/gigadevice/gd32a50x/soc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_ +#define _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ARM_GIGADEVICE_GD32A50X_SOC_H_ */ diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 6eb8fd9de2710..778834023ca46 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -141,6 +141,15 @@ #define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT #define ADC_1ST_CHANNEL_ID 3 +#elif defined(CONFIG_BOARD_GD32A503V_EVAL) + +#define ADC_DEVICE_NODE DT_INST(0, gd_gd32_adc) +#define ADC_RESOLUTION 12 +#define ADC_GAIN ADC_GAIN_1 +#define ADC_REFERENCE ADC_REF_INTERNAL +#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT +#define ADC_1ST_CHANNEL_ID 1 + #elif defined(CONFIG_BOARD_HEXIWEAR_K64) #define ADC_DEVICE_NODE DT_INST(0, nxp_kinetis_adc16) diff --git a/west.yml b/west.yml index cf7a9d36761b1..2f3410c5e8685 100644 --- a/west.yml +++ b/west.yml @@ -68,7 +68,7 @@ manifest: groups: - hal - name: hal_gigadevice - revision: 024ed9e3a7e0c093a3c7427d98dbade20e16c52d + revision: 2994b7dde8b0b0fa9b9c0ccb13474b6a486cddc3 path: modules/hal/gigadevice groups: - hal