From 77cacd7838685caf3a2c99afb9aa0278d3801791 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 08:55:02 -0300 Subject: [PATCH 1/7] dt-bindings: add esp32s3 signals Adds esp32s3 related gpio sigmap, intmux and clock related. Signed-off-by: Sylvio Alves --- .../zephyr/dt-bindings/clock/esp32s3_clock.h | 87 ++++ .../esp32s3-xtensa-intmux.h | 107 ++++ .../dt-bindings/pinctrl/esp32s3-gpio-sigmap.h | 455 ++++++++++++++++++ 3 files changed, 649 insertions(+) create mode 100644 include/zephyr/dt-bindings/clock/esp32s3_clock.h create mode 100644 include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h create mode 100644 include/zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h diff --git a/include/zephyr/dt-bindings/clock/esp32s3_clock.h b/include/zephyr/dt-bindings/clock/esp32s3_clock.h new file mode 100644 index 0000000000000..817aee45890c1 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/esp32s3_clock.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ + +/* System Clock Source */ +#define ESP32_CLK_SRC_XTAL 0U +#define ESP32_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RTC8M 2U +#define ESP32_CLK_SRC_APLL 3U + +/* Supported CPU Frequencies */ +#define ESP32_CLK_CPU_26M 26000000 +#define ESP32_CLK_CPU_40M 40000000 +#define ESP32_CLK_CPU_80M 80000000 +#define ESP32_CLK_CPU_160M 160000000 +#define ESP32_CLK_CPU_240M 240000000 + +/* Supported XTAL Frequencies */ +#define ESP32_CLK_XTAL_24M 0U +#define ESP32_CLK_XTAL_26M 1U +#define ESP32_CLK_XTAL_40M 2U +#define ESP32_CLK_XTAL_AUTO 3U + +/* Supported RTC fast clock frequencies */ +#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U + +/* Supported RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_FREQ_150K 150000U +#define ESP32_RTC_SLOW_CLK_FREQ_32K 32000U +#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_8M / 256) + +/* Modules IDs + * These IDs are actually offsets in CLK and RST Control registers. + * These IDs shouldn't be changed unless there is a Hardware change + * from Espressif. + * + * Basic Modules + * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG + */ +#define ESP32_LEDC_MODULE 0 +#define ESP32_UART0_MODULE 1 +#define ESP32_UART1_MODULE 2 +#define ESP32_UART2_MODULE 3 +#define ESP32_USB_MODULE 4 +#define ESP32_I2C0_MODULE 5 +#define ESP32_I2C1_MODULE 6 +#define ESP32_I2S0_MODULE 7 +#define ESP32_I2S1_MODULE 8 +#define ESP32_LCD_CAM_MODULE 9 +#define ESP32_TIMG0_MODULE 10 +#define ESP32_TIMG1_MODULE 11 +#define ESP32_PWM0_MODULE 12 +#define ESP32_PWM1_MODULE 13 +#define ESP32_PWM2_MODULE 14 +#define ESP32_PWM3_MODULE 15 +#define ESP32_UHCI0_MODULE 16 +#define ESP32_UHCI1_MODULE 17 +#define ESP32_RMT_MODULE 18 +#define ESP32_PCNT_MODULE 19 +#define ESP32_SPI_MODULE 20 +#define ESP32_SPI2_MODULE 21 +#define ESP32_SPI3_MODULE 22 +#define ESP32_SDMMC_MODULE 23 +#define ESP32_TWAI_MODULE 24 +#define ESP32_RNG_MODULE 25 +#define ESP32_WIFI_MODULE 26 +#define ESP32_BT_MODULE 27 +#define ESP32_WIFI_BT_COMMON_MODULE 28 +#define ESP32_BT_BASEBAND_MODULE 29 +#define ESP32_BT_LC_MODULE 30 +#define ESP32_AES_MODULE 31 +#define ESP32_SHA_MODULE 32 +#define ESP32_HMAC_MODULE 33 +#define ESP32_DS_MODULE 34 +#define ESP32_RSA_MODULE 35 +#define ESP32_SYSTIMER_MODULE 36 +#define ESP32_GDMA_MODULE 37 +#define ESP32_DEDIC_GPIO_MODULE 38 +#define ESP32_SARADC_MODULE 39 +#define ESP32_MODULE_MAX 40 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h new file mode 100644 index 0000000000000..5d3658a7f62ee --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_ + +#define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/ +#define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI */ +#define WIFI_PWR_INTR_SOURCE 2 +#define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/ +#define BT_MAC_INTR_SOURCE 4 /* will be cancelled*/ +#define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/ +#define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/ +#define RWBT_INTR_SOURCE 7 /* interrupt of RWBT, level*/ +#define RWBLE_INTR_SOURCE 8 /* interrupt of RWBLE, level*/ +#define RWBT_NMI_SOURCE 9 /* interrupt of RWBT, NMI*/ +#define RWBLE_NMI_SOURCE 10 /* interrupt of RWBLE, NMI*/ +#define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/ +#define SLC0_INTR_SOURCE 12 /* interrupt of SLC0, level*/ +#define SLC1_INTR_SOURCE 13 /* interrupt of SLC1, level*/ +#define UHCI0_INTR_SOURCE 14 /* interrupt of UHCI0, level*/ +#define UHCI1_INTR_SOURCE 15 /* interrupt of UHCI1, level*/ +#define GPIO_INTR_SOURCE 16 /* interrupt of GPIO, level*/ +#define GPIO_NMI_SOURCE 17 /* interrupt of GPIO, NMI*/ +#define GPIO_INTR_SOURCE2 18 /* interrupt of GPIO, level*/ +#define GPIO_NMI_SOURCE2 19 /* interrupt of GPIO, NMI*/ +#define SPI1_INTR_SOURCE 20 /* interrupt of SPI1, level*/ +#define SPI2_INTR_SOURCE 21 /* interrupt of SPI2, level*/ +#define SPI3_INTR_SOURCE 22 /* interrupt of SPI3, level*/ +#define LCD_CAM_INTR_SOURCE 24 /* interrupt of LCD camera, level*/ +#define I2S0_INTR_SOURCE 25 /* interrupt of I2S0, level*/ +#define I2S1_INTR_SOURCE 26 /* interrupt of I2S1, level*/ +#define UART0_INTR_SOURCE 27 /* interrupt of UART0, level*/ +#define UART1_INTR_SOURCE 28 /* interrupt of UART1, level*/ +#define UART2_INTR_SOURCE 29 /* interrupt of UART2, level*/ +#define SDIO_HOST_INTR_SOURCE 30 /* interrupt of SD/SDIO/MMC HOST, level*/ +#define PWM0_INTR_SOURCE 31 /* interrupt of PWM0, level, Reserved*/ +#define PWM1_INTR_SOURCE 32 /* interrupt of PWM1, level, Reserved*/ +#define LEDC_INTR_SOURCE 35 /* interrupt of LED PWM, level*/ +#define EFUSE_INTR_SOURCE 36 /* interrupt of efuse, level, not likely to use*/ +#define TWAI_INTR_SOURCE 37 /* interrupt of can, level*/ +#define USB_INTR_SOURCE 38 /* interrupt of USB, level*/ +#define RTC_CORE_INTR_SOURCE 39 /* interrupt of rtc core and watchdog, level*/ +#define RMT_INTR_SOURCE 40 /* interrupt of remote controller, level*/ +#define PCNT_INTR_SOURCE 41 /* interrupt of pluse count, level*/ +#define I2C_EXT0_INTR_SOURCE 42 /* interrupt of I2C controller1, level*/ +#define I2C_EXT1_INTR_SOURCE 43 /* interrupt of I2C controller0, level*/ +#define SPI2_DMA_INTR_SOURCE 44 /* interrupt of SPI2 DMA, level*/ +#define SPI3_DMA_INTR_SOURCE 45 /* interrupt of SPI3 DMA, level*/ +#define WDT_INTR_SOURCE 47 /* will be cancelled*/ +#define TIMER1_INTR_SOURCE 48 +#define TIMER2_INTR_SOURCE 49 +#define TG0_T0_LEVEL_INTR_SOURCE 50 /* interrupt of TIMER_GROUP0, TIMER0, EDGE*/ +#define TG0_T1_LEVEL_INTR_SOURCE 51 /* interrupt of TIMER_GROUP0, TIMER1, EDGE*/ +#define TG0_WDT_LEVEL_INTR_SOURCE 52 /* interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ +#define TG1_T0_LEVEL_INTR_SOURCE 53 /* interrupt of TIMER_GROUP1, TIMER0, EDGE*/ +#define TG1_T1_LEVEL_INTR_SOURCE 54 /* interrupt of TIMER_GROUP1, TIMER1, EDGE*/ +#define TG1_WDT_LEVEL_INTR_SOURCE 55 /* interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ +#define CACHE_IA_INTR_SOURCE 56 /* interrupt of Cache Invalied Access, LEVEL*/ +#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 57 /* interrupt of system timer 0, EDGE*/ +#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 58 /* interrupt of system timer 1, EDGE*/ +#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 59 /* interrupt of system timer 2, EDGE*/ +#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 60 /* interrupt of SPI0/SPI1 Cache/Rejected, LEVEL*/ +#define DCACHE_PRELOAD0_INTR_SOURCE 61 /* interrupt of DCache preload operation, LEVEL*/ +#define ICACHE_PRELOAD0_INTR_SOURCE 62 /* interrupt of ICache perload operation, LEVEL*/ +#define DCACHE_SYNC0_INTR_SOURCE 63 /* interrupt of data cache sync done, LEVEL*/ +#define ICACHE_SYNC0_INTR_SOURCE 64 /* interrupt of instr. cache sync done, LEVEL*/ +#define APB_ADC_INTR_SOURCE 65 /* interrupt of APB ADC, LEVEL*/ +#define DMA_IN_CH0_INTR_SOURCE 66 /* interrupt of general DMA RX channel 0, LEVEL*/ +#define DMA_IN_CH1_INTR_SOURCE 67 /* interrupt of general DMA RX channel 1, LEVEL*/ +#define DMA_IN_CH2_INTR_SOURCE 68 /* interrupt of general DMA RX channel 2, LEVEL*/ +#define DMA_IN_CH3_INTR_SOURCE 69 /* interrupt of general DMA RX channel 3, LEVEL*/ +#define DMA_IN_CH4_INTR_SOURCE 70 /* interrupt of general DMA RX channel 4, LEVEL*/ +#define DMA_OUT_CH0_INTR_SOURCE 71 /* interrupt of general DMA TX channel 0, LEVEL*/ +#define DMA_OUT_CH1_INTR_SOURCE 72 /* interrupt of general DMA TX channel 1, LEVEL*/ +#define DMA_OUT_CH2_INTR_SOURCE 73 /* interrupt of general DMA TX channel 2, LEVEL*/ +#define DMA_OUT_CH3_INTR_SOURCE 74 /* interrupt of general DMA TX channel 3, LEVEL*/ +#define DMA_OUT_CH4_INTR_SOURCE 75 /* interrupt of general DMA TX channel 4, LEVEL*/ +#define RSA_INTR_SOURCE 76 /* interrupt of RSA accelerator, level*/ +#define AES_INTR_SOURCE 77 /* interrupt of AES accelerator, level*/ +#define SHA_INTR_SOURCE 78 /* interrupt of SHA accelerator, level*/ +#define FROM_CPU_INTR0_SOURCE 79 /* interrupt0 generated from a CPU, level*/ +#define FROM_CPU_INTR1_SOURCE 80 /* interrupt1 generated from a CPU, level*/ +#define FROM_CPU_INTR2_SOURCE 81 /* interrupt2 generated from a CPU, level*/ +#define FROM_CPU_INTR3_SOURCE 82 /* interrupt3 generated from a CPU, level*/ +#define ASSIST_DEBUG_INTR_SOURCE 83 /* interrupt of Assist debug module, LEVEL*/ +#define DMA_APBPERI_PMS_INTR_SOURCE 84 +#define CORE0_IRAM0_PMS_INTR_SOURCE 85 +#define CORE0_DRAM0_PMS_INTR_SOURCE 86 +#define CORE0_PIF_PMS_INTR_SOURCE 87 +#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 88 +#define CORE1_IRAM0_PMS_INTR_SOURCE 89 +#define CORE1_DRAM0_PMS_INTR_SOURCE 90 +#define CORE1_PIF_PMS_INTR_SOURCE 91 +#define CORE1_PIF_PMS_SIZE_INTR_SOURCE 92 +#define BACKUP_PMS_VIOLATE_INTR_SOURCE 93 +#define CACHE_CORE0_ACS_INTR_SOURCE 94 +#define CACHE_CORE1_ACS_INTR_SOURCE 95 +#define USB_SERIAL_JTAG_INTR_SOURCE 96 +#define PREI_BACKUP_INTR_SOURCE 97 +#define DMA_EXTMEM_REJECT_SOURCE 98 +#define MAX_INTR_SOURCE 99 /* number of interrupt sources */ + +#endif diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h b/include/zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h new file mode 100644 index 0000000000000..47fd0f91302e1 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_GPIO_SIGMAP_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_GPIO_SIGMAP_H_ + +#define ESP_NOSIG ESP_SIG_INVAL + +#define ESP_SPIQ_IN 0 +#define ESP_SPIQ_OUT 0 +#define ESP_SPID_IN 1 +#define ESP_SPID_OUT 1 +#define ESP_SPIHD_IN 2 +#define ESP_SPIHD_OUT 2 +#define ESP_SPIWP_IN 3 +#define ESP_SPIWP_OUT 3 +#define ESP_SPICLK_OUT 4 +#define ESP_SPICS0_OUT 5 +#define ESP_SPICS1_OUT 6 +#define ESP_SPID4_IN 7 +#define ESP_SPID4_OUT 7 +#define ESP_SPID5_IN 8 +#define ESP_SPID5_OUT 8 +#define ESP_SPID6_IN 9 +#define ESP_SPID6_OUT 9 +#define ESP_SPID7_IN 10 +#define ESP_SPID7_OUT 10 +#define ESP_SPIDQS_IN 11 +#define ESP_SPIDQS_OUT 11 +#define ESP_U0RXD_IN 12 +#define ESP_U0TXD_OUT 12 +#define ESP_U0CTS_IN 13 +#define ESP_U0RTS_OUT 13 +#define ESP_U0DSR_IN 14 +#define ESP_U0DTR_OUT 14 +#define ESP_U1RXD_IN 15 +#define ESP_U1TXD_OUT 15 +#define ESP_U1CTS_IN 16 +#define ESP_U1RTS_OUT 16 +#define ESP_U1DSR_IN 17 +#define ESP_U1DTR_OUT 17 +#define ESP_U2RXD_IN 18 +#define ESP_U2TXD_OUT 18 +#define ESP_U2CTS_IN 19 +#define ESP_U2RTS_OUT 19 +#define ESP_U2DSR_IN 20 +#define ESP_U2DTR_OUT 20 +#define ESP_I2S1_MCLK_IN 21 +#define ESP_I2S1_MCLK_OUT 21 +#define ESP_I2S0O_BCK_IN 22 +#define ESP_I2S0O_BCK_OUT 22 +#define ESP_I2S0_MCLK_IN 23 +#define ESP_I2S0_MCLK_OUT 23 +#define ESP_I2S0O_WS_IN 24 +#define ESP_I2S0O_WS_OUT 24 +#define ESP_I2S0I_SD_IN 25 +#define ESP_I2S0O_SD_OUT 25 +#define ESP_I2S0I_BCK_IN 26 +#define ESP_I2S0I_BCK_OUT 26 +#define ESP_I2S0I_WS_IN 27 +#define ESP_I2S0I_WS_OUT 27 +#define ESP_I2S1O_BCK_IN 28 +#define ESP_I2S1O_BCK_OUT 28 +#define ESP_I2S1O_WS_IN 29 +#define ESP_I2S1O_WS_OUT 29 +#define ESP_I2S1I_SD_IN 30 +#define ESP_I2S1O_SD_OUT 30 +#define ESP_I2S1I_BCK_IN 31 +#define ESP_I2S1I_BCK_OUT 31 +#define ESP_I2S1I_WS_IN 32 +#define ESP_I2S1I_WS_OUT 32 +#define ESP_PCNT_SIG_CH0_IN0 33 +#define ESP_GPIO_WLAN_PRIO 33 +#define ESP_PCNT_SIG_CH1_IN0 34 +#define ESP_GPIO_WLAN_ACTIVE 34 +#define ESP_PCNT_CTRL_CH0_IN0 35 +#define ESP_BB_DIAG0 35 +#define ESP_PCNT_CTRL_CH1_IN0 36 +#define ESP_BB_DIAG1 36 +#define ESP_PCNT_SIG_CH0_IN1 37 +#define ESP_BB_DIAG2 37 +#define ESP_PCNT_SIG_CH1_IN1 38 +#define ESP_BB_DIAG3 38 +#define ESP_PCNT_CTRL_CH0_IN1 39 +#define ESP_BB_DIAG4 39 +#define ESP_PCNT_CTRL_CH1_IN1 40 +#define ESP_BB_DIAG5 40 +#define ESP_PCNT_SIG_CH0_IN2 41 +#define ESP_BB_DIAG6 41 +#define ESP_PCNT_SIG_CH1_IN2 42 +#define ESP_BB_DIAG7 42 +#define ESP_PCNT_CTRL_CH0_IN2 43 +#define ESP_BB_DIAG8 43 +#define ESP_PCNT_CTRL_CH1_IN2 44 +#define ESP_BB_DIAG9 44 +#define ESP_PCNT_SIG_CH0_IN3 45 +#define ESP_BB_DIAG10 45 +#define ESP_PCNT_SIG_CH1_IN3 46 +#define ESP_BB_DIAG11 46 +#define ESP_PCNT_CTRL_CH0_IN3 47 +#define ESP_BB_DIAG12 47 +#define ESP_PCNT_CTRL_CH1_IN3 48 +#define ESP_BB_DIAG13 48 +#define ESP_GPIO_BT_ACTIVE 49 +#define ESP_BB_DIAG14 49 +#define ESP_GPIO_BT_PRIORITY 50 +#define ESP_BB_DIAG15 50 +#define ESP_I2S0I_SD1_IN 51 +#define ESP_BB_DIAG16 51 +#define ESP_I2S0I_SD2_IN 52 +#define ESP_BB_DIAG17 52 +#define ESP_I2S0I_SD3_IN 53 +#define ESP_BB_DIAG18 53 +#define ESP_CORE1_GPIO_IN7 54 +#define ESP_CORE1_GPIO_OUT7 54 +#define ESP_USB_EXTPHY_VP 55 +#define ESP_USB_EXTPHY_OEN 55 +#define ESP_USB_EXTPHY_VM 56 +#define ESP_USB_EXTPHY_SPEED 56 +#define ESP_USB_EXTPHY_RCV 57 +#define ESP_USB_EXTPHY_VPO 57 +#define ESP_USB_OTG_IDDIG_IN 58 +#define ESP_USB_EXTPHY_VMO 58 +#define ESP_USB_OTG_AVALID_IN 59 +#define ESP_USB_EXTPHY_SUSPND 59 +#define ESP_USB_SRP_BVALID_IN 60 +#define ESP_USB_OTG_IDPULLUP 60 +#define ESP_USB_OTG_VBUSVALID_IN 61 +#define ESP_USB_OTG_DPPULLDOWN 61 +#define ESP_USB_SRP_SESSEND_IN 62 +#define ESP_USB_OTG_DMPULLDOWN 62 +#define ESP_USB_OTG_DRVVBUS 63 +#define ESP_USB_SRP_CHRGVBUS 64 +#define ESP_USB_SRP_DISCHRGVBUS 65 +#define ESP_SPI3_CLK_IN 66 +#define ESP_SPI3_CLK_OUT 66 +#define ESP_SPI3_Q_IN 67 +#define ESP_SPI3_Q_OUT 67 +#define ESP_SPI3_D_IN 68 +#define ESP_SPI3_D_OUT 68 +#define ESP_SPI3_HD_IN 69 +#define ESP_SPI3_HD_OUT 69 +#define ESP_SPI3_WP_IN 70 +#define ESP_SPI3_WP_OUT 70 +#define ESP_SPI3_CS0_IN 71 +#define ESP_SPI3_CS0_OUT 71 +#define ESP_SPI3_CS1_OUT 72 +#define ESP_EXT_ADC_START 73 +#define ESP_LEDC_LS_SIG_OUT0 73 +#define ESP_LEDC_LS_SIG_OUT1 74 +#define ESP_LEDC_LS_SIG_OUT2 75 +#define ESP_LEDC_LS_SIG_OUT3 76 +#define ESP_LEDC_LS_SIG_OUT4 77 +#define ESP_LEDC_LS_SIG_OUT5 78 +#define ESP_LEDC_LS_SIG_OUT6 79 +#define ESP_LEDC_LS_SIG_OUT7 80 +#define ESP_RMT_SIG_IN0 81 +#define ESP_RMT_SIG_OUT0 81 +#define ESP_RMT_SIG_IN1 82 +#define ESP_RMT_SIG_OUT1 82 +#define ESP_RMT_SIG_IN2 83 +#define ESP_RMT_SIG_OUT2 83 +#define ESP_RMT_SIG_IN3 84 +#define ESP_RMT_SIG_OUT3 84 +#define ESP_USB_JTAG_TCK 85 +#define ESP_USB_JTAG_TMS 86 +#define ESP_USB_JTAG_TDI 87 +#define ESP_USB_JTAG_TDO 88 +#define ESP_I2CEXT0_SCL_IN 89 +#define ESP_I2CEXT0_SCL_OUT 89 +#define ESP_I2CEXT0_SDA_IN 90 +#define ESP_I2CEXT0_SDA_OUT 90 +#define ESP_I2CEXT1_SCL_IN 91 +#define ESP_I2CEXT1_SCL_OUT 91 +#define ESP_I2CEXT1_SDA_IN 92 +#define ESP_I2CEXT1_SDA_OUT 92 +#define ESP_GPIO_SD0_OUT 93 +#define ESP_GPIO_SD1_OUT 94 +#define ESP_GPIO_SD2_OUT 95 +#define ESP_GPIO_SD3_OUT 96 +#define ESP_GPIO_SD4_OUT 97 +#define ESP_GPIO_SD5_OUT 98 +#define ESP_GPIO_SD6_OUT 99 +#define ESP_GPIO_SD7_OUT 100 +#define ESP_FSPICLK_IN 101 +#define ESP_FSPICLK_OUT 101 +#define ESP_FSPIQ_IN 102 +#define ESP_FSPIQ_OUT 102 +#define ESP_FSPID_IN 103 +#define ESP_FSPID_OUT 103 +#define ESP_FSPIHD_IN 104 +#define ESP_FSPIHD_OUT 104 +#define ESP_FSPIWP_IN 105 +#define ESP_FSPIWP_OUT 105 +#define ESP_FSPIIO4_IN 106 +#define ESP_FSPIIO4_OUT 106 +#define ESP_FSPIIO5_IN 107 +#define ESP_FSPIIO5_OUT 107 +#define ESP_FSPIIO6_IN 108 +#define ESP_FSPIIO6_OUT 108 +#define ESP_FSPIIO7_IN 109 +#define ESP_FSPIIO7_OUT 109 +#define ESP_FSPICS0_IN 110 +#define ESP_FSPICS0_OUT 110 +#define ESP_FSPICS1_OUT 111 +#define ESP_FSPICS2_OUT 112 +#define ESP_FSPICS3_OUT 113 +#define ESP_FSPICS4_OUT 114 +#define ESP_FSPICS5_OUT 115 +#define ESP_TWAI_RX 116 +#define ESP_TWAI_TX 116 +#define ESP_TWAI_BUS_OFF_ON 117 +#define ESP_TWAI_CLKOUT 118 +#define ESP_SUBSPICLK_OUT 119 +#define ESP_SUBSPIQ_IN 120 +#define ESP_SUBSPIQ_OUT 120 +#define ESP_SUBSPID_IN 121 +#define ESP_SUBSPID_OUT 121 +#define ESP_SUBSPIHD_IN 122 +#define ESP_SUBSPIHD_OUT 122 +#define ESP_SUBSPIWP_IN 123 +#define ESP_SUBSPIWP_OUT 123 +#define ESP_SUBSPICS0_OUT 124 +#define ESP_SUBSPICS1_OUT 125 +#define ESP_FSPIDQS_OUT 126 +#define ESP_SPI3_CS2_OUT 127 +#define ESP_I2S0O_SD1_OUT 128 +#define ESP_CORE1_GPIO_IN0 129 +#define ESP_CORE1_GPIO_OUT0 129 +#define ESP_CORE1_GPIO_IN1 130 +#define ESP_CORE1_GPIO_OUT1 130 +#define ESP_CORE1_GPIO_IN2 131 +#define ESP_CORE1_GPIO_OUT2 131 +#define ESP_LCD_CS 132 +#define ESP_CAM_DATA_IN0 133 +#define ESP_LCD_DATA_OUT0 133 +#define ESP_CAM_DATA_IN1 134 +#define ESP_LCD_DATA_OUT1 134 +#define ESP_CAM_DATA_IN2 135 +#define ESP_LCD_DATA_OUT2 135 +#define ESP_CAM_DATA_IN3 136 +#define ESP_LCD_DATA_OUT3 136 +#define ESP_CAM_DATA_IN4 137 +#define ESP_LCD_DATA_OUT4 137 +#define ESP_CAM_DATA_IN5 138 +#define ESP_LCD_DATA_OUT5 138 +#define ESP_CAM_DATA_IN6 139 +#define ESP_LCD_DATA_OUT6 139 +#define ESP_CAM_DATA_IN7 140 +#define ESP_LCD_DATA_OUT7 140 +#define ESP_CAM_DATA_IN8 141 +#define ESP_LCD_DATA_OUT8 141 +#define ESP_CAM_DATA_IN9 142 +#define ESP_LCD_DATA_OUT9 142 +#define ESP_CAM_DATA_IN10 143 +#define ESP_LCD_DATA_OUT10 143 +#define ESP_CAM_DATA_IN11 144 +#define ESP_LCD_DATA_OUT11 144 +#define ESP_CAM_DATA_IN12 145 +#define ESP_LCD_DATA_OUT12 145 +#define ESP_CAM_DATA_IN13 146 +#define ESP_LCD_DATA_OUT13 146 +#define ESP_CAM_DATA_IN14 147 +#define ESP_LCD_DATA_OUT14 147 +#define ESP_CAM_DATA_IN15 148 +#define ESP_LCD_DATA_OUT15 148 +#define ESP_CAM_PCLK 149 +#define ESP_CAM_CLK 149 +#define ESP_CAM_H_ENABLE 150 +#define ESP_LCD_H_ENABLE 150 +#define ESP_CAM_H_SYNC 151 +#define ESP_LCD_H_SYNC 151 +#define ESP_CAM_V_SYNC 152 +#define ESP_LCD_V_SYNC 152 +#define ESP_LCD_DC 153 +#define ESP_LCD_PCLK 154 +#define ESP_SUBSPID4_IN 155 +#define ESP_SUBSPID4_OUT 155 +#define ESP_SUBSPID5_IN 156 +#define ESP_SUBSPID5_OUT 156 +#define ESP_SUBSPID6_IN 157 +#define ESP_SUBSPID6_OUT 157 +#define ESP_SUBSPID7_IN 158 +#define ESP_SUBSPID7_OUT 158 +#define ESP_SUBSPIDQS_IN 159 +#define ESP_SUBSPIDQS_OUT 159 +#define ESP_PWM0_SYNC0_IN 160 +#define ESP_PWM0_OUT0A 160 +#define ESP_PWM0_SYNC1_IN 161 +#define ESP_PWM0_OUT0B 161 +#define ESP_PWM0_SYNC2_IN 162 +#define ESP_PWM0_OUT1A 162 +#define ESP_PWM0_F0_IN 163 +#define ESP_PWM0_OUT1B 163 +#define ESP_PWM0_F1_IN 164 +#define ESP_PWM0_OUT2A 164 +#define ESP_PWM0_F2_IN 165 +#define ESP_PWM0_OUT2B 165 +#define ESP_PWM0_CAP0_IN 166 +#define ESP_PWM1_OUT0A 166 +#define ESP_PWM0_CAP1_IN 167 +#define ESP_PWM1_OUT0B 167 +#define ESP_PWM0_CAP2_IN 168 +#define ESP_PWM1_OUT1A 168 +#define ESP_PWM1_SYNC0_IN 169 +#define ESP_PWM1_OUT1B 169 +#define ESP_PWM1_SYNC1_IN 170 +#define ESP_PWM1_OUT2A 170 +#define ESP_PWM1_SYNC2_IN 171 +#define ESP_PWM1_OUT2B 171 +#define ESP_PWM1_F0_IN 172 +#define ESP_SDHOST_CCLK_OUT_1 172 +#define ESP_PWM1_F1_IN 173 +#define ESP_SDHOST_CCLK_OUT_2 173 +#define ESP_PWM1_F2_IN 174 +#define ESP_SDHOST_RST_N_1 174 +#define ESP_PWM1_CAP0_IN 175 +#define ESP_SDHOST_RST_N_2 175 +#define ESP_PWM1_CAP1_IN 176 +#define ESP_SDHOST_CCMD_OD_PULLUP_EN_N176 +#define ESP_PWM1_CAP2_IN 177 +#define ESP_SDIO_TOHOST_INT_OUT 177 +#define ESP_SDHOST_CCMD_IN_1 178 +#define ESP_SDHOST_CCMD_OUT_1 178 +#define ESP_SDHOST_CCMD_IN_2 179 +#define ESP_SDHOST_CCMD_OUT_2 179 +#define ESP_SDHOST_CDATA_IN_10 180 +#define ESP_SDHOST_CDATA_OUT_10 180 +#define ESP_SDHOST_CDATA_IN_11 181 +#define ESP_SDHOST_CDATA_OUT_11 181 +#define ESP_SDHOST_CDATA_IN_12 182 +#define ESP_SDHOST_CDATA_OUT_12 182 +#define ESP_SDHOST_CDATA_IN_13 183 +#define ESP_SDHOST_CDATA_OUT_13 183 +#define ESP_SDHOST_CDATA_IN_14 184 +#define ESP_SDHOST_CDATA_OUT_14 184 +#define ESP_SDHOST_CDATA_IN_15 185 +#define ESP_SDHOST_CDATA_OUT_15 185 +#define ESP_SDHOST_CDATA_IN_16 186 +#define ESP_SDHOST_CDATA_OUT_16 186 +#define ESP_SDHOST_CDATA_IN_17 187 +#define ESP_SDHOST_CDATA_OUT_17 187 +#define ESP_PCMFSYNC_IN 188 +#define ESP_BT_AUDIO0_IRQ 188 +#define ESP_PCMCLK_IN 189 +#define ESP_BT_AUDIO1_IRQ 189 +#define ESP_PCMDIN 190 +#define ESP_BT_AUDIO2_IRQ 190 +#define ESP_RW_WAKEUP_REQ 191 +#define ESP_BLE_AUDIO0_IRQ 191 +#define ESP_SDHOST_DATA_STROBE_1 192 +#define ESP_BLE_AUDIO1_IRQ 192 +#define ESP_SDHOST_DATA_STROBE_2 193 +#define ESP_BLE_AUDIO2_IRQ 193 +#define ESP_SDHOST_CARD_DETECT_N_1 194 +#define ESP_PCMFSYNC_OUT 194 +#define ESP_SDHOST_CARD_DETECT_N_2 195 +#define ESP_PCMCLK_OUT 195 +#define ESP_SDHOST_CARD_WRITE_PRT_1 196 +#define ESP_PCMDOUT 196 +#define ESP_SDHOST_CARD_WRITE_PRT_2 197 +#define ESP_BLE_AUDIO_SYNC0_P 197 +#define ESP_SDHOST_CARD_INT_N_1 198 +#define ESP_BLE_AUDIO_SYNC1_P 198 +#define ESP_SDHOST_CARD_INT_N_2 199 +#define ESP_BLE_AUDIO_SYNC2_P 199 +#define ESP_ANT_SEL0 200 +#define ESP_ANT_SEL1 201 +#define ESP_ANT_SEL2 202 +#define ESP_ANT_SEL3 203 +#define ESP_ANT_SEL4 204 +#define ESP_ANT_SEL5 205 +#define ESP_ANT_SEL6 206 +#define ESP_ANT_SEL7 207 +#define ESP_SIG_IN_FUNC_208 208 +#define ESP_SIG_IN_FUNC208 208 +#define ESP_SIG_IN_FUNC_209 209 +#define ESP_SIG_IN_FUNC209 209 +#define ESP_SIG_IN_FUNC_210 210 +#define ESP_SIG_IN_FUNC210 210 +#define ESP_SIG_IN_FUNC_211 211 +#define ESP_SIG_IN_FUNC211 211 +#define ESP_SIG_IN_FUNC_212 212 +#define ESP_SIG_IN_FUNC212 212 +#define ESP_SDHOST_CDATA_IN_20 213 +#define ESP_SDHOST_CDATA_OUT_20 213 +#define ESP_SDHOST_CDATA_IN_21 214 +#define ESP_SDHOST_CDATA_OUT_21 214 +#define ESP_SDHOST_CDATA_IN_22 215 +#define ESP_SDHOST_CDATA_OUT_22 215 +#define ESP_SDHOST_CDATA_IN_23 216 +#define ESP_SDHOST_CDATA_OUT_23 216 +#define ESP_SDHOST_CDATA_IN_24 217 +#define ESP_SDHOST_CDATA_OUT_24 217 +#define ESP_SDHOST_CDATA_IN_25 218 +#define ESP_SDHOST_CDATA_OUT_25 218 +#define ESP_SDHOST_CDATA_IN_26 219 +#define ESP_SDHOST_CDATA_OUT_26 219 +#define ESP_SDHOST_CDATA_IN_27 220 +#define ESP_SDHOST_CDATA_OUT_27 220 +#define ESP_PRO_ALONEGPIO_IN0 221 +#define ESP_PRO_ALONEGPIO_OUT0 221 +#define ESP_PRO_ALONEGPIO_IN1 222 +#define ESP_PRO_ALONEGPIO_OUT1 222 +#define ESP_PRO_ALONEGPIO_IN2 223 +#define ESP_PRO_ALONEGPIO_OUT2 223 +#define ESP_PRO_ALONEGPIO_IN3 224 +#define ESP_PRO_ALONEGPIO_OUT3 224 +#define ESP_PRO_ALONEGPIO_IN4 225 +#define ESP_PRO_ALONEGPIO_OUT4 225 +#define ESP_PRO_ALONEGPIO_IN5 226 +#define ESP_PRO_ALONEGPIO_OUT5 226 +#define ESP_PRO_ALONEGPIO_IN6 227 +#define ESP_PRO_ALONEGPIO_OUT6 227 +#define ESP_PRO_ALONEGPIO_IN7 228 +#define ESP_PRO_ALONEGPIO_OUT7 228 +#define ESP_SYNCERR 229 +#define ESP_SYNCFOUND_FLAG 230 +#define ESP_EVT_CNTL_IMMEDIATE_ABORT 231 +#define ESP_LINKLBL 232 +#define ESP_DATA_EN 233 +#define ESP_DATA 234 +#define ESP_PKT_TX_ON 235 +#define ESP_PKT_RX_ON 236 +#define ESP_RW_TX_ON 237 +#define ESP_RW_RX_ON 238 +#define ESP_EVT_REQ_P 239 +#define ESP_EVT_STOP_P 240 +#define ESP_BT_MODE_ON 241 +#define ESP_GPIO_LC_DIAG0 242 +#define ESP_GPIO_LC_DIAG1 243 +#define ESP_GPIO_LC_DIAG2 244 +#define ESP_CH 245 +#define ESP_RX_WINDOW 246 +#define ESP_UPDATE_RX 247 +#define ESP_RX_STATUS 248 +#define ESP_CLK_GPIO 249 +#define ESP_NBT_BLE 250 +#define ESP_USB_JTAG_TDO_BRIDGE 251 +#define ESP_USB_JTAG_TRST 251 +#define ESP_CORE1_GPIO_IN3 252 +#define ESP_CORE1_GPIO_OUT3 252 +#define ESP_CORE1_GPIO_IN4 253 +#define ESP_CORE1_GPIO_OUT4 253 +#define ESP_CORE1_GPIO_IN5 254 +#define ESP_CORE1_GPIO_OUT5 254 +#define ESP_CORE1_GPIO_IN6 255 +#define ESP_CORE1_GPIO_OUT6 255 +#define ESP_SIG_GPIO_OUT 256 +#define ESP_GPIO_MAP_DATE 0x1907040 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_GPIO_SIGMAP_H_ */ From 10a3177edeee9345b77d130ea9624e8c22aa8adf Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:15:18 -0300 Subject: [PATCH 2/7] soc: esp32s3: add base source content This brings esp32s3 linker, DTS and all necessary files to allow the soc support. Signed-off-by: Sylvio Alves --- dts/xtensa/espressif/esp32s3.dtsi | 154 +++++ soc/xtensa/esp32s3/CMakeLists.txt | 83 +++ soc/xtensa/esp32s3/Kconfig.defconfig | 44 ++ soc/xtensa/esp32s3/Kconfig.soc | 266 ++++++++ soc/xtensa/esp32s3/include/_soc_inthandlers.h | 371 ++++++++++ soc/xtensa/esp32s3/linker.ld | 643 ++++++++++++++++++ soc/xtensa/esp32s3/loader.c | 96 +++ soc/xtensa/esp32s3/newlib_fix.c | 22 + soc/xtensa/esp32s3/pinctrl_soc.h | 78 +++ soc/xtensa/esp32s3/soc.c | 243 +++++++ soc/xtensa/esp32s3/soc.h | 72 ++ west.yml | 2 +- 12 files changed, 2073 insertions(+), 1 deletion(-) create mode 100644 dts/xtensa/espressif/esp32s3.dtsi create mode 100644 soc/xtensa/esp32s3/CMakeLists.txt create mode 100644 soc/xtensa/esp32s3/Kconfig.defconfig create mode 100644 soc/xtensa/esp32s3/Kconfig.soc create mode 100644 soc/xtensa/esp32s3/include/_soc_inthandlers.h create mode 100644 soc/xtensa/esp32s3/linker.ld create mode 100644 soc/xtensa/esp32s3/loader.c create mode 100644 soc/xtensa/esp32s3/newlib_fix.c create mode 100644 soc/xtensa/esp32s3/pinctrl_soc.h create mode 100644 soc/xtensa/esp32s3/soc.c create mode 100644 soc/xtensa/esp32s3/soc.h diff --git a/dts/xtensa/espressif/esp32s3.dtsi b/dts/xtensa/espressif/esp32s3.dtsi new file mode 100644 index 0000000000000..069a49e962ca6 --- /dev/null +++ b/dts/xtensa/espressif/esp32s3.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/ { + chosen { + zephyr,flash-controller = &flash; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <1>; + }; + + }; + + pinctrl: pin-controller { + compatible = "espressif,esp32-pinctrl"; + status = "okay"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + sram0: memory@3fc88000 { + compatible = "mmio-sram"; + reg = <0x3fc88000 0x77FFF>; + }; + + intc: interrupt-controller@600c2000 { + #interrupt-cells = <1>; + compatible = "espressif,esp32-intc"; + interrupt-controller; + reg = <0x600c2000 0x1000>; + status = "okay"; + }; + + rtc: rtc@60021000 { + compatible = "espressif,esp32-rtc"; + reg = <0x60021000 0x2000>; + xtal-freq = ; + #clock-cells = <1>; + status = "okay"; + + rtc_timer: rtc_timer { + compatible = "espressif,esp32-rtc-timer"; + slow-clk-freq = ; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; + }; + }; + + flash: flash-controller@60002000 { + compatible = "espressif,esp32-flash-controller"; + reg = <0x60002000 0x1000>; + /* interrupts = <3 0>; */ + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 0x800000>; + erase-block-size = <4096>; + write-block-size = <4>; + }; + }; + + uart0: uart@60000000 { + compatible = "espressif,esp32-uart"; + reg = <0x60000000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_UART0_MODULE>; + status = "disabled"; + }; + + uart1: uart@60010000 { + compatible = "espressif,esp32-uart"; + reg = <0x60010000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_UART1_MODULE>; + status = "disabled"; + }; + + uart2: uart@6002e000 { + compatible = "espressif,esp32-uart"; + reg = <0x6002e000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_UART2_MODULE>; + status = "disabled"; + }; + + gpio: gpio { + compatible = "simple-bus"; + gpio-map-mask = <0xffffffe0 0xffffffc0>; + gpio-map-pass-thru = <0x1f 0x3f>; + gpio-map = < + 0x00 0x0 &gpio0 0x0 0x0 + 0x20 0x0 &gpio1 0x0 0x0 + >; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@60004000 { + compatible = "espressif,esp32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60004000 0x800>; + interrupts = ; + interrupt-parent = <&intc>; + ngpios = <32>; + }; + + gpio1: gpio@60004800 { + compatible = "espressif,esp32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60004800 0x800>; + interrupts = ; + interrupt-parent = <&intc>; + ngpios = <13>; + }; + }; + + }; +}; diff --git a/soc/xtensa/esp32s3/CMakeLists.txt b/soc/xtensa/esp32s3/CMakeLists.txt new file mode 100644 index 0000000000000..2feca8a7e741a --- /dev/null +++ b/soc/xtensa/esp32s3/CMakeLists.txt @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + loader.c + ) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + +board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") diff --git a/soc/xtensa/esp32s3/Kconfig.defconfig b/soc/xtensa/esp32s3/Kconfig.defconfig new file mode 100644 index 0000000000000..b20609d27c0e0 --- /dev/null +++ b/soc/xtensa/esp32s3/Kconfig.defconfig @@ -0,0 +1,44 @@ +# ESP32 board configuration + +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ESP32S3 + +if BOOTLOADER_MCUBOOT + config HAS_FLASH_LOAD_OFFSET + default y + + config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + + config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + + config ROM_START_OFFSET + default 0x20 + + config HAS_DYNAMIC_DEVICE_HANDLES + default y +endif + +config SOC + default "esp32s3" + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s3" + +config HEAP_MEM_POOL_SIZE + default 32768 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +endif diff --git a/soc/xtensa/esp32s3/Kconfig.soc b/soc/xtensa/esp32s3/Kconfig.soc new file mode 100644 index 0000000000000..9c8dee0ade836 --- /dev/null +++ b/soc/xtensa/esp32s3/Kconfig.soc @@ -0,0 +1,266 @@ +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ESP32S3 + bool "ESP32S3" + select XTENSA + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select ARCH_SUPPORTS_COREDUMP + select PINCTRL + select XIP + select HAS_ESPRESSIF_HAL + +if SOC_ESP32S3 + +config IDF_TARGET_ESP32S3 + bool "ESP32S3 as target board" + default y + +config ESPTOOLPY_FLASHFREQ_80M + bool + default y + +config FLASH_SIZE + int + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + hex + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +choice ESP32S3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config ESP32S3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + config ESP32S3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config ESP32S3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config ESP32S3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" +endchoice + +config ESP32S3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi/BLE TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +menu "Cache config" + +choice ESP32S3_INSTRUCTION_CACHE_SIZE + prompt "Instruction cache size" + default ESP32S3_INSTRUCTION_CACHE_16KB + help + Instruction cache size to be set on application startup. + If you use 16KB instruction cache rather than 32KB instruction cache, + then the other 16KB will be managed by heap allocator. + + config ESP32S3_INSTRUCTION_CACHE_16KB + bool "16KB" + config ESP32S3_INSTRUCTION_CACHE_32KB + bool "32KB" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_SIZE + hex + default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB + default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB + +choice ESP32S3_ICACHE_ASSOCIATED_WAYS + prompt "Instruction cache associated ways" + default ESP32S3_INSTRUCTION_CACHE_8WAYS + help + Instruction cache associated ways to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_4WAYS + bool "4 ways" + config ESP32S3_INSTRUCTION_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_ICACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS + default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS + +choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + prompt "Instruction cache line size" + default ESP32S3_INSTRUCTION_CACHE_LINE_32B + help + Instruction cache line size to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_INSTRUCTION_CACHE_16KB + config ESP32S3_INSTRUCTION_CACHE_LINE_32B + bool "32 Bytes" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + int + default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B + default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B + +config ESP32S3_INSTRUCTION_CACHE_WRAP + bool "Define instruction cache wrap mode" + help + If enabled, instruction cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +choice ESP32S3_DATA_CACHE_SIZE + prompt "Data cache size" + default ESP32S3_DATA_CACHE_32KB + help + Data cache size to be set on application startup. + If you use 32KB data cache rather than 64KB data cache, + the other 32KB will be added to the heap. + + config ESP32S3_DATA_CACHE_16KB + bool "16KB" + config ESP32S3_DATA_CACHE_32KB + bool "32KB" + config ESP32S3_DATA_CACHE_64KB + bool "64KB" +endchoice + +config ESP32S3_DATA_CACHE_SIZE + hex + # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup + default 0x8000 if ESP32S3_DATA_CACHE_16KB + default 0x8000 if ESP32S3_DATA_CACHE_32KB + default 0x10000 if ESP32S3_DATA_CACHE_64KB + +choice ESP32S3_DCACHE_ASSOCIATED_WAYS + prompt "Data cache associated ways" + default ESP32S3_DATA_CACHE_8WAYS + help + Data cache associated ways to be set on application startup. + + config ESP32S3_DATA_CACHE_4WAYS + bool "4 ways" + config ESP32S3_DATA_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_DCACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_DATA_CACHE_4WAYS + default 8 if ESP32S3_DATA_CACHE_8WAYS + +choice ESP32S3_DATA_CACHE_LINE_SIZE + prompt "Data cache line size" + default ESP32S3_DATA_CACHE_LINE_32B + help + Data cache line size to be set on application startup. + + config ESP32S3_DATA_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB + config ESP32S3_DATA_CACHE_LINE_32B + bool "32 Bytes" + config ESP32S3_DATA_CACHE_LINE_64B + bool "64 Bytes" +endchoice + +config ESP32S3_DATA_CACHE_LINE_SIZE + int + default 16 if ESP32S3_DATA_CACHE_LINE_16B + default 32 if ESP32S3_DATA_CACHE_LINE_32B + default 64 if ESP32S3_DATA_CACHE_LINE_64B + +config ESP32S3_DATA_CACHE_WRAP + bool "Define data cache wrap mode" + help + If enabled, data cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +endmenu # Cache config + +endif # SOC_ESP32S3 diff --git a/soc/xtensa/esp32s3/include/_soc_inthandlers.h b/soc/xtensa/esp32s3/include/_soc_inthandlers.h new file mode 100644 index 0000000000000..6980643e71dd4 --- /dev/null +++ b/soc/xtensa/esp32s3/include/_soc_inthandlers.h @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + * + * Functions here are designed to produce efficient code to + * search an Xtensa bitmask of interrupts, inspecting only those bits + * declared to be associated with a given interrupt level. Each + * dispatcher will handle exactly one flagged interrupt, in numerical + * order (low bits first) and will return a mask of that bit that can + * then be cleared by the calling code. Unrecognized bits for the + * level will invoke an error handler. + */ + +#include +#include +#include + +#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif + +static inline int _xtensa_handle_one_int1(unsigned int mask) +{ + int irq; + + if (mask & 0x7f) { + if (mask & 0x7) { + if (mask & BIT(0)) { + mask = BIT(0); + irq = 0; + goto handle_irq; + } + if (mask & BIT(1)) { + mask = BIT(1); + irq = 1; + goto handle_irq; + } + if (mask & BIT(2)) { + mask = BIT(2); + irq = 2; + goto handle_irq; + } + } else { + if (mask & 0x18) { + if (mask & BIT(3)) { + mask = BIT(3); + irq = 3; + goto handle_irq; + } + if (mask & BIT(4)) { + mask = BIT(4); + irq = 4; + goto handle_irq; + } + } else { + if (mask & BIT(5)) { + mask = BIT(5); + irq = 5; + goto handle_irq; + } + if (mask & BIT(6)) { + mask = BIT(6); + irq = 6; + goto handle_irq; + } + } + } + } else { + if (mask & 0x780) { + if (mask & 0x180) { + if (mask & BIT(7)) { + mask = BIT(7); + irq = 7; + goto handle_irq; + } + if (mask & BIT(8)) { + mask = BIT(8); + irq = 8; + goto handle_irq; + } + } else { + if (mask & BIT(9)) { + mask = BIT(9); + irq = 9; + goto handle_irq; + } + if (mask & BIT(10)) { + mask = BIT(10); + irq = 10; + goto handle_irq; + } + } + } else { + if (mask & 0x3000) { + if (mask & BIT(12)) { + mask = BIT(12); + irq = 12; + goto handle_irq; + } + if (mask & BIT(13)) { + mask = BIT(13); + irq = 13; + goto handle_irq; + } + } else { + if (mask & BIT(17)) { + mask = BIT(17); + irq = 17; + goto handle_irq; + } + if (mask & BIT(18)) { + mask = BIT(18); + irq = 18; + goto handle_irq; + } + } + } + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int3(unsigned int mask) +{ + int irq; + + if (mask & 0x408800) { + if (mask & BIT(11)) { + mask = BIT(11); + irq = 11; + goto handle_irq; + } + if (mask & BIT(15)) { + mask = BIT(15); + irq = 15; + goto handle_irq; + } + if (mask & BIT(22)) { + mask = BIT(22); + irq = 22; + goto handle_irq; + } + } else { + if (mask & BIT(23)) { + mask = BIT(23); + irq = 23; + goto handle_irq; + } + if (mask & BIT(27)) { + mask = BIT(27); + irq = 27; + goto handle_irq; + } + if (mask & BIT(29)) { + mask = BIT(29); + irq = 29; + goto handle_irq; + } + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int7(unsigned int mask) +{ + int irq; + + if (mask & BIT(14)) { + mask = BIT(14); + irq = 14; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int5(unsigned int mask) +{ + int irq; + + if (mask & BIT(16)) { + mask = BIT(16); + irq = 16; + goto handle_irq; + } + if (mask & BIT(26)) { + mask = BIT(26); + irq = 26; + goto handle_irq; + } + if (mask & BIT(31)) { + mask = BIT(31); + irq = 31; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int2(unsigned int mask) +{ + int irq; + + if (mask & BIT(19)) { + mask = BIT(19); + irq = 19; + goto handle_irq; + } + if (mask & BIT(20)) { + mask = BIT(20); + irq = 20; + goto handle_irq; + } + if (mask & BIT(21)) { + mask = BIT(21); + irq = 21; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int4(unsigned int mask) +{ + int irq; + + if (mask & 0x3000000) { + if (mask & BIT(24)) { + mask = BIT(24); + irq = 24; + goto handle_irq; + } + if (mask & BIT(25)) { + mask = BIT(25); + irq = 25; + goto handle_irq; + } + } else { + if (mask & BIT(28)) { + mask = BIT(28); + irq = 28; + goto handle_irq; + } + if (mask & BIT(30)) { + mask = BIT(30); + irq = 30; + goto handle_irq; + } + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int0(unsigned int mask) +{ + return 0; +} +static inline int _xtensa_handle_one_int6(unsigned int mask) +{ + return 0; +} diff --git a/soc/xtensa/esp32s3/linker.ld b/soc/xtensa/esp32s3/linker.ld new file mode 100644 index 0000000000000..bad03af67b82a --- /dev/null +++ b/soc/xtensa/esp32s3/linker.ld @@ -0,0 +1,643 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the Xtensa platform. + */ + +#include +#include +#include +#include + +#define SRAM_IRAM_START 0x40370000 +#define SRAM_DIRAM_I_START 0x40378000 +#define SRAM_IRAM_END 0x403BA000 +#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) + +#define SRAM_DRAM_START 0x3FC88000 +#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) +#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) + +#define ICACHE_SIZE 0x8000 +#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) +#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) + +#define DCACHE_SIZE 0x10000 +#define SRAM_DRAM_ORG (SRAM_DRAM_START) + +#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE + +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION ROM + +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x800000 +#endif + +#ifdef CONFIG_BOOTLOADER_ESP_IDF + +#define IROM_SEG_ORG 0x42000020 +#define IROM_SEG_LEN FLASH_SIZE-0x20 +#define IROM_SEG_ALIGN 0x4 + +#else + +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define IROM_SEG_ALIGN 0x10000 + +#endif + +MEMORY +{ + mcuboot_hdr (RX): org = 0x0, len = 0x20 + metadata (RX): org = 0x20, len = 0x20 + ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 + iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN + + /* DROM is the first segment placed in generated binary. + * MCUboot binary for ESP32 has image header of 0x20 bytes. + * Additional load header of 0x20 bytes are appended to the image. + * Hence, an offset of 0x40 is added to DROM segment origin. + */ + drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + + /** + * RTC fast memory (executable). Persists over deep sleep. + */ + rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 + + /** + * RTC fast memory (same block as above), viewed from data bus + */ + rtc_data_seg(RW): org = 0x600fe000, len = 0x2000 + + /** + * RTC slow memory (data accessible). Persists over deep sleep. + */ + rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +_diram_i_start = 0x40378000; + +SECTIONS +{ + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* Magic byte for load header */ + LONG(0xace637d3) + + /* Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + } > metadata + +#include + + /* RTC fast memory holds RTC wake stub code, + including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + *(.rtc.entry.text) + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /** + * This section is required to skip rtc.text area because rtc_iram_seg and + * rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /** + * This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /** + * RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + *(.rtc.data) + *(.rtc.rodata) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /** + * This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /** + * This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + +/* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libgcov.a:(.literal .text .literal.* .text.*) + + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + _image_dram_start = LOADADDR(.dram0.data); + _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; + _image_dram_vaddr = ADDR(.dram0.data); + + /** + * This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + MAX(_iram_end - _iram_start, 0); + } GROUP_LINK_IN(RAMABLE_REGION) + + #include + + .dram0.data : + { + __data_start = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + _end = ABSOLUTE(.); + _heap_sentry = .; + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN(4); + *(.noinit .noinit.*) + . = ALIGN(4) ; + } GROUP_LINK_IN(RAMABLE_REGION) + +/* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + .flash.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + *(.literal .text .literal.* .text.*) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /** + * Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = .; + /* Start at the same alignment constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(0x10000) + 0x20; + _rodata_reserved_start = .; + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + .flash.appdesc : ALIGN(0x10) + { + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flah.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(_RODATA_SECTION_NAME)); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + +SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + { + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + . = ALIGN(4); + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. + * Executing directly from LMA is not possible. */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + #include + #include + #include + #include + #include + #include + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) + { + . = ALIGN(4); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + _image_iram_start = LOADADDR(.iram0.vectors); + _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; + _image_iram_vaddr = ADDR(.iram0.vectors); + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . = ALIGN(16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") diff --git a/soc/xtensa/esp32s3/loader.c b/soc/xtensa/esp32s3/loader.c new file mode 100644 index 0000000000000..cf3fafc53178c --- /dev/null +++ b/soc/xtensa/esp32s3/loader.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BOOTLOADER_MCUBOOT +#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) + +extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; +extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; + +void __start(void); + +static HDR_ATTR void (*_entry_point)(void) = &__start; + +static int map_rom_segments(void) +{ + int rc = 0; + size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); + uint32_t _app_irom_start = _partition_offset + + (uint32_t)&_image_irom_start; + uint32_t _app_irom_size = (uint32_t)&_image_irom_size; + uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; + + uint32_t _app_drom_start = _partition_offset + + (uint32_t)&_image_drom_start; + uint32_t _app_drom_size = (uint32_t)&_image_drom_size; + uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; + + Cache_Read_Disable(0); + Cache_Flush(0); + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ + for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) { + DPORT_PRO_FLASH_MMU_TABLE[i] = + DPORT_FLASH_MMU_TABLE_INVALID_VAL; + } + + uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK; + uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, + _app_drom_vaddr); + rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start + & MMU_FLASH_MASK, 64, drom_page_count); + rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start + & MMU_FLASH_MASK, 64, drom_page_count); + + uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK; + uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, + _app_irom_vaddr); + rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start + & MMU_FLASH_MASK, 64, irom_page_count); + rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start + & MMU_FLASH_MASK, 64, irom_page_count); + + DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, + (DPORT_PRO_CACHE_MASK_IRAM0) | + (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | + (DPORT_PRO_CACHE_MASK_IROM0 & 0) | + DPORT_PRO_CACHE_MASK_DROM0 | + DPORT_PRO_CACHE_MASK_DRAM1); + + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, + (DPORT_APP_CACHE_MASK_IRAM0) | + (DPORT_APP_CACHE_MASK_IRAM1 & 0) | + (DPORT_APP_CACHE_MASK_IROM0 & 0) | + DPORT_APP_CACHE_MASK_DROM0 | + DPORT_APP_CACHE_MASK_DRAM1); + + esp_rom_Cache_Read_Enable(0); + return rc; +} +#endif + +void __start(void) +{ +#ifdef CONFIG_BOOTLOADER_MCUBOOT + int err = map_rom_segments(); + + if (err != 0) { + ets_printf("Failed to setup XIP, aborting\n"); + abort(); + } +#endif + __esp_platform_start(); +} diff --git a/soc/xtensa/esp32s3/newlib_fix.c b/soc/xtensa/esp32s3/newlib_fix.c new file mode 100644 index 0000000000000..b0a0efcc4e60c --- /dev/null +++ b/soc/xtensa/esp32s3/newlib_fix.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include + +int __weak _gettimeofday_r(struct _reent *r, struct timeval *__tp, void *__tzp) +{ + ARG_UNUSED(r); + ARG_UNUSED(__tp); + ARG_UNUSED(__tzp); + + return -1; +} diff --git a/soc/xtensa/esp32s3/pinctrl_soc.h b/soc/xtensa/esp32s3/pinctrl_soc.h new file mode 100644 index 0000000000000..d5b846065085d --- /dev/null +++ b/soc/xtensa/esp32s3/pinctrl_soc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * ESP32S3 SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_ + +#include +#include + +#include + +/** @cond INTERNAL_HIDDEN */ + +/** Type for ESP32 pin. */ +struct pinctrl_soc_pin { + /** Pinmux settings (pin, direction and signal). */ + uint32_t pinmux; + /** Pincfg settings (bias). */ + uint32_t pincfg; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) \ + DT_PROP_BY_IDX(node_id, prop, idx) + +/** + * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \ + (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \ + ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \ + ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \ + ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT)) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { .pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \ + .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id) }, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +/** @endcond */ + +#endif /* ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_ */ diff --git a/soc/xtensa/esp32s3/soc.c b/soc/xtensa/esp32s3/soc.c new file mode 100644 index 0000000000000..21491600882a3 --- /dev/null +++ b/soc/xtensa/esp32s3/soc.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Include esp-idf headers first to avoid redefining BIT() macro */ +#include "soc.h" +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "esp_private/system_internal.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" +#include "soc/syscon_reg.h" +#include "hal/soc_ll.h" +#include "hal/wdt_hal.h" +#include "soc/cpu.h" +#include "soc/gpio_periph.h" +#include "esp_spi_flash.h" +#include "esp_err.h" +#include "esp_timer.h" +#include "esp_app_format.h" +#include "esp_clk_internal.h" +#include + +extern void z_cstart(void); +extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, + uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); +extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, + uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); +extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, + uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off); +extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); +extern int _rodata_reserved_start; +extern int _rodata_reserved_end; + +/* + * This is written in C rather than assembly since, during the port bring up, + * Zephyr is being booted by the Espressif bootloader. With it, the C stack + * is already set up. + */ +void IRAM_ATTR __esp_platform_start(void) +{ + extern uint32_t _init_start; + + /* Move the exception vector table to IRAM. */ + __asm__ __volatile__ ( + "wsr %0, vecbase" + : + : "r"(&_init_start)); + + z_bss_zero(); + + /* + * Configure the mode of instruction cache : + * cache size, cache associated ways, cache line size. + */ + rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, + CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); + + /* configure the mode of data: cache size, cache line size.*/ + Cache_Suspend_DCache(); + rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, + CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); + Cache_Resume_DCache(0); + + /* Configure the Cache MMU size for instruction and rodata in flash. */ + uint32_t rodata_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); + uint32_t cache_mmu_irom_size = ((rodata_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) + * sizeof(uint32_t); + uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_start_align + + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE) * sizeof(uint32_t); + + Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); + Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), + cache_mmu_drom_size / sizeof(uint32_t), (uint32_t)&_rodata_reserved_start, + (uint32_t)&_rodata_reserved_end, 0, 0); + +#if CONFIG_ESP32S3_DATA_CACHE_16KB + Cache_Invalidate_DCache_All(); + Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); +#endif + + /* Disable normal interrupts. */ + __asm__ __volatile__ ( + "wsr %0, PS" + : + : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + + /* Initialize the architecture CPU pointer. Some of the + * initialization code wants a valid _current before + * arch_kernel_init() is invoked. + */ + __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + + /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence + * related issues in application. Hence disable that as we are about to start + * Zephyr environment. + */ + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_feed(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + + esp_clk_init(); + + esp_timer_early_init(); + + esp_intr_initialize(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart_noos(); +} + +void IRAM_ATTR esp_restart_noos(void) +{ + /* disable interrupts */ + z_xt_ints_off(0xFFFFFFFF); + + /* enable RTC watchdog for 1 second */ + wdt_hal_context_t wdt_ctx; + uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); + + wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); + wdt_hal_write_protect_disable(&wdt_ctx); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + + /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ + wdt_hal_set_flashboot_en(&wdt_ctx, true); + wdt_hal_write_protect_enable(&wdt_ctx); + + /* disable TG0/TG1 watchdogs */ + wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; + + wdt_hal_write_protect_disable(&wdt0_context); + wdt_hal_disable(&wdt0_context); + wdt_hal_write_protect_enable(&wdt0_context); + + wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; + + wdt_hal_write_protect_disable(&wdt1_context); + wdt_hal_disable(&wdt1_context); + wdt_hal_write_protect_enable(&wdt1_context); + + /* Flush any data left in UART FIFOs */ + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + /* Disable cache */ + Cache_Disable_ICache(); + Cache_Disable_DCache(); + + const uint32_t core_id = cpu_hal_get_core_id(); +#if CONFIG_SMP + const uint32_t other_core_id = (core_id == 0) ? 1 : 0; + + soc_ll_reset_core(other_core_id); + soc_ll_stall_core(other_core_id); +#endif + + /* 2nd stage bootloader reconfigures SPI flash signals. */ + /* Reset them to the defaults expected by ROM */ + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ + SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | + SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | + SYSTEM_SDIO_HOST_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | + SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | + SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + /* Reset timer/spi/uart */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + + /* Reset DMA */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + + rtc_clk_cpu_freq_set_xtal(); + + /* Reset CPUs */ + if (core_id == 0) { + /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ + soc_ll_reset_core(1); + soc_ll_reset_core(0); + } else { + /* Running on APP CPU: need to reset PRO CPU and unstall it, */ + /* then reset APP CPU */ + soc_ll_reset_core(0); + soc_ll_stall_core(0); + soc_ll_reset_core(1); + } + + while (true) { + ; + } +} diff --git a/soc/xtensa/esp32s3/soc.h b/soc/xtensa/esp32s3/soc.h new file mode 100644 index 0000000000000..7643d2a027b1c --- /dev/null +++ b/soc/xtensa/esp32s3/soc.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SOC_H__ +#define __SOC_H__ +#include +#include +#include +#include +#include +#include "esp32s3/rom/cache.h" +#include +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" +#include "hal/cpu_hal.h" +#include "hal/cpu_types.h" +#include + +#include +#include +#include + +#include +#include + +void __esp_platform_start(void); + +static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr) +{ + sys_write32(sys_read32(mem_addr) | v, mem_addr); +} + +static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr) +{ + sys_write32(sys_read32(mem_addr) & ~v, mem_addr); +} + +static inline uint32_t esp_core_id(void) +{ + uint32_t id; + + __asm__ volatile ( + "rsr.prid %0\n" + "extui %0,%0,13,1" : "=r" (id)); + return id; +} + +extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, + bool inverted); +extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index, + bool out_inverted, + bool out_enabled_inverted); + +extern void esp_rom_uart_attach(void); +extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); +extern int esp_rom_uart_tx_one_char(uint8_t chr); +extern int esp_rom_uart_rx_one_char(uint8_t *chr); +extern void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate); + +extern void esp_rom_ets_set_appcpu_boot_addr(void *addr); +void esp_appcpu_start(void *entry_point); + +/* ROM functions which read/write internal i2c control bus for PLL, APLL */ +extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); +extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); + +#endif /* __SOC_H__ */ diff --git a/west.yml b/west.yml index e3f6f1afe878c..6c865dd36898c 100644 --- a/west.yml +++ b/west.yml @@ -57,7 +57,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 73e7af1e2ed64571ce49ff9f07dc02690b9f2df5 + revision: a06af2476671160f19e813c86570a17541f3b07e path: modules/hal/espressif west-commands: west/west-commands.yml groups: From c8344d4a5fd8444cba13995a9ca1906f0edead2c Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:16:46 -0300 Subject: [PATCH 3/7] kconfig: add esp32s3 into configuration Add ESP32-S3 information into Espressif's Kconfig definitions. Signed-off-by: Sylvio Alves --- Kconfig.zephyr | 2 +- modules/Kconfig.esp32 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index d40c011aa1c59..5164fdf2d1f0c 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -872,7 +872,7 @@ endif # BOOTLOADER_MCUBOOT config BOOTLOADER_ESP_IDF bool "ESP-IDF bootloader support" - depends on (SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3) && !BOOTLOADER_MCUBOOT + depends on (SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32S3) && !BOOTLOADER_MCUBOOT default y help This option will trigger the compilation of the ESP-IDF bootloader diff --git a/modules/Kconfig.esp32 b/modules/Kconfig.esp32 index 43095c24c96e9..8c432032a9fa1 100644 --- a/modules/Kconfig.esp32 +++ b/modules/Kconfig.esp32 @@ -3,4 +3,4 @@ config HAS_ESPRESSIF_HAL bool - depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32_NET + depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32_NET || SOC_ESP32S3 From 9638360f690b878d21e3b2725a18d5c04a98c7eb Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:19:02 -0300 Subject: [PATCH 4/7] clock: esp32s3: add peripheral initialization Update clock control source to enable proper ESP32S3 clock init. Signed-off-by: Sylvio Alves --- drivers/clock_control/clock_control_esp32.c | 108 +++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index cfe4fed89428f..d7bda543bb2b4 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -21,6 +21,12 @@ #include #include "esp32s2/rom/rtc.h" #include "soc/dport_reg.h" +#elif defined(CONFIG_SOC_ESP32S3) +#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 +#include +#include "esp32s3/rom/rtc.h" +#include "soc/dport_reg.h" +#include "esp32s3/clk.h" #elif CONFIG_IDF_TARGET_ESP32C3 #define DT_CPU_COMPAT espressif_riscv #include @@ -49,7 +55,7 @@ struct esp32_clock_config { }; static uint8_t const xtal_freq[] = { -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) +#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) || defined(CONFIG_SOC_ESP32S3) [ESP32_CLK_XTAL_24M] = 24, [ESP32_CLK_XTAL_26M] = 26, [ESP32_CLK_XTAL_40M] = 40, @@ -317,6 +323,106 @@ static void esp32_clock_perip_init(void) } #endif +#if defined(CONFIG_SOC_ESP32S3) +static void esp32_clock_perip_init(void) +{ + uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; + uint32_t common_perip_clk1 = 0; + + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + + /* For reason that only reset CPU, do not disable the clocks + * that have been enabled before reset. + */ + if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || + rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) { + common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); + hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); + wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); + } else { + common_perip_clk = SYSTEM_WDG_CLK_EN | + SYSTEM_I2S0_CLK_EN | + SYSTEM_UART1_CLK_EN | + SYSTEM_UART2_CLK_EN | + SYSTEM_USB_CLK_EN | + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_PCNT_CLK_EN | + SYSTEM_LEDC_CLK_EN | + SYSTEM_TIMERGROUP1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_PWM0_CLK_EN | + SYSTEM_TWAI_CLK_EN | + SYSTEM_PWM1_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN | + SYSTEM_PWM2_CLK_EN | + SYSTEM_PWM3_CLK_EN; + + common_perip_clk1 = 0; + + hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | + SYSTEM_CRYPTO_SHA_CLK_EN | + SYSTEM_CRYPTO_RSA_CLK_EN; + + wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | + SYSTEM_WIFI_CLK_BT_EN_M | + SYSTEM_WIFI_CLK_UNUSED_BIT5 | + SYSTEM_WIFI_CLK_UNUSED_BIT12 | + SYSTEM_WIFI_CLK_SDIO_HOST_EN; + } + + /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */ + common_perip_clk |= SYSTEM_I2S0_CLK_EN | + SYSTEM_UART1_CLK_EN | + SYSTEM_UART2_CLK_EN | + SYSTEM_USB_CLK_EN | + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_UHCI1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_I2C_EXT1_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN; + + common_perip_clk1 = 0; + + /* Disable some peripheral clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); + + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); + + /* Disable hardware crypto clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); + + /* Disable WiFi/BT/SDIO clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); + SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); + + /* Set WiFi light sleep clock source to RTC slow clock */ + REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); + CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); + SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); + + /* Enable RNG clock. */ + periph_module_enable(PERIPH_RNG_MODULE); + + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200); +} +#endif + #if defined(CONFIG_SOC_ESP32C3) static void esp32_clock_perip_init(void) { From 9482748584f2b118be46195a768b6e5f653f89dc Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:20:14 -0300 Subject: [PATCH 5/7] driver: uart: esp32s3: enable ESP32S3 uart interface Includes additional SoC specific headers. Signed-off-by: Sylvio Alves --- drivers/serial/uart_esp32.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index 8508512f89cb3..595f2e339f8f5 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -16,6 +16,9 @@ #include #include #include +#elif defined(CONFIG_SOC_ESP32S3) +#include +#include #elif defined(CONFIG_SOC_ESP32C3) #include #include From 066eab16b535b5832745b37ca7ee5980d2c4152e Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:20:51 -0300 Subject: [PATCH 6/7] drivers: interrupt: add esp32s3 interrupt controller Enables SoC specific interrupt controller. Signed-off-by: Sylvio Alves --- drivers/interrupt_controller/Kconfig.esp32 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index 1fb22c7c2f543..6080dcbc318e9 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32_NET + default y if SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32_NET || SOC_ESP32S3 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. From 7d54852e24e4a6c93ba8ce7b043039b22adf7e39 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 2 Jan 2023 09:21:52 -0300 Subject: [PATCH 7/7] boards: esp32s3_devkitm: initial soc board support Adds support to ESP32-S3 devkitm as initial SoC board. Signed-off-by: Sylvio Alves --- boards/xtensa/esp32s3_devkitm/Kconfig.board | 8 + .../xtensa/esp32s3_devkitm/Kconfig.defconfig | 8 + boards/xtensa/esp32s3_devkitm/board.cmake | 9 + boards/xtensa/esp32s3_devkitm/doc/index.rst | 175 ++++++++++++++++++ .../esp32s3_devkitm-pinctrl.dtsi | 21 +++ .../esp32s3_devkitm/esp32s3_devkitm.dts | 96 ++++++++++ .../esp32s3_devkitm/esp32s3_devkitm.yaml | 13 ++ .../esp32s3_devkitm/esp32s3_devkitm_defconfig | 14 ++ .../esp32s3_devkitm/support/openocd.cfg | 7 + tests/lib/heap/testcase.yaml | 2 +- 10 files changed, 352 insertions(+), 1 deletion(-) create mode 100644 boards/xtensa/esp32s3_devkitm/Kconfig.board create mode 100644 boards/xtensa/esp32s3_devkitm/Kconfig.defconfig create mode 100644 boards/xtensa/esp32s3_devkitm/board.cmake create mode 100644 boards/xtensa/esp32s3_devkitm/doc/index.rst create mode 100644 boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi create mode 100644 boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts create mode 100644 boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml create mode 100644 boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig create mode 100644 boards/xtensa/esp32s3_devkitm/support/openocd.cfg diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.board b/boards/xtensa/esp32s3_devkitm/Kconfig.board new file mode 100644 index 0000000000000..38d8db7a1127e --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/Kconfig.board @@ -0,0 +1,8 @@ +# ESP32S3 DevKitM board configuration + +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITM + bool "ESP32S3 DevKitM Board" + depends on SOC_ESP32S3 diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig b/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig new file mode 100644 index 0000000000000..b4e160532cd5a --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig @@ -0,0 +1,8 @@ +# ESP32S3 DevKitM board configuration + +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "esp32s3_devkitm" + depends on BOARD_ESP32S3_DEVKITM diff --git a/boards/xtensa/esp32s3_devkitm/board.cmake b/boards/xtensa/esp32s3_devkitm/board.cmake new file mode 100644 index 0000000000000..2f04d1fe8861e --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/xtensa/esp32s3_devkitm/doc/index.rst b/boards/xtensa/esp32s3_devkitm/doc/index.rst new file mode 100644 index 0000000000000..5d41114d16cac --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/doc/index.rst @@ -0,0 +1,175 @@ +.. _esp32s3_devkitm: + +ESP32S3-DevKitM +############### + +Overview +******** + +The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 +or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi +and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32-S3 DevKitM includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 45 programmable GPIOs +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x full-speed USB OTG +- 1x USB Serial/JTAG controller +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- Addressable RGB LED, driven by GPIO48. + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels +- 1x temperature sensor +- 14x touch sensing IOs + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +Current Zephyr's ESP32-S3-DevKitM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_devkitm`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_devkitm + +Debugging +--------- + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm + :goals: debug + +References +********** + +.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi new file mode 100644 index 0000000000000..5d0378d280950 --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts new file mode 100644 index 0000000000000..e052f090b2403 --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32s3_devkitm-pinctrl.dtsi" + +/ { + model = "esp32s3_devkitm"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + }; + + aliases { + uart-0 = &uart0; + sw0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml new file mode 100644 index 0000000000000..171b9bfd3eb06 --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml @@ -0,0 +1,13 @@ +identifier: esp32s3_devkitm +name: ESP32-S3 DevKitM +type: mcu +arch: xtensa +toolchain: + - espressif +supported: + - gpio + - uart +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig new file mode 100644 index 0000000000000..65acf1b660d0c --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XTENSA_RESET_VECTOR=n +CONFIG_BOARD_ESP32S3_DEVKITM=y +CONFIG_SOC_ESP32S3=y +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XTENSA_USE_CORE_CRT1=n +CONFIG_GPIO=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_devkitm/support/openocd.cfg b/boards/xtensa/esp32s3_devkitm/support/openocd.cfg new file mode 100644 index 0000000000000..2f740b4a36ab1 --- /dev/null +++ b/boards/xtensa/esp32s3_devkitm/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/tests/lib/heap/testcase.yaml b/tests/lib/heap/testcase.yaml index 3ae2f283f0a11..37ce33e2a4975 100644 --- a/tests/lib/heap/testcase.yaml +++ b/tests/lib/heap/testcase.yaml @@ -8,6 +8,6 @@ tests: libraries.heap: tags: heap - platform_exclude: m2gl025_miv qemu_xtensa esp32s2_saola + platform_exclude: m2gl025_miv qemu_xtensa esp32s2_saola esp32s3_devkitm filter: not CONFIG_SOC_NSIM timeout: 480