soc: esp32s3: added initial support

Kconfig.zephyr

@@ -872,7 +872,7 @@ endif # BOOTLOADER_MCUBOOT
 
 config BOOTLOADER_ESP_IDF
 	bool "ESP-IDF bootloader support"
-	depends on (SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3) && !BOOTLOADER_MCUBOOT
+	depends on (SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32S3) && !BOOTLOADER_MCUBOOT
 	default y
 	help
 	  This option will trigger the compilation of the ESP-IDF bootloader

boards/xtensa/esp32s3_devkitm/Kconfig.board

@@ -0,0 +1,8 @@
+# ESP32S3 DevKitM board configuration
+
+# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ESP32S3_DEVKITM
+	bool "ESP32S3 DevKitM Board"
+	depends on SOC_ESP32S3

boards/xtensa/esp32s3_devkitm/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# ESP32S3 DevKitM board configuration
+
+# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD
+	default "esp32s3_devkitm"
+	depends on BOARD_ESP32S3_DEVKITM

boards/xtensa/esp32s3_devkitm/board.cmake

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/xtensa/esp32s3_devkitm/doc/index.rst

@@ -0,0 +1,175 @@
+.. _esp32s3_devkitm:
+
+ESP32S3-DevKitM
+###############
+
+Overview
+********
+
+The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1
+or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi
+and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_
+
+Hardware
+********
+
+ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
+and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
+(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
+RF module, and numerous peripherals.
+
+ESP32-S3 DevKitM includes the following features:
+
+- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
+- Additional vector instructions support for AI acceleration
+- 512KB of SRAM
+- 384KB of ROM
+- Wi-Fi 802.11b/g/n
+- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate
+
+Digital interfaces:
+
+- 45 programmable GPIOs
+- 4x SPI
+- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411
+- 1x DVP 8-bit ~16-bit camera interface
+- 3x UART
+- 2x I2C
+- 2x I2S
+- 1x RMT (TX/RX)
+- 1x pulse counter
+- LED PWM controller, up to 8 channels
+- 1x full-speed USB OTG
+- 1x USB Serial/JTAG controller
+- 2x MCPWM
+- 1x SDIO host controller with 2 slots
+- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels
+- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
+- Addressable RGB LED, driven by GPIO48.
+
+Analog interfaces:
+
+- 2x 12-bit SAR ADCs, up to 20 channels
+- 1x temperature sensor
+- 14x touch sensing IOs
+
+Timers:
+
+- 4x 54-bit general-purpose timers
+- 1x 52-bit system timer
+- 3x watchdog timers
+
+Low Power:
+
+- Power Management Unit with five power modes
+- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM
+
+Security:
+
+- Secure boot
+- Flash encryption
+- 4-Kbit OTP, up to 1792 bits for users
+- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature)
+
+For more information, check the datasheet at `ESP32-S3 Datasheet`_.
+
+Supported Features
+==================
+
+Current Zephyr's ESP32-S3-DevKitM board supports the following features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
++------------+------------+-------------------------------------+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| USB-JTAG   | on-chip    | hardware interface                  |
++------------+------------+-------------------------------------+
+
+Prerequisites
+-------------
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+-------------------
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: esp32s3_devkitm
+   :goals: build
+
+The usual ``flash`` target will work with the ``esp32s3_devkitm`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: esp32s3_devkitm
+   :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! esp32s3_devkitm
+
+Debugging
+---------
+
+As with much custom hardware, the ESP32 modules require patches to
+OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
+the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
+``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
+parameter when building.
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: esp32s3_devkitm
+   :goals: build flash
+   :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
+
+You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: esp32s3_devkitm
+   :goals: debug
+
+References
+**********
+
+.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html
+.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf
+.. _`ESP32 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
+.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+};

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3.dtsi>
+#include "esp32s3_devkitm-pinctrl.dtsi"
+
+/ {
+	model = "esp32s3_devkitm";
+	compatible = "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		uart-0 = &uart0;
+		sw0 = &button0;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BOOT Button";
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <ESP32_CLK_CPU_240M>;
+};
+
+&cpu1 {
+	clock-frequency = <ESP32_CLK_CPU_240M>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&flash0 {
+	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserve 64kB for the bootloader */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x00010000>;
+			read-only;
+		};
+
+		/* Reserve 1024kB for the application in slot 0 */
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x00010000 0x00100000>;
+		};
+
+		/* Reserve 1024kB for the application in slot 1 */
+		slot1_partition: partition@110000 {
+			label = "image-1";
+			reg = <0x00110000 0x00100000>;
+		};
+
+		/* Reserve 256kB for the scratch partition */
+		scratch_partition: partition@210000 {
+			   label = "image-scratch";
+			   reg = <0x00210000 0x00040000>;
+		};
+
+		storage_partition: partition@250000 {
+			label = "storage";
+			reg = <0x00250000 0x00006000>;
+		};
+	};
+};

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml

@@ -0,0 +1,13 @@
+identifier: esp32s3_devkitm
+name: ESP32-S3 DevKitM
+type: mcu
+arch: xtensa
+toolchain:
+  - espressif
+supported:
+  - gpio
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XTENSA_RESET_VECTOR=n
+CONFIG_BOARD_ESP32S3_DEVKITM=y
+CONFIG_SOC_ESP32S3=y
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XTENSA_USE_CORE_CRT1=n
+CONFIG_GPIO=y
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+CONFIG_CLOCK_CONTROL=y

boards/xtensa/esp32s3_devkitm/support/openocd.cfg

@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]