diff --git a/CODEOWNERS b/CODEOWNERS index 81ae75325d9db..45f1c43719c4a 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -18,9 +18,9 @@ /MAINTAINERS.yml @MaureenHelm /arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev /arch/arm/ @MaureenHelm @galak @ioannisg -/arch/arm/core/aarch32/cortex_m/cmse/ @ioannisg -/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg -/arch/arm/core/aarch32/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio +/arch/arm/core/cortex_m/cmse/ @ioannisg +/arch/arm/include/cortex_m/cmse.h @ioannisg +/arch/arm/core/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio /arch/arm64/ @carlocaione /arch/arm64/core/cortex_r/ @povergoing /arch/arm64/core/xen/ @lorc @firscity @@ -655,11 +655,11 @@ /include/zephyr/arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev /include/zephyr/arch/arc/arch.h @abrodkin @ruuddw @evgeniy-paltsev /include/zephyr/arch/arc/v2/irq.h @abrodkin @ruuddw @evgeniy-paltsev -/include/zephyr/arch/arm/aarch32/ @MaureenHelm @galak @ioannisg -/include/zephyr/arch/arm/aarch32/cortex_a_r/ @stephanosio +/include/zephyr/arch/arm @MaureenHelm @galak @ioannisg +/include/zephyr/arch/arm/cortex_a_r/ @stephanosio /include/zephyr/arch/arm64/ @carlocaione /include/zephyr/arch/arm64/cortex_r/ @povergoing -/include/zephyr/arch/arm/aarch32/irq.h @carlocaione +/include/zephyr/arch/arm/irq.h @carlocaione /include/zephyr/arch/mips/ @frantony /include/zephyr/arch/nios2/ @nashif /include/zephyr/arch/nios2/arch.h @nashif diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 5a555645aa81c..0e3d96644c08d 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -141,7 +141,6 @@ ARM arch: files: - arch/arm/ - arch/arm/core/offsets/ - - include/zephyr/arch/arm/aarch32/ - include/zephyr/arch/arm/ - tests/arch/arm/ - doc/hardware/arch/arm_cortex_m.rst diff --git a/arch/arm/CMakeLists.txt b/arch/arm/CMakeLists.txt index 14c831b912079..5aa25f2039664 100644 --- a/arch/arm/CMakeLists.txt +++ b/arch/arm/CMakeLists.txt @@ -2,4 +2,4 @@ set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm) -add_subdirectory(core/aarch32) +add_subdirectory(core) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e17cf3f9b3100..da1878c740ca8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -69,7 +69,7 @@ config ARM_ON_EXIT_CPU_IDLE observed on some SoCs caused by a memory access following WFI/WFE instructions. -rsource "core/aarch32/Kconfig" -rsource "core/aarch32/Kconfig.vfp" +rsource "core/Kconfig" +rsource "core/Kconfig.vfp" endmenu diff --git a/arch/arm/core/aarch32/CMakeLists.txt b/arch/arm/core/CMakeLists.txt similarity index 81% rename from arch/arm/core/aarch32/CMakeLists.txt rename to arch/arm/core/CMakeLists.txt index 00bc7693cda09..11f22942c116a 100644 --- a/arch/arm/core/aarch32/CMakeLists.txt +++ b/arch/arm/core/CMakeLists.txt @@ -3,22 +3,14 @@ zephyr_library() zephyr_library_sources( - cpu_idle.S fatal.c - irq_manage.c nmi.c nmi_on_reset.S - prep_c.c - swap.c - swap_helper.S - thread.c ) -zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S) zephyr_library_sources_ifdef(CONFIG_CPP __aeabi_atexit.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) -zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S) -zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c) +zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_ARM_ZIMAGE_HEADER header.S) diff --git a/arch/arm/core/aarch32/Kconfig b/arch/arm/core/Kconfig similarity index 100% rename from arch/arm/core/aarch32/Kconfig rename to arch/arm/core/Kconfig diff --git a/arch/arm/core/aarch32/Kconfig.vfp b/arch/arm/core/Kconfig.vfp similarity index 100% rename from arch/arm/core/aarch32/Kconfig.vfp rename to arch/arm/core/Kconfig.vfp diff --git a/arch/arm/core/aarch32/__aeabi_atexit.c b/arch/arm/core/__aeabi_atexit.c similarity index 100% rename from arch/arm/core/aarch32/__aeabi_atexit.c rename to arch/arm/core/__aeabi_atexit.c diff --git a/arch/arm/core/aarch32/cortex_a_r/thread.c b/arch/arm/core/aarch32/cortex_a_r/thread.c deleted file mode 100644 index 736797f401144..0000000000000 --- a/arch/arm/core/aarch32/cortex_a_r/thread.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2021 Lexmark International, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -bool z_arm_thread_is_in_user_mode(void) -{ - uint32_t value; - - /* - * For Cortex-R, the mode (lower 5) bits will be 0x10 for user mode. - */ - value = __get_CPSR(); - return ((value & CPSR_M_Msk) == CPSR_M_USR); -} diff --git a/arch/arm/core/aarch32/cortex_m/thread.c b/arch/arm/core/aarch32/cortex_m/thread.c deleted file mode 100644 index 6ada938f6e1b9..0000000000000 --- a/arch/arm/core/aarch32/cortex_m/thread.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Lexmark International, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -bool z_arm_thread_is_in_user_mode(void) -{ - uint32_t value; - - /* return mode information */ - value = __get_CONTROL(); - return (value & CONTROL_nPRIV_Msk) != 0; -} diff --git a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt b/arch/arm/core/cortex_a_r/CMakeLists.txt similarity index 75% rename from arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt rename to arch/arm/core/cortex_a_r/CMakeLists.txt index c1cdc7e9c67b8..8b0dac374ee2b 100644 --- a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt +++ b/arch/arm/core/cortex_a_r/CMakeLists.txt @@ -12,8 +12,15 @@ zephyr_library_sources( stacks.c tcm.c vector_table.S + swap.c + swap_helper.S + irq_manage.c + prep_c.c + thread.c + cpu_idle.S ) +zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S) zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) diff --git a/arch/arm/core/aarch32/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/Kconfig rename to arch/arm/core/cortex_a_r/Kconfig diff --git a/arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S b/arch/arm/core/cortex_a_r/__aeabi_read_tp.S similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S rename to arch/arm/core/cortex_a_r/__aeabi_read_tp.S diff --git a/arch/arm/core/aarch32/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/cache.c rename to arch/arm/core/cortex_a_r/cache.c diff --git a/arch/arm/core/cortex_a_r/cpu_idle.S b/arch/arm/core/cortex_a_r/cpu_idle.S new file mode 100644 index 0000000000000..5c6ef3f12edf5 --- /dev/null +++ b/arch/arm/core/cortex_a_r/cpu_idle.S @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM Cortex-A and Cortex-R power management + * + */ + +#include +#include + +#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE) +#include +#endif + +_ASM_FILE_PROLOGUE + +GTEXT(arch_cpu_idle) +GTEXT(arch_cpu_atomic_idle) + +.macro _sleep_if_allowed wait_instruction +#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) + push {r0, lr} + bl z_arm_on_enter_cpu_idle + /* Skip the wait instruction if on_enter_cpu_idle() returns false. */ + cmp r0, #0 + beq _skip_\@ +#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ + + /* + * Wait for all memory transactions to complete before entering low + * power state. + */ + dsb + \wait_instruction + +#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE) + /* Inline the macro provided by SoC-specific code */ + SOC_ON_EXIT_CPU_IDLE +#endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */ + +#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) +_skip_\@: + pop {r0, lr} +#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ +.endm + +SECTION_FUNC(TEXT, arch_cpu_idle) +#ifdef CONFIG_TRACING + push {r0, lr} + bl sys_trace_idle + pop {r0, lr} +#endif /* CONFIG_TRACING */ + + /* Enter low power state */ + _sleep_if_allowed wfi + + /* + * Clear PRIMASK and flush instruction buffer to immediately service + * the wake-up interrupt. + */ + cpsie i + isb + + bx lr + +SECTION_FUNC(TEXT, arch_cpu_atomic_idle) +#ifdef CONFIG_TRACING + push {r0, lr} + bl sys_trace_idle + pop {r0, lr} +#endif /* CONFIG_TRACING */ + + /* + * Lock PRIMASK while sleeping: wfe will still get interrupted by + * incoming interrupts but the CPU will not service them right away. + */ + cpsid i + + /* r0: interrupt mask from caller */ + + /* No BASEPRI, call wfe directly + */ + _sleep_if_allowed wfe + + cmp r0, #0 + bne _irq_disabled + cpsie i +_irq_disabled: + + bx lr diff --git a/arch/arm/core/aarch32/cortex_a_r/exc.S b/arch/arm/core/cortex_a_r/exc.S similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/exc.S rename to arch/arm/core/cortex_a_r/exc.S diff --git a/arch/arm/core/aarch32/cortex_a_r/exc_exit.S b/arch/arm/core/cortex_a_r/exc_exit.S similarity index 98% rename from arch/arm/core/aarch32/cortex_a_r/exc_exit.S rename to arch/arm/core/cortex_a_r/exc_exit.S index 5706a39050047..67fc5fa6e00fd 100644 --- a/arch/arm/core/aarch32/cortex_a_r/exc_exit.S +++ b/arch/arm/core/cortex_a_r/exc_exit.S @@ -23,7 +23,7 @@ _ASM_FILE_PROLOGUE GTEXT(z_arm_exc_exit) GTEXT(z_arm_int_exit) -GTEXT(z_arm_pendsv) +GTEXT(z_arm_do_swap) GDATA(_kernel) .macro userspace_exc_exit @@ -148,7 +148,7 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit) ldr r1, [r3, #_kernel_offset_to_current] ldr r0, [r3, #_kernel_offset_to_ready_q_cache] cmp r0, r1 - blne z_arm_pendsv + blne z_arm_do_swap __EXIT_INT: #endif /* CONFIG_PREEMPT_ENABLED */ @@ -231,12 +231,12 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit) /* * Switch in the next scheduled thread. * - * Note that z_arm_pendsv must be called in the SVC mode because it + * Note that z_arm_do_swap must be called in the SVC mode because it * switches to the SVC mode during context switch and returns to the * caller using lr_svc. */ cps #MODE_SVC - bl z_arm_pendsv + bl z_arm_do_swap /* Decrement exception nesting count */ ldr r3, =_kernel diff --git a/arch/arm/core/aarch32/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/fault.c rename to arch/arm/core/cortex_a_r/fault.c diff --git a/arch/arm/core/aarch32/cortex_a_r/irq_init.c b/arch/arm/core/cortex_a_r/irq_init.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/irq_init.c rename to arch/arm/core/cortex_a_r/irq_init.c diff --git a/arch/arm/core/cortex_a_r/irq_manage.c b/arch/arm/core/cortex_a_r/irq_manage.c new file mode 100644 index 0000000000000..a381fad2a4871 --- /dev/null +++ b/arch/arm/core/cortex_a_r/irq_manage.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM Cortex-A and Cortex-R interrupt management + * + * + * Interrupt management: enabling/disabling and dynamic ISR + * connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for + * connecting ISRs at runtime. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void z_arm_reserved(void); + +/* + * For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM + * Generic Interrupt Controller (GIC) and therefore the architecture interrupt + * control functions are mapped to the GIC driver interface. + * + * When a custom interrupt controller is used (i.e. + * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture + * interrupt control functions are mapped to the SoC layer in + * `include/arch/arm/irq.h`. + */ + +#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) +void arch_irq_enable(unsigned int irq) +{ + arm_gic_irq_enable(irq); +} + +void arch_irq_disable(unsigned int irq) +{ + arm_gic_irq_disable(irq); +} + +int arch_irq_is_enabled(unsigned int irq) +{ + return arm_gic_irq_is_enabled(irq); +} + +/** + * @internal + * + * @brief Set an interrupt's priority + * + * The priority is verified if ASSERT_ON is enabled. The maximum number + * of priority levels is a little complex, as there are some hardware + * priority levels which are reserved: three for various types of exceptions, + * and possibly one additional to support zero latency interrupts. + */ +void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +{ + arm_gic_irq_set_priority(irq, prio, flags); +} +#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ + +void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); + +/** + * + * @brief Spurious interrupt handler + * + * Installed in all _sw_isr_table slots at boot time. Throws an error if + * called. + * + */ +void z_irq_spurious(const void *unused) +{ + ARG_UNUSED(unused); + + z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); +} + +#ifdef CONFIG_PM +void _arch_isr_direct_pm(void) +{ + unsigned int key; + + /* irq_lock() does what we want for this CPU */ + key = irq_lock(); + + if (_kernel.idle) { + _kernel.idle = 0; + z_pm_save_idle_exit(); + } + + irq_unlock(key); +} +#endif + +#ifdef CONFIG_DYNAMIC_INTERRUPTS +#ifdef CONFIG_GEN_ISR_TABLES +int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, + void (*routine)(const void *parameter), + const void *parameter, uint32_t flags) +{ + z_isr_install(irq, routine, parameter); + z_arm_irq_priority_set(irq, priority, flags); + return irq; +} +#endif /* CONFIG_GEN_ISR_TABLES */ + +#ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS +static inline void z_arm_irq_dynamic_direct_isr_dispatch(void) +{ + uint32_t irq = __get_IPSR() - 16; + + if (irq < IRQ_TABLE_SIZE) { + struct _isr_table_entry *isr_entry = &_sw_isr_table[irq]; + + isr_entry->isr(isr_entry->arg); + } +} + +ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule) +{ + z_arm_irq_dynamic_direct_isr_dispatch(); + + return 1; +} + +ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule) +{ + z_arm_irq_dynamic_direct_isr_dispatch(); + + return 0; +} + +#endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */ + +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/arm/core/aarch32/isr_wrapper.S b/arch/arm/core/cortex_a_r/isr_wrapper.S similarity index 70% rename from arch/arm/core/aarch32/isr_wrapper.S rename to arch/arm/core/cortex_a_r/isr_wrapper.S index 205420c5dcc2d..dc5fa9cac0487 100644 --- a/arch/arm/core/aarch32/isr_wrapper.S +++ b/arch/arm/core/cortex_a_r/isr_wrapper.S @@ -7,7 +7,7 @@ /** * @file - * @brief ARM Cortex-A, Cortex-M and Cortex-R wrapper for ISRs with parameter + * @brief ARM Cortex-A and Cortex-R wrapper for ISRs with parameter * * Wrapper installed in vector table for handling dynamic interrupts that accept * a parameter. @@ -45,10 +45,6 @@ GTEXT(z_arm_int_exit) */ SECTION_FUNC(TEXT, _isr_wrapper) -#if defined(CONFIG_CPU_CORTEX_M) - push {r0,lr} /* r0, lr are now the first items on the stack */ -#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) - #if defined(CONFIG_USERSPACE) /* See comment below about svc stack usage */ cps #MODE_SVC @@ -147,7 +143,6 @@ _vfp_not_enabled: ldr r0, [r2, #_kernel_offset_to_nested] add r0, r0, #1 str r0, [r2, #_kernel_offset_to_nested] -#endif /* CONFIG_CPU_CORTEX_M */ #ifdef CONFIG_TRACING_ISR bl sys_trace_isr_enter @@ -163,65 +158,21 @@ _vfp_not_enabled: * is called with interrupts disabled. */ -#if defined(CONFIG_CPU_CORTEX_M) - /* - * Disable interrupts to prevent nesting while exiting idle state. This - * is only necessary for the Cortex-M because it is the only ARM - * architecture variant that automatically enables interrupts when - * entering an ISR. - */ - cpsid i /* PRIMASK = 1 */ -#endif - /* is this a wakeup from idle ? */ ldr r2, =_kernel /* requested idle duration, in ticks */ ldr r0, [r2, #_kernel_offset_to_idle] cmp r0, #0 -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - beq _idle_state_cleared - movs.n r1, #0 - /* clear kernel idle state */ - str r1, [r2, #_kernel_offset_to_idle] - bl z_pm_save_idle_exit -_idle_state_cleared: - -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - ittt ne - movne r1, #0 - /* clear kernel idle state */ - strne r1, [r2, #_kernel_offset_to_idle] - blne z_pm_save_idle_exit -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) beq _idle_state_cleared movs r1, #0 /* clear kernel idle state */ str r1, [r2, #_kernel_offset_to_idle] bl z_pm_save_idle_exit _idle_state_cleared: -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ - -#if defined(CONFIG_CPU_CORTEX_M) - cpsie i /* re-enable interrupts (PRIMASK = 0) */ -#endif #endif /* CONFIG_PM */ -#if defined(CONFIG_CPU_CORTEX_M) - mrs r0, IPSR /* get exception number */ -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - ldr r1, =16 - subs r0, r1 /* get IRQ number */ - lsls r0, #3 /* table is 8-byte wide */ -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - sub r0, r0, #16 /* get IRQ number */ - lsl r0, r0, #3 /* table is 8-byte wide */ -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ -#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) /* Get active IRQ number from the interrupt controller */ #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) bl arm_gic_get_active @@ -230,11 +181,7 @@ _idle_state_cleared: #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ push {r0, r1} lsl r0, r0, #3 /* table is 8-byte wide */ -#else -#error Unknown ARM architecture -#endif /* CONFIG_CPU_CORTEX_M */ -#if !defined(CONFIG_CPU_CORTEX_M) /* * Enable interrupts to allow nesting. * @@ -254,7 +201,6 @@ _idle_state_cleared: lsl r1, r1, #3 cmp r0, r1 bge spurious_continue -#endif /* !CONFIG_CPU_CORTEX_M */ ldr r1, =_sw_isr_table add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay @@ -263,7 +209,6 @@ _idle_state_cleared: ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */ blx r3 /* call ISR */ -#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) spurious_continue: /* Signal end-of-interrupt */ pop {r0, r1} @@ -272,29 +217,11 @@ spurious_continue: #else bl z_soc_irq_eoi #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ -#endif /* CONFIG_CPU_AARCH32_CORTEX_R || CONFIG_CPU_AARCH32_CORTEX_A */ #ifdef CONFIG_TRACING_ISR bl sys_trace_isr_exit #endif -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - pop {r0, r3} - mov lr, r3 -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - pop {r0, lr} -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) - /* - * r0 and lr_irq were saved on the process stack since a swap could - * happen. exc_exit will handle getting those values back - * from the process stack to return to the correct location - * so there is no need to do anything here. - */ -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ - /* Use 'bx' instead of 'b' because 'bx' can jump further, and use * 'bx' instead of 'blx' because exception return is done in * z_arm_int_exit() */ diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c new file mode 100644 index 0000000000000..dc7786af59ee3 --- /dev/null +++ b/arch/arm/core/cortex_a_r/prep_c.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Full C support initialization + * + * + * Initialization of full C support: zero the .bss, copy the .data if XIP, + * call z_cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) +#include +#endif + +#if defined(__GNUC__) +/* + * GCC can detect if memcpy is passed a NULL argument, however one of + * the cases of relocate_vector_table() it is valid to pass NULL, so we + * suppress the warning for this case. We need to do this before + * string.h is included to get the declaration of memcpy. + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wnonnull" +#endif + +#include + +#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) +Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) +void *_vector_table_pointer; +#endif + +#if defined(CONFIG_AARCH32_ARMV8_R) + +#define VECTOR_ADDRESS ((uintptr_t)_vector_start) + +static inline void relocate_vector_table(void) +{ + write_sctlr(read_sctlr() & ~HIVECS); + write_vbar(VECTOR_ADDRESS & VBAR_MASK); + barrier_isync_fence_full(); +} + +#else +#define VECTOR_ADDRESS 0 + +void __weak relocate_vector_table(void) +{ +#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ + !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) + write_sctlr(read_sctlr() & ~HIVECS); + size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; + (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); +#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) + _vector_table_pointer = _vector_start; +#endif +} + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +#endif /* CONFIG_AARCH32_ARMV8_R */ + +#if defined(CONFIG_CPU_HAS_FPU) + +static inline void z_arm_floating_point_init(void) +{ +#if defined(CONFIG_FPU) + uint32_t reg_val = 0; + + /* + * CPACR : Coprocessor Access Control Register -> CP15 1/0/2 + * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, + * chap. B4.1.40 + * + * Must be accessed in >= PL1! + * [23..22] = CP11 access control bits, + * [21..20] = CP10 access control bits. + * 11b = Full access as defined for the respective CP, + * 10b = UNDEFINED, + * 01b = Access at PL1 only, + * 00b = No access. + */ + reg_val = __get_CPACR(); + /* Enable PL1 access to CP10, CP11 */ + reg_val |= (CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA)); + __set_CPACR(reg_val); + barrier_isync_fence_full(); + +#if !defined(CONFIG_FPU_SHARING) + /* + * FPEXC: Floating-Point Exception Control register + * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, + * chap. B6.1.38 + * + * Must be accessed in >= PL1! + * [31] EX bit = determines which registers comprise the current state + * of the FPU. The effects of setting this bit to 1 are + * subarchitecture defined. If EX=0, the following + * registers contain the complete current state + * information of the FPU and must therefore be saved + * during a context switch: + * * D0-D15 + * * D16-D31 if implemented + * * FPSCR + * * FPEXC. + * [30] EN bit = Advanced SIMD/Floating Point Extensions enable bit. + * [29..00] = Subarchitecture defined -> not relevant here. + */ + __set_FPEXC(FPEXC_EN); +#endif +#endif +} + +#endif /* CONFIG_CPU_HAS_FPU */ + +extern FUNC_NORETURN void z_cstart(void); + +/** + * + * @brief Prepare to and run C code + * + * This routine prepares for the execution of and runs C code. + * + */ +void z_arm_prep_c(void) +{ + relocate_vector_table(); +#if defined(CONFIG_CPU_HAS_FPU) + z_arm_floating_point_init(); +#endif + z_bss_zero(); + z_data_copy(); +#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS)) + z_arm_init_stacks(); +#endif + z_arm_interrupt_init(); + z_cstart(); + CODE_UNREACHABLE; +} diff --git a/arch/arm/core/aarch32/cortex_a_r/reboot.c b/arch/arm/core/cortex_a_r/reboot.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/reboot.c rename to arch/arm/core/cortex_a_r/reboot.c diff --git a/arch/arm/core/aarch32/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S similarity index 99% rename from arch/arm/core/aarch32/cortex_a_r/reset.S rename to arch/arm/core/cortex_a_r/reset.S index 32d1dc468df1d..c72f0814c7ab6 100644 --- a/arch/arm/core/aarch32/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include "vector_table.h" _ASM_FILE_PROLOGUE diff --git a/arch/arm/core/aarch32/cortex_a_r/semihost.c b/arch/arm/core/cortex_a_r/semihost.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/semihost.c rename to arch/arm/core/cortex_a_r/semihost.c diff --git a/arch/arm/core/aarch32/cortex_a_r/stacks.c b/arch/arm/core/cortex_a_r/stacks.c similarity index 96% rename from arch/arm/core/aarch32/cortex_a_r/stacks.c rename to arch/arm/core/cortex_a_r/stacks.c index 7f98deec9cb10..29a5062e29995 100644 --- a/arch/arm/core/aarch32/cortex_a_r/stacks.c +++ b/arch/arm/core/cortex_a_r/stacks.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include diff --git a/arch/arm/core/cortex_a_r/swap.c b/arch/arm/core/cortex_a_r/swap.c new file mode 100644 index 0000000000000..258999be7c796 --- /dev/null +++ b/arch/arm/core/cortex_a_r/swap.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 Linaro, Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +extern const int _k_neg_eagain; + +/* The 'key' actually represents the BASEPRI register + * prior to disabling interrupts via the BASEPRI mechanism. + * + * arch_swap() itself does not do much. + */ +int arch_swap(unsigned int key) +{ + /* store off key and return value */ + _current->arch.basepri = key; + _current->arch.swap_return_value = _k_neg_eagain; + + z_arm_cortex_r_svc(); + irq_unlock(key); + + /* Context switch is performed here. Returning implies the + * thread has been context-switched-in again. + */ + return _current->arch.swap_return_value; +} diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S new file mode 100644 index 0000000000000..c646e70cc7e58 --- /dev/null +++ b/arch/arm/core/cortex_a_r/swap_helper.S @@ -0,0 +1,427 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2017-2019 Nordic Semiconductor ASA. + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Thread context switching for ARM Cortex-A and Cortex-R + * + * This module implements the routines necessary for thread context switching + * on ARM Cortex-A and Cortex-R CPUs. + */ + +#include +#include +#include +#include +#include +#include + +_ASM_FILE_PROLOGUE + +GTEXT(z_arm_svc) +GTEXT(z_arm_do_swap) +GTEXT(z_do_kernel_oops) +#if defined(CONFIG_USERSPACE) +GTEXT(z_arm_do_syscall) +#endif + +GDATA(_kernel) + +/** + * + * @brief Routine to handle context switches + * + * For Cortex-R, this function is directly called either by z_arm_{exc,int}_exit + * in case of preemption, or z_arm_svc in case of cooperative switching. + */ + +SECTION_FUNC(TEXT, z_arm_do_swap) + +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + /* Register the context switch */ + push {r0, lr} + bl z_thread_mark_switched_out + pop {r0, lr} +#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */ + + /* load _kernel into r1 and current k_thread into r2 */ + ldr r1, =_kernel + ldr r2, [r1, #_kernel_offset_to_current] + +#if defined(CONFIG_ARM_STORE_EXC_RETURN) + /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */ + strb lr, [r2, #_thread_offset_to_mode_exc_return] +#endif + + /* addr of callee-saved regs in thread in r0 */ + ldr r0, =_thread_offset_to_callee_saved + add r0, r2 + + /* Store rest of process context */ + cps #MODE_SYS + stm r0, {r4-r11, sp} + cps #MODE_SVC + +#if defined(CONFIG_FPU_SHARING) + ldrb r0, [r2, #_thread_offset_to_user_options] + tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ + beq out_fp_inactive + + mov ip, #FPEXC_EN + vmsr fpexc, ip + + /* + * If the float context pointer is not null, then the VFP has not been + * used since this thread has used it. Consequently, the caller-saved + * float registers have not been saved away, so write them to the + * exception stack frame. + */ + ldr r0, [r1, #_kernel_offset_to_fp_ctx] + cmp r0, #0 + beq out_store_thread_context + + vstmia r0!, {s0-s15} +#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32 + vstmia r0!, {d16-d31} +#endif + vmrs r3, fpscr + stm r0, {r3, ip} + +out_store_thread_context: + /* Store s16-s31 to thread context */ + add r0, r2, #_thread_offset_to_preempt_float + vstmia r0, {s16-s31} + + mov ip, #0 + vmsr fpexc, ip + +out_fp_inactive: + /* + * The floating context has now been saved to the exception stack + * frame, so zero out the global pointer to note this. + */ + mov r0, #0 + str r0, [r1, #_kernel_offset_to_fp_ctx] +#endif /* CONFIG_FPU_SHARING */ + + /* fetch the thread to run from the ready queue cache */ + ldr r2, [r1, #_kernel_offset_to_ready_q_cache] + + str r2, [r1, #_kernel_offset_to_current] + +#if defined(CONFIG_THREAD_LOCAL_STORAGE) + /* Grab the TLS pointer */ + ldr r4, =_thread_offset_to_tls + adds r4, r2, r4 + ldr r0, [r4] + + /* Store TLS pointer in the "Process ID" register. + * This register is used as a base pointer to all + * thread variables with offsets added by toolchain. + */ + mcr 15, 0, r0, cr13, cr0, 3 +#endif + +#if defined(CONFIG_ARM_STORE_EXC_RETURN) + /* Restore EXC_RETURN value. */ + ldrsb lr, [r2, #_thread_offset_to_mode_exc_return] +#endif + + /* Restore previous interrupt disable state (irq_lock key) + * (We clear the arch.basepri field after restoring state) + */ + ldr r0, [r2, #_thread_offset_to_basepri] + movs r3, #0 + str r3, [r2, #_thread_offset_to_basepri] + +_thread_irq_disabled: + /* load _kernel into r1 and current k_thread into r2 */ + ldr r1, =_kernel + ldr r2, [r1, #_kernel_offset_to_current] + + /* addr of callee-saved regs in thread in r0 */ + ldr r0, =_thread_offset_to_callee_saved + add r0, r2 + + /* restore r4-r11 and sp for incoming thread */ + cps #MODE_SYS + ldm r0, {r4-r11, sp} + cps #MODE_SVC + +#if defined(CONFIG_FPU_SHARING) + ldrb r0, [r2, #_thread_offset_to_user_options] + tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ + beq in_fp_inactive + + mov r3, #FPEXC_EN + vmsr fpexc, r3 + + /* Restore s16-s31 from thread context */ + add r0, r2, #_thread_offset_to_preempt_float + vldmia r0, {s16-s31} + + mov r3, #0 + vmsr fpexc, r3 + +in_fp_inactive: +#endif /* CONFIG_FPU_SHARING */ + +#if defined (CONFIG_ARM_MPU) + /* r2 contains k_thread */ + mov r0, r2 + /* Re-program dynamic memory map */ + push {r2, lr} + bl z_arm_configure_dynamic_mpu_regions + pop {r2, lr} +#endif + +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + /* Register the context switch */ + push {r0, lr} + bl z_thread_mark_switched_in + pop {r0, lr} +#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */ + + /* + * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc) + */ + bx lr + +#if defined(CONFIG_FPU_SHARING) +#define FPU_SF_SIZE ___fpu_t_SIZEOF +#else +#define FPU_SF_SIZE 0 +#endif + +/** + * + * @brief Service call handler + * + * The service call (svc) is used in the following occasions: + * - Cooperative context switching + * - IRQ offloading + * - Kernel run-time exceptions + * + */ +SECTION_FUNC(TEXT, z_arm_svc) +#if defined(CONFIG_USERSPACE) + /* Determine if incoming thread was in user context */ + push {r0} + mrs r0, spsr + and r0, #MODE_MASK + cmp r0, #MODE_USR + bne svc_system_thread + + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + + /* Save away user stack pointer */ + cps #MODE_SYS + str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */ + + /* Switch to privileged stack */ + ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */ + cps #MODE_SVC + +svc_system_thread: + pop {r0} +#endif + + /* + * Switch to system mode to store r0-r3 to the process stack pointer. + * Save r12 and the lr as we could be swapping in another process and + * returning to a different location. + */ + srsdb #MODE_SYS! + cps #MODE_SYS + push {r0-r3, r12, lr} + +#if defined(CONFIG_FPU_SHARING) + sub sp, sp, #___fpu_t_SIZEOF + + /* + * Note that this handler was entered with the VFP unit enabled. + * The undefined instruction handler uses this to know that it + * needs to save the current floating context. + */ + vmrs r0, fpexc + str r0, [sp, #___fpu_t_SIZEOF - 4] + tst r0, #FPEXC_EN + beq _vfp_not_enabled + vmrs r0, fpscr + str r0, [sp, #___fpu_t_SIZEOF - 8] + + /* Disable VFP */ + mov r0, #0 + vmsr fpexc, r0 + +_vfp_not_enabled: + /* + * Mark where to store the floating context for the undefined + * instruction handler + */ + ldr r2, =_kernel + ldr r0, [r2, #_kernel_offset_to_fp_ctx] + cmp r0, #0 + streq sp, [r2, #_kernel_offset_to_fp_ctx] +#endif /* CONFIG_FPU_SHARING */ + + mov ip, sp + + cps #MODE_SVC + + /* + * Store lr_svc to the SVC mode stack. This value will be restored prior to + * exiting the SVC call in z_arm_int_exit. + */ + push {lr} + + /* Align stack at double-word boundary */ + and r3, sp, #4 + sub sp, sp, r3 + push {r2, r3} + + /* Increment interrupt nesting count */ + ldr r2, =_kernel + ldr r0, [r2, #_kernel_offset_to_nested] + add r0, r0, #1 + str r0, [r2, #_kernel_offset_to_nested] + + /* Get SVC number */ + mrs r0, spsr + tst r0, #0x20 + + ldreq r1, [lr, #-4] + biceq r1, #0xff000000 + beq demux + + ldr r1, [lr, #-2] + and r1, #0xff + + /* + * grab service call number: + * 0: context switch + * 1: irq_offload (if configured) + * 2: kernel panic or oops (software generated fatal exception) + * 3: system calls for memory protection + */ +demux: + +#if defined(CONFIG_USERSPACE) + cmp r1, #_SVC_CALL_SYSTEM_CALL + beq _do_syscall +#endif + + cmp r1, #_SVC_CALL_CONTEXT_SWITCH + beq _context_switch + + cmp r1, #_SVC_CALL_RUNTIME_EXCEPT + beq _oops + +#if CONFIG_IRQ_OFFLOAD + blx z_irq_do_offload /* call C routine which executes the offload */ + + /* exception return is done in z_arm_int_exit() */ + b z_arm_int_exit +#endif + +_context_switch: + /* handler mode exit, to PendSV */ + bl z_arm_do_swap + + b z_arm_int_exit + +_oops: + /* + * Pass the exception frame to z_do_kernel_oops. r0 contains the + * exception reason. + */ + cps #MODE_SYS + mov r0, sp + cps #MODE_SVC + bl z_do_kernel_oops + b z_arm_int_exit + +#if defined(CONFIG_USERSPACE) + /* + * System call will setup a jump to the _do_arm_syscall function + * running in system mode when returning from the exception. + * + * There is some trickery involved here because we have to preserve + * the original PC value so that we can return back to the caller of + * the SVC. + * + * On SVC exception, the USER/SYSTEM stack looks like the following: + * { possible FPU space } - r0 - r1 - r2 - r3 - r12 - LR - PC - SPSR + * + * Registers look like: + * r0 - arg1 + * r1 - arg2 + * r2 - arg3 + * r3 - arg4 + * r4 - arg5 + * r5 - arg6 + * r6 - call_id + * r8 - saved link register + */ +_do_syscall: + /* grab address of LR from stack frame */ + ldr r8, [ip, #(FPU_SF_SIZE + ___basic_sf_t_pc_OFFSET)] + + /* Make the exception return to system state */ + ldr r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_xpsr_OFFSET)] + + /* If leaving thumb mode, set the return address to thumb mode */ + tst r1, #T_BIT + orrne r8, #1 + + bic r1, #(MODE_MASK | T_BIT) + orr r1, r1, #MODE_SYS + str r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_xpsr_OFFSET)] + + /* + * Store the address of z_arm_do_syscall for the exit so the exception + * return goes there in system state. + */ + ldr r1, =z_arm_do_syscall + str r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_pc_OFFSET)] + + /* validate syscall limit, only set priv mode if valid */ + ldr ip, =K_SYSCALL_LIMIT + cmp r6, ip + blo valid_syscall_id + + /* bad syscall id. Set arg0 to bad id and set call_id to SYSCALL_BAD */ + cps #MODE_SYS + str r6, [sp] + cps #MODE_SVC + ldr r6, =K_SYSCALL_BAD + +valid_syscall_id: + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + ldr r1, [r0, #_thread_offset_to_mode] + bic r1, #1 + /* Store (privileged) mode in thread's mode state variable */ + str r1, [r0, #_thread_offset_to_mode] + dsb + + /* ISB is not strictly necessary here (stack pointer is not being + * touched), but it's recommended to avoid executing pre-fetched + * instructions with the previous privilege. + */ + isb + + /* Return to _arm_do_syscall in system state. */ + b z_arm_int_exit +#endif + +GTEXT(z_arm_cortex_r_svc) +SECTION_FUNC(TEXT, z_arm_cortex_r_svc) + svc #_SVC_CALL_CONTEXT_SWITCH + bx lr diff --git a/arch/arm/core/aarch32/cortex_a_r/tcm.c b/arch/arm/core/cortex_a_r/tcm.c similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/tcm.c rename to arch/arm/core/cortex_a_r/tcm.c diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c new file mode 100644 index 0000000000000..c5dbdc81ba623 --- /dev/null +++ b/arch/arm/core/cortex_a_r/thread.c @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2021 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief New thread creation for ARM Cortex-A and Cortex-R + * + * Core thread related primitives for the ARM Cortex-A and + * Cortex-R processor architecture. + */ + +#include +#include +#include +#include +#include + +#if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE) +#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \ + MPU_GUARD_ALIGN_AND_SIZE) +#else +#define FP_GUARD_EXTRA_SIZE 0 +#endif + +#ifndef EXC_RETURN_FTYPE +/* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_FTYPE (0x00000010UL) +#endif + +/* Default last octet of EXC_RETURN, for threads that have not run yet. + * The full EXC_RETURN value will be e.g. 0xFFFFFFBC. + */ +#define DEFAULT_EXC_RETURN 0xFD; + +/* An initial context, to be "restored" by z_arm_pendsv(), is put at the other + * end of the stack, and thus reusable by the stack when not needed anymore. + * + * The initial context is an exception stack frame (ESF) since exiting the + * PendSV exception will want to pop an ESF. Interestingly, even if the lsb of + * an instruction address to jump to must always be set since the CPU always + * runs in thumb mode, the ESF expects the real address of the instruction, + * with the lsb *not* set (instructions are always aligned on 16 bit + * halfwords). Since the compiler automatically sets the lsb of function + * addresses, we have to unset it manually before storing it in the 'pc' field + * of the ESF. + */ +void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, + char *stack_ptr, k_thread_entry_t entry, + void *p1, void *p2, void *p3) +{ + struct __basic_sf *iframe; + +#ifdef CONFIG_MPU_STACK_GUARD +#if defined(CONFIG_USERSPACE) + if (z_stack_is_user_capable(stack)) { + /* Guard area is carved-out of the buffer instead of reserved + * for stacks that can host user threads + */ + thread->stack_info.start += MPU_GUARD_ALIGN_AND_SIZE; + thread->stack_info.size -= MPU_GUARD_ALIGN_AND_SIZE; + } +#endif /* CONFIG_USERSPACE */ +#if FP_GUARD_EXTRA_SIZE > 0 + if ((thread->base.user_options & K_FP_REGS) != 0) { + /* Larger guard needed due to lazy stacking of FP regs may + * overshoot the guard area without writing anything. We + * carve it out of the stack buffer as-needed instead of + * unconditionally reserving it. + */ + thread->stack_info.start += FP_GUARD_EXTRA_SIZE; + thread->stack_info.size -= FP_GUARD_EXTRA_SIZE; + } +#endif /* FP_GUARD_EXTRA_SIZE */ +#endif /* CONFIG_MPU_STACK_GUARD */ + + iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr); +#if defined(CONFIG_USERSPACE) + if ((thread->base.user_options & K_USER) != 0) { + iframe->pc = (uint32_t)arch_user_mode_enter; + } else { + iframe->pc = (uint32_t)z_thread_entry; + } +#else + iframe->pc = (uint32_t)z_thread_entry; +#endif + + iframe->a1 = (uint32_t)entry; + iframe->a2 = (uint32_t)p1; + iframe->a3 = (uint32_t)p2; + iframe->a4 = (uint32_t)p3; + + iframe->xpsr = A_BIT | MODE_SYS; +#if defined(CONFIG_COMPILER_ISA_THUMB2) + iframe->xpsr |= T_BIT; +#endif /* CONFIG_COMPILER_ISA_THUMB2 */ + +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + iframe = (struct __basic_sf *) + ((uintptr_t)iframe - sizeof(struct __fpu_sf)); + memset(iframe, 0, sizeof(struct __fpu_sf)); +#endif + + thread->callee_saved.psp = (uint32_t)iframe; + thread->arch.basepri = 0; + +#if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE) + thread->arch.mode = 0; +#if defined(CONFIG_ARM_STORE_EXC_RETURN) + thread->arch.mode_exc_return = DEFAULT_EXC_RETURN; +#endif +#if FP_GUARD_EXTRA_SIZE > 0 + if ((thread->base.user_options & K_FP_REGS) != 0) { + thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk; + } +#endif +#if defined(CONFIG_USERSPACE) + thread->arch.priv_stack_start = 0; +#endif +#endif + /* + * initial values in all other registers/thread entries are + * irrelevant. + */ +} + +#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) \ + && defined(CONFIG_FPU_SHARING) + +static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, + bool use_large_guard) +{ + if (use_large_guard) { + /* Switch to use a large MPU guard if not already. */ + if ((thread->arch.mode & + Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) { + /* Default guard size is used. Update required. */ + thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk; +#if defined(CONFIG_USERSPACE) + if (thread->arch.priv_stack_start) { + /* User thread */ + thread->arch.priv_stack_start += + FP_GUARD_EXTRA_SIZE; + } else +#endif /* CONFIG_USERSPACE */ + { + /* Privileged thread */ + thread->stack_info.start += + FP_GUARD_EXTRA_SIZE; + thread->stack_info.size -= + FP_GUARD_EXTRA_SIZE; + } + } + } else { + /* Switch to use the default MPU guard size if not already. */ + if ((thread->arch.mode & + Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) { + /* Large guard size is used. Update required. */ + thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk; +#if defined(CONFIG_USERSPACE) + if (thread->arch.priv_stack_start) { + /* User thread */ + thread->arch.priv_stack_start -= + FP_GUARD_EXTRA_SIZE; + } else +#endif /* CONFIG_USERSPACE */ + { + /* Privileged thread */ + thread->stack_info.start -= + FP_GUARD_EXTRA_SIZE; + thread->stack_info.size += + FP_GUARD_EXTRA_SIZE; + } + } + } +} + +#endif + +#ifdef CONFIG_USERSPACE +FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, + void *p1, void *p2, void *p3) +{ + + /* Set up privileged stack before entering user mode */ + _current->arch.priv_stack_start = + (uint32_t)z_priv_stack_find(_current->stack_obj); +#if defined(CONFIG_MPU_STACK_GUARD) +#if defined(CONFIG_THREAD_STACK_INFO) + /* We're dropping to user mode which means the guard area is no + * longer used here, it instead is moved to the privilege stack + * to catch stack overflows there. Un-do the calculations done + * which accounted for memory borrowed from the thread stack. + */ +#if FP_GUARD_EXTRA_SIZE > 0 + if ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) { + _current->stack_info.start -= FP_GUARD_EXTRA_SIZE; + _current->stack_info.size += FP_GUARD_EXTRA_SIZE; + } +#endif /* FP_GUARD_EXTRA_SIZE */ + _current->stack_info.start -= MPU_GUARD_ALIGN_AND_SIZE; + _current->stack_info.size += MPU_GUARD_ALIGN_AND_SIZE; +#endif /* CONFIG_THREAD_STACK_INFO */ + + /* Stack guard area reserved at the bottom of the thread's + * privileged stack. Adjust the available (writable) stack + * buffer area accordingly. + */ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + _current->arch.priv_stack_start += + ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ? + MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE; +#else + _current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE; +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +#endif /* CONFIG_MPU_STACK_GUARD */ + +#if defined(CONFIG_CPU_AARCH32_CORTEX_R) + _current->arch.priv_stack_end = + _current->arch.priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE; +#endif + + z_arm_userspace_enter(user_entry, p1, p2, p3, + (uint32_t)_current->stack_info.start, + _current->stack_info.size - + _current->stack_info.delta); + CODE_UNREACHABLE; +} + +bool z_arm_thread_is_in_user_mode(void) +{ + uint32_t value; + + /* + * For Cortex-R, the mode (lower 5) bits will be 0x10 for user mode. + */ + value = __get_CPSR(); + return ((value & CPSR_M_Msk) == CPSR_M_USR); +} + +#endif + +#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) + +#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \ + ((fault_addr != -EINVAL) ? \ + ((fault_addr >= guard_start) && \ + (fault_addr < (guard_start + guard_len)) && \ + (stack_ptr < (guard_start + guard_len))) \ + : \ + (stack_ptr < (guard_start + guard_len))) + +/** + * @brief Assess occurrence of current thread's stack corruption + * + * This function performs an assessment whether a memory fault (on a + * given memory address) is the result of stack memory corruption of + * the current thread. + * + * Thread stack corruption for supervisor threads or user threads in + * privilege mode (when User Space is supported) is reported upon an + * attempt to access the stack guard area (if MPU Stack Guard feature + * is supported). Additionally the current PSP (process stack pointer) + * must be pointing inside or below the guard area. + * + * Thread stack corruption for user threads in user mode is reported, + * if the current PSP is pointing below the start of the current + * thread's stack. + * + * Notes: + * - we assume a fully descending stack, + * - we assume a stacking error has occurred, + * - the function shall be called when handling MemManage and Bus fault, + * and only if a Stacking error has been reported. + * + * If stack corruption is detected, the function returns the lowest + * allowed address where the Stack Pointer can safely point to, to + * prevent from errors when un-stacking the corrupted stack frame + * upon exception return. + * + * @param fault_addr memory address on which memory access violation + * has been reported. It can be invalid (-EINVAL), + * if only Stacking error has been reported. + * @param psp current address the PSP points to + * + * @return The lowest allowed stack frame pointer, if error is a + * thread stack corruption, otherwise return 0. + */ +uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp) +{ +#if defined(CONFIG_MULTITHREADING) + const struct k_thread *thread = _current; + + if (thread == NULL) { + return 0; + } +#endif + +#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \ + defined(CONFIG_MPU_STACK_GUARD) + uint32_t guard_len = + ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ? + MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE; +#else + /* If MPU_STACK_GUARD is not enabled, the guard length is + * effectively zero. Stack overflows may be detected only + * for user threads in nPRIV mode. + */ + uint32_t guard_len = MPU_GUARD_ALIGN_AND_SIZE; +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ + +#if defined(CONFIG_USERSPACE) + if (thread->arch.priv_stack_start) { + /* User thread */ + if (z_arm_thread_is_in_user_mode() == false) { + /* User thread in privilege mode */ + if (IS_MPU_GUARD_VIOLATION( + thread->arch.priv_stack_start - guard_len, + guard_len, + fault_addr, psp)) { + /* Thread's privilege stack corruption */ + return thread->arch.priv_stack_start; + } + } else { + if (psp < (uint32_t)thread->stack_obj) { + /* Thread's user stack corruption */ + return (uint32_t)thread->stack_obj; + } + } + } else { + /* Supervisor thread */ + if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - + guard_len, + guard_len, + fault_addr, psp)) { + /* Supervisor thread stack corruption */ + return thread->stack_info.start; + } + } +#else /* CONFIG_USERSPACE */ +#if defined(CONFIG_MULTITHREADING) + if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, + guard_len, + fault_addr, psp)) { + /* Thread stack corruption */ + return thread->stack_info.start; + } +#else + if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack, + guard_len, + fault_addr, psp)) { + /* Thread stack corruption */ + return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack); + } +#endif +#endif /* CONFIG_USERSPACE */ + + return 0; +} +#endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */ + +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) +int arch_float_disable(struct k_thread *thread) +{ + if (thread != _current) { + return -EINVAL; + } + + if (arch_is_in_isr()) { + return -EINVAL; + } + + /* Disable all floating point capabilities for the thread */ + + /* K_FP_REG flag is used in SWAP and stack check fail. Locking + * interrupts here prevents a possible context-switch or MPU + * fault to take an outdated thread user_options flag into + * account. + */ + int key = arch_irq_lock(); + + thread->base.user_options &= ~K_FP_REGS; + + __set_FPEXC(0); + + /* No need to add an ISB barrier after setting the CONTROL + * register; arch_irq_unlock() already adds one. + */ + + arch_irq_unlock(key); + + return 0; +} + +int arch_float_enable(struct k_thread *thread, unsigned int options) +{ + /* This is not supported in Cortex-A and Cortex-R */ + return -ENOTSUP; +} +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ diff --git a/arch/arm/core/aarch32/cortex_a_r/vector_table.S b/arch/arm/core/cortex_a_r/vector_table.S similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/vector_table.S rename to arch/arm/core/cortex_a_r/vector_table.S diff --git a/arch/arm/core/aarch32/cortex_a_r/vector_table.h b/arch/arm/core/cortex_a_r/vector_table.h similarity index 100% rename from arch/arm/core/aarch32/cortex_a_r/vector_table.h rename to arch/arm/core/cortex_a_r/vector_table.h diff --git a/arch/arm/core/aarch32/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt similarity index 87% rename from arch/arm/core/aarch32/cortex_m/CMakeLists.txt rename to arch/arm/core/cortex_m/CMakeLists.txt index 8d12299e9653e..7ec2441f12f01 100644 --- a/arch/arm/core/aarch32/cortex_m/CMakeLists.txt +++ b/arch/arm/core/cortex_m/CMakeLists.txt @@ -12,14 +12,21 @@ zephyr_library_sources( scb.c thread_abort.c vector_table.S + swap.c + swap_helper.S + irq_manage.c + prep_c.c + thread.c + cpu_idle.S ) -zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) +zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S) zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_PM_S2RAM pm_s2ram.c pm_s2ram.S) zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c) +zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S) if(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT) zephyr_library_sources(debug.c) diff --git a/arch/arm/core/aarch32/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig similarity index 100% rename from arch/arm/core/aarch32/cortex_m/Kconfig rename to arch/arm/core/cortex_m/Kconfig diff --git a/arch/arm/core/aarch32/cortex_m/__aeabi_read_tp.S b/arch/arm/core/cortex_m/__aeabi_read_tp.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/__aeabi_read_tp.S rename to arch/arm/core/cortex_m/__aeabi_read_tp.S diff --git a/arch/arm/core/aarch32/cortex_m/cache.c b/arch/arm/core/cortex_m/cache.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/cache.c rename to arch/arm/core/cortex_m/cache.c diff --git a/arch/arm/core/aarch32/cortex_m/cmse/CMakeLists.txt b/arch/arm/core/cortex_m/cmse/CMakeLists.txt similarity index 100% rename from arch/arm/core/aarch32/cortex_m/cmse/CMakeLists.txt rename to arch/arm/core/cortex_m/cmse/CMakeLists.txt diff --git a/arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c similarity index 99% rename from arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c rename to arch/arm/core/cortex_m/cmse/arm_core_cmse.c index 7ddab21d5477a..aac96472ecf4f 100644 --- a/arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c +++ b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c @@ -5,7 +5,7 @@ */ #include -#include +#include int arm_cmse_mpu_region_get(uint32_t addr) { diff --git a/arch/arm/core/aarch32/cortex_m/coredump.c b/arch/arm/core/cortex_m/coredump.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/coredump.c rename to arch/arm/core/cortex_m/coredump.c diff --git a/arch/arm/core/aarch32/cpu_idle.S b/arch/arm/core/cortex_m/cpu_idle.S similarity index 93% rename from arch/arm/core/aarch32/cpu_idle.S rename to arch/arm/core/cortex_m/cpu_idle.S index 8164959ab291f..d79ea4f0c1647 100644 --- a/arch/arm/core/aarch32/cpu_idle.S +++ b/arch/arm/core/cortex_m/cpu_idle.S @@ -6,7 +6,7 @@ /** * @file - * @brief ARM Cortex-A, Cortex-M and Cortex-R power management + * @brief ARM Cortex-M power management * */ @@ -23,34 +23,12 @@ GTEXT(z_arm_cpu_idle_init) GTEXT(arch_cpu_idle) GTEXT(arch_cpu_atomic_idle) -#if defined(CONFIG_CPU_CORTEX_M) #define _SCB_SCR 0xE000ED10 #define _SCB_SCR_SEVONPEND (1 << 4) #define _SCB_SCR_SLEEPDEEP (1 << 2) #define _SCB_SCR_SLEEPONEXIT (1 << 1) #define _SCR_INIT_BITS _SCB_SCR_SEVONPEND -#endif - -/** - * - * @brief Initialization of CPU idle - * - * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's - * duration. - * - * C function prototype: - * - * void z_arm_cpu_idle_init(void); - */ - -SECTION_FUNC(TEXT, z_arm_cpu_idle_init) -#if defined(CONFIG_CPU_CORTEX_M) - ldr r1, =_SCB_SCR - movs.n r2, #_SCR_INIT_BITS - str r2, [r1] -#endif - bx lr .macro _sleep_if_allowed wait_instruction #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) @@ -84,6 +62,24 @@ _skip_\@: #endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ .endm +/** + * + * @brief Initialization of CPU idle + * + * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's + * duration. + * + * C function prototype: + * + * void z_arm_cpu_idle_init(void); + */ + +SECTION_FUNC(TEXT, z_arm_cpu_idle_init) + ldr r1, =_SCB_SCR + movs.n r2, #_SCR_INIT_BITS + str r2, [r1] + bx lr + SECTION_FUNC(TEXT, arch_cpu_idle) #ifdef CONFIG_TRACING push {r0, lr} @@ -162,10 +158,7 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle) /* r0: interrupt mask from caller */ -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) \ - || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) /* No BASEPRI, call wfe directly * (SEVONPEND is set in z_arm_cpu_idle_init()) */ diff --git a/arch/arm/core/aarch32/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c similarity index 99% rename from arch/arm/core/aarch32/cortex_m/debug.c rename to arch/arm/core/cortex_m/debug.c index 70394b2d361c7..8d83cd07f2fd0 100644 --- a/arch/arm/core/aarch32/cortex_m/debug.c +++ b/arch/arm/core/cortex_m/debug.c @@ -12,7 +12,7 @@ #include #include -#include +#include /** * @brief Assess whether a debug monitor event should be treated as an error diff --git a/arch/arm/core/aarch32/cortex_m/exc_exit.S b/arch/arm/core/cortex_m/exc_exit.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/exc_exit.S rename to arch/arm/core/cortex_m/exc_exit.S diff --git a/arch/arm/core/aarch32/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/fault.c rename to arch/arm/core/cortex_m/fault.c diff --git a/arch/arm/core/aarch32/cortex_m/fault_s.S b/arch/arm/core/cortex_m/fault_s.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/fault_s.S rename to arch/arm/core/cortex_m/fault_s.S diff --git a/arch/arm/core/aarch32/cortex_m/fpu.c b/arch/arm/core/cortex_m/fpu.c similarity index 96% rename from arch/arm/core/aarch32/cortex_m/fpu.c rename to arch/arm/core/cortex_m/fpu.c index 0e6084470e9fc..a9c964d14d1a7 100644 --- a/arch/arm/core/aarch32/cortex_m/fpu.c +++ b/arch/arm/core/cortex_m/fpu.c @@ -7,7 +7,7 @@ #include #include -#include +#include /** * @file @brief Helper functions for saving and restoring the FP context. diff --git a/arch/arm/core/aarch32/cortex_m/irq_init.c b/arch/arm/core/cortex_m/irq_init.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/irq_init.c rename to arch/arm/core/cortex_m/irq_init.c diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/cortex_m/irq_manage.c similarity index 78% rename from arch/arm/core/aarch32/irq_manage.c rename to arch/arm/core/cortex_m/irq_manage.c index 6ad5adf7cdab0..cd0c6f6e5bfb2 100644 --- a/arch/arm/core/aarch32/irq_manage.c +++ b/arch/arm/core/cortex_m/irq_manage.c @@ -6,7 +6,7 @@ /** * @file - * @brief ARM Cortex-A, Cortex-M and Cortex-R interrupt management + * @brief ARM Cortex-M interrupt management * * * Interrupt management: enabling/disabling and dynamic ISR @@ -16,12 +16,7 @@ #include #include -#if defined(CONFIG_CPU_CORTEX_M) #include -#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \ - || defined(CONFIG_CPU_AARCH32_CORTEX_R) -#include -#endif #include #include #include @@ -33,7 +28,6 @@ extern void z_arm_reserved(void); -#if defined(CONFIG_CPU_CORTEX_M) #define NUM_IRQS_PER_REG 32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) @@ -96,53 +90,6 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) NVIC_SetPriority((IRQn_Type)irq, prio); } -#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \ - || defined(CONFIG_CPU_AARCH32_CORTEX_R) -/* - * For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM - * Generic Interrupt Controller (GIC) and therefore the architecture interrupt - * control functions are mapped to the GIC driver interface. - * - * When a custom interrupt controller is used (i.e. - * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture - * interrupt control functions are mapped to the SoC layer in - * `include/arch/arm/aarch32/irq.h`. - */ - -#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) -void arch_irq_enable(unsigned int irq) -{ - arm_gic_irq_enable(irq); -} - -void arch_irq_disable(unsigned int irq) -{ - arm_gic_irq_disable(irq); -} - -int arch_irq_is_enabled(unsigned int irq) -{ - return arm_gic_irq_is_enabled(irq); -} - -/** - * @internal - * - * @brief Set an interrupt's priority - * - * The priority is verified if ASSERT_ON is enabled. The maximum number - * of priority levels is a little complex, as there are some hardware - * priority levels which are reserved: three for various types of exceptions, - * and possibly one additional to support zero latency interrupts. - */ -void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) -{ - arm_gic_irq_set_priority(irq, prio, flags); -} -#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ - -#endif /* CONFIG_CPU_CORTEX_M */ - void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); /** @@ -163,10 +110,7 @@ void z_irq_spurious(const void *unused) #ifdef CONFIG_PM void _arch_isr_direct_pm(void) { -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) \ - || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) unsigned int key; /* irq_lock() does what we want for this CPU */ @@ -174,7 +118,7 @@ void _arch_isr_direct_pm(void) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* Lock all interrupts. irq_lock() will on this CPU only disable those * lower than BASEPRI, which is not what we want. See comments in - * arch/arm/core/aarch32/isr_wrapper.S + * arch/arm/core/isr_wrapper.S */ __asm__ volatile("cpsid i" : : : "memory"); #else @@ -186,10 +130,7 @@ void _arch_isr_direct_pm(void) z_pm_save_idle_exit(); } -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) \ - || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) irq_unlock(key); #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) __asm__ volatile("cpsie i" : : : "memory"); diff --git a/arch/arm/core/aarch32/irq_relay.S b/arch/arm/core/cortex_m/irq_relay.S similarity index 100% rename from arch/arm/core/aarch32/irq_relay.S rename to arch/arm/core/cortex_m/irq_relay.S diff --git a/arch/arm/core/cortex_m/isr_wrapper.S b/arch/arm/core/cortex_m/isr_wrapper.S new file mode 100644 index 0000000000000..78ad6cd1e83a7 --- /dev/null +++ b/arch/arm/core/cortex_m/isr_wrapper.S @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2020 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM Cortex-M wrapper for ISRs with parameter + * + * Wrapper installed in vector table for handling dynamic interrupts that accept + * a parameter. + */ +/* + * Tell armclang that stack alignment are ensured. + */ +.eabi_attribute Tag_ABI_align_preserved, 1 + +#include +#include +#include +#include +#include + + +_ASM_FILE_PROLOGUE + +GDATA(_sw_isr_table) + +GTEXT(_isr_wrapper) +GTEXT(z_arm_int_exit) + +/** + * + * @brief Wrapper around ISRs when inserted in software ISR table + * + * When inserted in the vector table, _isr_wrapper() demuxes the ISR table + * using the running interrupt number as the index, and invokes the registered + * ISR with its corresponding argument. When returning from the ISR, it + * determines if a context switch needs to happen (see documentation for + * z_arm_pendsv()) and pends the PendSV exception if so: the latter will + * perform the context switch itself. + * + */ +SECTION_FUNC(TEXT, _isr_wrapper) + + push {r0,lr} /* r0, lr are now the first items on the stack */ + +#ifdef CONFIG_TRACING_ISR + bl sys_trace_isr_enter +#endif + +#ifdef CONFIG_PM + /* + * All interrupts are disabled when handling idle wakeup. For tickless + * idle, this ensures that the calculation and programming of the + * device for the next timer deadline is not interrupted. For + * non-tickless idle, this ensures that the clearing of the kernel idle + * state is not interrupted. In each case, z_pm_save_idle_exit + * is called with interrupts disabled. + */ + + /* + * Disable interrupts to prevent nesting while exiting idle state. This + * is only necessary for the Cortex-M because it is the only ARM + * architecture variant that automatically enables interrupts when + * entering an ISR. + */ + cpsid i /* PRIMASK = 1 */ + + /* is this a wakeup from idle ? */ + ldr r2, =_kernel + /* requested idle duration, in ticks */ + ldr r0, [r2, #_kernel_offset_to_idle] + cmp r0, #0 + +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + beq _idle_state_cleared + movs.n r1, #0 + /* clear kernel idle state */ + str r1, [r2, #_kernel_offset_to_idle] + bl z_pm_save_idle_exit +_idle_state_cleared: + +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + ittt ne + movne r1, #0 + /* clear kernel idle state */ + strne r1, [r2, #_kernel_offset_to_idle] + blne z_pm_save_idle_exit +#else +#error Unknown ARM architecture +#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ + + cpsie i /* re-enable interrupts (PRIMASK = 0) */ + +#endif /* CONFIG_PM */ + + mrs r0, IPSR /* get exception number */ +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + ldr r1, =16 + subs r0, r1 /* get IRQ number */ + lsls r0, #3 /* table is 8-byte wide */ +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + sub r0, r0, #16 /* get IRQ number */ + lsl r0, r0, #3 /* table is 8-byte wide */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ + + ldr r1, =_sw_isr_table + add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay + * in thumb mode */ + + ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */ + blx r3 /* call ISR */ + +#ifdef CONFIG_TRACING_ISR + bl sys_trace_isr_exit +#endif + +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + pop {r0, r3} + mov lr, r3 +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + pop {r0, lr} +#else +#error Unknown ARM architecture +#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ + + /* Use 'bx' instead of 'b' because 'bx' can jump further, and use + * 'bx' instead of 'blx' because exception return is done in + * z_arm_int_exit() */ + ldr r1, =z_arm_int_exit + bx r1 diff --git a/arch/arm/core/aarch32/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/pm_s2ram.S rename to arch/arm/core/cortex_m/pm_s2ram.S diff --git a/arch/arm/core/aarch32/cortex_m/pm_s2ram.c b/arch/arm/core/cortex_m/pm_s2ram.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/pm_s2ram.c rename to arch/arm/core/cortex_m/pm_s2ram.c diff --git a/arch/arm/core/aarch32/prep_c.c b/arch/arm/core/cortex_m/prep_c.c similarity index 71% rename from arch/arm/core/aarch32/prep_c.c rename to arch/arm/core/cortex_m/prep_c.c index 80765dd7f4f7b..ad166775ca478 100644 --- a/arch/arm/core/aarch32/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -21,14 +21,6 @@ #include #include -#if !defined(CONFIG_CPU_CORTEX_M) -#include -#endif - -#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) -#include -#endif - #if defined(__GNUC__) /* * GCC can detect if memcpy is passed a NULL argument, however one of @@ -58,17 +50,6 @@ static inline void relocate_vector_table(void) barrier_isync_fence_full(); } -#elif defined(CONFIG_AARCH32_ARMV8_R) - -#define VECTOR_ADDRESS ((uintptr_t)_vector_start) - -static inline void relocate_vector_table(void) -{ - write_sctlr(read_sctlr() & ~HIVECS); - write_vbar(VECTOR_ADDRESS & VBAR_MASK); - barrier_isync_fence_full(); -} - #else #define VECTOR_ADDRESS 0 @@ -76,9 +57,6 @@ void __weak relocate_vector_table(void) { #if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) -#if !defined(CONFIG_CPU_CORTEX_M) - write_sctlr(read_sctlr() & ~HIVECS); -#endif size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); #elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) @@ -93,7 +71,6 @@ void __weak relocate_vector_table(void) #endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */ #if defined(CONFIG_CPU_HAS_FPU) -#if defined(CONFIG_CPU_CORTEX_M) static inline void z_arm_floating_point_init(void) { /* @@ -191,58 +168,6 @@ static inline void z_arm_floating_point_init(void) #endif } -#else - -static inline void z_arm_floating_point_init(void) -{ -#if defined(CONFIG_FPU) - uint32_t reg_val = 0; - - /* - * CPACR : Coprocessor Access Control Register -> CP15 1/0/2 - * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, - * chap. B4.1.40 - * - * Must be accessed in >= PL1! - * [23..22] = CP11 access control bits, - * [21..20] = CP10 access control bits. - * 11b = Full access as defined for the respective CP, - * 10b = UNDEFINED, - * 01b = Access at PL1 only, - * 00b = No access. - */ - reg_val = __get_CPACR(); - /* Enable PL1 access to CP10, CP11 */ - reg_val |= (CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA)); - __set_CPACR(reg_val); - barrier_isync_fence_full(); - -#if !defined(CONFIG_FPU_SHARING) - /* - * FPEXC: Floating-Point Exception Control register - * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, - * chap. B6.1.38 - * - * Must be accessed in >= PL1! - * [31] EX bit = determines which registers comprise the current state - * of the FPU. The effects of setting this bit to 1 are - * subarchitecture defined. If EX=0, the following - * registers contain the complete current state - * information of the FPU and must therefore be saved - * during a context switch: - * * D0-D15 - * * D16-D31 if implemented - * * FPSCR - * * FPEXC. - * [30] EN bit = Advanced SIMD/Floating Point Extensions enable bit. - * [29..00] = Subarchitecture defined -> not relevant here. - */ - __set_FPEXC(FPEXC_EN); -#endif -#endif -} - -#endif /* CONFIG_CPU_CORTEX_M */ #endif /* CONFIG_CPU_HAS_FPU */ extern FUNC_NORETURN void z_cstart(void); @@ -262,9 +187,6 @@ void z_arm_prep_c(void) #endif z_bss_zero(); z_data_copy(); -#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS)) - z_arm_init_stacks(); -#endif z_arm_interrupt_init(); z_cstart(); CODE_UNREACHABLE; diff --git a/arch/arm/core/aarch32/cortex_m/relay_vector_table.ld b/arch/arm/core/cortex_m/relay_vector_table.ld similarity index 100% rename from arch/arm/core/aarch32/cortex_m/relay_vector_table.ld rename to arch/arm/core/cortex_m/relay_vector_table.ld diff --git a/arch/arm/core/aarch32/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/reset.S rename to arch/arm/core/cortex_m/reset.S diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/scb.c rename to arch/arm/core/cortex_m/scb.c diff --git a/arch/arm/core/aarch32/cortex_m/semihost.c b/arch/arm/core/cortex_m/semihost.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/semihost.c rename to arch/arm/core/cortex_m/semihost.c diff --git a/arch/arm/core/aarch32/swap.c b/arch/arm/core/cortex_m/swap.c similarity index 91% rename from arch/arm/core/aarch32/swap.c rename to arch/arm/core/cortex_m/swap.c index 525dc53671ef8..f41ae2e4e8466 100644 --- a/arch/arm/core/aarch32/swap.c +++ b/arch/arm/core/cortex_m/swap.c @@ -36,16 +36,11 @@ int arch_swap(unsigned int key) _current->arch.basepri = key; _current->arch.swap_return_value = _k_neg_eagain; -#if defined(CONFIG_CPU_CORTEX_M) /* set pending bit to make sure we will take a PendSV exception */ SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; /* clear mask or enable all irqs to take a pendsv */ irq_unlock(0); -#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) - z_arm_cortex_r_svc(); - irq_unlock(key); -#endif /* Context switch is performed here. Returning implies the * thread has been context-switched-in again. diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S similarity index 61% rename from arch/arm/core/aarch32/swap_helper.S rename to arch/arm/core/cortex_m/swap_helper.S index d125e0d740c93..af1d0d791dd30 100644 --- a/arch/arm/core/aarch32/swap_helper.S +++ b/arch/arm/core/cortex_m/swap_helper.S @@ -8,10 +8,10 @@ /** * @file - * @brief Thread context switching for ARM Cortex-M and Cortex-R + * @brief Thread context switching for ARM Cortex-M * * This module implements the routines necessary for thread context switching - * on ARM Cortex-A, Cortex-M and Cortex-R CPUs. + * on ARM Cortex-M CPUs. */ #include @@ -21,9 +21,7 @@ #include #include -#if defined(CONFIG_CPU_CORTEX_M) -#include -#endif +#include _ASM_FILE_PROLOGUE GTEXT(z_arm_svc) @@ -35,7 +33,7 @@ GTEXT(z_arm_do_syscall) GDATA(_kernel) -#if defined(CONFIG_THREAD_LOCAL_STORAGE) && defined(CONFIG_CPU_CORTEX_M) +#if defined(CONFIG_THREAD_LOCAL_STORAGE) GDATA(z_arm_tls_ptr) #endif @@ -52,10 +50,6 @@ GDATA(z_arm_tls_ptr) * have to swap *something*. * * For Cortex-M, z_arm_pendsv() is invoked with no arguments. - * - * For Cortex-R, PendSV exception is not supported by the architecture and this - * function is directly called either by z_arm_{exc,int}_exit in case of - * preemption, or z_arm_svc in case of cooperative switching. */ SECTION_FUNC(TEXT, z_arm_pendsv) @@ -86,9 +80,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv) add r0, r2 /* save callee-saved + psp in thread */ -#if defined(CONFIG_CPU_CORTEX_M) mrs ip, PSP -#endif #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) /* Store current r4-r7 */ @@ -121,54 +113,6 @@ out_fp_endif: * regardless of whether the thread has an active FP context. */ #endif /* CONFIG_FPU_SHARING */ -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) - /* Store rest of process context */ - cps #MODE_SYS - stm r0, {r4-r11, sp} - cps #MODE_SVC - -#if defined(CONFIG_FPU_SHARING) - ldrb r0, [r2, #_thread_offset_to_user_options] - tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ - beq out_fp_inactive - - mov ip, #FPEXC_EN - vmsr fpexc, ip - - /* - * If the float context pointer is not null, then the VFP has not been - * used since this thread has used it. Consequently, the caller-saved - * float registers have not been saved away, so write them to the - * exception stack frame. - */ - ldr r0, [r1, #_kernel_offset_to_fp_ctx] - cmp r0, #0 - beq out_store_thread_context - - vstmia r0!, {s0-s15} -#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32 - vstmia r0!, {d16-d31} -#endif - vmrs r3, fpscr - stm r0, {r3, ip} - -out_store_thread_context: - /* Store s16-s31 to thread context */ - add r0, r2, #_thread_offset_to_preempt_float - vstmia r0, {s16-s31} - - mov ip, #0 - vmsr fpexc, ip - -out_fp_inactive: - /* - * The floating context has now been saved to the exception stack - * frame, so zero out the global pointer to note this. - */ - mov r0, #0 - str r0, [r1, #_kernel_offset_to_fp_ctx] -#endif /* CONFIG_FPU_SHARING */ #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ @@ -180,12 +124,6 @@ out_fp_inactive: movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI_MAX, r0 isb /* Make the effect of disabling interrupts be realized immediately */ -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) - /* - * Interrupts are still disabled from arch_swap so empty clause - * here to avoid the preprocessor error below - */ #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ @@ -197,10 +135,8 @@ out_fp_inactive: * to pend PendSV have been taken with the current kernel * state and this is what we're handling currently. */ -#if defined(CONFIG_CPU_CORTEX_M) ldr v4, =_SCS_ICSR ldr v3, =_SCS_ICSR_UNPENDSV -#endif /* _kernel is still in r1 */ @@ -219,9 +155,7 @@ out_fp_inactive: */ /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */ -#if defined(CONFIG_CPU_CORTEX_M) str v3, [v4, #0] -#endif #if defined(CONFIG_THREAD_LOCAL_STORAGE) /* Grab the TLS pointer */ @@ -229,15 +163,6 @@ out_fp_inactive: adds r4, r2, r4 ldr r0, [r4] -#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) - /* Store TLS pointer in the "Process ID" register. - * This register is used as a base pointer to all - * thread variables with offsets added by toolchain. - */ - mcr 15, 0, r0, cr13, cr0, 3 -#endif - -#if defined(CONFIG_CPU_CORTEX_M) /* For Cortex-M, store TLS pointer in a global variable, * as it lacks the process ID or thread ID register * to be used by toolchain to access thread data. @@ -246,8 +171,6 @@ out_fp_inactive: str r0, [r4] #endif -#endif - #if defined(CONFIG_ARM_STORE_EXC_RETURN) /* Restore EXC_RETURN value. */ ldrsb lr, [r2, #_thread_offset_to_mode_exc_return] @@ -389,55 +312,11 @@ in_fp_endif: /* load callee-saved + psp from thread */ add r0, r2, #_thread_offset_to_callee_saved ldmia r0, {v1-v8, ip} -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) -_thread_irq_disabled: - /* load _kernel into r1 and current k_thread into r2 */ - ldr r1, =_kernel - ldr r2, [r1, #_kernel_offset_to_current] - - /* addr of callee-saved regs in thread in r0 */ - ldr r0, =_thread_offset_to_callee_saved - add r0, r2 - - /* restore r4-r11 and sp for incoming thread */ - cps #MODE_SYS - ldm r0, {r4-r11, sp} - cps #MODE_SVC - -#if defined(CONFIG_FPU_SHARING) - ldrb r0, [r2, #_thread_offset_to_user_options] - tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ - beq in_fp_inactive - - mov r3, #FPEXC_EN - vmsr fpexc, r3 - - /* Restore s16-s31 from thread context */ - add r0, r2, #_thread_offset_to_preempt_float - vldmia r0, {s16-s31} - - mov r3, #0 - vmsr fpexc, r3 - -in_fp_inactive: -#endif /* CONFIG_FPU_SHARING */ - -#if defined (CONFIG_ARM_MPU) - /* r2 contains k_thread */ - mov r0, r2 - /* Re-program dynamic memory map */ - push {r2, lr} - bl z_arm_configure_dynamic_mpu_regions - pop {r2, lr} -#endif #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ -#if defined(CONFIG_CPU_CORTEX_M) msr PSP, ip -#endif #ifdef CONFIG_BUILTIN_STACK_GUARD /* r2 contains k_thread */ @@ -461,13 +340,9 @@ in_fp_inactive: /* * Cortex-M: return from PendSV exception - * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc) */ bx lr -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \ - defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - /** * * @brief Service call handler @@ -686,244 +561,3 @@ valid_syscall_id: /* return from SVC to the modified LR - z_arm_do_syscall */ bx lr #endif /* CONFIG_USERSPACE */ - -#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) - -#if defined(CONFIG_FPU_SHARING) -#define FPU_SF_SIZE ___fpu_t_SIZEOF -#else -#define FPU_SF_SIZE 0 -#endif - -/** - * - * @brief Service call handler - * - * The service call (svc) is used in the following occasions: - * - Cooperative context switching - * - IRQ offloading - * - Kernel run-time exceptions - * - */ -SECTION_FUNC(TEXT, z_arm_svc) -#if defined(CONFIG_USERSPACE) - /* Determine if incoming thread was in user context */ - push {r0} - mrs r0, spsr - and r0, #MODE_MASK - cmp r0, #MODE_USR - bne svc_system_thread - - ldr r0, =_kernel - ldr r0, [r0, #_kernel_offset_to_current] - - /* Save away user stack pointer */ - cps #MODE_SYS - str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */ - - /* Switch to privileged stack */ - ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */ - cps #MODE_SVC - -svc_system_thread: - pop {r0} -#endif - - /* - * Switch to system mode to store r0-r3 to the process stack pointer. - * Save r12 and the lr as we could be swapping in another process and - * returning to a different location. - */ - srsdb #MODE_SYS! - cps #MODE_SYS - push {r0-r3, r12, lr} - -#if defined(CONFIG_FPU_SHARING) - sub sp, sp, #___fpu_t_SIZEOF - - /* - * Note that this handler was entered with the VFP unit enabled. - * The undefined instruction handler uses this to know that it - * needs to save the current floating context. - */ - vmrs r0, fpexc - str r0, [sp, #___fpu_t_SIZEOF - 4] - tst r0, #FPEXC_EN - beq _vfp_not_enabled - vmrs r0, fpscr - str r0, [sp, #___fpu_t_SIZEOF - 8] - - /* Disable VFP */ - mov r0, #0 - vmsr fpexc, r0 - -_vfp_not_enabled: - /* - * Mark where to store the floating context for the undefined - * instruction handler - */ - ldr r2, =_kernel - ldr r0, [r2, #_kernel_offset_to_fp_ctx] - cmp r0, #0 - streq sp, [r2, #_kernel_offset_to_fp_ctx] -#endif /* CONFIG_FPU_SHARING */ - - mov ip, sp - - cps #MODE_SVC - - /* - * Store lr_svc to the SVC mode stack. This value will be restored prior to - * exiting the SVC call in z_arm_int_exit. - */ - push {lr} - - /* Align stack at double-word boundary */ - and r3, sp, #4 - sub sp, sp, r3 - push {r2, r3} - - /* Increment interrupt nesting count */ - ldr r2, =_kernel - ldr r0, [r2, #_kernel_offset_to_nested] - add r0, r0, #1 - str r0, [r2, #_kernel_offset_to_nested] - - /* Get SVC number */ - mrs r0, spsr - tst r0, #0x20 - - ldreq r1, [lr, #-4] - biceq r1, #0xff000000 - beq demux - - ldr r1, [lr, #-2] - and r1, #0xff - - /* - * grab service call number: - * 0: context switch - * 1: irq_offload (if configured) - * 2: kernel panic or oops (software generated fatal exception) - * 3: system calls for memory protection - */ -demux: - -#if defined(CONFIG_USERSPACE) - cmp r1, #_SVC_CALL_SYSTEM_CALL - beq _do_syscall -#endif - - cmp r1, #_SVC_CALL_CONTEXT_SWITCH - beq _context_switch - - cmp r1, #_SVC_CALL_RUNTIME_EXCEPT - beq _oops - -#if CONFIG_IRQ_OFFLOAD - blx z_irq_do_offload /* call C routine which executes the offload */ - - /* exception return is done in z_arm_int_exit() */ - b z_arm_int_exit -#endif - -_context_switch: - /* handler mode exit, to PendSV */ - bl z_arm_pendsv - - b z_arm_int_exit - -_oops: - /* - * Pass the exception frame to z_do_kernel_oops. r0 contains the - * exception reason. - */ - cps #MODE_SYS - mov r0, sp - cps #MODE_SVC - bl z_do_kernel_oops - b z_arm_int_exit - -#if defined(CONFIG_USERSPACE) - /* - * System call will setup a jump to the _do_arm_syscall function - * running in system mode when returning from the exception. - * - * There is some trickery involved here because we have to preserve - * the original PC value so that we can return back to the caller of - * the SVC. - * - * On SVC exception, the USER/SYSTEM stack looks like the following: - * { possible FPU space } - r0 - r1 - r2 - r3 - r12 - LR - PC - SPSR - * - * Registers look like: - * r0 - arg1 - * r1 - arg2 - * r2 - arg3 - * r3 - arg4 - * r4 - arg5 - * r5 - arg6 - * r6 - call_id - * r8 - saved link register - */ -_do_syscall: - /* grab address of LR from stack frame */ - ldr r8, [ip, #(FPU_SF_SIZE + ___basic_sf_t_pc_OFFSET)] - - /* Make the exception return to system state */ - ldr r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_xpsr_OFFSET)] - - /* If leaving thumb mode, set the return address to thumb mode */ - tst r1, #T_BIT - orrne r8, #1 - - bic r1, #(MODE_MASK | T_BIT) - orr r1, r1, #MODE_SYS - str r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_xpsr_OFFSET)] - - /* - * Store the address of z_arm_do_syscall for the exit so the exception - * return goes there in system state. - */ - ldr r1, =z_arm_do_syscall - str r1, [ip, #(FPU_SF_SIZE + ___basic_sf_t_pc_OFFSET)] - - /* validate syscall limit, only set priv mode if valid */ - ldr ip, =K_SYSCALL_LIMIT - cmp r6, ip - blo valid_syscall_id - - /* bad syscall id. Set arg0 to bad id and set call_id to SYSCALL_BAD */ - cps #MODE_SYS - str r6, [sp] - cps #MODE_SVC - ldr r6, =K_SYSCALL_BAD - -valid_syscall_id: - ldr r0, =_kernel - ldr r0, [r0, #_kernel_offset_to_current] - ldr r1, [r0, #_thread_offset_to_mode] - bic r1, #1 - /* Store (privileged) mode in thread's mode state variable */ - str r1, [r0, #_thread_offset_to_mode] - dsb - - /* ISB is not strictly necessary here (stack pointer is not being - * touched), but it's recommended to avoid executing pre-fetched - * instructions with the previous privilege. - */ - isb - - /* Return to _arm_do_syscall in system state. */ - b z_arm_int_exit -#endif - -GTEXT(z_arm_cortex_r_svc) -SECTION_FUNC(TEXT, z_arm_cortex_r_svc) - svc #_SVC_CALL_CONTEXT_SWITCH - bx lr - -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ diff --git a/arch/arm/core/aarch32/thread.c b/arch/arm/core/cortex_m/thread.c similarity index 93% rename from arch/arm/core/aarch32/thread.c rename to arch/arm/core/cortex_m/thread.c index f09d809e91b80..0ada94e8b2788 100644 --- a/arch/arm/core/aarch32/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -1,20 +1,23 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2021 Lexmark International, Inc. * * SPDX-License-Identifier: Apache-2.0 */ /** * @file - * @brief New thread creation for ARM Cortex-A, Cortex-M and Cortex-R + * @brief New thread creation for ARM Cortex-M * - * Core thread related primitives for the ARM Cortex-A, Cortex-M and - * Cortex-R processor architecture. + * Core thread related primitives for the ARM Cortex-M + * processor architecture. */ #include #include #include +#include +#include #if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE) #define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \ @@ -37,7 +40,7 @@ #define DEFAULT_EXC_RETURN 0xFD; #endif -#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M) +#if !defined(CONFIG_MULTITHREADING) K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE); #endif @@ -93,31 +96,15 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, iframe->pc = (uint32_t)z_thread_entry; #endif -#if defined(CONFIG_CPU_CORTEX_M) /* force ARM mode by clearing LSB of address */ iframe->pc &= 0xfffffffe; -#endif iframe->a1 = (uint32_t)entry; iframe->a2 = (uint32_t)p1; iframe->a3 = (uint32_t)p2; iframe->a4 = (uint32_t)p3; -#if defined(CONFIG_CPU_CORTEX_M) iframe->xpsr = 0x01000000UL; /* clear all, thumb bit is 1, even if RO */ -#else - iframe->xpsr = A_BIT | MODE_SYS; -#if defined(CONFIG_COMPILER_ISA_THUMB2) - iframe->xpsr |= T_BIT; -#endif /* CONFIG_COMPILER_ISA_THUMB2 */ -#endif /* CONFIG_CPU_CORTEX_M */ - -#if !defined(CONFIG_CPU_CORTEX_M) \ - && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) - iframe = (struct __basic_sf *) - ((uintptr_t)iframe - sizeof(struct __fpu_sf)); - memset(iframe, 0, sizeof(struct __fpu_sf)); -#endif thread->callee_saved.psp = (uint32_t)iframe; thread->arch.basepri = 0; @@ -274,11 +261,6 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ #endif /* CONFIG_MPU_STACK_GUARD */ -#if defined(CONFIG_CPU_AARCH32_CORTEX_R) - _current->arch.priv_stack_end = - _current->arch.priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE; -#endif - z_arm_userspace_enter(user_entry, p1, p2, p3, (uint32_t)_current->stack_info.start, _current->stack_info.size - @@ -286,6 +268,15 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, CODE_UNREACHABLE; } + +bool z_arm_thread_is_in_user_mode(void) +{ + uint32_t value; + + /* return mode information */ + value = __get_CONTROL(); + return (value & CONTROL_nPRIV_Msk) != 0; +} #endif #if defined(CONFIG_BUILTIN_STACK_GUARD) @@ -477,11 +468,7 @@ int arch_float_disable(struct k_thread *thread) thread->base.user_options &= ~K_FP_REGS; -#if defined(CONFIG_CPU_CORTEX_M) __set_CONTROL(__get_CONTROL() & (~CONTROL_FPCA_Msk)); -#else - __set_FPEXC(0); -#endif /* No need to add an ISB barrier after setting the CONTROL * register; arch_irq_unlock() already adds one. @@ -519,7 +506,7 @@ static void z_arm_prepare_switch_to_main(void) #else __set_FPSCR(0); #endif -#if defined(CONFIG_CPU_CORTEX_M) && defined(CONFIG_FPU_SHARING) +#if defined(CONFIG_FPU_SHARING) /* In Sharing mode clearing FPSCR may set the CONTROL.FPCA flag. */ __set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk))); barrier_isync_fence_full(); @@ -534,7 +521,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, _current = main_thread; -#if defined(CONFIG_THREAD_LOCAL_STORAGE) && defined(CONFIG_CPU_CORTEX_M) +#if defined(CONFIG_THREAD_LOCAL_STORAGE) /* On Cortex-M, TLS uses a global variable as pointer to * the thread local storage area. So this needs to point * to the main thread's TLS area before switching to any @@ -575,15 +562,10 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, */ __asm__ volatile ( "mov r0, %0\n\t" /* Store _main in R0 */ -#if defined(CONFIG_CPU_CORTEX_M) "msr PSP, %1\n\t" /* __set_PSP(stack_ptr) */ -#endif "movs r1, #0\n\t" -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) \ - || defined(CONFIG_AARCH32_ARMV8_R) \ - || defined(CONFIG_ARMV7_A) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) "cpsie i\n\t" /* __enable_irq() */ #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) "cpsie if\n\t" /* __enable_irq(); __enable_fault_irq() */ @@ -603,7 +585,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, CODE_UNREACHABLE; } -#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M) +#if !defined(CONFIG_MULTITHREADING) FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( k_thread_entry_t main_entry, void *p1, void *p2, void *p3) @@ -664,4 +646,4 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ } -#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */ +#endif /* !CONFIG_MULTITHREADING */ diff --git a/arch/arm/core/aarch32/cortex_m/thread_abort.c b/arch/arm/core/cortex_m/thread_abort.c similarity index 100% rename from arch/arm/core/aarch32/cortex_m/thread_abort.c rename to arch/arm/core/cortex_m/thread_abort.c diff --git a/arch/arm/core/aarch32/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c similarity index 98% rename from arch/arm/core/aarch32/cortex_m/timing.c rename to arch/arm/core/cortex_m/timing.c index 2e2912487f88c..861f1a9995aaa 100644 --- a/arch/arm/core/aarch32/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/core/aarch32/cortex_m/tz/CMakeLists.txt b/arch/arm/core/cortex_m/tz/CMakeLists.txt similarity index 100% rename from arch/arm/core/aarch32/cortex_m/tz/CMakeLists.txt rename to arch/arm/core/cortex_m/tz/CMakeLists.txt diff --git a/arch/arm/core/aarch32/cortex_m/tz/Kconfig b/arch/arm/core/cortex_m/tz/Kconfig similarity index 100% rename from arch/arm/core/aarch32/cortex_m/tz/Kconfig rename to arch/arm/core/cortex_m/tz/Kconfig diff --git a/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c b/arch/arm/core/cortex_m/tz/arm_core_tz.c similarity index 98% rename from arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c rename to arch/arm/core/cortex_m/tz/arm_core_tz.c index 1a316be7265d7..8371a08bfef9a 100644 --- a/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c +++ b/arch/arm/core/cortex_m/tz/arm_core_tz.c @@ -5,8 +5,8 @@ */ #include -#include -#include +#include +#include static void configure_nonsecure_vtor_offset(uint32_t vtor_ns) { diff --git a/arch/arm/core/aarch32/cortex_m/tz/secure_entry_functions.ld b/arch/arm/core/cortex_m/tz/secure_entry_functions.ld similarity index 100% rename from arch/arm/core/aarch32/cortex_m/tz/secure_entry_functions.ld rename to arch/arm/core/cortex_m/tz/secure_entry_functions.ld diff --git a/arch/arm/core/aarch32/cortex_m/vector_table.S b/arch/arm/core/cortex_m/vector_table.S similarity index 100% rename from arch/arm/core/aarch32/cortex_m/vector_table.S rename to arch/arm/core/cortex_m/vector_table.S diff --git a/arch/arm/core/aarch32/cortex_m/vector_table.h b/arch/arm/core/cortex_m/vector_table.h similarity index 100% rename from arch/arm/core/aarch32/cortex_m/vector_table.h rename to arch/arm/core/cortex_m/vector_table.h diff --git a/arch/arm/core/aarch32/cortex_m/vector_table_pad.ld b/arch/arm/core/cortex_m/vector_table_pad.ld similarity index 100% rename from arch/arm/core/aarch32/cortex_m/vector_table_pad.ld rename to arch/arm/core/cortex_m/vector_table_pad.ld diff --git a/arch/arm/core/aarch32/cortex_m/vt_pointer_section.ld b/arch/arm/core/cortex_m/vt_pointer_section.ld similarity index 100% rename from arch/arm/core/aarch32/cortex_m/vt_pointer_section.ld rename to arch/arm/core/cortex_m/vt_pointer_section.ld diff --git a/arch/arm/core/aarch32/fatal.c b/arch/arm/core/fatal.c similarity index 100% rename from arch/arm/core/aarch32/fatal.c rename to arch/arm/core/fatal.c diff --git a/arch/arm/core/aarch32/header.S b/arch/arm/core/header.S similarity index 100% rename from arch/arm/core/aarch32/header.S rename to arch/arm/core/header.S diff --git a/arch/arm/core/aarch32/irq_offload.c b/arch/arm/core/irq_offload.c similarity index 100% rename from arch/arm/core/aarch32/irq_offload.c rename to arch/arm/core/irq_offload.c diff --git a/arch/arm/core/aarch32/mmu/CMakeLists.txt b/arch/arm/core/mmu/CMakeLists.txt similarity index 100% rename from arch/arm/core/aarch32/mmu/CMakeLists.txt rename to arch/arm/core/mmu/CMakeLists.txt diff --git a/arch/arm/core/aarch32/mmu/Kconfig b/arch/arm/core/mmu/Kconfig similarity index 100% rename from arch/arm/core/aarch32/mmu/Kconfig rename to arch/arm/core/mmu/Kconfig diff --git a/arch/arm/core/aarch32/mmu/arm_mmu.c b/arch/arm/core/mmu/arm_mmu.c similarity index 99% rename from arch/arm/core/aarch32/mmu/arm_mmu.c rename to arch/arm/core/mmu/arm_mmu.c index 3658b2df639c2..5281d265cd0ef 100644 --- a/arch/arm/core/aarch32/mmu/arm_mmu.c +++ b/arch/arm/core/mmu/arm_mmu.c @@ -31,7 +31,7 @@ #include -#include +#include #include "arm_mmu_priv.h" LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); diff --git a/arch/arm/core/aarch32/mmu/arm_mmu_priv.h b/arch/arm/core/mmu/arm_mmu_priv.h similarity index 100% rename from arch/arm/core/aarch32/mmu/arm_mmu_priv.h rename to arch/arm/core/mmu/arm_mmu_priv.h diff --git a/arch/arm/core/aarch32/mpu/CMakeLists.txt b/arch/arm/core/mpu/CMakeLists.txt similarity index 100% rename from arch/arm/core/aarch32/mpu/CMakeLists.txt rename to arch/arm/core/mpu/CMakeLists.txt diff --git a/arch/arm/core/aarch32/mpu/Kconfig b/arch/arm/core/mpu/Kconfig similarity index 100% rename from arch/arm/core/aarch32/mpu/Kconfig rename to arch/arm/core/mpu/Kconfig diff --git a/arch/arm/core/aarch32/mpu/arm_core_mpu.c b/arch/arm/core/mpu/arm_core_mpu.c similarity index 100% rename from arch/arm/core/aarch32/mpu/arm_core_mpu.c rename to arch/arm/core/mpu/arm_core_mpu.c diff --git a/arch/arm/core/aarch32/mpu/arm_core_mpu_dev.h b/arch/arm/core/mpu/arm_core_mpu_dev.h similarity index 100% rename from arch/arm/core/aarch32/mpu/arm_core_mpu_dev.h rename to arch/arm/core/mpu/arm_core_mpu_dev.h diff --git a/arch/arm/core/aarch32/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c similarity index 100% rename from arch/arm/core/aarch32/mpu/arm_mpu.c rename to arch/arm/core/mpu/arm_mpu.c diff --git a/arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h b/arch/arm/core/mpu/arm_mpu_v7_internal.h similarity index 100% rename from arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h rename to arch/arm/core/mpu/arm_mpu_v7_internal.h diff --git a/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h similarity index 99% rename from arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h rename to arch/arm/core/mpu/arm_mpu_v8_internal.h index dd5e7f94bfb0d..1f7cb04839e25 100644 --- a/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h @@ -8,7 +8,7 @@ #ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_ #define ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_ -#include +#include #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL #include #include diff --git a/arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h b/arch/arm/core/mpu/cortex_a_r/arm_mpu_internal.h similarity index 100% rename from arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h rename to arch/arm/core/mpu/cortex_a_r/arm_mpu_internal.h diff --git a/arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h b/arch/arm/core/mpu/cortex_m/arm_mpu_internal.h similarity index 100% rename from arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h rename to arch/arm/core/mpu/cortex_m/arm_mpu_internal.h diff --git a/arch/arm/core/aarch32/mpu/nxp_mpu.c b/arch/arm/core/mpu/nxp_mpu.c similarity index 100% rename from arch/arm/core/aarch32/mpu/nxp_mpu.c rename to arch/arm/core/mpu/nxp_mpu.c diff --git a/arch/arm/core/aarch32/nmi.c b/arch/arm/core/nmi.c similarity index 100% rename from arch/arm/core/aarch32/nmi.c rename to arch/arm/core/nmi.c diff --git a/arch/arm/core/aarch32/nmi_on_reset.S b/arch/arm/core/nmi_on_reset.S similarity index 100% rename from arch/arm/core/aarch32/nmi_on_reset.S rename to arch/arm/core/nmi_on_reset.S diff --git a/arch/arm/core/common/tls.c b/arch/arm/core/tls.c similarity index 100% rename from arch/arm/core/common/tls.c rename to arch/arm/core/tls.c diff --git a/arch/arm/core/aarch32/userspace.S b/arch/arm/core/userspace.S similarity index 99% rename from arch/arm/core/aarch32/userspace.S rename to arch/arm/core/userspace.S index 58553a8c91542..bf89c7d663d26 100644 --- a/arch/arm/core/aarch32/userspace.S +++ b/arch/arm/core/userspace.S @@ -12,7 +12,7 @@ #include #include -#include +#include #if defined(CONFIG_CPU_AARCH32_CORTEX_R) #include diff --git a/arch/arm/core/aarch32/vector_table.ld b/arch/arm/core/vector_table.ld similarity index 100% rename from arch/arm/core/aarch32/vector_table.ld rename to arch/arm/core/vector_table.ld diff --git a/arch/arm/core/aarch32/zimage_header.ld b/arch/arm/core/zimage_header.ld similarity index 100% rename from arch/arm/core/aarch32/zimage_header.ld rename to arch/arm/core/zimage_header.ld diff --git a/arch/arm/include/aarch32/offsets_short_arch.h b/arch/arm/include/aarch32/offsets_short_arch.h deleted file mode 100644 index 5f41a7fe195b3..0000000000000 --- a/arch/arm/include/aarch32/offsets_short_arch.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_ -#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_ - -#include - -/* kernel */ - -/* nothing for now */ - -/* end - kernel */ - -/* threads */ - -#define _thread_offset_to_basepri \ - (___thread_t_arch_OFFSET + ___thread_arch_t_basepri_OFFSET) - -#define _thread_offset_to_preempt_float \ - (___thread_t_arch_OFFSET + ___thread_arch_t_preempt_float_OFFSET) - -#if defined(CONFIG_USERSPACE) || defined(CONFIG_FPU_SHARING) -#define _thread_offset_to_mode \ - (___thread_t_arch_OFFSET + ___thread_arch_t_mode_OFFSET) -#endif - -#if defined(CONFIG_ARM_STORE_EXC_RETURN) -#define _thread_offset_to_mode_exc_return \ - (___thread_t_arch_OFFSET + ___thread_arch_t_mode_exc_return_OFFSET) -#endif - -#ifdef CONFIG_USERSPACE -#define _thread_offset_to_priv_stack_start \ - (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET) - -#if defined(CONFIG_CPU_AARCH32_CORTEX_R) -#define _thread_offset_to_priv_stack_end \ - (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_end_OFFSET) - -#define _thread_offset_to_sp_usr \ - (___thread_t_arch_OFFSET + ___thread_arch_t_sp_usr_OFFSET) -#endif -#endif - -#if defined(CONFIG_THREAD_STACK_INFO) -#define _thread_offset_to_stack_info_start \ - (___thread_stack_info_t_start_OFFSET + ___thread_t_stack_info_OFFSET) -#endif - - -/* end - threads */ - -#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/arm/include/aarch32/cortex_a_r/exc.h b/arch/arm/include/cortex_a_r/exc.h similarity index 82% rename from arch/arm/include/aarch32/cortex_a_r/exc.h rename to arch/arm/include/cortex_a_r/exc.h index 8f4c7d17c44b6..b77febbc047ce 100644 --- a/arch/arm/include/aarch32/cortex_a_r/exc.h +++ b/arch/arm/include/cortex_a_r/exc.h @@ -54,26 +54,6 @@ static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t } #endif -/** - * @brief Setup system exceptions - * - * Enable fault exceptions. - * - */ -static ALWAYS_INLINE void z_arm_exc_setup(void) -{ -} - -/** - * @brief Clear Fault exceptions - * - * Clear out exceptions for Mem, Bus, Usage and Hard Faults - * - */ -static ALWAYS_INLINE void z_arm_clear_faults(void) -{ -} - extern void z_arm_cortex_r_svc(void); #ifdef __cplusplus diff --git a/arch/arm/include/cortex_a_r/kernel_arch_func.h b/arch/arm/include/cortex_a_r/kernel_arch_func.h new file mode 100644 index 0000000000000..5bca1214da17b --- /dev/null +++ b/arch/arm/include/cortex_a_r/kernel_arch_func.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** + * @file + * @brief Private kernel definitions (ARM) + * + * This file contains private kernel function definitions and various + * other definitions for the 32-bit ARM Cortex-A/R processor architecture + * family. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. + */ + +#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _ASMLANGUAGE +#ifdef CONFIG_ARM_MPU +extern void z_arm_configure_static_mpu_regions(void); +extern int z_arm_mpu_init(void); +#endif /* CONFIG_ARM_MPU */ +#ifdef CONFIG_ARM_AARCH32_MMU +extern int z_arm_mmu_init(void); +#endif /* CONFIG_ARM_AARCH32_MMU */ + +static ALWAYS_INLINE void arch_kernel_init(void) +{ +#if defined(CONFIG_ARM_MPU) + z_arm_mpu_init(); + /* Configure static memory map. This will program MPU regions, + * to set up access permissions for fixed memory sections, such + * as Application Memory or No-Cacheable SRAM area. + * + * This function is invoked once, upon system initialization. + */ + z_arm_configure_static_mpu_regions(); +#endif /* CONFIG_ARM_MPU */ +#if defined(CONFIG_ARM_AARCH32_MMU) + z_arm_mmu_init(); +#endif /* CONFIG_ARM_AARCH32_MMU */ +} + +static ALWAYS_INLINE void +arch_thread_return_value_set(struct k_thread *thread, unsigned int value) +{ + thread->arch.swap_return_value = value; +} + +extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, + void *p1, void *p2, void *p3, + uint32_t stack_end, + uint32_t stack_start); + +extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); + +#endif /* _ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/arm/include/aarch32/cortex_a_r/stack.h b/arch/arm/include/cortex_a_r/stack.h similarity index 75% rename from arch/arm/include/aarch32/cortex_a_r/stack.h rename to arch/arm/include/cortex_a_r/stack.h index e6648f1914ea2..5638c49ee23ba 100644 --- a/arch/arm/include/aarch32/cortex_a_r/stack.h +++ b/arch/arm/include/cortex_a_r/stack.h @@ -26,17 +26,6 @@ extern "C" { extern void z_arm_init_stacks(void); -/** - * - * @brief Setup interrupt stack - * - * On Cortex-A and Cortex-R, the interrupt stack is set up by reset.S - * - */ -static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) -{ -} - #endif /* _ASMLANGUAGE */ #ifdef __cplusplus diff --git a/arch/arm/include/aarch32/cortex_a_r/tcm.h b/arch/arm/include/cortex_a_r/tcm.h similarity index 100% rename from arch/arm/include/aarch32/cortex_a_r/tcm.h rename to arch/arm/include/cortex_a_r/tcm.h diff --git a/arch/arm/include/aarch32/cortex_m/cmse.h b/arch/arm/include/cortex_m/cmse.h similarity index 100% rename from arch/arm/include/aarch32/cortex_m/cmse.h rename to arch/arm/include/cortex_m/cmse.h diff --git a/arch/arm/include/aarch32/cortex_m/dwt.h b/arch/arm/include/cortex_m/dwt.h similarity index 100% rename from arch/arm/include/aarch32/cortex_m/dwt.h rename to arch/arm/include/cortex_m/dwt.h diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h similarity index 99% rename from arch/arm/include/aarch32/cortex_m/exc.h rename to arch/arm/include/cortex_m/exc.h index 13fc08f178d60..b46e74341a92f 100644 --- a/arch/arm/include/aarch32/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -23,7 +23,7 @@ #else #include -#include +#include #include #ifdef __cplusplus diff --git a/arch/arm/include/aarch32/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h similarity index 79% rename from arch/arm/include/aarch32/kernel_arch_func.h rename to arch/arm/include/cortex_m/kernel_arch_func.h index 08f4a6d92b507..77619c9d6c4f8 100644 --- a/arch/arm/include/aarch32/kernel_arch_func.h +++ b/arch/arm/include/cortex_m/kernel_arch_func.h @@ -1,15 +1,14 @@ /* - * Copyright (c) 2013-2016 Wind River Systems, Inc. + * Copyright (c) 2019 Carlo Caione * * SPDX-License-Identifier: Apache-2.0 */ - /** * @file * @brief Private kernel definitions (ARM) * * This file contains private kernel function definitions and various - * other definitions for the 32-bit ARM Cortex-A/R/M processor architecture + * other definitions for the 32-bit ARM Cortex-M processor architecture * family. * * This file is also included by assembly language files which must #define @@ -18,10 +17,8 @@ * in the offsets.o module. */ -#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_ -#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_ - -#include +#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_ #ifdef __cplusplus extern "C" { @@ -56,9 +53,6 @@ static ALWAYS_INLINE void arch_kernel_init(void) */ z_arm_configure_static_mpu_regions(); #endif /* CONFIG_ARM_MPU */ -#if defined(CONFIG_ARM_AARCH32_MMU) - z_arm_mmu_init(); -#endif /* CONFIG_ARM_AARCH32_MMU */ } static ALWAYS_INLINE void @@ -67,7 +61,7 @@ arch_thread_return_value_set(struct k_thread *thread, unsigned int value) thread->arch.swap_return_value = value; } -#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M) +#if !defined(CONFIG_MULTITHREADING) extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( k_thread_entry_t main_func, void *p1, void *p2, void *p3); @@ -75,7 +69,7 @@ extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( #define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \ z_arm_switch_to_main_no_multithreading -#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */ +#endif /* !CONFIG_MULTITHREADING */ extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3, @@ -90,4 +84,4 @@ extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); } #endif -#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_ */ +#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/arm/include/aarch32/cortex_m/stack.h b/arch/arm/include/cortex_m/stack.h similarity index 100% rename from arch/arm/include/aarch32/cortex_m/stack.h rename to arch/arm/include/cortex_m/stack.h diff --git a/arch/arm/include/aarch32/cortex_m/tz.h b/arch/arm/include/cortex_m/tz.h similarity index 100% rename from arch/arm/include/aarch32/cortex_m/tz.h rename to arch/arm/include/cortex_m/tz.h diff --git a/arch/arm/include/aarch32/cortex_m/tz_ns.h b/arch/arm/include/cortex_m/tz_ns.h similarity index 100% rename from arch/arm/include/aarch32/cortex_m/tz_ns.h rename to arch/arm/include/cortex_m/tz_ns.h diff --git a/arch/arm/include/kernel_arch_data.h b/arch/arm/include/kernel_arch_data.h index 832e4b1042c4c..6ae5f643341d6 100644 --- a/arch/arm/include/kernel_arch_data.h +++ b/arch/arm/include/kernel_arch_data.h @@ -25,11 +25,11 @@ #include #if defined(CONFIG_CPU_CORTEX_M) -#include -#include +#include +#include #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) -#include -#include +#include +#include #endif #ifndef _ASMLANGUAGE diff --git a/arch/arm/include/kernel_arch_func.h b/arch/arm/include/kernel_arch_func.h index b680da356f8f0..b8d67137b5213 100644 --- a/arch/arm/include/kernel_arch_func.h +++ b/arch/arm/include/kernel_arch_func.h @@ -3,10 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Private kernel definitions (ARM) + * + * This file contains private kernel function definitions and various + * other definitions for the 32-bit ARM Cortex-A/R/M processor architecture + * family. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. + */ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ -#include +#include + +#if defined(CONFIG_CPU_CORTEX_M) +#include +#else +#include +#endif #endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/arm/include/offsets_short_arch.h b/arch/arm/include/offsets_short_arch.h index f09f24a72f617..78a2607655c88 100644 --- a/arch/arm/include/offsets_short_arch.h +++ b/arch/arm/include/offsets_short_arch.h @@ -7,6 +7,51 @@ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include + +/* kernel */ + +/* nothing for now */ + +/* end - kernel */ + +/* threads */ + +#define _thread_offset_to_basepri \ + (___thread_t_arch_OFFSET + ___thread_arch_t_basepri_OFFSET) + +#define _thread_offset_to_preempt_float \ + (___thread_t_arch_OFFSET + ___thread_arch_t_preempt_float_OFFSET) + +#if defined(CONFIG_USERSPACE) || defined(CONFIG_FPU_SHARING) +#define _thread_offset_to_mode \ + (___thread_t_arch_OFFSET + ___thread_arch_t_mode_OFFSET) +#endif + +#if defined(CONFIG_ARM_STORE_EXC_RETURN) +#define _thread_offset_to_mode_exc_return \ + (___thread_t_arch_OFFSET + ___thread_arch_t_mode_exc_return_OFFSET) +#endif + +#ifdef CONFIG_USERSPACE +#define _thread_offset_to_priv_stack_start \ + (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET) + +#if defined(CONFIG_CPU_AARCH32_CORTEX_R) +#define _thread_offset_to_priv_stack_end \ + (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_end_OFFSET) + +#define _thread_offset_to_sp_usr \ + (___thread_t_arch_OFFSET + ___thread_arch_t_sp_usr_OFFSET) +#endif +#endif + +#if defined(CONFIG_THREAD_STACK_INFO) +#define _thread_offset_to_stack_info_start \ + (___thread_stack_info_t_start_OFFSET + ___thread_t_stack_info_OFFSET) +#endif + + +/* end - threads */ #endif /* ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/boards/arm/ip_k66f/linker.ld b/boards/arm/ip_k66f/linker.ld index e1005cd32b798..21e9d0e4c1f00 100644 --- a/boards/arm/ip_k66f/linker.ld +++ b/boards/arm/ip_k66f/linker.ld @@ -44,4 +44,4 @@ ITERABLE_SECTION_RAM(net_if_dev, 4) \ ITERABLE_SECTION_RAM(net_l2, 4) \ ITERABLE_SECTION_RAM(eth_bridge, 4) -#include +#include diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst index 1e70b10cc8c95..48e517259ed5b 100644 --- a/doc/hardware/arch/arm_cortex_m.rst +++ b/doc/hardware/arch/arm_cortex_m.rst @@ -169,7 +169,7 @@ PendSV exception return sequence restores the new thread's caller-saved register return address, as part of unstacking the exception stack frame. The implementation of the context-switch mechanism is present in -:file:`arch/arm/core/aarch32/swap_helper.S`. +:file:`arch/arm/core/swap_helper.S`. Stack limit checking (Arm v8-M) ------------------------------- @@ -262,7 +262,7 @@ interrupt. If the ZLI feature is enabled in Mainline Cortex-M builds (see * Regular HW interrupts are assigned priority levels lower than SVC. The priority level configuration in Cortex-M is implemented in -:file:`include/arch/arm/aarch32/exc.h`. +:file:`include/arch/arm/exc.h`. Locking and unlocking IRQs -------------------------- @@ -337,7 +337,7 @@ CPU Idling The Cortex-M architecture port implements both k_cpu_idle() and k_cpu_atomic_idle(). The implementation is present in -:file:`arch/arm/core/aarch32/cpu_idle.S`. +:file:`arch/arm/core/cpu_idle.S`. In both implementations, the processor will attempt to put the core to low power mode. @@ -624,7 +624,7 @@ Linking Cortex-M applications ***************************** Most Cortex-M platforms make use of the default Cortex-M -GCC linker script in :file:`include/arch/arm/aarch32/cortex-m/scripts/linked.ld`, +GCC linker script in :file:`include/arch/arm/cortex-m/scripts/linked.ld`, although it is possible for platforms to use a custom linker script as well. diff --git a/doc/hardware/porting/arch.rst b/doc/hardware/porting/arch.rst index 8b9e96503b2c6..a4e1e753cffff 100644 --- a/doc/hardware/porting/arch.rst +++ b/doc/hardware/porting/arch.rst @@ -160,7 +160,7 @@ we strongly suggest that handlers at least print some debug information. The information helps figuring out what went wrong when hitting an exception that is a fault, like divide-by-zero or invalid memory access, or an interrupt that is not expected (:dfn:`spurious interrupt`). See the ARM implementation in -:zephyr_file:`arch/arm/core/aarch32/cortex_m/fault.c` for an example. +:zephyr_file:`arch/arm/core/cortex_m/fault.c` for an example. Thread Context Switching ************************ @@ -299,7 +299,7 @@ gracefully exits its entry point function. This means implementing an architecture-specific version of :c:func:`k_thread_abort`, and setting the Kconfig option :kconfig:option:`CONFIG_ARCH_HAS_THREAD_ABORT` as needed for the architecture (e.g. see -:zephyr_file:`arch/arm/core/aarch32/cortex_m/Kconfig`). +:zephyr_file:`arch/arm/core/cortex_m/Kconfig`). Thread Local Storage ******************** diff --git a/doc/kernel/code-relocation.rst b/doc/kernel/code-relocation.rst index ee534ffe3efad..a9da18e98cd4a 100644 --- a/doc/kernel/code-relocation.rst +++ b/doc/kernel/code-relocation.rst @@ -135,7 +135,7 @@ A test showcasing this feature is provided at This test shows how the code relocation feature is used. This test will place .text, .data, .bss from 3 files to various parts in the SRAM -using a custom linker file derived from ``include/arch/arm/aarch32/cortex_m/scripts/linker.ld`` +using a custom linker file derived from ``include/zephyr/arch/arm/cortex_m/scripts/linker.ld`` A sample showcasing the NOCOPY flag is provided at ``$ZEPHYR_BASE/samples/application_development/code_relocation_nocopy/`` diff --git a/doc/kernel/usermode/memory_domain.rst b/doc/kernel/usermode/memory_domain.rst index ff5d419ffd89e..a1ddcd395e98a 100644 --- a/doc/kernel/usermode/memory_domain.rst +++ b/doc/kernel/usermode/memory_domain.rst @@ -419,7 +419,7 @@ dependent. The complete list of available partition attributes for a specific architecture is found in the architecture-specific include file -``include/arch//arch.h``, (for example, ``include/arch/arm/aarch32/arch.h``.) +``include/zephyr/arch//arch.h``, (for example, ``include/zehpyr/arch/arm/arch.h``.) Some examples of partition attributes are: .. code-block:: c diff --git a/doc/releases/release-notes-3.5.rst b/doc/releases/release-notes-3.5.rst index 9019af80123af..9b6af90284834 100644 --- a/doc/releases/release-notes-3.5.rst +++ b/doc/releases/release-notes-3.5.rst @@ -22,6 +22,11 @@ Architectures * ARM + * Architectural support for Arm Cortex-M has been separated from Arm + Cortex-A and Cortex-R. This includes separate source modules to handle + tasks like IRQ management, exception handling, thread handling and swap. + For implementation details see :github:`60031`. + * ARM * ARM64 diff --git a/drivers/interrupt_controller/intc_vim.c b/drivers/interrupt_controller/intc_vim.c index df4eb4a960523..01d2633413d57 100644 --- a/drivers/interrupt_controller/intc_vim.c +++ b/drivers/interrupt_controller/intc_vim.c @@ -8,7 +8,7 @@ #include -#include +#include #include #include #include diff --git a/drivers/watchdog/wdt_cmsdk_apb.c b/drivers/watchdog/wdt_cmsdk_apb.c index 9d4fa1b979d4b..543a9ecf39ebf 100644 --- a/drivers/watchdog/wdt_cmsdk_apb.c +++ b/drivers/watchdog/wdt_cmsdk_apb.c @@ -12,7 +12,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/watchdog/wdt_smartbond.c b/drivers/watchdog/wdt_smartbond.c index 4e48aa5c5c4e0..5ae0767124772 100644 --- a/drivers/watchdog/wdt_smartbond.c +++ b/drivers/watchdog/wdt_smartbond.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/include/zephyr/arch/arch_inlines.h b/include/zephyr/arch/arch_inlines.h index a4173d2a95b04..4e1cd149dfb4d 100644 --- a/include/zephyr/arch/arch_inlines.h +++ b/include/zephyr/arch/arch_inlines.h @@ -15,7 +15,7 @@ #if defined(CONFIG_X86) || defined(CONFIG_X86_64) #include #elif defined(CONFIG_ARM) -#include +#include #elif defined(CONFIG_ARM64) #include #elif defined(CONFIG_ARC) diff --git a/include/zephyr/arch/arm/aarch32/arch.h b/include/zephyr/arch/arm/arch.h similarity index 91% rename from include/zephyr/arch/arm/aarch32/arch.h rename to include/zephyr/arch/arm/arch.h index 15426b39e068d..a726bba8502ad 100644 --- a/include/zephyr/arch/arm/aarch32/arch.h +++ b/include/zephyr/arch/arm/arch.h @@ -22,29 +22,29 @@ /* ARM GPRs are often designated by two different names */ #define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; } -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include #include #include -#include -#include +#include +#include #include #ifdef CONFIG_CPU_CORTEX_M -#include -#include +#include +#include #include #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) -#include -#include +#include +#include #if defined(CONFIG_AARCH32_ARMV8_R) -#include -#include +#include +#include #else -#include +#include #endif #endif @@ -265,14 +265,14 @@ enum k_fatal_error_reason_arch { /* Legacy case: retain containing extern "C" with C++ */ #ifdef CONFIG_ARM_MPU #ifdef CONFIG_CPU_HAS_ARM_MPU -#include +#include #endif /* CONFIG_CPU_HAS_ARM_MPU */ #ifdef CONFIG_CPU_HAS_NXP_MPU -#include +#include #endif /* CONFIG_CPU_HAS_NXP_MPU */ #endif /* CONFIG_ARM_MPU */ #ifdef CONFIG_ARM_AARCH32_MMU -#include +#include #endif /* CONFIG_ARM_AARCH32_MMU */ #ifdef __cplusplus diff --git a/include/zephyr/arch/arm/aarch32/arch_inlines.h b/include/zephyr/arch/arm/arch_inlines.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/arch_inlines.h rename to include/zephyr/arch/arm/arch_inlines.h diff --git a/include/zephyr/arch/arm/aarch32/asm_inline.h b/include/zephyr/arch/arm/asm_inline.h similarity index 90% rename from include/zephyr/arch/arm/aarch32/asm_inline.h rename to include/zephyr/arch/arm/asm_inline.h index 0f1aa22310cf9..c083adcd47a7a 100644 --- a/include/zephyr/arch/arm/aarch32/asm_inline.h +++ b/include/zephyr/arch/arm/asm_inline.h @@ -15,7 +15,7 @@ */ #if defined(__GNUC__) -#include +#include #else #include #endif diff --git a/include/zephyr/arch/arm/aarch32/asm_inline_gcc.h b/include/zephyr/arch/arm/asm_inline_gcc.h similarity index 96% rename from include/zephyr/arch/arm/aarch32/asm_inline_gcc.h rename to include/zephyr/arch/arm/asm_inline_gcc.h index 71665eefdfb35..7bb58d9897c61 100644 --- a/include/zephyr/arch/arm/aarch32/asm_inline_gcc.h +++ b/include/zephyr/arch/arm/asm_inline_gcc.h @@ -19,10 +19,10 @@ #ifndef _ASMLANGUAGE #include -#include +#include #if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) -#include +#include #endif #ifdef __cplusplus diff --git a/include/zephyr/arch/arm/aarch32/barrier.h b/include/zephyr/arch/arm/barrier.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/barrier.h rename to include/zephyr/arch/arm/barrier.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/armv8_timer.h b/include/zephyr/arch/arm/cortex_a_r/armv8_timer.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/armv8_timer.h rename to include/zephyr/arch/arm/cortex_a_r/armv8_timer.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h b/include/zephyr/arch/arm/cortex_a_r/cmsis.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h rename to include/zephyr/arch/arm/cortex_a_r/cmsis.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/cpu.h b/include/zephyr/arch/arm/cortex_a_r/cpu.h similarity index 98% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/cpu.h rename to include/zephyr/arch/arm/cortex_a_r/cpu.h index 4c4901f5cbe9d..806d28247ac57 100644 --- a/include/zephyr/arch/arm/aarch32/cortex_a_r/cpu.h +++ b/include/zephyr/arch/arm/cortex_a_r/cpu.h @@ -8,7 +8,7 @@ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CPU_H_ #if defined(CONFIG_ARM_MPU) -#include +#include #endif /* diff --git a/include/zephyr/arch/arm/cortex_a_r/exc.h b/include/zephyr/arch/arm/cortex_a_r/exc.h new file mode 100644 index 0000000000000..92f074f1b36a7 --- /dev/null +++ b/include/zephyr/arch/arm/cortex_a_r/exc.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM AArch32 Cortex-A and Cortex-R public exception handling + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_ + +#ifdef _ASMLANGUAGE +GTEXT(z_arm_exc_exit); +#else +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + +/* Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls. + * + * Registers s0-s15 (d0-d7, q0-q3) do not have to be preserved (and can be used + * for passing arguments or returning results in standard procedure-call variants). + * + * Registers d16-d31 (q8-q15), do not have to be preserved. + */ +struct __fpu_sf { + uint32_t s[16]; /* s0~s15 (d0-d7) */ +#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32 + uint64_t d[16]; /* d16~d31 */ +#endif + uint32_t fpscr; + uint32_t undefined; +}; +#endif + +/* Additional register state that is not stacked by hardware on exception + * entry. + * + * These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error(). + * When information for a member is unavailable, the field is set to zero. + */ +#if defined(CONFIG_EXTRA_EXCEPTION_INFO) +struct __extra_esf_info { + _callee_saved_t *callee; + uint32_t msp; + uint32_t exc_return; +}; +#endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + +struct __esf { +#if defined(CONFIG_EXTRA_EXCEPTION_INFO) + struct __extra_esf_info extra_info; +#endif +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + struct __fpu_sf fpu; +#endif + struct __basic_sf { + sys_define_gpr_with_alias(a1, r0); + sys_define_gpr_with_alias(a2, r1); + sys_define_gpr_with_alias(a3, r2); + sys_define_gpr_with_alias(a4, r3); + sys_define_gpr_with_alias(ip, r12); + sys_define_gpr_with_alias(lr, r14); + sys_define_gpr_with_alias(pc, r15); + uint32_t xpsr; + } basic; +}; + +extern uint32_t z_arm_coredump_fault_sp; + +typedef struct __esf z_arch_esf_t; + +extern void z_arm_exc_exit(bool fatal); + +#ifdef __cplusplus +} +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_ */ diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/lib_helpers.h b/include/zephyr/arch/arm/cortex_a_r/lib_helpers.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/lib_helpers.h rename to include/zephyr/arch/arm/cortex_a_r/lib_helpers.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/mpu.h b/include/zephyr/arch/arm/cortex_a_r/mpu.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/mpu.h rename to include/zephyr/arch/arm/cortex_a_r/mpu.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/scripts/app_data_alignment.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/app_data_alignment.ld similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/scripts/app_data_alignment.ld rename to include/zephyr/arch/arm/cortex_a_r/scripts/app_data_alignment.ld diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/scripts/linker.ld rename to include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h b/include/zephyr/arch/arm/cortex_a_r/sys_io.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h rename to include/zephyr/arch/arm/cortex_a_r/sys_io.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/timer.h b/include/zephyr/arch/arm/cortex_a_r/timer.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_a_r/timer.h rename to include/zephyr/arch/arm/cortex_a_r/timer.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/arm_mpu_mem_cfg.h b/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h similarity index 98% rename from include/zephyr/arch/arm/aarch32/cortex_m/arm_mpu_mem_cfg.h rename to include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h index c16d1f4d782f0..4f1132af6b0e2 100644 --- a/include/zephyr/arch/arm/aarch32/cortex_m/arm_mpu_mem_cfg.h +++ b/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h @@ -6,7 +6,7 @@ #ifndef _ARM_CORTEX_M_MPU_MEM_CFG_H_ #define _ARM_CORTEX_M_MPU_MEM_CFG_H_ -#include +#include #if !defined(CONFIG_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_MAINLINE) diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h b/include/zephyr/arch/arm/cortex_m/cmsis.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h rename to include/zephyr/arch/arm/cortex_m/cmsis.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/cpu.h b/include/zephyr/arch/arm/cortex_m/cpu.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/cpu.h rename to include/zephyr/arch/arm/cortex_m/cpu.h diff --git a/include/zephyr/arch/arm/aarch32/exc.h b/include/zephyr/arch/arm/cortex_m/exc.h similarity index 77% rename from include/zephyr/arch/arm/aarch32/exc.h rename to include/zephyr/arch/arm/cortex_m/exc.h index b9d6157369862..8a2cfc8cc3f4f 100644 --- a/include/zephyr/arch/arm/aarch32/exc.h +++ b/include/zephyr/arch/arm/cortex_m/exc.h @@ -6,19 +6,15 @@ /** * @file - * @brief ARM AArch32 public exception handling - * - * ARM AArch32-specific kernel exception handling interface. Included by - * arm/arch.h. + * @brief ARM AArch32 Cortex-M public exception handling */ -#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ -#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_ -#if defined(CONFIG_CPU_CORTEX_M) #include -#include +#include /* for assembler, only works with constants */ #define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff) @@ -59,7 +55,6 @@ /* Use lowest possible priority level for PendSV */ #define _EXC_PENDSV_PRIO 0xff #define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO) -#endif /* CONFIG_CPU_CORTEX_M */ #ifdef _ASMLANGUAGE GTEXT(z_arm_exc_exit); @@ -103,8 +98,6 @@ struct __extra_esf_info { }; #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ -#if defined(CONFIG_CPU_CORTEX_M) - struct __esf { struct __basic_sf { sys_define_gpr_with_alias(a1, r0); @@ -124,38 +117,11 @@ struct __esf { #endif }; -#else - -struct __esf { -#if defined(CONFIG_EXTRA_EXCEPTION_INFO) - struct __extra_esf_info extra_info; -#endif -#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) - struct __fpu_sf fpu; -#endif - struct __basic_sf { - sys_define_gpr_with_alias(a1, r0); - sys_define_gpr_with_alias(a2, r1); - sys_define_gpr_with_alias(a3, r2); - sys_define_gpr_with_alias(a4, r3); - sys_define_gpr_with_alias(ip, r12); - sys_define_gpr_with_alias(lr, r14); - sys_define_gpr_with_alias(pc, r15); - uint32_t xpsr; - } basic; -}; - -#endif - extern uint32_t z_arm_coredump_fault_sp; typedef struct __esf z_arch_esf_t; -#ifdef CONFIG_CPU_CORTEX_M extern void z_arm_exc_exit(void); -#else -extern void z_arm_exc_exit(bool fatal); -#endif #ifdef __cplusplus } @@ -163,4 +129,4 @@ extern void z_arm_exc_exit(bool fatal); #endif /* _ASMLANGUAGE */ -#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_ */ diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/fpu.h b/include/zephyr/arch/arm/cortex_m/fpu.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/fpu.h rename to include/zephyr/arch/arm/cortex_m/fpu.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/memory_map.h b/include/zephyr/arch/arm/cortex_m/memory_map.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/memory_map.h rename to include/zephyr/arch/arm/cortex_m/memory_map.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/nvic.h b/include/zephyr/arch/arm/cortex_m/nvic.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/nvic.h rename to include/zephyr/arch/arm/cortex_m/nvic.h diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld rename to include/zephyr/arch/arm/cortex_m/scripts/linker.ld diff --git a/include/zephyr/arch/arm/aarch32/cortex_r/scripts/app_data_alignment.ld b/include/zephyr/arch/arm/cortex_r/scripts/app_data_alignment.ld similarity index 100% rename from include/zephyr/arch/arm/aarch32/cortex_r/scripts/app_data_alignment.ld rename to include/zephyr/arch/arm/cortex_r/scripts/app_data_alignment.ld diff --git a/include/zephyr/arch/arm/aarch32/cortex_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_r/scripts/linker.ld similarity index 63% rename from include/zephyr/arch/arm/aarch32/cortex_r/scripts/linker.ld rename to include/zephyr/arch/arm/cortex_r/scripts/linker.ld index 545b371bbd545..28aa5f7c37691 100644 --- a/include/zephyr/arch/arm/aarch32/cortex_r/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_r/scripts/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/include/zephyr/arch/arm/aarch32/error.h b/include/zephyr/arch/arm/error.h similarity index 96% rename from include/zephyr/arch/arm/aarch32/error.h rename to include/zephyr/arch/arm/error.h index fdb0f1f1a4562..603e1d000888c 100644 --- a/include/zephyr/arch/arm/aarch32/error.h +++ b/include/zephyr/arch/arm/error.h @@ -15,8 +15,8 @@ #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ERROR_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ERROR_H_ -#include -#include +#include +#include #include #ifdef __cplusplus diff --git a/include/zephyr/arch/arm/exc.h b/include/zephyr/arch/arm/exc.h new file mode 100644 index 0000000000000..9cd664e2c6b5d --- /dev/null +++ b/include/zephyr/arch/arm/exc.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM AArch32 public exception handling + * + * ARM AArch32-specific kernel exception handling interface. Included by + * arm/arch.h. + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ + +#if defined(CONFIG_CPU_CORTEX_M) +#include +#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R) +#include +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M */ + +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ */ diff --git a/include/zephyr/arch/arm/aarch32/irq.h b/include/zephyr/arch/arm/irq.h similarity index 99% rename from include/zephyr/arch/arm/aarch32/irq.h rename to include/zephyr/arch/arm/irq.h index 5edcd1af4b2b6..aafc56a19a77c 100644 --- a/include/zephyr/arch/arm/aarch32/irq.h +++ b/include/zephyr/arch/arm/irq.h @@ -149,7 +149,7 @@ extern void _arch_isr_direct_pm(void); #define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header() #define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap) -/* arch/arm/core/aarch32/exc_exit.S */ +/* arch/arm/core/exc_exit.S */ extern void z_arm_int_exit(void); #ifdef CONFIG_TRACING_ISR diff --git a/include/zephyr/arch/arm/aarch32/misc.h b/include/zephyr/arch/arm/misc.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/misc.h rename to include/zephyr/arch/arm/misc.h diff --git a/include/zephyr/arch/arm/aarch32/mmu/arm_mmu.h b/include/zephyr/arch/arm/mmu/arm_mmu.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/mmu/arm_mmu.h rename to include/zephyr/arch/arm/mmu/arm_mmu.h diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu.h b/include/zephyr/arch/arm/mpu/arm_mpu.h similarity index 94% rename from include/zephyr/arch/arm/aarch32/mpu/arm_mpu.h rename to include/zephyr/arch/arm/mpu/arm_mpu.h index 65d9194b7a260..857465a4824cc 100644 --- a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu.h +++ b/include/zephyr/arch/arm/mpu/arm_mpu.h @@ -11,12 +11,12 @@ defined(CONFIG_CPU_CORTEX_M4) || \ defined(CONFIG_CPU_CORTEX_M7) || \ defined(CONFIG_ARMV7_R) -#include +#include #elif defined(CONFIG_CPU_CORTEX_M23) || \ defined(CONFIG_CPU_CORTEX_M33) || \ defined(CONFIG_CPU_CORTEX_M55) || \ defined(CONFIG_AARCH32_ARMV8_R) -#include +#include #else #error "Unsupported ARM CPU" #endif diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h b/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h rename to include/zephyr/arch/arm/mpu/arm_mpu_v7m.h diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h b/include/zephyr/arch/arm/mpu/arm_mpu_v8.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h rename to include/zephyr/arch/arm/mpu/arm_mpu_v8.h diff --git a/include/zephyr/arch/arm/aarch32/mpu/nxp_mpu.h b/include/zephyr/arch/arm/mpu/nxp_mpu.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/mpu/nxp_mpu.h rename to include/zephyr/arch/arm/mpu/nxp_mpu.h diff --git a/include/zephyr/arch/arm/aarch32/nmi.h b/include/zephyr/arch/arm/nmi.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/nmi.h rename to include/zephyr/arch/arm/nmi.h diff --git a/include/zephyr/arch/arm/aarch32/syscall.h b/include/zephyr/arch/arm/syscall.h similarity index 99% rename from include/zephyr/arch/arm/aarch32/syscall.h rename to include/zephyr/arch/arm/syscall.h index f8561d8c24ae5..a4e067307ec78 100644 --- a/include/zephyr/arch/arm/aarch32/syscall.h +++ b/include/zephyr/arch/arm/syscall.h @@ -26,7 +26,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/include/zephyr/arch/arm/aarch32/thread.h b/include/zephyr/arch/arm/thread.h similarity index 100% rename from include/zephyr/arch/arm/aarch32/thread.h rename to include/zephyr/arch/arm/thread.h diff --git a/include/zephyr/arch/cpu.h b/include/zephyr/arch/cpu.h index 5fbe8f8c6288d..17ec125b395da 100644 --- a/include/zephyr/arch/cpu.h +++ b/include/zephyr/arch/cpu.h @@ -16,7 +16,7 @@ #elif defined(CONFIG_ARM64) #include #elif defined(CONFIG_ARM) -#include +#include #elif defined(CONFIG_ARC) #include #elif defined(CONFIG_NIOS2) diff --git a/include/zephyr/arch/syscall.h b/include/zephyr/arch/syscall.h index 3c745921070e8..b657717e3d4bc 100644 --- a/include/zephyr/arch/syscall.h +++ b/include/zephyr/arch/syscall.h @@ -18,7 +18,7 @@ #elif defined(CONFIG_ARM64) #include #elif defined(CONFIG_ARM) -#include +#include #elif defined(CONFIG_ARC) #include #elif defined(CONFIG_RISCV) diff --git a/include/zephyr/linker/irq-vector-table-section.ld b/include/zephyr/linker/irq-vector-table-section.ld index af4da725706f2..17c483db98f5c 100644 --- a/include/zephyr/linker/irq-vector-table-section.ld +++ b/include/zephyr/linker/irq-vector-table-section.ld @@ -6,6 +6,6 @@ KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS)) /* * Some ARM platforms require this symbol to be placed after the IRQ vector * table (like STM32F0). The symbol defined here is overriding the one in - * arch/arm/core/aarch32/vector_table.ld when the IRQ vector table is enbled. + * arch/arm/core/vector_table.ld when the IRQ vector table is enbled. */ _vector_end = .; diff --git a/include/zephyr/sys/barrier.h b/include/zephyr/sys/barrier.h index dacc0ba62f598..5390cb38cf091 100644 --- a/include/zephyr/sys/barrier.h +++ b/include/zephyr/sys/barrier.h @@ -11,7 +11,7 @@ #if defined(CONFIG_BARRIER_OPERATIONS_ARCH) # if defined(CONFIG_ARM) -# include +# include # elif defined(CONFIG_ARM64) # include # endif diff --git a/modules/cmsis/cmsis_core_m.h b/modules/cmsis/cmsis_core_m.h index 849c496a9bde4..880ff614b5b60 100644 --- a/modules/cmsis/cmsis_core_m.h +++ b/modules/cmsis/cmsis_core_m.h @@ -14,7 +14,7 @@ #ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ #define ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ -#include +#include #include diff --git a/modules/trusted-firmware-m/interface/interface.c b/modules/trusted-firmware-m/interface/interface.c index c89a572a788c6..ad0ed1abdfe65 100644 --- a/modules/trusted-firmware-m/interface/interface.c +++ b/modules/trusted-firmware-m/interface/interface.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include diff --git a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld index e28cfefd675fe..934f928596cfb 100644 --- a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld +++ b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld @@ -44,4 +44,4 @@ MEMORY #endif /* CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP */ -#include +#include diff --git a/samples/philosophers/README.rst b/samples/philosophers/README.rst index fbf3ff96f3ed4..77c07cba67001 100644 --- a/samples/philosophers/README.rst +++ b/samples/philosophers/README.rst @@ -86,23 +86,23 @@ OpenOCD Sample Output Thread 1 received signal SIGINT, Interrupt. [Switching to Thread 537003160] - arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/aarch32/cpu_idle.S:107 + arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107 107 cpsie i (gdb) i threads Id Target Id Frame - * 1 Thread 537003160 (Name: idle 00, prio:40,useropts:1) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/aarch32/cpu_idle.S:107 + * 1 Thread 537003160 (Name: idle 00, prio:40,useropts:1) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107 Info : Getting thread 537002984 reg list - 2 Thread 537002984 (Name: Philosopher 5, prio:-2,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 2 Thread 537002984 (Name: Philosopher 5, prio:-2,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 Info : Getting thread 537002808 reg list - 3 Thread 537002808 (Name: Philosopher 4, prio:-1,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 3 Thread 537002808 (Name: Philosopher 4, prio:-1,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 Info : Getting thread 537002632 reg list - 4 Thread 537002632 (Name: Philosopher 3, prio:0,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 4 Thread 537002632 (Name: Philosopher 3, prio:0,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 Info : Getting thread 537002456 reg list - 5 Thread 537002456 (Name: Philosopher 2, prio:1,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 5 Thread 537002456 (Name: Philosopher 2, prio:1,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 Info : Getting thread 537002280 reg list - 6 Thread 537002280 (Name: Philosopher 1, prio:2,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 6 Thread 537002280 (Name: Philosopher 1, prio:2,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 Info : Getting thread 537002104 reg list - 7 Thread 537002104 (Name: Philosopher 0, prio:3,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/aarch32/asm_inline_gcc.h:95 + 7 Thread 537002104 (Name: Philosopher 0, prio:3,useropts:4) 0x08001404 in arch_irq_unlock (key=0) at zephyr/mainline/zephyr/include/arch/arm/asm_inline_gcc.h:95 .. code-block:: console @@ -121,17 +121,17 @@ J-Link Sample Output Thread 2 received signal SIGTRAP, Trace/breakpoint trap. [Switching to Thread 537920592] - arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/aarch32/cpu_idle.S:107 + arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107 107 cpsie i (gdb) i threads Id Target Id Frame - * 2 Thread 537920592 (idle 00 UNKNOWN PRIO 40) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/aarch32/cpu_idle.S:107 - 3 Thread 537919536 (Philosopher 0 PENDING PRIO 3) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 - 4 Thread 537919712 (Philosopher 1 SUSPENDED PRIO 2) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 - 5 Thread 537919888 (Philosopher 2 SUSPENDED PRIO 1) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 - 6 Thread 537920064 (Philosopher 3 SUSPENDED PRIO 0) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 - 7 Thread 537920240 (Philosopher 4 PENDING PRIO 255) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 - 8 Thread 537920416 (Philosopher 5 SUSPENDED PRIO 254) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/aarch32/swap.c:53 + * 2 Thread 537920592 (idle 00 UNKNOWN PRIO 40) arch_cpu_idle () at zephyr/mainline/zephyr/arch/arm/core/cpu_idle.S:107 + 3 Thread 537919536 (Philosopher 0 PENDING PRIO 3) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 + 4 Thread 537919712 (Philosopher 1 SUSPENDED PRIO 2) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 + 5 Thread 537919888 (Philosopher 2 SUSPENDED PRIO 1) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 + 6 Thread 537920064 (Philosopher 3 SUSPENDED PRIO 0) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 + 7 Thread 537920240 (Philosopher 4 PENDING PRIO 255) arch_swap (key=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 + 8 Thread 537920416 (Philosopher 5 SUSPENDED PRIO 254) arch_swap (key=key@entry=0) at zephyr/mainline/zephyr/arch/arm/core/swap.c:53 .. code-block:: console diff --git a/samples/subsys/debug/debugmon/src/main.c b/samples/subsys/debug/debugmon/src/main.c index a05bb2b4117df..9029cc44ae771 100644 --- a/samples/subsys/debug/debugmon/src/main.c +++ b/samples/subsys/debug/debugmon/src/main.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #define LED0_NODE DT_ALIAS(led0) static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios); diff --git a/soc/arm/ambiq/apollo4x/linker.ld b/soc/arm/ambiq/apollo4x/linker.ld index 9c1ab8ff301ea..ab996aa993927 100644 --- a/soc/arm/ambiq/apollo4x/linker.ld +++ b/soc/arm/ambiq/apollo4x/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/beetle/linker.ld b/soc/arm/arm/beetle/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/beetle/linker.ld +++ b/soc/arm/arm/beetle/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/designstart/linker.ld b/soc/arm/arm/designstart/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/designstart/linker.ld +++ b/soc/arm/arm/designstart/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c b/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c index e756a81bccc6a..b1c91d15d9aef 100644 --- a/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c +++ b/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c @@ -5,7 +5,7 @@ #include #include -#include +#include #define DEVICE_REGION_START 0x80000000UL #define DEVICE_REGION_END 0xFFFFFFFFUL diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/linker.ld b/soc/arm/arm/fvp_aemv8r_aarch32/linker.ld index 924b5ab62d413..76b6c7a54501b 100644 --- a/soc/arm/arm/fvp_aemv8r_aarch32/linker.ld +++ b/soc/arm/arm/fvp_aemv8r_aarch32/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/mps2/linker.ld b/soc/arm/arm/mps2/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/mps2/linker.ld +++ b/soc/arm/arm/mps2/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/mps3/linker.ld b/soc/arm/arm/mps3/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/mps3/linker.ld +++ b/soc/arm/arm/mps3/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/musca_b1/linker.ld b/soc/arm/arm/musca_b1/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/musca_b1/linker.ld +++ b/soc/arm/arm/musca_b1/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/arm/musca_s1/linker.ld b/soc/arm/arm/musca_s1/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/arm/musca_s1/linker.ld +++ b/soc/arm/arm/musca_s1/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/aspeed/ast10x0/linker.ld b/soc/arm/aspeed/ast10x0/linker.ld index ef034e1f70e2a..fec4d373a8214 100644 --- a/soc/arm/aspeed/ast10x0/linker.ld +++ b/soc/arm/aspeed/ast10x0/linker.ld @@ -7,4 +7,4 @@ MEMORY { SRAM_NC (wx) : ORIGIN = CONFIG_SRAM_NC_BASE_ADDRESS, LENGTH = CONFIG_SRAM_NC_SIZE * 1024 } -#include +#include diff --git a/soc/arm/atmel_sam/sam3x/linker.ld b/soc/arm/atmel_sam/sam3x/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/atmel_sam/sam3x/linker.ld +++ b/soc/arm/atmel_sam/sam3x/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam/sam4e/linker.ld b/soc/arm/atmel_sam/sam4e/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/atmel_sam/sam4e/linker.ld +++ b/soc/arm/atmel_sam/sam4e/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam/sam4l/linker.ld b/soc/arm/atmel_sam/sam4l/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/atmel_sam/sam4l/linker.ld +++ b/soc/arm/atmel_sam/sam4l/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam/sam4s/linker.ld b/soc/arm/atmel_sam/sam4s/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/atmel_sam/sam4s/linker.ld +++ b/soc/arm/atmel_sam/sam4s/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam/same70/linker.ld b/soc/arm/atmel_sam/same70/linker.ld index e9411a5f88960..cb361723b39be 100644 --- a/soc/arm/atmel_sam/same70/linker.ld +++ b/soc/arm/atmel_sam/same70/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam/samv71/linker.ld b/soc/arm/atmel_sam/samv71/linker.ld index e9411a5f88960..cb361723b39be 100644 --- a/soc/arm/atmel_sam/samv71/linker.ld +++ b/soc/arm/atmel_sam/samv71/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samc20/linker.ld b/soc/arm/atmel_sam0/samc20/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/samc20/linker.ld +++ b/soc/arm/atmel_sam0/samc20/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samc21/linker.ld b/soc/arm/atmel_sam0/samc21/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/samc21/linker.ld +++ b/soc/arm/atmel_sam0/samc21/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samd20/linker.ld b/soc/arm/atmel_sam0/samd20/linker.ld index 5068c8fa74a68..75ef287b6d9b3 100644 --- a/soc/arm/atmel_sam0/samd20/linker.ld +++ b/soc/arm/atmel_sam0/samd20/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samd21/linker.ld b/soc/arm/atmel_sam0/samd21/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/samd21/linker.ld +++ b/soc/arm/atmel_sam0/samd21/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samd51/linker.ld b/soc/arm/atmel_sam0/samd51/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/samd51/linker.ld +++ b/soc/arm/atmel_sam0/samd51/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/same51/linker.ld b/soc/arm/atmel_sam0/same51/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/same51/linker.ld +++ b/soc/arm/atmel_sam0/same51/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/same53/linker.ld b/soc/arm/atmel_sam0/same53/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/same53/linker.ld +++ b/soc/arm/atmel_sam0/same53/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/same54/linker.ld b/soc/arm/atmel_sam0/same54/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/same54/linker.ld +++ b/soc/arm/atmel_sam0/same54/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/saml21/linker.ld b/soc/arm/atmel_sam0/saml21/linker.ld index 799b8baa700f0..6b4498f093227 100644 --- a/soc/arm/atmel_sam0/saml21/linker.ld +++ b/soc/arm/atmel_sam0/saml21/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samr21/linker.ld b/soc/arm/atmel_sam0/samr21/linker.ld index 3ff98161e1115..745c7ad8b2a7e 100644 --- a/soc/arm/atmel_sam0/samr21/linker.ld +++ b/soc/arm/atmel_sam0/samr21/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samr34/linker.ld b/soc/arm/atmel_sam0/samr34/linker.ld index 799b8baa700f0..6b4498f093227 100644 --- a/soc/arm/atmel_sam0/samr34/linker.ld +++ b/soc/arm/atmel_sam0/samr34/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/atmel_sam0/samr35/linker.ld b/soc/arm/atmel_sam0/samr35/linker.ld index 799b8baa700f0..6b4498f093227 100644 --- a/soc/arm/atmel_sam0/samr35/linker.ld +++ b/soc/arm/atmel_sam0/samr35/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/bcm_vk/valkyrie/linker.ld b/soc/arm/bcm_vk/valkyrie/linker.ld index 5a1f77932532e..a17ecaeaf3250 100644 --- a/soc/arm/bcm_vk/valkyrie/linker.ld +++ b/soc/arm/bcm_vk/valkyrie/linker.ld @@ -4,4 +4,4 @@ */ -#include +#include diff --git a/soc/arm/bcm_vk/viper/linker_m7.ld b/soc/arm/bcm_vk/viper/linker_m7.ld index 3e28ca6c5677c..670bb23c78be8 100644 --- a/soc/arm/bcm_vk/viper/linker_m7.ld +++ b/soc/arm/bcm_vk/viper/linker_m7.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/common/cortex_m/arm_mpu_regions.c b/soc/arm/common/cortex_m/arm_mpu_regions.c index 557079ef5bc2b..7eb3eb24f1d94 100644 --- a/soc/arm/common/cortex_m/arm_mpu_regions.c +++ b/soc/arm/common/cortex_m/arm_mpu_regions.c @@ -5,10 +5,10 @@ */ #include -#include +#include #include -#include +#include static const struct arm_mpu_region mpu_regions[] = { /* Region 0 */ diff --git a/soc/arm/cypress/psoc6/linker.ld b/soc/arm/cypress/psoc6/linker.ld index bd76ded366c89..e0657c31ee5e8 100644 --- a/soc/arm/cypress/psoc6/linker.ld +++ b/soc/arm/cypress/psoc6/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/gigadevice/gd32a50x/linker.ld b/soc/arm/gigadevice/gd32a50x/linker.ld index 32362bbe6e748..34a8f747bdc1e 100644 --- a/soc/arm/gigadevice/gd32a50x/linker.ld +++ b/soc/arm/gigadevice/gd32a50x/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32e10x/linker.ld b/soc/arm/gigadevice/gd32e10x/linker.ld index 39c3b98803716..1223f99d9293e 100644 --- a/soc/arm/gigadevice/gd32e10x/linker.ld +++ b/soc/arm/gigadevice/gd32e10x/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32e50x/linker.ld b/soc/arm/gigadevice/gd32e50x/linker.ld index 32362bbe6e748..34a8f747bdc1e 100644 --- a/soc/arm/gigadevice/gd32e50x/linker.ld +++ b/soc/arm/gigadevice/gd32e50x/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32f3x0/linker.ld b/soc/arm/gigadevice/gd32f3x0/linker.ld index d0bc3bd873731..67650d4eb8dfb 100644 --- a/soc/arm/gigadevice/gd32f3x0/linker.ld +++ b/soc/arm/gigadevice/gd32f3x0/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32f403/linker.ld b/soc/arm/gigadevice/gd32f403/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/gigadevice/gd32f403/linker.ld +++ b/soc/arm/gigadevice/gd32f403/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32f4xx/linker.ld b/soc/arm/gigadevice/gd32f4xx/linker.ld index 32362bbe6e748..34a8f747bdc1e 100644 --- a/soc/arm/gigadevice/gd32f4xx/linker.ld +++ b/soc/arm/gigadevice/gd32f4xx/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/gigadevice/gd32l23x/linker.ld b/soc/arm/gigadevice/gd32l23x/linker.ld index a5bd1ec82a5e1..520d4ee69f0aa 100644 --- a/soc/arm/gigadevice/gd32l23x/linker.ld +++ b/soc/arm/gigadevice/gd32l23x/linker.ld @@ -3,4 +3,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/infineon_cat1/psoc6/linker.ld b/soc/arm/infineon_cat1/psoc6/linker.ld index d2e0572cbede8..9af77e1c52317 100644 --- a/soc/arm/infineon_cat1/psoc6/linker.ld +++ b/soc/arm/infineon_cat1/psoc6/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/infineon_xmc/4xxx/linker.ld b/soc/arm/infineon_xmc/4xxx/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/infineon_xmc/4xxx/linker.ld +++ b/soc/arm/infineon_xmc/4xxx/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/intel_socfpga_std/cyclonev/linker.ld b/soc/arm/intel_socfpga_std/cyclonev/linker.ld index c481264073922..ef4c62338b44e 100644 --- a/soc/arm/intel_socfpga_std/cyclonev/linker.ld +++ b/soc/arm/intel_socfpga_std/cyclonev/linker.ld @@ -5,4 +5,4 @@ * Adding support for Cyclone V SoC FPGA, using arm32 linker */ -#include +#include diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.c b/soc/arm/intel_socfpga_std/cyclonev/soc.c index 70e697dd62baa..73f7617d792e1 100644 --- a/soc/arm/intel_socfpga_std/cyclonev/soc.c +++ b/soc/arm/intel_socfpga_std/cyclonev/soc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "soc.h" #include diff --git a/soc/arm/microchip_mec/mec1501/linker.ld b/soc/arm/microchip_mec/mec1501/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/microchip_mec/mec1501/linker.ld +++ b/soc/arm/microchip_mec/mec1501/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/microchip_mec/mec1501/timing.c b/soc/arm/microchip_mec/mec1501/timing.c index 016cfa249f4db..a67844f60d280 100644 --- a/soc/arm/microchip_mec/mec1501/timing.c +++ b/soc/arm/microchip_mec/mec1501/timing.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/soc/arm/microchip_mec/mec172x/linker.ld b/soc/arm/microchip_mec/mec172x/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/microchip_mec/mec172x/linker.ld +++ b/soc/arm/microchip_mec/mec172x/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/microchip_mec/mec172x/timing.c b/soc/arm/microchip_mec/mec172x/timing.c index c415e3223d5e4..8dafb73544c0d 100644 --- a/soc/arm/microchip_mec/mec172x/timing.c +++ b/soc/arm/microchip_mec/mec172x/timing.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/soc/arm/nordic_nrf/nrf51/linker.ld b/soc/arm/nordic_nrf/nrf51/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/nordic_nrf/nrf51/linker.ld +++ b/soc/arm/nordic_nrf/nrf51/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nordic_nrf/nrf52/linker.ld b/soc/arm/nordic_nrf/nrf52/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/nordic_nrf/nrf52/linker.ld +++ b/soc/arm/nordic_nrf/nrf52/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nordic_nrf/nrf53/linker.ld b/soc/arm/nordic_nrf/nrf53/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/nordic_nrf/nrf53/linker.ld +++ b/soc/arm/nordic_nrf/nrf53/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nordic_nrf/nrf91/linker.ld b/soc/arm/nordic_nrf/nrf91/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/nordic_nrf/nrf91/linker.ld +++ b/soc/arm/nordic_nrf/nrf91/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nordic_nrf/timing.c b/soc/arm/nordic_nrf/timing.c index e75be5f9cdb54..402e97f2141b7 100644 --- a/soc/arm/nordic_nrf/timing.c +++ b/soc/arm/nordic_nrf/timing.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/soc/arm/nuvoton_npcx/npcx4/linker.ld b/soc/arm/nuvoton_npcx/npcx4/linker.ld index 7b1a077291837..36859865d024d 100644 --- a/soc/arm/nuvoton_npcx/npcx4/linker.ld +++ b/soc/arm/nuvoton_npcx/npcx4/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nuvoton_npcx/npcx7/linker.ld b/soc/arm/nuvoton_npcx/npcx7/linker.ld index 4856bf0a71d37..c27b59604dc04 100644 --- a/soc/arm/nuvoton_npcx/npcx7/linker.ld +++ b/soc/arm/nuvoton_npcx/npcx7/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c b/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c index 7592a2e39a22f..e9d4c07330588 100644 --- a/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c +++ b/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include static const struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("FLASH_0_0", diff --git a/soc/arm/nuvoton_npcx/npcx9/linker.ld b/soc/arm/nuvoton_npcx/npcx9/linker.ld index 554ea2c78a7b3..a07329b636027 100644 --- a/soc/arm/nuvoton_npcx/npcx9/linker.ld +++ b/soc/arm/nuvoton_npcx/npcx9/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nuvoton_numaker/m46x/linker.ld b/soc/arm/nuvoton_numaker/m46x/linker.ld index b9a80770518a0..37c968fda6357 100644 --- a/soc/arm/nuvoton_numaker/m46x/linker.ld +++ b/soc/arm/nuvoton_numaker/m46x/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nuvoton_numicro/m48x/linker.ld b/soc/arm/nuvoton_numicro/m48x/linker.ld index 11d1f0f8f32ed..737722a161143 100644 --- a/soc/arm/nuvoton_numicro/m48x/linker.ld +++ b/soc/arm/nuvoton_numicro/m48x/linker.ld @@ -4,4 +4,4 @@ * Copyright (c) 2020 Linumiz */ -#include +#include diff --git a/soc/arm/nxp_imx/mcimx6x_m4/linker.ld b/soc/arm/nxp_imx/mcimx6x_m4/linker.ld index aabc45a605979..3cf863608e1d3 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/linker.ld +++ b/soc/arm/nxp_imx/mcimx6x_m4/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nxp_imx/mcimx7_m4/linker.ld b/soc/arm/nxp_imx/mcimx7_m4/linker.ld index aabc45a605979..3cf863608e1d3 100644 --- a/soc/arm/nxp_imx/mcimx7_m4/linker.ld +++ b/soc/arm/nxp_imx/mcimx7_m4/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld b/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld index 26ae2082fa5cc..0b4006dd73251 100644 --- a/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld +++ b/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld @@ -16,7 +16,7 @@ MEMORY #endif } -#include +#include SECTIONS { diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c b/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c index 7964712f646dd..ed7deb8575abf 100644 --- a/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c +++ b/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c @@ -5,7 +5,7 @@ */ #include -#include +#include #define REGION_MASK_BASE_ADDRESS 0x00000000U #define REGION_ITCM_BASE_ADDRESS 0x00000000U diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld b/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld index b6698210b528c..b1a954f245a11 100644 --- a/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld +++ b/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include SECTIONS { diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/linker.ld b/soc/arm/nxp_imx/mimx8mq6_m4/linker.ld index ebf224afbaf8b..895341fda8d43 100644 --- a/soc/arm/nxp_imx/mimx8mq6_m4/linker.ld +++ b/soc/arm/nxp_imx/mimx8mq6_m4/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nxp_imx/rt/linker.ld b/soc/arm/nxp_imx/rt/linker.ld index b26f1a38aaf60..e4d5ad56db00c 100644 --- a/soc/arm/nxp_imx/rt/linker.ld +++ b/soc/arm/nxp_imx/rt/linker.ld @@ -15,4 +15,4 @@ MEMORY #endif } -#include +#include diff --git a/soc/arm/nxp_imx/rt/mpu_regions.c b/soc/arm/nxp_imx/rt/mpu_regions.c index 663e448f5dd74..dae2535415561 100644 --- a/soc/arm/nxp_imx/rt/mpu_regions.c +++ b/soc/arm/nxp_imx/rt/mpu_regions.c @@ -8,7 +8,7 @@ #include #include -#include +#include static const struct arm_mpu_region mpu_regions[] = { /* Region 0 */ diff --git a/soc/arm/nxp_imx/rt5xx/linker.ld b/soc/arm/nxp_imx/rt5xx/linker.ld index 3b84d02a52782..2b6a4d63fba92 100644 --- a/soc/arm/nxp_imx/rt5xx/linker.ld +++ b/soc/arm/nxp_imx/rt5xx/linker.ld @@ -21,4 +21,4 @@ FLEXSPI2 (wx) : ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi2), 1), LENGTH = DT_REG_SIZE_BY_IDX(DT_NODELABEL(flexspi2), 1) #endif } -#include +#include diff --git a/soc/arm/nxp_imx/rt6xx/linker.ld b/soc/arm/nxp_imx/rt6xx/linker.ld index d9eaca7598c55..cf5cc4c9968c7 100644 --- a/soc/arm/nxp_imx/rt6xx/linker.ld +++ b/soc/arm/nxp_imx/rt6xx/linker.ld @@ -11,4 +11,4 @@ */ -#include +#include diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c index 8ba2aa9dcec41..e04499b289d84 100644 --- a/soc/arm/nxp_imx/rt6xx/soc.c +++ b/soc/arm/nxp_imx/rt6xx/soc.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/soc/arm/nxp_kinetis/k2x/linker.ld b/soc/arm/nxp_kinetis/k2x/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/k2x/linker.ld +++ b/soc/arm/nxp_kinetis/k2x/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/k6x/linker.ld b/soc/arm/nxp_kinetis/k6x/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/k6x/linker.ld +++ b/soc/arm/nxp_kinetis/k6x/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c b/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c index 8108ca7df8820..41d0df3d6896b 100644 --- a/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c +++ b/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include +#include static const struct nxp_mpu_region mpu_regions[] = { /* Region 0 */ diff --git a/soc/arm/nxp_kinetis/k8x/linker.ld b/soc/arm/nxp_kinetis/k8x/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/k8x/linker.ld +++ b/soc/arm/nxp_kinetis/k8x/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c b/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c index d7bcce1cd9bd7..599f1e149efd5 100644 --- a/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c +++ b/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include +#include static const struct nxp_mpu_region mpu_regions[] = { /* Region 0 */ diff --git a/soc/arm/nxp_kinetis/ke1xf/linker.ld b/soc/arm/nxp_kinetis/ke1xf/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/ke1xf/linker.ld +++ b/soc/arm/nxp_kinetis/ke1xf/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c b/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c index d7bcce1cd9bd7..599f1e149efd5 100644 --- a/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c +++ b/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include +#include static const struct nxp_mpu_region mpu_regions[] = { /* Region 0 */ diff --git a/soc/arm/nxp_kinetis/kl2x/linker.ld b/soc/arm/nxp_kinetis/kl2x/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/kl2x/linker.ld +++ b/soc/arm/nxp_kinetis/kl2x/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/kv5x/linker.ld b/soc/arm/nxp_kinetis/kv5x/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/kv5x/linker.ld +++ b/soc/arm/nxp_kinetis/kv5x/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_kinetis/kwx/linker.ld b/soc/arm/nxp_kinetis/kwx/linker.ld index 5d6126629f9f9..7a1df7beaa524 100644 --- a/soc/arm/nxp_kinetis/kwx/linker.ld +++ b/soc/arm/nxp_kinetis/kwx/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images and XIP images. */ -#include +#include diff --git a/soc/arm/nxp_lpc/lpc11u6x/linker.ld b/soc/arm/nxp_lpc/lpc11u6x/linker.ld index d729ed4c3a747..ad9319b497743 100644 --- a/soc/arm/nxp_lpc/lpc11u6x/linker.ld +++ b/soc/arm/nxp_lpc/lpc11u6x/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/nxp_lpc/lpc51u68/linker.ld b/soc/arm/nxp_lpc/lpc51u68/linker.ld index 1023aa660055f..8724d8f68dd91 100644 --- a/soc/arm/nxp_lpc/lpc51u68/linker.ld +++ b/soc/arm/nxp_lpc/lpc51u68/linker.ld @@ -9,4 +9,4 @@ */ __Vectors = _vector_table; -#include +#include diff --git a/soc/arm/nxp_lpc/lpc54xxx/linker.ld b/soc/arm/nxp_lpc/lpc54xxx/linker.ld index 817f1d948d038..b6a1fb0bbcc22 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/linker.ld +++ b/soc/arm/nxp_lpc/lpc54xxx/linker.ld @@ -16,4 +16,4 @@ */ __Vectors = _vector_table; -#include +#include diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c index df7e5ac1c06ee..bbc689dbc68d1 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c @@ -18,7 +18,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/soc/arm/nxp_lpc/lpc55xxx/linker.ld b/soc/arm/nxp_lpc/lpc55xxx/linker.ld index e7c360409f75a..186914f102c70 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/linker.ld +++ b/soc/arm/nxp_lpc/lpc55xxx/linker.ld @@ -17,4 +17,4 @@ __Vectors = _vector_table; -#include +#include diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c index 8f756b39c3dc4..a16b5c959f0d1 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/soc/arm/nxp_s32/s32k/linker.ld b/soc/arm/nxp_s32/s32k/linker.ld index dbbca346ba01b..8681f1cd3f380 100644 --- a/soc/arm/nxp_s32/s32k/linker.ld +++ b/soc/arm/nxp_s32/s32k/linker.ld @@ -12,4 +12,4 @@ MEMORY } #endif -#include +#include diff --git a/soc/arm/nxp_s32/s32k/mpu_regions.c b/soc/arm/nxp_s32/s32k/mpu_regions.c index 9c4316d0aa932..48078bde6bfb6 100644 --- a/soc/arm/nxp_s32/s32k/mpu_regions.c +++ b/soc/arm/nxp_s32/s32k/mpu_regions.c @@ -6,7 +6,7 @@ #include #include -#include +#include #if !defined(CONFIG_XIP) extern char _rom_attr[]; diff --git a/soc/arm/nxp_s32/s32ze/linker.ld b/soc/arm/nxp_s32/s32ze/linker.ld index c8a7570e89156..d04a2dc6065b4 100644 --- a/soc/arm/nxp_s32/s32ze/linker.ld +++ b/soc/arm/nxp_s32/s32ze/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/nxp_s32/s32ze/mpu_regions.c b/soc/arm/nxp_s32/s32ze/mpu_regions.c index aa4109f492ff8..33c41d362b5da 100644 --- a/soc/arm/nxp_s32/s32ze/mpu_regions.c +++ b/soc/arm/nxp_s32/s32ze/mpu_regions.c @@ -5,7 +5,7 @@ */ #include -#include +#include #define DEVICE_REGION_START 0x40000000UL #define DEVICE_REGION_END 0x76FFFFFFUL diff --git a/soc/arm/quicklogic_eos_s3/linker.ld b/soc/arm/quicklogic_eos_s3/linker.ld index 448ac908598f9..5d2ea23f26669 100644 --- a/soc/arm/quicklogic_eos_s3/linker.ld +++ b/soc/arm/quicklogic_eos_s3/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/renesas_rcar/gen3/linker.ld b/soc/arm/renesas_rcar/gen3/linker.ld index 257f496c64d9d..f94542d9256e9 100644 --- a/soc/arm/renesas_rcar/gen3/linker.ld +++ b/soc/arm/renesas_rcar/gen3/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/renesas_smartbond/da1469x/linker.ld b/soc/arm/renesas_smartbond/da1469x/linker.ld index f3b675269bb1f..dfa36b95d49ca 100644 --- a/soc/arm/renesas_smartbond/da1469x/linker.ld +++ b/soc/arm/renesas_smartbond/da1469x/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/rpi_pico/rp2/linker.ld b/soc/arm/rpi_pico/rp2/linker.ld index bf594a89e9876..5e1db9a817588 100644 --- a/soc/arm/rpi_pico/rp2/linker.ld +++ b/soc/arm/rpi_pico/rp2/linker.ld @@ -26,4 +26,4 @@ SECTIONS } #endif /* CONFIG_RP2_REQUIRES_SECOND_STAGE_BOOT */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32gg11b/linker.ld b/soc/arm/silabs_exx32/efm32gg11b/linker.ld index 95b76e19ce04c..120507fb63f74 100644 --- a/soc/arm/silabs_exx32/efm32gg11b/linker.ld +++ b/soc/arm/silabs_exx32/efm32gg11b/linker.ld @@ -13,4 +13,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32gg12b/linker.ld b/soc/arm/silabs_exx32/efm32gg12b/linker.ld index c7955ec596c97..f478ff72c4021 100644 --- a/soc/arm/silabs_exx32/efm32gg12b/linker.ld +++ b/soc/arm/silabs_exx32/efm32gg12b/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images. */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32hg/linker.ld b/soc/arm/silabs_exx32/efm32hg/linker.ld index ff791e999d260..da96a05932a68 100644 --- a/soc/arm/silabs_exx32/efm32hg/linker.ld +++ b/soc/arm/silabs_exx32/efm32hg/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32jg12b/linker.ld b/soc/arm/silabs_exx32/efm32jg12b/linker.ld index e93018c0980cc..cb2bbd2fdf1c7 100644 --- a/soc/arm/silabs_exx32/efm32jg12b/linker.ld +++ b/soc/arm/silabs_exx32/efm32jg12b/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32pg12b/linker.ld b/soc/arm/silabs_exx32/efm32pg12b/linker.ld index e93018c0980cc..cb2bbd2fdf1c7 100644 --- a/soc/arm/silabs_exx32/efm32pg12b/linker.ld +++ b/soc/arm/silabs_exx32/efm32pg12b/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32pg1b/linker.ld b/soc/arm/silabs_exx32/efm32pg1b/linker.ld index e93018c0980cc..cb2bbd2fdf1c7 100644 --- a/soc/arm/silabs_exx32/efm32pg1b/linker.ld +++ b/soc/arm/silabs_exx32/efm32pg1b/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efm32wg/linker.ld b/soc/arm/silabs_exx32/efm32wg/linker.ld index 7c8c33eb93724..d877abf5fd4fd 100644 --- a/soc/arm/silabs_exx32/efm32wg/linker.ld +++ b/soc/arm/silabs_exx32/efm32wg/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32bg13p/linker.ld b/soc/arm/silabs_exx32/efr32bg13p/linker.ld index b0530df09bd91..09c3e1cf94344 100644 --- a/soc/arm/silabs_exx32/efr32bg13p/linker.ld +++ b/soc/arm/silabs_exx32/efr32bg13p/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32bg22/linker.ld b/soc/arm/silabs_exx32/efr32bg22/linker.ld index 9fcfb60618db0..38d9b250c5b08 100644 --- a/soc/arm/silabs_exx32/efr32bg22/linker.ld +++ b/soc/arm/silabs_exx32/efr32bg22/linker.ld @@ -11,4 +11,4 @@ * This is the linker script for both standard images. */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32bg27/linker.ld b/soc/arm/silabs_exx32/efr32bg27/linker.ld index 77214fcef49a7..b65086a5ce154 100644 --- a/soc/arm/silabs_exx32/efr32bg27/linker.ld +++ b/soc/arm/silabs_exx32/efr32bg27/linker.ld @@ -2,4 +2,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32fg13p/linker.ld b/soc/arm/silabs_exx32/efr32fg13p/linker.ld index e93018c0980cc..cb2bbd2fdf1c7 100644 --- a/soc/arm/silabs_exx32/efr32fg13p/linker.ld +++ b/soc/arm/silabs_exx32/efr32fg13p/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32fg1p/linker.ld b/soc/arm/silabs_exx32/efr32fg1p/linker.ld index e93018c0980cc..cb2bbd2fdf1c7 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/linker.ld +++ b/soc/arm/silabs_exx32/efr32fg1p/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32mg12p/linker.ld b/soc/arm/silabs_exx32/efr32mg12p/linker.ld index b0530df09bd91..09c3e1cf94344 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/linker.ld +++ b/soc/arm/silabs_exx32/efr32mg12p/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32mg21/linker.ld b/soc/arm/silabs_exx32/efr32mg21/linker.ld index d61039d397a0d..7295169eae8aa 100644 --- a/soc/arm/silabs_exx32/efr32mg21/linker.ld +++ b/soc/arm/silabs_exx32/efr32mg21/linker.ld @@ -12,4 +12,4 @@ */ -#include +#include diff --git a/soc/arm/silabs_exx32/efr32mg24/linker.ld b/soc/arm/silabs_exx32/efr32mg24/linker.ld index d83e2a6653046..0d44f86361317 100644 --- a/soc/arm/silabs_exx32/efr32mg24/linker.ld +++ b/soc/arm/silabs_exx32/efr32mg24/linker.ld @@ -13,4 +13,4 @@ #include -#include +#include diff --git a/soc/arm/st_stm32/stm32c0/linker.ld b/soc/arm/st_stm32/stm32c0/linker.ld index fda50c307af00..d5f07ed942a1f 100644 --- a/soc/arm/st_stm32/stm32c0/linker.ld +++ b/soc/arm/st_stm32/stm32c0/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f0/linker.ld b/soc/arm/st_stm32/stm32f0/linker.ld index 876802cb7ee09..c39286d86f52c 100644 --- a/soc/arm/st_stm32/stm32f0/linker.ld +++ b/soc/arm/st_stm32/stm32f0/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f1/linker.ld b/soc/arm/st_stm32/stm32f1/linker.ld index 876802cb7ee09..c39286d86f52c 100644 --- a/soc/arm/st_stm32/stm32f1/linker.ld +++ b/soc/arm/st_stm32/stm32f1/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f2/linker.ld b/soc/arm/st_stm32/stm32f2/linker.ld index 83708c438f6e9..b5f5c77d59c27 100644 --- a/soc/arm/st_stm32/stm32f2/linker.ld +++ b/soc/arm/st_stm32/stm32f2/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f3/linker.ld b/soc/arm/st_stm32/stm32f3/linker.ld index 876802cb7ee09..c39286d86f52c 100644 --- a/soc/arm/st_stm32/stm32f3/linker.ld +++ b/soc/arm/st_stm32/stm32f3/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f4/linker.ld b/soc/arm/st_stm32/stm32f4/linker.ld index 876802cb7ee09..c39286d86f52c 100644 --- a/soc/arm/st_stm32/stm32f4/linker.ld +++ b/soc/arm/st_stm32/stm32f4/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32f7/linker.ld b/soc/arm/st_stm32/stm32f7/linker.ld index bf8d6789236ec..be06b7accb609 100644 --- a/soc/arm/st_stm32/stm32f7/linker.ld +++ b/soc/arm/st_stm32/stm32f7/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32g0/linker.ld b/soc/arm/st_stm32/stm32g0/linker.ld index e5b8916fc1ffa..a5c6d669295d7 100644 --- a/soc/arm/st_stm32/stm32g0/linker.ld +++ b/soc/arm/st_stm32/stm32g0/linker.ld @@ -7,4 +7,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32g4/linker.ld b/soc/arm/st_stm32/stm32g4/linker.ld index 954d9eb75875b..8053c5cfc1164 100644 --- a/soc/arm/st_stm32/stm32g4/linker.ld +++ b/soc/arm/st_stm32/stm32g4/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32h5/linker.ld b/soc/arm/st_stm32/stm32h5/linker.ld index 8bd989bc732f4..f20e6999579b3 100644 --- a/soc/arm/st_stm32/stm32h5/linker.ld +++ b/soc/arm/st_stm32/stm32h5/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32h7/linker.ld b/soc/arm/st_stm32/stm32h7/linker.ld index 078ef2a807b1e..20713e9bfd3b8 100644 --- a/soc/arm/st_stm32/stm32h7/linker.ld +++ b/soc/arm/st_stm32/stm32h7/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32h7/mpu_regions.c b/soc/arm/st_stm32/stm32h7/mpu_regions.c index f2ba721d2dff5..01daccdd01df6 100644 --- a/soc/arm/st_stm32/stm32h7/mpu_regions.c +++ b/soc/arm/st_stm32/stm32h7/mpu_regions.c @@ -5,7 +5,7 @@ */ #include -#include +#include static const struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS, diff --git a/soc/arm/st_stm32/stm32l0/linker.ld b/soc/arm/st_stm32/stm32l0/linker.ld index 268542adab16f..31b070c6950f4 100644 --- a/soc/arm/st_stm32/stm32l0/linker.ld +++ b/soc/arm/st_stm32/stm32l0/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32l1/linker.ld b/soc/arm/st_stm32/stm32l1/linker.ld index 48056b3970882..0bbb83d949ba2 100644 --- a/soc/arm/st_stm32/stm32l1/linker.ld +++ b/soc/arm/st_stm32/stm32l1/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32l4/linker.ld b/soc/arm/st_stm32/stm32l4/linker.ld index 876802cb7ee09..c39286d86f52c 100644 --- a/soc/arm/st_stm32/stm32l4/linker.ld +++ b/soc/arm/st_stm32/stm32l4/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32l5/linker.ld b/soc/arm/st_stm32/stm32l5/linker.ld index 484e77214bea2..987547b1ee1b3 100644 --- a/soc/arm/st_stm32/stm32l5/linker.ld +++ b/soc/arm/st_stm32/stm32l5/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32mp1/linker.ld b/soc/arm/st_stm32/stm32mp1/linker.ld index 1ff5da841e594..7f9a84501ef11 100644 --- a/soc/arm/st_stm32/stm32mp1/linker.ld +++ b/soc/arm/st_stm32/stm32mp1/linker.ld @@ -7,7 +7,7 @@ */ -#include +#include SECTIONS { diff --git a/soc/arm/st_stm32/stm32u5/linker.ld b/soc/arm/st_stm32/stm32u5/linker.ld index c28ef22f9a00a..a5b0e37e825ff 100644 --- a/soc/arm/st_stm32/stm32u5/linker.ld +++ b/soc/arm/st_stm32/stm32u5/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32wb/linker.ld b/soc/arm/st_stm32/stm32wb/linker.ld index 078ef2a807b1e..20713e9bfd3b8 100644 --- a/soc/arm/st_stm32/stm32wb/linker.ld +++ b/soc/arm/st_stm32/stm32wb/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32wba/linker.ld b/soc/arm/st_stm32/stm32wba/linker.ld index 8bd989bc732f4..f20e6999579b3 100644 --- a/soc/arm/st_stm32/stm32wba/linker.ld +++ b/soc/arm/st_stm32/stm32wba/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/st_stm32/stm32wl/linker.ld b/soc/arm/st_stm32/stm32wl/linker.ld index 8050cf9b60c77..c81df32357e9c 100644 --- a/soc/arm/st_stm32/stm32wl/linker.ld +++ b/soc/arm/st_stm32/stm32wl/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/ti_k3/am62x_m4/linker.ld b/soc/arm/ti_k3/am62x_m4/linker.ld index 793177b7f7242..5e478a0541ff0 100644 --- a/soc/arm/ti_k3/am62x_m4/linker.ld +++ b/soc/arm/ti_k3/am62x_m4/linker.ld @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include SECTIONS { diff --git a/soc/arm/ti_lm3s6965/linker.ld b/soc/arm/ti_lm3s6965/linker.ld index 96ec397da785b..757d858cb690a 100644 --- a/soc/arm/ti_lm3s6965/linker.ld +++ b/soc/arm/ti_lm3s6965/linker.ld @@ -6,4 +6,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/linker.ld b/soc/arm/ti_simplelink/cc13x2_cc26x2/linker.ld index 42f44928045b7..643b4899397da 100644 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/linker.ld +++ b/soc/arm/ti_simplelink/cc13x2_cc26x2/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld index f7ba43c42ca7a..772be96ca3baf 100644 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/ti_simplelink/cc32xx/linker.ld b/soc/arm/ti_simplelink/cc32xx/linker.ld index e8b364e4dcff2..812d6f503317d 100644 --- a/soc/arm/ti_simplelink/cc32xx/linker.ld +++ b/soc/arm/ti_simplelink/cc32xx/linker.ld @@ -5,4 +5,4 @@ * linker.ld - Linker command/script file */ -#include +#include diff --git a/soc/arm/ti_simplelink/msp432p4xx/linker.ld b/soc/arm/ti_simplelink/msp432p4xx/linker.ld index e8b364e4dcff2..812d6f503317d 100644 --- a/soc/arm/ti_simplelink/msp432p4xx/linker.ld +++ b/soc/arm/ti_simplelink/msp432p4xx/linker.ld @@ -5,4 +5,4 @@ * linker.ld - Linker command/script file */ -#include +#include diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/linker.ld b/soc/arm/xilinx_zynq7000/xc7zxxx/linker.ld index 38f1212398db2..00ffe9ceff3ad 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/linker.ld +++ b/soc/arm/xilinx_zynq7000/xc7zxxx/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c index 5c7317ac3f748..a8d3eab7c737b 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c +++ b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "soc.h" /* System Level Control Registers (SLCR) */ diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/linker.ld b/soc/arm/xilinx_zynq7000/xc7zxxxs/linker.ld index 38f1212398db2..00ffe9ceff3ad 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/linker.ld +++ b/soc/arm/xilinx_zynq7000/xc7zxxxs/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c index 7f794c5e9f7d2..66e17b56bc9eb 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c +++ b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "soc.h" /* System Level Configuration Registers */ diff --git a/soc/arm/xilinx_zynqmp/arm_mpu_regions.c b/soc/arm/xilinx_zynqmp/arm_mpu_regions.c index f10ba5d94e05b..5a6f8dc6c2110 100644 --- a/soc/arm/xilinx_zynqmp/arm_mpu_regions.c +++ b/soc/arm/xilinx_zynqmp/arm_mpu_regions.c @@ -4,7 +4,7 @@ */ #include -#include +#include #define MPUTYPE_READ_ONLY \ { \ diff --git a/soc/arm/xilinx_zynqmp/linker.ld b/soc/arm/xilinx_zynqmp/linker.ld index 744cd1c5f36dc..4f22c8618cf50 100644 --- a/soc/arm/xilinx_zynqmp/linker.ld +++ b/soc/arm/xilinx_zynqmp/linker.ld @@ -7,5 +7,5 @@ #if defined(CONFIG_SOC_XILINX_ZYNQMP_RPU) -#include +#include #endif diff --git a/soc/riscv/openisa_rv32m1/linker.ld b/soc/riscv/openisa_rv32m1/linker.ld index 7ade2d4e8dd3c..784ba791722bf 100644 --- a/soc/riscv/openisa_rv32m1/linker.ld +++ b/soc/riscv/openisa_rv32m1/linker.ld @@ -5,7 +5,7 @@ * * This file is based on: * - * - include/arch/arm/aarch32/cortex_m/scripts/linker.ld + * - include/arch/arm/cortex_m/scripts/linker.ld * - include/arch/riscv/common/linker.ld * - include/arch/riscv/pulpino/linker.ld * diff --git a/tests/arch/arm/arm_irq_vector_table/irq-vector-table.ld b/tests/arch/arm/arm_irq_vector_table/irq-vector-table.ld index 833b94a26b0da..5f25268a2c721 100644 --- a/tests/arch/arm/arm_irq_vector_table/irq-vector-table.ld +++ b/tests/arch/arm/arm_irq_vector_table/irq-vector-table.ld @@ -5,6 +5,6 @@ KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS)) /* * Some ARM platforms require this symbol to be placed after the IRQ vector * table (like STM32F0). The symbol defined here is overriding the one in - * arch/arm/core/aarch32/vector_table.ld when the IRQ vector table is enabled. + * arch/arm/core/vector_table.ld when the IRQ vector table is enabled. */ _vector_end = .; diff --git a/tests/arch/arm/arm_mpu_regions/src/main.c b/tests/arch/arm/arm_mpu_regions/src/main.c index ec784787bb4d7..72df578f2c0af 100644 --- a/tests/arch/arm/arm_mpu_regions/src/main.c +++ b/tests/arch/arm/arm_mpu_regions/src/main.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include diff --git a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c index 870993c59e710..79a4bbedca3c0 100644 --- a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c +++ b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/tests/arch/arm/arm_tz_wrap_func/src/main.c b/tests/arch/arm/arm_tz_wrap_func/src/main.c index 0323bd5061768..407873f906b70 100644 --- a/tests/arch/arm/arm_tz_wrap_func/src/main.c +++ b/tests/arch/arm/arm_tz_wrap_func/src/main.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include static bool expect_preface;