diff --git a/boards/arm64/rcar_spider/Kconfig.board b/boards/arm64/rcar_spider/Kconfig.board new file mode 100644 index 0000000000000..bbb06ebeedb20 --- /dev/null +++ b/boards/arm64/rcar_spider/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SPIDER + bool "Renesas Spider" + depends on SOC_R8A779F diff --git a/boards/arm64/rcar_spider/Kconfig.defconfig b/boards/arm64/rcar_spider/Kconfig.defconfig new file mode 100644 index 0000000000000..7309a995e09aa --- /dev/null +++ b/boards/arm64/rcar_spider/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RCAR_SPIDER + +config BOARD + default "rcar_spider" + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_RCAR_SPIDER diff --git a/boards/arm64/rcar_spider/doc/index.rst b/boards/arm64/rcar_spider/doc/index.rst new file mode 100644 index 0000000000000..e79985187fe20 --- /dev/null +++ b/boards/arm64/rcar_spider/doc/index.rst @@ -0,0 +1,80 @@ +.. _rcar_spider: + +R-CAR Spider (ARMv8) +##################################### +Note: currently, the board can be used only as a Xen Initial Domain, i.e. Dom0, +because there isn't support of UART driver. So, it can be built only with ``xen_dom0`` +shield. + +Overview +******** +The R-Car Spider (S4) is an SOC that features the basic functions for +next-generation car Gateway systems. + +Hardware +******** +The R-Car S4 includes: + +* eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters; +* 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported); +* two 400MHz G4MH cores (hardware Lock step is supported); +* memory controller for LPDDR4X-3200 with 32bit bus (16bit x 1ch + 16bit x 1ch) with ECC; +* SD card host interface / eMMC; +* UFS 3.0 x 1 channel; +* PCI Express Gen4.0 interface (Dual lane x 2ch); +* ICUMX; +* ICUMH; +* SHIP-S x 3 channels; +* AES Accerator x 8 channels; +* CAN FD interface x 16 channels; +* R-Switch2 (Ether); +* 100base EtherAVB x 1 channel; +* Gbit-EtherTSN x 3 channels; +* 1 unit FlexRay (A,B 2ch) interface. + +Supported Features +================== +The Renesas rcar_spider board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| MMC | renesas_rcar_mmc | | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file: + + ``boards/arm64/rcar_spider/rcar_spider_defconfig`` + +Programming and Debugging +************************* + +Correct shield designation for Xen must be entered when you invoke ``west build``. +For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :board: rcar_spider + :shield: xen_dom0 + :goals: build + +For more details, look at documentation of ``xen_dom0`` shield. + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux Spider page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux Spider page: + https://elinux.org/R-Car/Boards/Spider diff --git a/boards/arm64/rcar_spider/rcar_spider.dts b/boards/arm64/rcar_spider/rcar_spider.dts new file mode 100644 index 0000000000000..be3deeb1e4adf --- /dev/null +++ b/boards/arm64/rcar_spider/rcar_spider.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include "spider-pinctrl.dtsi" + +/ { + model = "Spider (S4)"; + chosen { + zephyr,sram = &ram; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + sdhc0 = &mmc0; + }; + + ram: memory@48000000 { + device_type = "mmio-sram"; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_clk &mmc_cmd &mmc_ds + &mmc_data0 &mmc_data1 &mmc_data2 &mmc_data3 + &mmc_data4 &mmc_data5 &mmc_data6 &mmc_data7>; + pinctrl-1 = <&mmc_clk &mmc_cmd &mmc_ds + &mmc_data0 &mmc_data1 &mmc_data2 &mmc_data3 + &mmc_data4 &mmc_data5 &mmc_data6 &mmc_data7>; + pinctrl-names = "default", "uhs"; + disk { + compatible = "zephyr,mmc-disk"; + status = "disabled"; + }; + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; +}; diff --git a/boards/arm64/rcar_spider/rcar_spider.yaml b/boards/arm64/rcar_spider/rcar_spider.yaml new file mode 100644 index 0000000000000..dccc9a1f97af4 --- /dev/null +++ b/boards/arm64/rcar_spider/rcar_spider.yaml @@ -0,0 +1,17 @@ +identifier: rcar_spider +name: Renesas Spider based on r8a779f (S4) +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - clock_control + - uart +testing: + default: true + ignore_tags: + - net + - bluetooth + - isotp diff --git a/boards/arm64/rcar_spider/rcar_spider_defconfig b/boards/arm64/rcar_spider/rcar_spider_defconfig new file mode 100644 index 0000000000000..967a15bf27ebf --- /dev/null +++ b/boards/arm64/rcar_spider/rcar_spider_defconfig @@ -0,0 +1,21 @@ +CONFIG_SOC_R8A779F=y +CONFIG_SOC_SERIES_RCAR_GEN4=y +CONFIG_BOARD_RCAR_SPIDER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=16666000 +CONFIG_XIP=n + +CONFIG_MAX_XLAT_TABLES=24 + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm64/rcar_spider/spider-pinctrl.dtsi b/boards/arm64/rcar_spider/spider-pinctrl.dtsi new file mode 100644 index 0000000000000..1cae503c5d21f --- /dev/null +++ b/boards/arm64/rcar_spider/spider-pinctrl.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pfc { + mmc_clk: mmc_clk { + pin = ; + }; + + mmc_cmd: mmc_cmd { + pin = ; + }; + + mmc_data0: mmc_data0 { + pin = ; + }; + + mmc_data1: mmc_data1 { + pin = ; + }; + + mmc_data2: mmc_data2 { + pin = ; + }; + + mmc_data3: mmc_data3 { + pin = ; + }; + + mmc_data4: mmc_data4 { + pin = ; + }; + + mmc_data5: mmc_data5 { + pin = ; + }; + + mmc_data6: mmc_data6 { + pin = ; + }; + + mmc_data7: mmc_data7 { + pin = ; + }; + + mmc_ds: mmc_ds { + pin = ; + }; +}; diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index c2542965ead1c..1c1d248e25f00 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -64,6 +64,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex.c) if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR) zephyr_library_sources(clock_control_renesas_cpg_mssr.c) zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED clock_control_r8a7795_cpg_mssr.c) + zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A779F_CPG_MSSR_ENABLED clock_control_r8a779f_cpg_mssr.c) endif() zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c) diff --git a/drivers/clock_control/Kconfig.rcar b/drivers/clock_control/Kconfig.rcar index b4a69a47e355e..d8cba993f8053 100644 --- a/drivers/clock_control/Kconfig.rcar +++ b/drivers/clock_control/Kconfig.rcar @@ -4,6 +4,6 @@ config CLOCK_CONTROL_RCAR_CPG_MSSR bool "RCar CPG MSSR driver" default y - depends on DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED + depends on DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED || DT_HAS_RENESAS_R8A779F_CPG_MSSR_ENABLED help Enable support for Renesas RCar CPG MSSR driver. diff --git a/drivers/clock_control/clock_control_r8a779f_cpg_mssr.c b/drivers/clock_control/clock_control_r8a779f_cpg_mssr.c new file mode 100644 index 0000000000000..03b2103a5898a --- /dev/null +++ b/drivers/clock_control/clock_control_r8a779f_cpg_mssr.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * r8a779f Clock Pulse Generator / Module Standby and Software Reset + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_r8a779f_cpg_mssr + +#include +#include +#include +#include +#include +#include +#include +#include "clock_control_renesas_cpg_mssr.h" + +#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL +#include +LOG_MODULE_DECLARE(clock_control_rcar); + +#define R8A779F_CLK_SD_STOP_BIT 8 +#define R8A779F_CLK_SD_DIV_MASK 0x3 +#define R8A779F_CLK_SD_DIV_SHIFT 0 + +#define R8A779F_CLK_SDH_STOP_BIT 9 +#define R8A779F_CLK_SDH_DIV_MASK 0x7 +#define R8A779F_CLK_SDH_DIV_SHIFT 2 + +#define R8A779F_CLK_SD0CKCR1_DIV_MASK 0x3 +#define R8A779F_CLK_SD0CKCR1_DIV_SHIFT 29 + +struct r8a779f_cpg_mssr_cfg { + DEVICE_MMIO_ROM; /* Must be first */ +}; + +struct r8a779f_cpg_mssr_data { + struct rcar_cpg_mssr_data cmn; /* Must be first */ +}; + +/* NOTE: the array MUST be sorted by module field */ +static struct cpg_clk_info_table core_props[] = { + RCAR_CORE_CLK_INFO_ITEM(R8A779F_CLK_PLL5VCO, RCAR_CPG_NONE, + RCAR_CPG_NONE, RCAR_CPG_MHZ(3200)), + + RCAR_CORE_CLK_INFO_ITEM(R8A779F_CLK_SD0CKCR1, 0x08A4, R8A779F_CLK_PLL5VCO, RCAR_CPG_NONE), + RCAR_CORE_CLK_INFO_ITEM(R8A779F_CLK_SDH, 0x0870, R8A779F_CLK_SD0CKCR1, RCAR_CPG_NONE), + RCAR_CORE_CLK_INFO_ITEM(R8A779F_CLK_SD, 0x0870, R8A779F_CLK_SDH, RCAR_CPG_NONE), +}; + +/* NOTE: the array MUST be sorted by module field */ +static struct cpg_clk_info_table mod_props[] = { + RCAR_MOD_CLK_INFO_ITEM(706, R8A779F_CLK_SD), +}; + + +static int r8a779f_cpg_enable_disable_core(const struct device *dev, + struct cpg_clk_info_table *clk_info, + uint32_t enable) +{ + int ret = 0; + uint32_t reg; + + enable = !!enable; + + switch (clk_info->module) { + case R8A779F_CLK_SD0CKCR1: + return 0; + case R8A779F_CLK_SD: + reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); + reg &= ~(1 << R8A779F_CLK_SD_STOP_BIT); + reg |= (!enable << R8A779F_CLK_SD_STOP_BIT); + break; + case R8A779F_CLK_SDH: + reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); + reg &= ~(1 << R8A779F_CLK_SDH_STOP_BIT); + reg |= (!enable << R8A779F_CLK_SDH_STOP_BIT); + break; + default: + ret = -ENOTSUP; + break; + } + + if (!ret) { + rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); + } + return ret; +} + +static int r8a779f_cpg_core_clock_endisable(const struct device *dev, + struct rcar_cpg_clk *clk, + bool enable) +{ + struct cpg_clk_info_table *clk_info; + struct r8a779f_cpg_mssr_data *data = dev->data; + k_spinlock_key_t key; + int ret = 0; + + clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); + if (!clk_info) { + return -EINVAL; + } + + if (enable) { + if (clk->rate > 0) { + uintptr_t rate = clk->rate; + + ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, + (clock_control_subsys_rate_t)rate); + if (ret < 0) { + return ret; + } + } + } + + key = k_spin_lock(&data->cmn.lock); + r8a779f_cpg_enable_disable_core(dev, clk_info, enable); + k_spin_unlock(&data->cmn.lock, key); + + return ret; +} + +int r8a779f_cpg_mssr_start_stop(const struct device *dev, + clock_control_subsys_t sys, bool enable) +{ + const struct r8a779f_cpg_mssr_cfg *config; + struct r8a779f_cpg_mssr_data *data; + struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; + int ret = -EINVAL; + k_spinlock_key_t key; + + if (!dev || !sys) { + return -EINVAL; + } + + if (clk->domain == CPG_CORE) { + return r8a779f_cpg_core_clock_endisable(dev, clk, enable); + } + + config = dev->config; + data = dev->data; + + key = k_spin_lock(&data->cmn.lock); + ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); + k_spin_unlock(&data->cmn.lock, key); + return ret; +} + +static int r8a779f_cpg_mssr_start(const struct device *dev, + clock_control_subsys_t sys) +{ + return r8a779f_cpg_mssr_start_stop(dev, sys, true); +} + +static int r8a779f_cpg_mssr_stop(const struct device *dev, + clock_control_subsys_t sys) +{ + return r8a779f_cpg_mssr_start_stop(dev, sys, false); +} + +static int r8a779f_cpg_mssr_init(const struct device *dev) +{ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + + rcar_cpg_build_clock_relationship(dev); + rcar_cpg_update_all_in_out_freq(dev); + return 0; +} + +static uint32_t r8a779f_get_div_helper(uint32_t reg_val, uint32_t module) +{ + uint32_t divider = RCAR_CPG_NONE; + + switch (module) { + case R8A779F_CLK_SD0CKCR1: + reg_val >>= R8A779F_CLK_SD0CKCR1_DIV_SHIFT; + reg_val &= R8A779F_CLK_SD0CKCR1_DIV_MASK; + /* setting of 3 is prohibited */ + if (reg_val < 3) { + /* real divider is in range 4 - 6 */ + divider = reg_val + 4; + } + break; + case R8A779F_CLK_SDH: + reg_val >>= R8A779F_CLK_SDH_DIV_SHIFT; + /* setting of value bigger than 4 is prohibited */ + if ((reg_val & R8A779F_CLK_SDH_DIV_MASK) < 5) { + divider = 1 << (reg_val & R8A779F_CLK_SDH_DIV_MASK); + } + break; + case R8A779F_CLK_SD: + /* convert only two possible values 0,1 to 2,4 */ + divider = 1 << ((reg_val & R8A779F_CLK_SD_DIV_MASK) + 1); + break; + default: + break; + } + + return divider; +} + +static int r8a779f_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) +{ + int ret = -ENOTSUP; + + switch (module) { + case R8A779F_CLK_SD0CKCR1: + /* divider has to be in range 4-6 */ + if (*divider > 3 && *divider < 7) { + /* we can write to register value in range 0-2 */ + *divider -= 4; + *divider <<= R8A779F_CLK_SD0CKCR1_DIV_SHIFT; + *div_mask = R8A779F_CLK_SD0CKCR1_DIV_MASK << + R8A779F_CLK_SD0CKCR1_DIV_SHIFT; + ret = 0; + } else { + ret = -EINVAL; + } + break; + case R8A779F_CLK_SD: + /* possible to have only 2 or 4 */ + if (*divider == 2 || *divider == 4) { + /* convert 2/4 to 0/1 */ + *divider >>= 2; + *div_mask = R8A779F_CLK_SD_DIV_MASK << R8A779F_CLK_SD_DIV_SHIFT; + ret = 0; + } else { + ret = -EINVAL; + } + break; + case R8A779F_CLK_SDH: + /* diveder should be power of two number and last possible value 16 */ + if (!is_power_of_two(*divider) || *divider > 16) { + ret = -EINVAL; + break; + } + ret = 0; + /* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */ + *divider = (find_lsb_set(*divider) - 1) << R8A779F_CLK_SDH_DIV_SHIFT; + *div_mask = R8A779F_CLK_SDH_DIV_MASK << R8A779F_CLK_SDH_DIV_SHIFT; + break; + default: + break; + } + + return ret; +} + +static const struct clock_control_driver_api r8a779f_cpg_mssr_api = { + .on = r8a779f_cpg_mssr_start, + .off = r8a779f_cpg_mssr_stop, + .get_rate = rcar_cpg_get_rate, + .set_rate = rcar_cpg_set_rate, +}; + +#define R8A779F_MSSR_INIT(inst) \ + static struct r8a779f_cpg_mssr_cfg cpg_mssr##inst##_cfg = { \ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \ + }; \ + \ + static struct r8a779f_cpg_mssr_data cpg_mssr##inst##_data = { \ + .cmn.clk_info_table[CPG_CORE] = core_props, \ + .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \ + .cmn.clk_info_table[CPG_MOD] = mod_props, \ + .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \ + .cmn.get_div_helper = r8a779f_get_div_helper, \ + .cmn.set_rate_helper = r8a779f_set_rate_helper \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, \ + &r8a779f_cpg_mssr_init, \ + NULL, \ + &cpg_mssr##inst##_data, \ + &cpg_mssr##inst##_cfg, \ + PRE_KERNEL_1, \ + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ + &r8a779f_cpg_mssr_api); + +DT_INST_FOREACH_STATUS_OKAY(R8A779F_MSSR_INIT) diff --git a/drivers/clock_control/clock_control_renesas_cpg_mssr.h b/drivers/clock_control/clock_control_renesas_cpg_mssr.h index 13d3cbeeb4e46..a70580c8090e0 100644 --- a/drivers/clock_control/clock_control_renesas_cpg_mssr.h +++ b/drivers/clock_control/clock_control_renesas_cpg_mssr.h @@ -109,7 +109,35 @@ static const uint16_t srcr[] = { /* Peripherals Clocks */ #define S3D4_CLK_RATE 66600000 /* SCIF */ #define S0D12_CLK_RATE 66600000 /* PWM */ -#endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */ +#elif defined(CONFIG_SOC_SERIES_RCAR_GEN4) +/* Software Reset Clearing Register offsets */ +#define SRSTCLR(i) (0x2C80 + (i) * 4) + +/* CPG write protect offset */ +#define CPGWPR 0x0 + +/* Realtime Module Stop Control Register offsets */ +static const uint16_t mstpcr[] = { + 0x2D00, 0x2D04, 0x2D08, 0x2D0C, + 0x2D10, 0x2D14, 0x2D18, 0x2D1C, + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, + 0x2D30, 0x2D34, 0x2D38, 0x2D3C, + 0x2D40, 0x2D44, 0x2D48, 0x2D4C, + 0x2D50, 0x2D54, 0x2D58, 0x2D5C, + 0x2D60, 0x2D64, 0x2D68, 0x2D6C, +}; + +/* Software Reset Register offsets */ +static const uint16_t srcr[] = { + 0x2C00, 0x2C04, 0x2C08, 0x2C0C, + 0x2C10, 0x2C14, 0x2C18, 0x2C1C, + 0x2C20, 0x2C24, 0x2C28, 0x2C2C, + 0x2C30, 0x2C34, 0x2C38, 0x2C3C, + 0x2C40, 0x2C44, 0x2C48, 0x2C4C, + 0x2C50, 0x2C54, 0x2C58, 0x2C5C, + 0x2C60, 0x2C64, 0x2C68, 0x2C6C, +}; +#endif void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val); diff --git a/drivers/pinctrl/pfc_rcar.c b/drivers/pinctrl/pfc_rcar.c index 14529d42fe9a6..f0968cdcde54b 100644 --- a/drivers/pinctrl/pfc_rcar.c +++ b/drivers/pinctrl/pfc_rcar.c @@ -16,9 +16,20 @@ DEVICE_MMIO_TOPLEVEL_STATIC(pfc, DT_DRV_INST(0)); #define PFC_REG_BASE DEVICE_MMIO_TOPLEVEL_GET(pfc) + +#ifdef CONFIG_SOC_R8A779F +/* + * todo: add support of pin groups,the next registers + * offset is for a group 0 + */ +#define PFC_RCAR_PMMR 0x0 +#define PFC_RCAR_GPSR 0x040 +#define PFC_RCAR_IPSR 0x060 +#else #define PFC_RCAR_PMMR 0x0 #define PFC_RCAR_GPSR 0x100 #define PFC_RCAR_IPSR 0x200 +#endif /* * Each drive step is either encoded in 2 or 3 bits. @@ -165,6 +176,63 @@ int pfc_rcar_set_bias(uint16_t pin, uint16_t flags) return 0; } +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +static const struct pfc_pocctrl_reg *pfc_rcar_get_pocctrl_reg(uint16_t pin, uint8_t *bit) +{ + const struct pfc_pocctrl_reg *voltage_regs = pfc_rcar_get_io_voltage_regs(); + + BUILD_ASSERT(ARRAY_SIZE(voltage_regs->pins) < UINT8_MAX); + + /* Loop around all the registers to find the bit for a given pin */ + while (voltage_regs && voltage_regs->offset) { + uint8_t i; + + for (i = 0U; i < ARRAY_SIZE(voltage_regs->pins); i++) { + if (voltage_regs->pins[i] == pin) { + *bit = i; + return voltage_regs; + } + } + voltage_regs++; + } + + return NULL; +} + +static void pfc_rcar_set_voltage(uint16_t pin, uint16_t voltage) +{ + uint32_t val; + uint8_t bit; + const struct pfc_pocctrl_reg *voltage_reg; + + voltage_reg = pfc_rcar_get_pocctrl_reg(pin, &bit); + if (!voltage_reg) { + return; + } + + val = sys_read32(PFC_REG_BASE + voltage_reg->offset); + + switch (voltage) { + case PIN_VOLTAGE_1P8V: + if (!(val & BIT(bit))) { + return; + } + val &= ~BIT(bit); + break; + case PIN_VOLTAGE_3P3V: + if (val & BIT(bit)) { + return; + } + val |= BIT(bit); + break; + default: + break; + } + + pfc_rcar_write(voltage_reg->offset, val); +} +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) { int ret = 0; @@ -177,6 +245,12 @@ int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) return -EINVAL; } +#ifdef CONFIG_PIN_VOLTAGE_CONTROL + if (pin->voltage != PIN_VOLTAGE_NONE) { + pfc_rcar_set_voltage(pin->pin, pin->voltage); + } +#endif + /* Select function for pin */ if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) != 0U) { pfc_rcar_set_ipsr(&pin->func); diff --git a/dts/arm64/renesas/r8a779f.dtsi b/dts/arm64/renesas/r8a779f.dtsi new file mode 100644 index 0000000000000..2d2aec946f2ad --- /dev/null +++ b/dts/arm64/renesas/r8a779f.dtsi @@ -0,0 +1,91 @@ +/* + * Device Tree Source for the R-Car S4 (R8A779F) SoC + * + * Copyright (C) 2023 EPAM Systems. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a779f"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a55: cpu@0 { + compatible = "arm,armv8"; + reg = <0>; + device_type = "cpu"; + /* todo: fix bindings for a55 */ + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-600", "arm,gic-v3", "arm,gic"; + #interrupt-cells = <4>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1000000 0 0x20000>, + <0 0xf1060000 0 0x110000>; + status = "okay"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779f-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,rcar-mmc"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F_CLK_SDH>; + max-frequency = <200000000>; + status = "disabled"; + }; + + pfc: pin-controller@e6050000 { + compatible = "renesas,rcar-pfc"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>, + <0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>, + <0 0xdfd91000 0 0x16c>, <0 0xdfd91800 0 0x16c>; + }; + }; +}; diff --git a/dts/bindings/clock/renesas,r8a779f-cpg-mssr.yaml b/dts/bindings/clock/renesas,r8a779f-cpg-mssr.yaml new file mode 100644 index 0000000000000..7031678270c8d --- /dev/null +++ b/dts/bindings/clock/renesas,r8a779f-cpg-mssr.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas R8A779F SoC Clock Pulse Generator / Module Standby and Software Reset + +compatible: "renesas,r8a779f-cpg-mssr" + +include: renesas,rcar-cpg-mssr.yaml diff --git a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml index fa94cd11c05eb..8d7ee2c6bbb5b 100644 --- a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml +++ b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml @@ -51,6 +51,7 @@ description: | - bias-pull-down - bias-pull-up - drive-strength + - power-source To link pin configurations with a device, use a pinctrl-N property for some number N, like this example you could place in your board's DTS file: @@ -82,6 +83,7 @@ child-binding: - bias-pull-down - bias-pull-up - drive-strength + - power-source properties: pin: diff --git a/include/zephyr/dt-bindings/clock/r8a779f_cpg_mssr.h b/include/zephyr/dt-bindings/clock/r8a779f_cpg_mssr.h new file mode 100644 index 0000000000000..c82069a019011 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/r8a779f_cpg_mssr.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F_H_ + +#include "renesas_cpg_mssr.h" + +/* r8a779f CPG Core Clocks */ +#define R8A779F_CLK_PLL5VCO 10 +#define R8A779F_CLK_SD0CKCR1 11 +#define R8A779F_CLK_SDH 12 +#define R8A779F_CLK_SD 13 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f.h new file mode 100644 index 0000000000000..6a382e6f6e2d3 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_ + +#include "pinctrl-rcar-common.h" + +/* Pins declaration */ +#define PIN_NONE -1 + +/* + * note: we don't need ipsr configuration for sd/mmc pins, + * they don't have alternative functions. + */ +#define PIN_SD_WP RCAR_GP_PIN(1, 24) +#define PIN_SD_CD RCAR_GP_PIN(1, 23) +#define PIN_MMC_SD_CMD RCAR_GP_PIN(1, 22) +#define PIN_MMC_DS RCAR_GP_PIN(1, 20) +#define PIN_MMC_D7 RCAR_GP_PIN(1, 21) +#define PIN_MMC_D6 RCAR_GP_PIN(1, 19) +#define PIN_MMC_D5 RCAR_GP_PIN(1, 17) +#define PIN_MMC_D4 RCAR_GP_PIN(1, 18) +#define PIN_MMC_SD_D3 RCAR_GP_PIN(1, 16) +#define PIN_MMC_SD_D2 RCAR_GP_PIN(1, 15) +#define PIN_MMC_SD_D1 RCAR_GP_PIN(1, 14) +#define PIN_MMC_SD_D0 RCAR_GP_PIN(1, 13) +#define PIN_MMC_SD_CLK RCAR_GP_PIN(1, 12) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h index fc8d5090e84b2..a6ea33f0adb11 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h @@ -40,4 +40,8 @@ */ #define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin) +#define PIN_VOLTAGE_NONE 0 +#define PIN_VOLTAGE_1P8V 1 +#define PIN_VOLTAGE_3P3V 2 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */ diff --git a/soc/arm64/renesas_rcar/Kconfig b/soc/arm64/renesas_rcar/Kconfig index 413523e23a75d..2f4b34a64eafa 100644 --- a/soc/arm64/renesas_rcar/Kconfig +++ b/soc/arm64/renesas_rcar/Kconfig @@ -12,6 +12,10 @@ config SOC_FAMILY string default "renesas_rcar" +config PIN_VOLTAGE_CONTROL + bool + default y + source "soc/arm64/renesas_rcar/*/Kconfig.soc" endif # SOC_FAMILY_RCAR diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c b/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c index c59be6cfe6fdf..c5feb62c7fd43 100644 --- a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c +++ b/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c @@ -528,6 +528,55 @@ const struct pfc_bias_reg pfc_bias_regs[] = { } }, { /* sentinel */ }, }; + +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +const struct pfc_pocctrl_reg pfc_io_voltage_regs[] = { + { + .offset = 0x0380, + .pins = { + [0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [6] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [7] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [8] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [9] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [12] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [13] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [14] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [15] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [16] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [17] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [18] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [19] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [20] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [21] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + [22] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [23] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [24] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [25] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [26] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [27] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [28] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [29] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [30] = PIN_NONE, + [31] = PIN_NONE, + } + }, + { /* sentinel */ }, +}; + +const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void) +{ + return pfc_io_voltage_regs; +} +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) { return pfc_bias_regs; diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c b/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c index c130dd510a834..58f4fe026cd09 100644 --- a/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c +++ b/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c @@ -136,6 +136,55 @@ const struct pfc_bias_reg pfc_bias_regs[] = { } }, { /* sentinel */ }, }; + +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +const struct pfc_pocctrl_reg pfc_io_voltage_regs[] = { + { + .offset = 0x0380, + .pins = { + [0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [6] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [7] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [8] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [9] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [12] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [13] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [14] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [15] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [16] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [17] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [18] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [19] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [20] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [21] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + [22] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [23] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [24] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [25] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [26] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [27] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [28] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [29] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [30] = PIN_NONE, + [31] = PIN_NONE, + } + }, + { /* sentinel */ }, +}; + +const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void) +{ + return pfc_io_voltage_regs; +} +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) { return pfc_bias_regs; diff --git a/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h b/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h index 92f7aa507a44f..9447551ded5dd 100644 --- a/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h +++ b/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h @@ -37,6 +37,7 @@ typedef struct pinctrl_soc_pin { struct rcar_pin_func func; uint8_t flags; uint8_t drive_strength; + uint8_t voltage; } pinctrl_soc_pin_t; #define RCAR_IPSR(node_id) DT_PROP_BY_IDX(node_id, pin, 1) @@ -65,6 +66,10 @@ typedef struct pinctrl_soc_pin { .drive_strength = \ COND_CODE_1(DT_NODE_HAS_PROP(node_id, drive_strength), \ (DT_PROP(node_id, drive_strength)), (0)), \ + .voltage = COND_CODE_1(DT_NODE_HAS_PROP(node_id, \ + power_source), \ + (DT_PROP(node_id, power_source)), \ + (PIN_VOLTAGE_NONE)), \ }, /** @@ -103,6 +108,16 @@ struct pfc_bias_reg { const uint16_t pins[32]; }; +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +/* POC Control Register can control IO voltage level that is supplied to the pin */ +struct pfc_pocctrl_reg { + uint32_t offset; + const uint16_t pins[32]; +}; + +const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void); +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void); const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void); diff --git a/soc/arm64/renesas_rcar/gen4/CMakeLists.txt b/soc/arm64/renesas_rcar/gen4/CMakeLists.txt new file mode 100644 index 0000000000000..906d848b584d7 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F pfc_r8a779f.c) +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) diff --git a/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.r8a779f b/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.r8a779f new file mode 100644 index 0000000000000..9ec56eb74a7cf --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.r8a779f @@ -0,0 +1,9 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if SOC_R8A779F + +config SOC + default "r8a779f" + +endif # SOC_R8A779F diff --git a/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.series b/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.series new file mode 100644 index 0000000000000..972fd7e6f9a65 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.series @@ -0,0 +1,18 @@ +# Renesas R-Car Gen3 SoC line +# +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RCAR_GEN4 + +config SOC_SERIES + default "gen4" + +config NUM_IRQS + int + default 500 + +config PINCTRL + default y + +endif # SOC_SERIES_RCAR_GEN4 diff --git a/soc/arm64/renesas_rcar/gen4/Kconfig.series b/soc/arm64/renesas_rcar/gen4/Kconfig.series new file mode 100644 index 0000000000000..bcb48db0d6ed1 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/Kconfig.series @@ -0,0 +1,12 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN4 + bool "Renesas RCAR Gen4 Cortex A" + select ARM64 + select CPU_CORTEX_A55 + select SOC_FAMILY_RCAR + select ARM_ARCH_TIMER + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + help + Enable support for Renesas RCar Gen4 SoC series diff --git a/soc/arm64/renesas_rcar/gen4/Kconfig.soc b/soc/arm64/renesas_rcar/gen4/Kconfig.soc new file mode 100644 index 0000000000000..18a7b416d7852 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Renesas RCar Gen4 SoC Selection" + depends on SOC_SERIES_RCAR_GEN4 + +config SOC_R8A779F + bool "R8A779F" + +endchoice diff --git a/soc/arm64/renesas_rcar/gen4/linker.ld b/soc/arm64/renesas_rcar/gen4/linker.ld new file mode 100644 index 0000000000000..0deb8cd27942c --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/linker.ld @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm64/renesas_rcar/gen4/mmu_regions.c b/soc/arm64/renesas_rcar/gen4/mmu_regions.c new file mode 100644 index 0000000000000..64cfa47978503 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/mmu_regions.c @@ -0,0 +1,25 @@ +/* + * Copyright 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_RW | MT_NS), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/arm64/renesas_rcar/gen4/pfc_r8a779f.c b/soc/arm64/renesas_rcar/gen4/pfc_r8a779f.c new file mode 100644 index 0000000000000..c2cf6d12740a7 --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/pfc_r8a779f.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "pinctrl_soc.h" +#include + +const struct pfc_drive_reg pfc_drive_regs[] = { + /* DRV1CTRL1 */ + { 0x884, { + { PIN_MMC_SD_D2, 28, 3 }, + { PIN_MMC_SD_D1, 24, 3 }, + { PIN_MMC_SD_D0, 20, 3 }, + { PIN_MMC_SD_CLK, 16, 3 }, + } }, + /* DRV2CTRL1 */ + { 0x888, { + { PIN_SD_CD, 28, 3 }, + { PIN_MMC_SD_CMD, 24, 3 }, + { PIN_MMC_D7, 20, 3 }, + { PIN_MMC_DS, 16, 3 }, + { PIN_MMC_D6, 12, 3 }, + { PIN_MMC_D4, 8, 3 }, + { PIN_MMC_D5, 4, 3 }, + { PIN_MMC_SD_D3, 0, 3 }, + } }, + /* DRV3CTRL1 */ + { 0x88c, { + { PIN_SD_WP, 0, 3 }, + } }, + { }, +}; + +#define PFC_BIAS_REG(r1, r2) \ + .puen = r1, \ + .pud = r2, \ + .pins = + +const struct pfc_bias_reg pfc_bias_regs[] = { + /* PUEN1, PUD1 */ + { PFC_BIAS_REG(0x8c0, 0x8e0) { + [0 ... 11] = PIN_NONE, + [12] = PIN_MMC_SD_CLK, + [13] = PIN_MMC_SD_D0, + [14] = PIN_MMC_SD_D1, + [15] = PIN_MMC_SD_D2, + [16] = PIN_MMC_SD_D3, + [17] = PIN_MMC_D5, + [18] = PIN_MMC_D4, + [19] = PIN_MMC_D6, + [20] = PIN_MMC_DS, + [21] = PIN_MMC_D7, + [22] = PIN_MMC_SD_CMD, + [23] = PIN_SD_CD, + [24] = PIN_SD_WP, + [25 ... 31] = PIN_NONE, + } }, + { /* sentinel */ }, +}; + +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +const struct pfc_pocctrl_reg pfc_io_voltage_regs[] = { + { + .offset = 0x08a0, /* POC1 */ + .pins = { + [0 ... 11] = PIN_NONE, + [12] = PIN_MMC_SD_CLK, + [13] = PIN_MMC_SD_D0, + [14] = PIN_MMC_SD_D1, + [15] = PIN_MMC_SD_D2, + [16] = PIN_MMC_SD_D3, + [17] = PIN_MMC_D5, + [18] = PIN_MMC_D4, + [19] = PIN_MMC_D6, + [20] = PIN_MMC_DS, + [21] = PIN_MMC_D7, + [22] = PIN_MMC_SD_CMD, + [23] = PIN_SD_CD, + [24] = PIN_SD_WP, + [25 ... 31] = PIN_NONE, + }, + }, + { /* sentinel */ }, +}; + +const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void) +{ + return pfc_io_voltage_regs; +} +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + +const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) +{ + return pfc_bias_regs; +} +const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) +{ + return pfc_drive_regs; +} diff --git a/soc/arm64/renesas_rcar/gen4/pinctrl_soc.h b/soc/arm64/renesas_rcar/gen4/pinctrl_soc.h new file mode 100644 index 0000000000000..f08f5a155635f --- /dev/null +++ b/soc/arm64/renesas_rcar/gen4/pinctrl_soc.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ + +#include +#include +#include +#include + +struct rcar_pin_func { + uint8_t bank:5; /* bank number 0 - 18 */ + uint8_t shift:5; /* bit shift 0 - 28 */ + uint8_t func:4; /* choice from 0x0 to 0xF */ +}; +/** Pull-up, pull-down, or bias disable is requested */ +#define RCAR_PIN_FLAGS_PULL_SET BIT(0) +/** Performs on/off control of the pull resistors */ +#define RCAR_PIN_FLAGS_PUEN BIT(1) +/** Select pull-up resistor if set pull-down otherwise */ +#define RCAR_PIN_FLAGS_PUD BIT(2) +/** Alternate function for the pin is requested */ +#define RCAR_PIN_FLAGS_FUNC_SET BIT(3) + +#define RCAR_PIN_PULL_UP (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN | RCAR_PIN_FLAGS_PUD) +#define RCAR_PIN_PULL_DOWN (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN) +#define RCAR_PIN_PULL_DISABLE RCAR_PIN_FLAGS_PULL_SET + +/** Type for R-Car pin. */ +typedef struct pinctrl_soc_pin { + uint16_t pin; + struct rcar_pin_func func; + uint8_t flags; + uint8_t drive_strength; + uint8_t voltage; +} pinctrl_soc_pin_t; + +#define RCAR_IPSR(node_id) DT_PROP_BY_IDX(node_id, pin, 1) +#define RCAR_HAS_IPSR(node_id) DT_PROP_HAS_IDX(node_id, pin, 1) + +/* Offsets are defined in dt-bindings pinctrl-rcar-common.h */ +#define RCAR_PIN_FUNC(node_id) \ + { \ + ((RCAR_IPSR(node_id) >> 10U) & 0x1FU), \ + ((RCAR_IPSR(node_id) >> 4U) & 0x1FU), \ + ((RCAR_IPSR(node_id) & 0xFU)) \ + } + +#define RCAR_PIN_FLAGS(node_id) \ + DT_PROP(node_id, bias_pull_up) * RCAR_PIN_PULL_UP | \ + DT_PROP(node_id, bias_pull_down) * RCAR_PIN_PULL_DOWN | \ + DT_PROP(node_id, bias_disable) * RCAR_PIN_PULL_DISABLE | \ + RCAR_HAS_IPSR(node_id) * RCAR_PIN_FLAGS_FUNC_SET + +#define RCAR_DT_PIN(node_id) \ + { \ + .pin = DT_PROP_BY_IDX(node_id, pin, 0), \ + .func = COND_CODE_1(RCAR_HAS_IPSR(node_id), \ + (RCAR_PIN_FUNC(node_id)), ({0})), \ + .flags = RCAR_PIN_FLAGS(node_id), \ + .drive_strength = \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, drive_strength), \ + (DT_PROP(node_id, drive_strength)), (0)), \ + .voltage = COND_CODE_1(DT_NODE_HAS_PROP(node_id, \ + power_source), \ + (DT_PROP(node_id, power_source)), \ + (PIN_VOLTAGE_NONE)), \ + }, + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param state_prop State property name. + * @param idx State property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + RCAR_DT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)) + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +struct pfc_drive_reg_field { + uint16_t pin; + uint8_t offset; + uint8_t size; +}; + +struct pfc_drive_reg { + uint32_t reg; + const struct pfc_drive_reg_field fields[8]; +}; + +struct pfc_bias_reg { + uint32_t puen; /** Pull-enable or pull-up control register */ + uint32_t pud; /** Pull-up/down or pull-down control register */ + const uint16_t pins[32]; +}; + +#ifdef CONFIG_PIN_VOLTAGE_CONTROL +/* POC Control Register can control IO voltage level that is supplied to the pin */ +struct pfc_pocctrl_reg { + uint32_t offset; + const uint16_t pins[32]; +}; + +const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void); + +#endif /* CONFIG_PIN_VOLTAGE_CONTROL */ + +const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void); +const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void); + +/** + * @brief Utility macro to check if a pin is GPIO capable + * + * @param pin + * @return true if pin is GPIO capable false otherwise + */ +#define RCAR_IS_GP_PIN(pin) (pin < PIN_NOGPSR_START) + +#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */ diff --git a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml index 5e8500a8dece2..16369401de0b6 100644 --- a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml +++ b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml @@ -19,6 +19,7 @@ tests: - xenvm_gicv3 - rcar_h3ulcb_ca57 - rcar_salvator_xs_m3 + - rcar_spider integration_platforms: - qemu_x86 drivers.sbs_gauge_new_api.emulated_64_bit_i2c_addr: