diff --git a/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 new file mode 100644 index 0000000000000..5eaad77c79c7f --- /dev/null +++ b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA2A1 + select SOC_R7FA2A1AB3CFM diff --git a/boards/renesas/ek_ra2a1/board.cmake b/boards/renesas/ek_ra2a1/board.cmake new file mode 100644 index 0000000000000..98ad18aa9bbd6 --- /dev/null +++ b/boards/renesas/ek_ra2a1/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA2A1AB") + +board_runner_args(pyocd "--target=r7fa2a1ab") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra2a1/board.yml b/boards/renesas/ek_ra2a1/board.yml new file mode 100644 index 0000000000000..82c498850aa89 --- /dev/null +++ b/boards/renesas/ek_ra2a1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra2a1 + vendor: renesas + socs: + - name: r7fa2a1ab3cfm diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst new file mode 100644 index 0000000000000..060f1627d2cf2 --- /dev/null +++ b/boards/renesas/ek_ra2a1/doc/index.rst @@ -0,0 +1,105 @@ +.. _ek_ra2a1: + +RA2A1 Evaluation Kit +#################### + +Overview +******** + +The EK-RA2A1 is an evaluation kit for Renesas RA2A1 Microcontroller Group. + +Renesas RA2A1 Microcontroller Group has following features + +- 48MHz, Arm Cortex-M23 core +- 256kB Code Flash, 8kB Data Flash, 32kB SRAM +- USB 2.0 Full-Sppeed +- SCI x 3 +- SPI x 2 +- I2C x 2 +- CAN x 1 +- 16-bit A/D Converter +- 24-bit Sigma-Delta A/D Converter +- 12-bit D/A Converter +- 8-bit D/A Converter x 2 +- High-Speed Analog Comparator +- Low-Power Analog Comparator +- OPAMP x 3 +- Temperature Sensor +- General PWM Timer 32-bit x 1 +- General PWM Timer 16-bit x 6 +- Low Power Asynchronous General-Purpose Timer x 2 +- Watchdog Timer +- 49 Input/Output pins + +Hardware +******** + +EK-RA2A1 has following features. + +- Native pin access through 4x 40-pin male headers +- MCU current measurement points +- SEGGER J-Link on-board programmer and debugger +- Two Digilent Pmod (SPI and UART) +- User LED +- Mechanical user button +- Capacitive user button + +Supported Features +================== + +The Renesas EK-RA2A1 board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------+ +| Interface | Controller | Driver/components | ++===========+============+===============================+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------+ +| UART | on-chip | uart | ++-----------+------------+-------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig` + + +Programming and debugging +************************* + +Building & Flashing +=================== + +You can build and flash an application with onboard J-Link debug adapter. +:ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ek_ra2a1 + :goals: build flash + + +Debugging +========= + +Debugging also can be done with onboard J-Link debug adapter. +The following command is debugging the :zephyr:code-sample:`blinky` application. +Also, see the instructions specific to the debug server that you use. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ek_ra2a1 + :maybe-skip-config: + :goals: debug + + +References +********** + +.. EK-RA2A1 Web site: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi new file mode 100644 index 0000000000000..cded3e5f6556b --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* rx */ + psels = ; + }; + group2 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + }; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts new file mode 100644 index 0000000000000..eb14660f8ac05 --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra2a1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA2A1"; + compatible = "renesas,ra2a1", "renesas,ra2"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 5 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml new file mode 100644 index 0000000000000..78000823a984d --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra2a1 +name: Renesas EK-RA2A1 +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig new file mode 100644 index 0000000000000..6058aa5eb98c9 --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi new file mode 100644 index 0000000000000..ed2059d993b2b --- /dev/null +++ b/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + flash1: flash@40100000 { + compatible = "soc-nv-flash"; + reg = <0x40100000 DT_SIZE_K(8)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi new file mode 100644 index 0000000000000..23e990b1010a6 --- /dev/null +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/delete-node/ &sci2; +/delete-node/ &sci3; +/delete-node/ &ioport6; +/delete-node/ &ioport7; +/delete-node/ &ioport8; + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(32)>; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + + sdadcclk: sdadcclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi new file mode 100644 index 0000000000000..5839795b2be23 --- /dev/null +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m23"; + reg = <0>; + }; + }; + + soc { + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + ioport0: gpio@40040000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@40040020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@40040040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@40040060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@40040080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@400400a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport6: gpio@400400c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400400e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport8: gpio@40040100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport9: gpio@40040120 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040120 0x20>; + port = <9>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-controller@40040800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x40040800 0x3c0>; + status = "okay"; + }; + + sci0: sci@40070000 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070000 0x20>; + clocks = <&pclkb MSTPB 31>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci1: sci@40070020 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070020 0x20>; + clocks = <&pclkb MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci@40070040 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070040 0x20>; + clocks = <&pclkb MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci@40070060 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070060 0x20>; + clocks = <&pclkb MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci9: sci@40070120 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070120 0x20>; + clocks = <&pclkb MSTPB 22>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + id_code: id_code@1010018 { + compatible = "zephyr,memory-region"; + reg = <0x01010018 0x20>; + zephyr,memory-region = "ID_CODE"; + status = "okay"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h index 09035308b0188..024f4d554a8a0 100644 --- a/include/zephyr/dt-bindings/clock/ra_clock.h +++ b/include/zephyr/dt-bindings/clock/ra_clock.h @@ -126,6 +126,17 @@ #define RA_LCD_CLOCK_DIV_6 3 #define RA_LCD_CLOCK_DIV_8 4 +/* SDADC clock divider options. */ +#define RA_SDADC_CLOCK_DIV_1 0 +#define RA_SDADC_CLOCK_DIV_2 1 +#define RA_SDADC_CLOCK_DIV_3 2 +#define RA_SDADC_CLOCK_DIV_4 3 +#define RA_SDADC_CLOCK_DIV_5 4 +#define RA_SDADC_CLOCK_DIV_6 5 +#define RA_SDADC_CLOCK_DIV_8 6 +#define RA_SDADC_CLOCK_DIV_12 7 +#define RA_SDADC_CLOCK_DIV_16 8 + #define MSTPA 0x40203000 #define MSTPB 0x40203004 #define MSTPC 0x40203008 diff --git a/soc/renesas/ra/ra2a1/CMakeLists.txt b/soc/renesas/ra/ra2a1/CMakeLists.txt new file mode 100644 index 0000000000000..223a8efd7a41c --- /dev/null +++ b/soc/renesas/ra/ra2a1/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(DATA_SECTIONS data_sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) +zephyr_linker_sources(ROM_START rom_start.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra2a1/Kconfig b/soc/renesas/ra/ra2a1/Kconfig new file mode 100644 index 0000000000000..f447a628c3a5c --- /dev/null +++ b/soc/renesas/ra/ra2a1/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA2A1 + select ARM + select CPU_CORTEX_M23 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_VTOR + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_SWO + select XIP + select HAS_RENESAS_RA_FSP diff --git a/soc/renesas/ra/ra2a1/Kconfig.defconfig b/soc/renesas/ra/ra2a1/Kconfig.defconfig new file mode 100644 index 0000000000000..33a1effb92b6b --- /dev/null +++ b/soc/renesas/ra/ra2a1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA2A1 + +config NUM_IRQS + default 32 + +config PINCTRL + default y + +endif # SOC_SERIES_RA2A1 diff --git a/soc/renesas/ra/ra2a1/Kconfig.soc b/soc/renesas/ra/ra2a1/Kconfig.soc new file mode 100644 index 0000000000000..23af5c7dbf8cc --- /dev/null +++ b/soc/renesas/ra/ra2a1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA2A1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA2A1 series + +config SOC_R7FA2A1AB3CFM + bool + select SOC_SERIES_RA2A1 + help + R7FA2A1AB3CFM + +config SOC_SERIES + default "ra2a1" if SOC_SERIES_RA2A1 + +config SOC + default "r7fa2a1ab3cfm" if SOC_R7FA2A1AB3CFM diff --git a/soc/renesas/ra/ra2a1/data_sections.ld b/soc/renesas/ra/ra2a1/data_sections.ld new file mode 100644 index 0000000000000..84cb7c088e838 --- /dev/null +++ b/soc/renesas/ra/ra2a1/data_sections.ld @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION diff --git a/soc/renesas/ra/ra2a1/ram_sections.ld b/soc/renesas/ra/ra2a1/ram_sections.ld new file mode 100644 index 0000000000000..2f1217ef57bdb --- /dev/null +++ b/soc/renesas/ra/ra2a1/ram_sections.ld @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) diff --git a/soc/renesas/ra/ra2a1/rom_start.ld b/soc/renesas/ra/ra2a1/rom_start.ld new file mode 100644 index 0000000000000..64eb3c891e043 --- /dev/null +++ b/soc/renesas/ra/ra2a1/rom_start.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra2a1/sections.ld b/soc/renesas/ra/ra2a1/sections.ld new file mode 100644 index 0000000000000..e3034adb244ea --- /dev/null +++ b/soc/renesas/ra/ra2a1/sections.ld @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay) + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay) + +SECTION_PROLOGUE(.option_setting_ns,,) +{ + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = __OPTION_SETTING_NS_Start + 0x04; + KEEP(*(.option_setting_ofs3)) + . = __OPTION_SETTING_NS_Start + 0x10; + KEEP(*(.option_setting_banksel)) + . = __OPTION_SETTING_NS_Start + 0x40; + KEEP(*(.option_setting_bps0)) + . = __OPTION_SETTING_NS_Start + 0x44; + KEEP(*(.option_setting_bps1)) + . = __OPTION_SETTING_NS_Start + 0x48; + KEEP(*(.option_setting_bps2)) + . = __OPTION_SETTING_NS_Start + 0x4C; + KEEP(*(.option_setting_bps3)) + . = __OPTION_SETTING_NS_Start + 0x60; + KEEP(*(.option_setting_pbps0)) + . = __OPTION_SETTING_NS_Start + 0x64; + KEEP(*(.option_setting_pbps1)) + . = __OPTION_SETTING_NS_Start + 0x68; + KEEP(*(.option_setting_pbps2)) + . = __OPTION_SETTING_NS_Start + 0x6C; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; +} GROUP_LINK_IN(OPTION_SETTING) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay) + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF + +#endif diff --git a/soc/renesas/ra/ra2a1/soc.c b/soc/renesas/ra/ra2a1/soc.c new file mode 100644 index 0000000000000..5b944eaa92dd6 --- /dev/null +++ b/soc/renesas/ra/ra2a1/soc.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA2A1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra2a1_init(void) +{ + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + bsp_clock_init(); + + return 0; +} + +SYS_INIT(renesas_ra2a1_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra2a1/soc.h b/soc/renesas/ra/ra2a1/soc.h new file mode 100644 index 0000000000000..3dab874487bb1 --- /dev/null +++ b/soc/renesas/ra/ra2a1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA2A1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index 7e2bfeeb6334b..cf3c90523bc07 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -1,6 +1,9 @@ family: - name: renesas_ra series: + - name: ra2a1 + socs: + - name: r7fa2a1ab3cfm - name: ra4m1 socs: - name: r7fa4m1ab3cfm