From 6e2bc4379a9cdf00879127cded58665174ea6545 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 12 Jun 2024 10:01:28 -0700 Subject: [PATCH 1/3] boards: rename qemu_xtensa to qemu_xtensa/dc233c This is in preparation for adding another SoC where qemu_xtensa is no longer valid choice. So use qemu_xtensa/dc233c as it is the same as the old qemu_xtensa. Signed-off-by: Daniel Leung --- boards/deprecated.cmake | 3 +++ boards/qemu/xtensa/doc/index.rst | 2 +- .../xtensa/{qemu_xtensa.dts => qemu_xtensa_dc233c.dts} | 0 .../xtensa/{qemu_xtensa.yaml => qemu_xtensa_dc233c.yaml} | 2 +- ...qemu_xtensa_defconfig => qemu_xtensa_dc233c_defconfig} | 0 doc/releases/migration-guide-4.0.rst | 2 ++ samples/subsys/llext/modules/README.rst | 4 ++-- samples/subsys/llext/modules/sample.yaml | 4 ++-- .../portability/cmsis_rtos_v1/philosophers/src/main.c | 2 +- .../portability/cmsis_rtos_v2/philosophers/sample.yaml | 2 +- .../application_development/code_relocation/testcase.yaml | 2 +- tests/kernel/cache/testcase.yaml | 4 ++-- tests/lib/heap/testcase.yaml | 4 ++-- tests/lib/mpsc_pbuf/testcase.yaml | 3 ++- tests/posix/shm/testcase.yaml | 2 +- tests/subsys/debug/symtab/testcase.yaml | 2 +- tests/subsys/llext/simple/testcase.yaml | 8 ++++---- 17 files changed, 26 insertions(+), 20 deletions(-) rename boards/qemu/xtensa/{qemu_xtensa.dts => qemu_xtensa_dc233c.dts} (100%) rename boards/qemu/xtensa/{qemu_xtensa.yaml => qemu_xtensa_dc233c.yaml} (85%) rename boards/qemu/xtensa/{qemu_xtensa_defconfig => qemu_xtensa_dc233c_defconfig} (100%) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index a96f68b12dab0..84d5f3c768e6d 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -721,6 +721,9 @@ set(qemu_x86_virt_DEPRECATED set(qemu_x86_xip_DEPRECATED qemu_x86/atom/xip ) +set(qemu_xtensa_DEPRECATED + qemu_xtensa/dc233c +) set(qemu_xtensa_mmu_DEPRECATED qemu_xtensa/dc233c/mmu ) diff --git a/boards/qemu/xtensa/doc/index.rst b/boards/qemu/xtensa/doc/index.rst index 1bc8b2b2acebe..f0ec7e9deec71 100644 --- a/boards/qemu/xtensa/doc/index.rst +++ b/boards/qemu/xtensa/doc/index.rst @@ -18,7 +18,7 @@ emulated environment, for example, with the :zephyr:code-sample:`synchronization .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: qemu_xtensa + :board: qemu_xtensa/dc233c :goals: run This will build an image with the synchronization sample app, boot it using diff --git a/boards/qemu/xtensa/qemu_xtensa.dts b/boards/qemu/xtensa/qemu_xtensa_dc233c.dts similarity index 100% rename from boards/qemu/xtensa/qemu_xtensa.dts rename to boards/qemu/xtensa/qemu_xtensa_dc233c.dts diff --git a/boards/qemu/xtensa/qemu_xtensa.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml similarity index 85% rename from boards/qemu/xtensa/qemu_xtensa.yaml rename to boards/qemu/xtensa/qemu_xtensa_dc233c.yaml index 1190d0d3f8e4e..a3ac9b1ca4fab 100644 --- a/boards/qemu/xtensa/qemu_xtensa.yaml +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml @@ -1,4 +1,4 @@ -identifier: qemu_xtensa +identifier: qemu_xtensa/dc233c name: QEMU Emulation for Xtensa type: qemu simulation: qemu diff --git a/boards/qemu/xtensa/qemu_xtensa_defconfig b/boards/qemu/xtensa/qemu_xtensa_dc233c_defconfig similarity index 100% rename from boards/qemu/xtensa/qemu_xtensa_defconfig rename to boards/qemu/xtensa/qemu_xtensa_dc233c_defconfig diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst index 992d797b06e12..e86005fdc8abb 100644 --- a/doc/releases/migration-guide-4.0.rst +++ b/doc/releases/migration-guide-4.0.rst @@ -35,6 +35,8 @@ Boards * STM32WBA: The command used for fetching blobs required to build ble applications is now ``west blobs fetch hal_stm32`` instead of ``west blobs fetch stm32``. +* Board ``qemu_xtensa`` is deprecated. Use ``qemu_xtensa/dc233c`` instead. + STM32 ===== diff --git a/samples/subsys/llext/modules/README.rst b/samples/subsys/llext/modules/README.rst index 58dc540f729a5..4149dffab25b8 100644 --- a/samples/subsys/llext/modules/README.rst +++ b/samples/subsys/llext/modules/README.rst @@ -41,7 +41,7 @@ Building and running .. zephyr-app-commands:: :zephyr-app: samples/subsys/llext/modules - :board: qemu_xtensa + :board: qemu_xtensa/dc233c :goals: build run :compact: @@ -50,7 +50,7 @@ Building and running .. zephyr-app-commands:: :zephyr-app: samples/subsys/llext/modules - :board: qemu_xtensa + :board: qemu_xtensa/dc233c :goals: build run :west-args: -T sample.llext.modules.module_build :compact: diff --git a/samples/subsys/llext/modules/sample.yaml b/samples/subsys/llext/modules/sample.yaml index 955c4abbad7a5..4fc5d4005aa15 100644 --- a/samples/subsys/llext/modules/sample.yaml +++ b/samples/subsys/llext/modules/sample.yaml @@ -6,9 +6,9 @@ common: - qemu_cortex_a53 # ARM Cortex-A53 (ARMv8-A ISA) - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA) - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA) - - qemu_xtensa + - qemu_xtensa/dc233c integration_platforms: - - qemu_xtensa + - qemu_xtensa/dc233c - mps2/an385 - qemu_cortex_a53 harness: console diff --git a/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/main.c b/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/main.c index ccaa8224c2323..b5f22a3035057 100644 --- a/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/main.c +++ b/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/main.c @@ -72,7 +72,7 @@ osSemaphoreId forks[NUM_PHIL]; #define fork(x) (forks[x]) /* - * CMSIS limits the stack size, but qemu_x86_64, qemu_xtensa, + * CMSIS limits the stack size, but qemu_x86_64, qemu_xtensa (all), * qemu_leon3 and the boards such as up_squared, intel_ehl_crb, * acrn_ehl_crb need 1024 to run this. * For other arch and boards suggested stack size is 512. diff --git a/samples/subsys/portability/cmsis_rtos_v2/philosophers/sample.yaml b/samples/subsys/portability/cmsis_rtos_v2/philosophers/sample.yaml index af5a69f0af789..801b997fcb128 100644 --- a/samples/subsys/portability/cmsis_rtos_v2/philosophers/sample.yaml +++ b/samples/subsys/portability/cmsis_rtos_v2/philosophers/sample.yaml @@ -8,7 +8,7 @@ common: min_ram: 32 min_flash: 34 platform_exclude: - - qemu_xtensa + - qemu_xtensa/dc233c - qemu_x86_64 harness: console harness_config: diff --git a/tests/application_development/code_relocation/testcase.yaml b/tests/application_development/code_relocation/testcase.yaml index 2fcf97b6aa629..45582025a85c6 100644 --- a/tests/application_development/code_relocation/testcase.yaml +++ b/tests/application_development/code_relocation/testcase.yaml @@ -37,4 +37,4 @@ tests: - qemu_riscv64 application_development.code_relocation.xtensa: extra_args: CONF_FILE="prj_xtensa.conf" - platform_allow: qemu_xtensa + platform_allow: qemu_xtensa/dc233c diff --git a/tests/kernel/cache/testcase.yaml b/tests/kernel/cache/testcase.yaml index 22cd07fbdac2f..bb0cc45df07a7 100644 --- a/tests/kernel/cache/testcase.yaml +++ b/tests/kernel/cache/testcase.yaml @@ -8,7 +8,7 @@ tests: - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - - qemu_xtensa + - qemu_xtensa/dc233c - qemu_cortex_a53 - nsim/nsim_em - qemu_x86 @@ -23,7 +23,7 @@ tests: - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - - qemu_xtensa + - qemu_xtensa/dc233c - qemu_cortex_a53 - nsim/nsim_em - qemu_x86 diff --git a/tests/lib/heap/testcase.yaml b/tests/lib/heap/testcase.yaml index 279aa0c9a68b4..d522fd4a59acc 100644 --- a/tests/lib/heap/testcase.yaml +++ b/tests/lib/heap/testcase.yaml @@ -3,14 +3,14 @@ # minutes (vs. ~20 seconds for qemu) to complete in CI. There's # little value there, this is a unit test of library code and we have # coverage of the RISC-V architectures via qemu platforms already. -# Excludes qemu_xtensa due to pathological runtimes which cannot be +# Excludes qemu_xtensa/dc233c due to pathological runtimes which cannot be # reproduced on real hardware. tests: libraries.heap: tags: heap platform_exclude: - m2gl025_miv - - qemu_xtensa + - qemu_xtensa/dc233c - esp32s2_saola - esp32s2_lolin_mini timeout: 480 diff --git a/tests/lib/mpsc_pbuf/testcase.yaml b/tests/lib/mpsc_pbuf/testcase.yaml index 124c3a7669cba..50d9722e42642 100644 --- a/tests/lib/mpsc_pbuf/testcase.yaml +++ b/tests/lib/mpsc_pbuf/testcase.yaml @@ -14,7 +14,8 @@ tests: - qemu_riscv64 - qemu_x86 - qemu_x86_64 - - qemu_xtensa + - qemu_xtensa/dc233c + - native_posix - native_sim integration_platforms: - native_sim diff --git a/tests/posix/shm/testcase.yaml b/tests/posix/shm/testcase.yaml index d0fb52be995f0..1928a6e177c2e 100644 --- a/tests/posix/shm/testcase.yaml +++ b/tests/posix/shm/testcase.yaml @@ -9,7 +9,7 @@ common: - simulation platform_exclude: # linker_zephyr_pre0.cmd:140: syntax error (??) - - qemu_xtensa + - qemu_xtensa/dc233c # CONFIG_MMU=y but no arch_mem_map() or arch_mem_unmap() - intel_ish_5_4_1 - intel_ish_5_6_0 diff --git a/tests/subsys/debug/symtab/testcase.yaml b/tests/subsys/debug/symtab/testcase.yaml index e20c196705a1f..43d4c54a2e4af 100644 --- a/tests/subsys/debug/symtab/testcase.yaml +++ b/tests/subsys/debug/symtab/testcase.yaml @@ -5,7 +5,7 @@ common: - qemu_riscv64 - qemu_cortex_a53 - qemu_cortex_m3 - - qemu_xtensa + - qemu_xtensa/dc233c tags: - debug - symtab diff --git a/tests/subsys/llext/simple/testcase.yaml b/tests/subsys/llext/simple/testcase.yaml index 6352e5d30f1fb..59cdccf6e3a04 100644 --- a/tests/subsys/llext/simple/testcase.yaml +++ b/tests/subsys/llext/simple/testcase.yaml @@ -64,7 +64,7 @@ tests: llext.simple.writable: arch_allow: arm xtensa integration_platforms: - - qemu_xtensa # Xtensa ISA + - qemu_xtensa/dc233c # Xtensa ISA filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n @@ -73,7 +73,7 @@ tests: llext.simple.writable_relocatable: arch_allow: arm xtensa integration_platforms: - - qemu_xtensa # Xtensa ISA + - qemu_xtensa/dc233c # Xtensa ISA filter: not CONFIG_MPU and not CONFIG_MMU extra_configs: - arch:arm:CONFIG_ARM_MPU=n @@ -86,7 +86,7 @@ tests: llext.simple.writable_slid_linking: arch_allow: arm xtensa integration_platforms: - - qemu_xtensa # Xtensa ISA + - qemu_xtensa/dc233c # Xtensa ISA filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n @@ -96,7 +96,7 @@ tests: llext.simple.writable_relocatable_slid_linking: arch_allow: arm xtensa integration_platforms: - - qemu_xtensa # Xtensa ISA + - qemu_xtensa/dc233c # Xtensa ISA filter: not CONFIG_MPU and not CONFIG_MMU extra_configs: - arch:arm:CONFIG_ARM_MPU=n From 1aa8c5f4491538882cf6d8b4d989c013da1b7639 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 24 Apr 2024 10:41:05 -0700 Subject: [PATCH 2/3] soc: xtensa: add sample_controller32 Add sample_controller32 for Xtensa which has MPU. Signed-off-by: Daniel Leung --- dts/xtensa/sample_controller32.dtsi | 40 ++ soc/cdns/sample_controller32/CMakeLists.txt | 7 + soc/cdns/sample_controller32/Kconfig | 9 + soc/cdns/sample_controller32/Kconfig.soc | 12 + .../include/_soc_inthandlers.h | 296 +++++++++ .../include/xtensa-sample-controller32.ld | 588 ++++++++++++++++++ soc/cdns/sample_controller32/mpu.c | 16 + soc/cdns/sample_controller32/soc.yml | 4 + 8 files changed, 972 insertions(+) create mode 100644 dts/xtensa/sample_controller32.dtsi create mode 100644 soc/cdns/sample_controller32/CMakeLists.txt create mode 100644 soc/cdns/sample_controller32/Kconfig create mode 100644 soc/cdns/sample_controller32/Kconfig.soc create mode 100644 soc/cdns/sample_controller32/include/_soc_inthandlers.h create mode 100644 soc/cdns/sample_controller32/include/xtensa-sample-controller32.ld create mode 100644 soc/cdns/sample_controller32/mpu.c create mode 100644 soc/cdns/sample_controller32/soc.yml diff --git a/dts/xtensa/sample_controller32.dtsi b/dts/xtensa/sample_controller32.dtsi new file mode 100644 index 0000000000000..2b85bd4bc3f70 --- /dev/null +++ b/dts/xtensa/sample_controller32.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "sample_controller"; + reg = <0>; + }; + }; + + sram0: memory@60000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60000000 0x4000000>; + }; + + srom0: memory@fe000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x50000000 0x1000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + }; +}; diff --git a/soc/cdns/sample_controller32/CMakeLists.txt b/soc/cdns/sample_controller32/CMakeLists.txt new file mode 100644 index 0000000000000..684003a0f95d9 --- /dev/null +++ b/soc/cdns/sample_controller32/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) + +zephyr_library_sources_ifdef(CONFIG_XTENSA_MPU mpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-sample-controller32.ld CACHE INTERNAL "") diff --git a/soc/cdns/sample_controller32/Kconfig b/soc/cdns/sample_controller32/Kconfig new file mode 100644 index 0000000000000..69ba20c5fc89e --- /dev/null +++ b/soc/cdns/sample_controller32/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER32 + select XTENSA + select XTENSA_HAL + select ATOMIC_OPERATIONS_C + select CPU_HAS_MPU + select ARCH_HAS_USERSPACE if XTENSA_MPU diff --git a/soc/cdns/sample_controller32/Kconfig.soc b/soc/cdns/sample_controller32/Kconfig.soc new file mode 100644 index 0000000000000..90e0556b3c9af --- /dev/null +++ b/soc/cdns/sample_controller32/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER32 + bool + +config SOC + default "sample_controller32" if SOC_XTENSA_SAMPLE_CONTROLLER32 + +config SOC_TOOLCHAIN_NAME + string + default "sample_controller32" if SOC_XTENSA_SAMPLE_CONTROLLER32 diff --git a/soc/cdns/sample_controller32/include/_soc_inthandlers.h b/soc/cdns/sample_controller32/include/_soc_inthandlers.h new file mode 100644 index 0000000000000..e0d60d348c212 --- /dev/null +++ b/soc/cdns/sample_controller32/include/_soc_inthandlers.h @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + * + * Functions here are designed to produce efficient code to + * search an Xtensa bitmask of interrupts, inspecting only those bits + * declared to be associated with a given interrupt level. Each + * dispatcher will handle exactly one flagged interrupt, in numerical + * order (low bits first) and will return a mask of that bit that can + * then be cleared by the calling code. Unrecognized bits for the + * level will invoke an error handler. + */ + +#include +#include +#include + +#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 +#error core-isa.h interrupt level does not match dispatcher! +#endif + +static inline int _xtensa_handle_one_int1(unsigned int mask) +{ + int irq; + + if (mask & 0x7f) { + if (mask & 0x7) { + if (mask & BIT(0)) { + mask = BIT(0); + irq = 0; + goto handle_irq; + } + if (mask & BIT(1)) { + mask = BIT(1); + irq = 1; + goto handle_irq; + } + if (mask & BIT(2)) { + mask = BIT(2); + irq = 2; + goto handle_irq; + } + } else { + if (mask & 0x18) { + if (mask & BIT(3)) { + mask = BIT(3); + irq = 3; + goto handle_irq; + } + if (mask & BIT(4)) { + mask = BIT(4); + irq = 4; + goto handle_irq; + } + } else { + if (mask & BIT(5)) { + mask = BIT(5); + irq = 5; + goto handle_irq; + } + if (mask & BIT(6)) { + mask = BIT(6); + irq = 6; + goto handle_irq; + } + } + } + } else { + if (mask & 0x38080) { + if (mask & 0x8080) { + if (mask & BIT(7)) { + mask = BIT(7); + irq = 7; + goto handle_irq; + } + if (mask & BIT(15)) { + mask = BIT(15); + irq = 15; + goto handle_irq; + } + } else { + if (mask & BIT(16)) { + mask = BIT(16); + irq = 16; + goto handle_irq; + } + if (mask & BIT(17)) { + mask = BIT(17); + irq = 17; + goto handle_irq; + } + } + } else { + if (mask & 0xc0000) { + if (mask & BIT(18)) { + mask = BIT(18); + irq = 18; + goto handle_irq; + } + if (mask & BIT(19)) { + mask = BIT(19); + irq = 19; + goto handle_irq; + } + } else { + if (mask & BIT(20)) { + mask = BIT(20); + irq = 20; + goto handle_irq; + } + if (mask & BIT(22)) { + mask = BIT(22); + irq = 22; + goto handle_irq; + } + } + } + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int2(unsigned int mask) +{ + int irq; + + if (mask & BIT(8)) { + mask = BIT(8); + irq = 8; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int3(unsigned int mask) +{ + int irq; + + if (mask & 0x600) { + if (mask & BIT(9)) { + mask = BIT(9); + irq = 9; + goto handle_irq; + } + if (mask & BIT(10)) { + mask = BIT(10); + irq = 10; + goto handle_irq; + } + } else { + if (mask & BIT(11)) { + mask = BIT(11); + irq = 11; + goto handle_irq; + } + if (mask & BIT(21)) { + mask = BIT(21); + irq = 21; + goto handle_irq; + } + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int4(unsigned int mask) +{ + int irq; + + if (mask & BIT(12)) { + mask = BIT(12); + irq = 12; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int5(unsigned int mask) +{ + int irq; + + if (mask & BIT(13)) { + mask = BIT(13); + irq = 13; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int7(unsigned int mask) +{ + int irq; + + if (mask & BIT(14)) { + mask = BIT(14); + irq = 14; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int0(unsigned int mask) +{ + return 0; +} +static inline int _xtensa_handle_one_int6(unsigned int mask) +{ + return 0; +} diff --git a/soc/cdns/sample_controller32/include/xtensa-sample-controller32.ld b/soc/cdns/sample_controller32/include/xtensa-sample-controller32.ld new file mode 100644 index 0000000000000..2bda535cf29ea --- /dev/null +++ b/soc/cdns/sample_controller32/include/xtensa-sample-controller32.ld @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the Xtensa platform. + */ + +#include + +#include + +#include +#include +#include + +#define RAMABLE_REGION RAM :sram0_phdr +#define ROMABLE_REGION RAM :sram0_phdr + +#ifdef CONFIG_MPU +#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(XCHAL_MPU_ALIGN); +#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN) +#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN) +#define LAST_RAM_ALIGN MPU_SEGMENT_SIZE_ALIGN +#else +#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(4); +#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4) +#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4096) +#endif + +#define PHYS_SRAM0_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0))) +#define PHYS_SRAM0_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) + +#define PHYS_ROM0_ADDR (DT_REG_ADDR(DT_NODELABEL(srom0))) +#define PHYS_ROM0_SIZE (DT_REG_SIZE(DT_NODELABEL(srom0))) + +/* Usable RAM is after the exception vectors and page-aligned. */ +#define PHYS_RAM_ADDR (PHYS_SRAM0_ADDR + CONFIG_SRAM_OFFSET) +#define PHYS_RAM_SIZE (PHYS_SRAM0_SIZE - CONFIG_SRAM_OFFSET) + +MEMORY +{ + dram1_0_seg : org = 0x3FFC0000, len = 0x20000 + dram0_0_seg : org = 0x3FFE0000, len = 0x20000 + iram0_0_seg : org = 0x40000000, len = 0x178 + iram0_1_seg : org = 0x40000178, len = 0x8 + iram0_2_seg : org = 0x40000180, len = 0x38 + iram0_3_seg : org = 0x400001B8, len = 0x8 + iram0_4_seg : org = 0x400001C0, len = 0x38 + iram0_5_seg : org = 0x400001F8, len = 0x8 + iram0_6_seg : org = 0x40000200, len = 0x38 + iram0_7_seg : org = 0x40000238, len = 0x8 + iram0_8_seg : org = 0x40000240, len = 0x38 + iram0_9_seg : org = 0x40000278, len = 0x8 + iram0_10_seg : org = 0x40000280, len = 0x38 + iram0_11_seg : org = 0x400002B8, len = 0x8 + iram0_12_seg : org = 0x400002C0, len = 0x38 + iram0_13_seg : org = 0x400002F8, len = 0x8 + iram0_14_seg : org = 0x40000300, len = 0x38 + iram0_15_seg : org = 0x40000338, len = 0x8 + iram0_16_seg : org = 0x40000340, len = 0x38 + iram0_17_seg : org = 0x40000378, len = 0x48 + iram0_18_seg : org = 0x400003C0, len = 0x40 + iram0_19_seg : org = 0x40000400, len = 0x1FC00 +#ifdef CONFIG_MPU + vec_helpers : org = 0x40002400, len = (PHYS_RAM_ADDR - 0x00002400) +#endif + srom0_seg : org = PHYS_ROM0_ADDR, len = PHYS_ROM0_SIZE + RAM : org = PHYS_RAM_ADDR, len = PHYS_RAM_SIZE + +#ifdef CONFIG_GEN_ISR_TABLES + /* The space before exception vectors is not being used. + * So we stuff the temporary IDT_LIST there to avoid + * some linker issues which would balloon the size of + * the intermediate files (like zephyr_pre0.elf, to + * couple hundred MBs or even GBs). + */ + IDT_LIST : org = 0x3FFBE000, len = 0x2000 +#endif +} + +PHDRS +{ + dram1_0_phdr PT_LOAD; + dram1_0_bss_phdr PT_LOAD; + dram0_0_phdr PT_LOAD; + dram0_0_bss_phdr PT_LOAD; + iram0_0_phdr PT_LOAD; + iram0_1_phdr PT_LOAD; + iram0_2_phdr PT_LOAD; + iram0_3_phdr PT_LOAD; + iram0_4_phdr PT_LOAD; + iram0_5_phdr PT_LOAD; + iram0_6_phdr PT_LOAD; + iram0_7_phdr PT_LOAD; + iram0_8_phdr PT_LOAD; + iram0_9_phdr PT_LOAD; + iram0_10_phdr PT_LOAD; + iram0_11_phdr PT_LOAD; + iram0_12_phdr PT_LOAD; + iram0_13_phdr PT_LOAD; + iram0_14_phdr PT_LOAD; + iram0_15_phdr PT_LOAD; + iram0_16_phdr PT_LOAD; + iram0_17_phdr PT_LOAD; + iram0_18_phdr PT_LOAD; + +#ifdef CONFIG_XTENSA_MPU + vec_helpers_phdr PT_LOAD; +#endif + + srom0_phdr PT_LOAD; + sram0_phdr PT_LOAD; + sram0_bss_phdr PT_LOAD; +} + + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = 0x40000000); +PROVIDE(_memmap_reset_vector = 0x50000000); + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x00001110; +_memmap_cacheattr_wt_base = 0x00001110; +_memmap_cacheattr_bp_base = 0x00002220; +_memmap_cacheattr_unused_mask = 0xFFFF000F; +_memmap_cacheattr_wb_trapnull = 0x2222111F; +_memmap_cacheattr_wba_trapnull = 0x2222111F; +_memmap_cacheattr_wbna_trapnull = 0x2222111F; +_memmap_cacheattr_wt_trapnull = 0x2222111F; +_memmap_cacheattr_bp_trapnull = 0x2222222F; +_memmap_cacheattr_wb_strict = 0xFFFF111F; +_memmap_cacheattr_wt_strict = 0xFFFF111F; +_memmap_cacheattr_bp_strict = 0xFFFF222F; +_memmap_cacheattr_wb_allvalid = 0x22221112; +_memmap_cacheattr_wt_allvalid = 0x22221112; +_memmap_cacheattr_bp_allvalid = 0x22222222; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_bp_trapnull); + +SECTIONS +{ + +#include + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + + .dram1.rodata : ALIGN(4) + { + _dram1_rodata_start = ABSOLUTE(.); + *(.dram1.rodata) + _dram1_rodata_end = ABSOLUTE(.); + } >dram1_0_seg :dram1_0_phdr + + .dram1.literal : ALIGN(4) + { + _dram1_literal_start = ABSOLUTE(.); + *(.dram1.literal) + _dram1_literal_end = ABSOLUTE(.); + } >dram1_0_seg :dram1_0_phdr + + .dram1.data : ALIGN(4) + { + _dram1_data_start = ABSOLUTE(.); + *(.dram1.data) + _dram1_data_end = ABSOLUTE(.); + } >dram1_0_seg :dram1_0_phdr + + .dram1.bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _dram1_bss_start = ABSOLUTE(.); + *(.dram1.bss) + . = ALIGN (8); + _dram1_bss_end = ABSOLUTE(.); + _memmap_seg_dram1_0_end = ALIGN(0x8); + } >dram1_0_seg :dram1_0_bss_phdr + + .dram0.rodata : ALIGN(4) + { + _dram0_rodata_start = ABSOLUTE(.); + *(.dram0.rodata) + _dram0_rodata_end = ABSOLUTE(.); + } >dram0_0_seg :dram0_0_phdr + + .dram0.literal : ALIGN(4) + { + _dram0_literal_start = ABSOLUTE(.); + *(.dram0.literal) + _dram0_literal_end = ABSOLUTE(.); + } >dram0_0_seg :dram0_0_phdr + + .dram0.data : ALIGN(4) + { + _dram0_data_start = ABSOLUTE(.); + *(.dram0.data) + _dram0_data_end = ABSOLUTE(.); + } >dram0_0_seg :dram0_0_phdr + + .dram0.bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _dram0_bss_start = ABSOLUTE(.); + *(.dram0.bss) + . = ALIGN (8); + _dram0_bss_end = ABSOLUTE(.); + _memmap_seg_dram0_0_end = ALIGN(0x8); + } >dram0_0_seg :dram0_0_bss_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >iram0_0_seg :iram0_0_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >iram0_1_seg :iram0_1_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >iram0_2_seg :iram0_2_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >iram0_3_seg :iram0_3_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >iram0_4_seg :iram0_4_phdr + + .Level4InterruptVector.literal : ALIGN(4) + { + _Level4InterruptVector_literal_start = ABSOLUTE(.); + *(.Level4InterruptVector.literal) + _Level4InterruptVector_literal_end = ABSOLUTE(.); + } >iram0_5_seg :iram0_5_phdr + + .Level4InterruptVector.text : ALIGN(4) + { + _Level4InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level4InterruptVector.text)) + _Level4InterruptVector_text_end = ABSOLUTE(.); + } >iram0_6_seg :iram0_6_phdr + + .Level5InterruptVector.literal : ALIGN(4) + { + _Level5InterruptVector_literal_start = ABSOLUTE(.); + *(.Level5InterruptVector.literal) + _Level5InterruptVector_literal_end = ABSOLUTE(.); + } >iram0_7_seg :iram0_7_phdr + + .Level5InterruptVector.text : ALIGN(4) + { + _Level5InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level5InterruptVector.text)) + _Level5InterruptVector_text_end = ABSOLUTE(.); + } >iram0_8_seg :iram0_8_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >iram0_9_seg :iram0_9_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >iram0_10_seg :iram0_10_phdr + + .NMIExceptionVector.literal : ALIGN(4) + { + _NMIExceptionVector_literal_start = ABSOLUTE(.); + *(.NMIExceptionVector.literal) + _NMIExceptionVector_literal_end = ABSOLUTE(.); + } >iram0_11_seg :iram0_11_phdr + + .NMIExceptionVector.text : ALIGN(4) + { + _NMIExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.NMIExceptionVector.text)) + _NMIExceptionVector_text_end = ABSOLUTE(.); + } >iram0_12_seg :iram0_12_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >iram0_13_seg :iram0_13_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >iram0_14_seg :iram0_14_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >iram0_15_seg :iram0_15_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >iram0_16_seg :iram0_16_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >iram0_17_seg :iram0_17_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >iram0_18_seg :iram0_18_phdr + +#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func) \ + *##library##:##obj_file##(.literal.##func .text.##func) \ + +#ifdef CONFIG_XTENSA_MPU + .vec_helpers : + { + /* There is quite some space between .DoubleExceptionVector + * and the beginning of .text. We can put exception handling + * code here. + */ + + *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal .text) + *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text .iram0.text) + + *libarch__xtensa__core.a:window_vectors.S.obj(.iram.text) + + *libarch__xtensa__core.a:crt1.S.obj(.literal .text) + + LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_asm2.c.obj,*) + LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,fatal.c.obj,*) + LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,cpu_idle.c.obj,*) + + *(.literal.arch_is_in_isr .text.arch_is_in_isr) + + /* To support backtracing */ + LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_backtrace.c.obj,*) + + *libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal .iram1) + + /* Userspace related stuff */ + LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,xtensa_do_syscall) + + /* Below are to speed up execution by avoiding TLB misses + * on frequently used functions. + * + * There is almost 1MB space (due to TLB pinning) so we can + * be generous. + */ + LIB_OBJ_FUNC_IN_SECT(libkernel.a,,*) + + LIB_OBJ_FUNC_IN_SECT(libdrivers__console.a,,*) + LIB_OBJ_FUNC_IN_SECT(libdrivers__timer.a,,*) + + *(.literal.z_vrfy_* .text.z_vrfy_*) + *(.literal.z_mrsh_* .text.z_mrsh_*) + *(.literal.z_impl_* .text.z_impl_*) + *(.literal.z_obj_* .text.z_obj_*) + + *(.literal.k_sys_fatal_error_handler .text.k_sys_fatal_error_handler) + } >vec_helpers :vec_helpers_phdr +#endif /* CONFIG_XTENSA_MPU */ + +#ifdef CONFIG_CODE_DATA_RELOCATION +#include +#endif + + .ResetVector.text : ALIGN(4) + { + __rom_region_start = ABSOLUTE(.); + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >srom0_seg :srom0_phdr + + .text : HDR_MPU_SEGMENT_SIZE_ALIGN + { + _stext = .; + __text_region_start = .; + z_mapped_start = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *(.iram1.literal .iram1) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + + #include + + MPU_SEGMENT_SIZE_ALIGN + + _text_end = ABSOLUTE(.); + _etext = .; + } >RAMABLE_REGION + __text_region_end = .; + + .rodata : HDR_MPU_SEGMENT_SIZE_ALIGN + { + __rodata_region_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + + . = ALIGN(4); + #include + #include + } >RAMABLE_REGION + +#include + +#include + +#include + + .rodata_end : ALIGN(4) + { + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + + MPU_SEGMENT_SIZE_ALIGN + + __rodata_region_end = ABSOLUTE(.); + } >RAMABLE_REGION + +#ifdef CONFIG_USERSPACE +#define SMEM_PARTITION_ALIGN(size) MPU_SEGMENT_SIZE_ALIGN +#define APP_SHARED_ALIGN MPU_SEGMENT_SIZE_ALIGN + +#include + + _image_ram_start = _app_smem_start; + _app_smem_size = _app_smem_end - _app_smem_start; + _app_smem_num_words = _app_smem_size >> 2; + _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); + _app_smem_num_words = _app_smem_size >> 2; +#endif /* CONFIG_USERSPACE */ + + .data : HDR_MPU_SEGMENT_SIZE_ALIGN + { +#ifndef CONFIG_USERSPACE + _image_ram_start = ABSOLUTE(.); +#endif + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + + . = ALIGN(4); + #include + . = ALIGN(4); + + MPU_SEGMENT_SIZE_ALIGN + + __data_end = ABSOLUTE(.); + } >RAMABLE_REGION + +#include + +#include + +#include + +#include + +#include + + .bss (NOLOAD) : HDR_MPU_SEGMENT_SIZE_ALIGN + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.sram.bss) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + + MPU_SEGMENT_SIZE_ALIGN + + } >RAM :sram0_bss_phdr + +#include + +/* Must be last in RAM */ +#include + +#include + + _heap_start = .; + + PROVIDE(_heap_sentry = ORIGIN(RAM) + LENGTH(RAM)); + PROVIDE(_heap_end = ORIGIN(RAM) + LENGTH(RAM)); + + PROVIDE(__stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE); + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .debug.xt.callgraph 0 : + { + KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) + } +} diff --git a/soc/cdns/sample_controller32/mpu.c b/soc/cdns/sample_controller32/mpu.c new file mode 100644 index 0000000000000..c4ddb042a08bb --- /dev/null +++ b/soc/cdns/sample_controller32/mpu.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +#include +#include +#include + +const struct xtensa_mpu_range xtensa_soc_mpu_ranges[0]; +const int xtensa_soc_mpu_ranges_num; diff --git a/soc/cdns/sample_controller32/soc.yml b/soc/cdns/sample_controller32/soc.yml new file mode 100644 index 0000000000000..8f29326a09aba --- /dev/null +++ b/soc/cdns/sample_controller32/soc.yml @@ -0,0 +1,4 @@ +series: +- name: sample_controller32 + socs: + - name: sample_controller32 From 6052decc3986d03d85ad2550f49abe32e6af044c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 24 Apr 2024 10:51:48 -0700 Subject: [PATCH 3/3] boards: add qemu_xtensa/sample_controller32/mpu This adds the necessary bit to enable testing Xtensa MPU on QEMU. Signed-off-by: Daniel Leung --- boards/qemu/xtensa/Kconfig | 1 + boards/qemu/xtensa/Kconfig.qemu_xtensa | 3 ++- boards/qemu/xtensa/board.cmake | 4 ++-- boards/qemu/xtensa/board.yml | 3 +++ .../qemu_xtensa_sample_controller32_mpu.dts | 22 +++++++++++++++++++ .../qemu_xtensa_sample_controller32_mpu.yaml | 10 +++++++++ ...u_xtensa_sample_controller32_mpu_defconfig | 11 ++++++++++ 7 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts create mode 100644 boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml create mode 100644 boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig diff --git a/boards/qemu/xtensa/Kconfig b/boards/qemu/xtensa/Kconfig index 8cdc6ec28ff21..9ec79f85c1ee6 100644 --- a/boards/qemu/xtensa/Kconfig +++ b/boards/qemu/xtensa/Kconfig @@ -7,3 +7,4 @@ config BOARD_QEMU_XTENSA select QEMU_TARGET select ARCH_SUPPORTS_COREDUMP select XTENSA_MMU if BOARD_QEMU_XTENSA_DC233C_MMU + select XTENSA_MPU if BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU diff --git a/boards/qemu/xtensa/Kconfig.qemu_xtensa b/boards/qemu/xtensa/Kconfig.qemu_xtensa index f0aa1c8010c3b..6d1a9f9ce976c 100644 --- a/boards/qemu/xtensa/Kconfig.qemu_xtensa +++ b/boards/qemu/xtensa/Kconfig.qemu_xtensa @@ -4,4 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_QEMU_XTENSA - select SOC_XTENSA_DC233C + select SOC_XTENSA_SAMPLE_CONTROLLER32 if BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU + select SOC_XTENSA_DC233C if !BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU diff --git a/boards/qemu/xtensa/board.cmake b/boards/qemu/xtensa/board.cmake index 40818845da6d0..a11c7e8c1583a 100644 --- a/boards/qemu/xtensa/board.cmake +++ b/boards/qemu/xtensa/board.cmake @@ -3,10 +3,10 @@ set(SUPPORTED_EMU_PLATFORMS qemu) if(CONFIG_BOARD_QEMU_XTENSA) - set(QEMU_CPU_TYPE_${ARCH} dc233c) + set(QEMU_CPU_TYPE_${ARCH} ${CONFIG_SOC}) set(QEMU_FLAGS_${ARCH} - -machine sim -semihosting -nographic -cpu dc233c + -machine sim -semihosting -nographic -cpu ${CONFIG_SOC} ) endif() diff --git a/boards/qemu/xtensa/board.yml b/boards/qemu/xtensa/board.yml index 1441dcc25fc6a..0b2afcd488326 100644 --- a/boards/qemu/xtensa/board.yml +++ b/boards/qemu/xtensa/board.yml @@ -5,3 +5,6 @@ board: - name: dc233c variants: - name: mmu + - name: sample_controller32 + variants: + - name: mpu diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts new file mode 100644 index 0000000000000..4fba5a197f0ff --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "sample_controller32.dtsi" + +/ { + model = "qemu_xtensa_mpu"; + compatible = "cdns,xtensa-sample-controller32"; + + chosen { + zephyr,sram = &sram0; + }; +}; + +&cpu0 { + clock-frequency = <10000000>; +}; diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml new file mode 100644 index 0000000000000..5c91f09db79ce --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml @@ -0,0 +1,10 @@ +identifier: qemu_xtensa/sample_controller32/mpu +name: QEMU Emulation for Xtensa with MPU +type: qemu +simulation: qemu +arch: xtensa +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig new file mode 100644 index 0000000000000..8e34107fe3df3 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_STACK_SENTINEL=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_SIMULATOR_XTENSA=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_PRIVILEGED_STACK_SIZE=4096