diff --git a/boards/adi/max32666evkit/Kconfig.max32666evkit b/boards/adi/max32666evkit/Kconfig.max32666evkit new file mode 100644 index 0000000000000..a648082e50617 --- /dev/null +++ b/boards/adi/max32666evkit/Kconfig.max32666evkit @@ -0,0 +1,7 @@ +# MAX32666EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32666EVKIT + select SOC_MAX32666_CPU0 if BOARD_MAX32666EVKIT_MAX32666_CPU0 diff --git a/boards/adi/max32666evkit/board.cmake b/boards/adi/max32666evkit/board.cmake new file mode 100644 index 0000000000000..80033d85bdc65 --- /dev/null +++ b/boards/adi/max32666evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]") +board_runner_args(jlink "--device=MAX32666" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32666evkit/board.yml b/boards/adi/max32666evkit/board.yml new file mode 100644 index 0000000000000..5d1beff771670 --- /dev/null +++ b/boards/adi/max32666evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32666evkit + vendor: adi + socs: + - name: max32666 diff --git a/boards/adi/max32666evkit/doc/img/max32666evkit.webp b/boards/adi/max32666evkit/doc/img/max32666evkit.webp new file mode 100644 index 0000000000000..6eed641e25263 Binary files /dev/null and b/boards/adi/max32666evkit/doc/img/max32666evkit.webp differ diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst new file mode 100644 index 0000000000000..bd9384bfb319a --- /dev/null +++ b/boards/adi/max32666evkit/doc/index.rst @@ -0,0 +1,313 @@ +.. _max32666evkit: + +MAX32666EVKIT +############# + +Overview +******** +The MAX32666EVKIT provides a platform for evaluating the capabilities of the MAX32665 and MAX32666 +high-efficiency Arm® microcontrollers and audio DSP for wearable and hearable device applications. + + +The Zephyr port is running on the MAX32666 MCU. + +.. image:: img/max32666evkit.webp + :align: center + :alt: MAX32666EVKIT Front + + +Hardware +******** + +- MAX32666 MCU: + + - High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices + + - Arm Cortex-M4 with FPU Up to 96MHz + - Optional Second Arm Cortex-M4 with FPU Optimized for Data Processing + - Low-Power 7.3728MHz System Clock Option + - 1MB Flash, Organized into Dual Banks 2 x 512KB + - 560KB (448KB ECC) SRAM; 3 x 16KB Cache + - Optional Error Correction Code (ECC-SEC-DED)for Cache, SRAM, and Internal Flash + + - Bluetooth 5 Low Energy Radio + + - 1Mbps and 2Mbps Data Throughput + - Long Range (125kbps and 500kbps) + - Advertising Extension + - Rx Sensitivity: -95dbm; Tx Power Up to +4.5dbm + - On-Chip Matching with Single-Ended Antenna Port + + - Power Management Maximizes Operating Time for Battery Applications + + - Integrated SIMO SMPS for Coin-Cell Operation + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 27.3μA/MHz at 3.3V Executing from Cache + - Selectable SRAM Retention in Low Power Modes with RTC Enabled + + - Multiple Peripherals for System Control + + - Three QSPI Master/Slave with Three Chip Selects Each + - Three 4-Wire UARTs + - Three I2C Master/Slave + - Up to 50 GPIO + - QSPI (SPIXF) with Real-Time Flash Decryption + - QSPI (SPIXR) RAM Interface Provides SRAMExpansion + - 8-Input 10-Bit Delta-Sigma ADC 7.8ksps + - USB 2.0 HS Engine with Internal Transceiver + - PDM Interface Supports Two Digital Microphones + - I2S with TDM + - Six 32-Bit Timers + - Two High-Speed Timers + - 1-Wire Master + - Sixteen Pulse Trains (PWM) + - Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51 + + - Secure Valuable IP/Data with Hardware Security + + - Trust Protection Unit (TPU) with MAA SupportsFast ECDSA and Modular Arithmetic + - AES128/192/256, DES, 3DES, Hardware Accelerator + - TRNG Seed Generator + - SHA-2 Accelerator•Secure Bootloader + +- Benefits and Features of MAX32666EVKIT: + + - Bluetooth SMA connector with a 2.4GHz Hinged Whip Antenna + - 1.28in 128 x 128 Monochrome TFT Display + - 64MB XIP Flash + - 1MB XIP RAM + - Stereo Audio Codec with Line-In and Line-Out 3.5mm Jacks + - Digital Audio Microphone + - USB 2.0 Micro B Interface + - USB 2.0 Micro B to Serial UARTs + - Micro SD Card Interface + - Select GPIOs Accessed Through a 0.1in Header + - Access to the 8 Analog Inputs Through a 0.1in Header + - Arm® or SWD JTAG 20-Pin Header + - 1-Wire RJ11 Port + - Can Be Solely Sourced by a Coin Cell Battery + - Board Power Provided by Either USB Port + - Individual Power Measurement on All IC Rails Through Jumpers + - On-Board 1.8V and 3.3V Regulators + - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32666EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | I2C0_SCL/SDA | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C0 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C0 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C1_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C1 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C1 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C2_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C2 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C2 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | P1_14 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D2 from P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D2 to P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | P1_15 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D3 from P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D3 to P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | VBUS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VBUS to USB connector CN1 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VBUS to USB connector CN2 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_20 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_20 (RX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_28 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_28 (RX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_21 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_21 (TX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_29 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_29 (TX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_22 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_22 (CTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_30 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_30 (CTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_23 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_23 (RTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_31 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_31 (RTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VREGI | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VREGI to the coin cell battery. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VREGI to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects VDDIOH to VREGO_A | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Connects VDDIOH to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Connects VDDIOH to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | VDDB | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VDDIO to VREGO_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VDDIO to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCORE_A | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCORE_B | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | VTXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | VRXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32666 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J6. +Logic levels are fixed to VDDIOH (1.8V or 3.3V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 20-pin connector (J7) or a Cortex® 10-pin connector (J6). + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32666EVKIT web page`_ + +.. _MAX32666EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32666EVKIT.html diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts new file mode 100644 index 0000000000000..daa88c3a1e9c3 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32666EVKIT"; + compatible = "adi,max32666evkit"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio1 14 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio1 15 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p0_21 &uart1_rx_p0_20>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml new file mode 100644 index 0000000000000..0c28b7099f9c7 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml @@ -0,0 +1,15 @@ +identifier: max32666evkit/max32666/cpu0 +name: max32666evkit cpu0 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng +ram: 560 +flash: 1024 diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig new file mode 100644 index 0000000000000..fc547f746b1d0 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32666fthr/Kconfig.max32666fthr b/boards/adi/max32666fthr/Kconfig.max32666fthr new file mode 100644 index 0000000000000..ca6e313e6c14d --- /dev/null +++ b/boards/adi/max32666fthr/Kconfig.max32666fthr @@ -0,0 +1,7 @@ +# MAX32666FTHR boards configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32666FTHR + select SOC_MAX32666_CPU0 if BOARD_MAX32666FTHR_MAX32666_CPU0 diff --git a/boards/adi/max32666fthr/board.cmake b/boards/adi/max32666fthr/board.cmake new file mode 100644 index 0000000000000..b2315d05907d7 --- /dev/null +++ b/boards/adi/max32666fthr/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]") +board_runner_args(jlink "--device=MAX32666" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32666fthr/board.yml b/boards/adi/max32666fthr/board.yml new file mode 100644 index 0000000000000..a071afb909eb3 --- /dev/null +++ b/boards/adi/max32666fthr/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32666fthr + vendor: adi + socs: + - name: max32666 diff --git a/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg b/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg new file mode 100644 index 0000000000000..0e04eeb25eb3c Binary files /dev/null and b/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg differ diff --git a/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg b/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg new file mode 100644 index 0000000000000..84d109f9cc749 Binary files /dev/null and b/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg differ diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst new file mode 100644 index 0000000000000..850849e74b1ab --- /dev/null +++ b/boards/adi/max32666fthr/doc/index.rst @@ -0,0 +1,226 @@ +.. _max32666_fthr: + +MAX32666FTHR +############ + +Overview +******** +The MAX32666FTHR board is a rapid development platform to help engineers quickly implement battery +optimized Bluetooth® 5 solutions with the MAX32666 Arm® Cortex®-M4 processor with FPU. The board +also includes the MAX1555 1-Cell Li+ battery charger for battery management. The form factor is +a small 0.9in by 2.0in dualrow header footprint that is compatible with breadboards and +off-the-shelf peripheral expansion boards. The board also includes a variety of peripherals, +such as a micro SD card connector, 6-axis accelerometer/gyro, RGB indicator LED, and pushbutton. +This platform provides poweroptimized flexible for quick proof-of-concepts and early software +development to enhance time to market. + + +The Zephyr port is running on the MAX32666 MCU. + +.. image:: img/max32666fthr_img1.jpg + :align: center + :alt: MAX32666FTHR Front + +.. image:: img/max32666fthr_img1.jpg + :align: center + :alt: MAX32666FTHR Back + +Hardware +******** + +- MAX32666 MCU: + + - High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices + + - Arm Cortex-M4 with FPU Up to 96MHz + - Optional Second Arm Cortex-M4 with FPU Optimized for Data Processing + - Low-Power 7.3728MHz System Clock Option + - 1MB Flash, Organized into Dual Banks 2 x 512KB + - 560KB (448KB ECC) SRAM; 3 x 16KB Cache + - Optional Error Correction Code (ECC-SEC-DED)for Cache, SRAM, and Internal Flash + + - Bluetooth 5 Low Energy Radio + + - 1Mbps and 2Mbps Data Throughput + - Long Range (125kbps and 500kbps) + - Advertising Extension + - Rx Sensitivity: -95dbm; Tx Power Up to +4.5dbm + - On-Chip Matching with Single-Ended Antenna Port + + - Power Management Maximizes Operating Time for Battery Applications + + - Integrated SIMO SMPS for Coin-Cell Operation + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 27.3μA/MHz at 3.3V Executing from Cache + - Selectable SRAM Retention in Low Power Modes with RTC Enabled + + - Multiple Peripherals for System Control + + - Three QSPI Master/Slave with Three Chip Selects Each + - Three 4-Wire UARTs + - Three I2C Master/Slave + - Up to 50 GPIO + - QSPI (SPIXF) with Real-Time Flash Decryption + - QSPI (SPIXR) RAM Interface Provides SRAMExpansion + - 8-Input 10-Bit Delta-Sigma ADC 7.8ksps + - USB 2.0 HS Engine with Internal Transceiver + - PDM Interface Supports Two Digital Microphones + - I2S with TDM + - Six 32-Bit Timers + - Two High-Speed Timers + - 1-Wire Master + - Sixteen Pulse Trains (PWM) + - Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51 + + - Secure Valuable IP/Data with Hardware Security + + - Trust Protection Unit (TPU) with MAA SupportsFast ECDSA and Modular Arithmetic + - AES128/192/256, DES, 3DES, Hardware Accelerator + - TRNG Seed Generator + - SHA-2 Accelerator•Secure Bootloader + +- External devices connected to the MAX32666FTHR: + + - MAX1555 1-Cell Li+ Battery Charger + - Breadboard Compatible Headers + - 10-Pin Cortex Debug Header + - Micro USB Connector + - Micro SD Card Connector + - RGB Indicator LED and One General Purpose Push Button Switch + - 6-Axis Accelerometer/Gyro + - Bluetooth Surface Mount Antenna + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32666FTHR. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + +JH3 Pinout +********** + ++---------+----------+-------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+=================================================================================================+ +| 1 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 2 | P0_9 | UART0 Tx | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 3 | P0_10 | UART0 Rx | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 4 | P0_26 | QSPI2 MISO | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 5 | P0_25 | QSPI2 MOSI | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 6 | P0_27 | QSPI2 SCK | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 7 | AIN_5 | ADC Analog Input. Alternatively, AIN2N or P0_21 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 8 | AIN_4 | ADC Analog Input. Alternatively, AIN2P or P0_20 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 9 | AIN_3 | ADC Analog Input. Alternatively, AIN1N or P0_19 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 10 | AIN_2 | ADC Analog Input. Alternatively, AIN1P or P0_18 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 11 | AIN_1 | ADC Analog Input. Alternatively, AIN0N or P0_17 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 12 | AIN_0 | ADC Analog Input. Alternatively, AIN0P or P0_16 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 13 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 14 | NC | No Connection | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 15 | 3V3 | 3.3V Output. Typically used to provide 3.3V to peripherals connected to the expansion headers | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 16 | RSTN | Master Reset Signal | ++---------+----------+-------------------------------------------------------------------------------------------------+ + + +JH4 Pinout +********** + ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+===========================================================================================================+ +| 1 | SYS | SYS switched connection to the Battery. This is the primary system power supply and | +| | | automatically switches between the battery voltage and the USB supply when available. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 2 | PWREN | Power Enable. This is connected to the ON pin of the MAX4995 LDO. It turns off the LDO if shorted to GND. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 3 | VBUS | USB VBUS Signal. This can be used as a 5V supply when connected to USB. This pin can also be used as | +| | | an input to power the board, but this should only be done when not using the USB connector since there is | +| | | no circuitry to prevent current from flowing back into the USB connector. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 4 | P0_12 | 1-Wire master signal | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 5 | P0_3 | SPIXF SCK | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 6 | P0_5 | SPIXF SDIO3 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 7 | P0_4 | SPIXF SDIO2 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 8 | P0_2 | SPIXF SDIO1/MISO | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 9 | P0_1 | SPIXF SDIO0/MOSI | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 10 | P0_0 | SPIXF SS0 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 11 | P0_6 | I2CM0 SCL. Pulled to MAX32666 VDDIOH, connected to BMI160. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 12 | P0_7 | I2CM0 SDA. Pulled to MAX32666 VDDIOH, connected to BMI160. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32666 MCU can be flashed by connecting an external debug probe to the SWD port. +SWD debug can be accessed through the Cortex 10-pin connector, JH2. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH2) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32666FTHR web page`_ + +.. _MAX32666FTHR web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32666FTHR.html diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts new file mode 100644 index 0000000000000..cd201ea58c19e --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32666FTHR"; + compatible = "adi,max32666fthr"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + led3: led_3 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + sw0 = &pb1; + }; + + /* Used for accessing other pins */ + feather_header: feather_connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <12 0 &gpio0 7 0>, /* SDA */ + <13 0 &gpio0 6 0>, /* SCL */ + <14 0 &gpio0 0 0>, /* GPIO */ + <15 0 &gpio0 1 0>, /* GPIO */ + <16 0 &gpio0 2 0>, /* GPIO */ + <17 0 &gpio0 4 0>, /* GPIO */ + <18 0 &gpio0 5 0>, /* GPIO */ + <19 0 &gpio0 3 0>, /* GPIO */ + <20 0 &gpio0 12 0>, /* OWM */ + /* 11 not connected */ + <10 0 &gpio0 9 0>, /* TX */ + <9 0 &gpio0 10 0>, /* RX */ + <8 0 &gpio0 26 0>, /* MISO */ + <7 0 &gpio0 25 0>, /* MOSI */ + <6 0 &gpio0 27 0>, /* SCK */ + <5 0 &gpio0 21 0>, /* AIN5 */ + <4 0 &gpio0 20 0>, /* AIN4 */ + <3 0 &gpio0 19 0>, /* AIN3 */ + <2 0 &gpio0 18 0>, /* AIN2 */ + <1 0 &gpio0 17 0>, /* AIN1 */ + <0 0 &gpio0 16 0>; /* AIN0 */ + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p1_13 &uart1_rx_p1_12>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml new file mode 100644 index 0000000000000..42d8f981577ff --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -0,0 +1,15 @@ +identifier: max32666fthr/max32666/cpu0 +name: max32666fthr cpu0 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng +ram: 560 +flash: 1024 diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig new file mode 100644 index 0000000000000..b0a3b911431ba --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/dts/arm/adi/max32/max32666-pinctrl.dtsi b/dts/arm/adi/max32/max32666-pinctrl.dtsi new file mode 100644 index 0000000000000..a44553f74a045 --- /dev/null +++ b/dts/arm/adi/max32/max32666-pinctrl.dtsi @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + pinctrl: pin-controller@40008000 { + + /omit-if-no-ref/ spixf_ss0_p0_0: spixf_ss0_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_cts_p0_0: uart2_cts_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_0: tmr0_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ spixf_mosi_p0_1: spixf_mosi_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_tx_p0_1: uart2_tx_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_1: tmr1_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ spixf_miso_p0_2: spixf_miso_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_rx_p0_2: uart2_rx_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2_p0_2: tmr2_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ spixf_sck_p0_3: spixf_sck_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_rts_p0_3: uart2_rts_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3_p0_3: tmr3_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ spixf_sdio2_p0_4: spixf_sdio2_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_io_p0_4: owm_io_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4_p0_4: tmr4_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ spixf_sdio3_p0_5: spixf_sdio3_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/owm_pe_p0_5: owm_pe_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5_p0_5: tmr5_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0_scl_p0_6: i2c0_scl_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ swdio2_p0_6: swdio2_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_6: tmr0_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0_sda_p0_7: i2c0_sda_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ swclk2_p0_7: swclck2_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_7: tmr1_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_ss0_p0_8: spixr_ss0_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss0_p0_8: spi0_ss0_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_cts_p0_8: uart0_cts_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2_p0_8: tmr2_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_mosi_p0_9: spixr_mosi_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_mosi_p0_9: spi0_mosi_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3_p0_9: tmr3_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_miso_p0_10: spixr_miso_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_miso_p0_10: spi0_miso_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rx_p0_10: uart0_rx_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4_p0_10: tmr4_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_sck_p0_11: spixr_sck_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sck_p0_11: spi0_sck_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rts_p0_11: uart0_rts_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5_p0_11: tmr5_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_sdio2_p0_12: spixr_sdio2_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sdio2_p0_12: spi0_sdio2_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_io_p0_12: owm_io_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_12: tmr0_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ spixr_sdio3_p0_13: spixr_sdio3_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sdio3_p0_13: spi0_sdio3_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_pe_p0_13: owm_pe_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_13: tmr1_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1_scl_p0_14: i2c1_scl_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss1_p0_14: spi0_ss1_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2_p0_14: tmr2_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1_sda_p0_15: i2c1_sda_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss2_p0_15: spi0_ss2_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3_p0_15: tmr3_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ ain0n_p0_16: ain0n_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_ss0_p0_16: spi1_ss0_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_io_p0_16: owm_io_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4_p0_16: tmr4_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ ain0p_p0_17: ain0p_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_mosi_p0_17: spi1_mosi_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_pe_p0_17: owm_pe_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5_p0_17: tmr5_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ ain1n_p0_18: ain1n_p0_18 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_miso_p0_18: spi1_miso_p0_18 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_18: tmr0_p0_18 { + pinmux = ; + }; + + /omit-if-no-ref/ ain1p_p0_19: ain1p_p0_19 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_sck_p0_19: spi1_sck_p0_19 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_19: tmr1_p0_19 { + pinmux = ; + }; + + /omit-if-no-ref/ ain2n_p0_20: ain2n_p0_20 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_sdio2_p0_20: spi1_sdio2_p0_20 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rx_p0_20: uart1_rx_p0_20 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2_p0_20: tmr2_p0_20 { + pinmux = ; + }; + + /omit-if-no-ref/ ain2p_p0_21: ain2p_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_sdio3_p0_21: spi1_sdio3_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_tx_p0_21: uart1_tx_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3_p0_21: tmr3_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ ain3n_p0_22: ain3n_p0_22 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_ss1_p0_22: spi1_ss1_p0_22 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_cts_p0_22: uart1_cts_p0_22 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4_p0_22: tmr4_p0_22 { + pinmux = ; + }; + + /omit-if-no-ref/ ain3p_p0_23: ain3p_p0_23 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_ss2_p0_23: spi1_ss2_p0_23 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rts_p0_23: uart1_rts_p0_23 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5_p0_23: tmr5_p0_23 { + pinmux = ; + }; + + /omit-if-no-ref/ pcm_lrclk_p0_24: pcm_lrclk_p0_24 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_ss0_p0_24: spi2_ss0_p0_24 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_io_p0_24: owm_io_p0_24 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_24: tmr0_p0_24 { + pinmux = ; + }; + + /omit-if-no-ref/ pcm_dout_p0_25: pcm_dout_p0_25 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_mosi_p0_25: spi2_mosi_p0_25 { + pinmux = ; + }; + + /omit-if-no-ref/ owm_pe_p0_25: owm_pe_p0_25 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_25: tmr1_p0_25 { + pinmux = ; + }; + + /omit-if-no-ref/ pcm_din_p0_26: pcm_din_p0_26 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_miso_p0_26: spi2_miso_p0_26 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2_p0_26: tmr2_p0_26 { + pinmux = ; + }; + + /omit-if-no-ref/ pcm_bclk_p0_27: pcm_bclk_p0_27 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_sck_p0_27: spi2_sck_p0_27 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3_p0_27: tmr3_p0_27 { + pinmux = ; + }; + + /omit-if-no-ref/ pdm_data2_p0_28: pdm_data2_p0_28 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_sdio2_p0_28: spi2_sdio2_p0_28 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_rx_p0_28: uart2_rx_p0_28 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4_p0_28: tmr4_p0_28 { + pinmux = ; + }; + + /omit-if-no-ref/ pdm_data3_p0_29: pdm_data3_p0_29 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_sdio3_p0_29: spi2_sdio3_p0_29 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_tx_p0_29: uart2_tx_p0_29 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5_p0_29: tmr5_p0_29 { + pinmux = ; + }; + + /omit-if-no-ref/ pdm_rx_clk_p0_30: pdm_rx_clk_p0_30 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_ss1_p0_30: spi2_ss1_p0_30 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_cts_p0_30: uart2_cts_p0_30 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_30: tmr0_p0_30 { + pinmux = ; + }; + + /omit-if-no-ref/ pdm_mclk_p0_31: pdm_mclk_p0_31 { + pinmux = ; + }; + + /omit-if-no-ref/ spi2_ss2_p0_31: spi2_ss2_p0_31 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2_rts_p0_31: uart2_rts_p0_31 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1_p0_31: tmr1_p0_31 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_dat3_p1_0: sdhc_dat3_p1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ sdma_tms_p1_0: sdma_tms_p1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ pt0_p1_0: pt0_p1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_cmd_p1_1: sdhc_cmd_p1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ sdma_tdo_p1_1: sdma_tdo_p1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ pt1_p1_1: pt1_p1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_dat0_p1_2: sdhc_dat0_p1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ sdma_tdi_p1_2: sdma_tdi_p1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ pt2_p1_2: pt2_p1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_clk_p1_3: sdhc_clk_p1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ sdma_tck_p1_3: sdma_tck_p1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ pt3_p1_3: pt3_p1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_dat1_p1_4: sdhc_dat1_p1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rx_p1_4: uart0_rx_p1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ pt5_p1_4: pt5_p1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_dat2_p1_5: sdhc_dat2_p1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_tx_p1_5: uart0_tx_p1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ pt5_p1_5: pt5_p1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_wp_p1_6: sdhc_wp_p1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_cts_p1_6: uart0_cts_p1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ pt6_p1_6: pt6_p1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ sdhc_cdn_p1_7: sdhc_cdn_p1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rts_p1_7: uart0_rts_p1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ pt7_p1_7: pt7_p1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss0_p1_8: spi0_ss0_p1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ pt8_p1_8: pt8_p1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_mosi_p1_9: spi0_mosi_p1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ pt9_p1_9: pt9_p1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_miso_p1_10: spi0_miso_p1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ pt10_p1_10: pt10_p1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sck_p1_11: spi0_sck_p1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ pt11_p1_11: pt11_p1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sdio2_p1_12: spi0_sdio2_p1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rx_p1_12: uart1_rx_p1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ pt12_p1_12: pt12_p1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sdio3_p1_13: spi0_sdio3_p1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_tx_p1_13: uart1_tx_p1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ pt13_p1_13: pt13_p1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c2_scl_p1_14: i2c2_scl_p1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_cts_p1_14: uart1_cts_p1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ pt14_p1_14: pt14_p1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c2_sda_p1_15: i2c2_sda_p1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rts_p1_15: uart1_rts_p1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ pt15_p1_15: pt15_p1_15 { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi new file mode 100644 index 0000000000000..e9fd4bc9b679f --- /dev/null +++ b/dts/arm/adi/max32/max32666.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&clk_ipo { + clock-frequency = ; +}; + +&uart0 { + /delete-property/ clock-source; +}; + +&uart1 { + /delete-property/ clock-source; +}; + +&uart2 { + /delete-property/ clock-source; +}; + +/* MAX32666 extra peripherals. */ +/ { + soc { + sram1: memory@20008000 { + compatible = "mmio-sram"; + reg = <0x20008000 DT_SIZE_K(32)>; + }; + + sram2: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 DT_SIZE_K(64)>; + }; + + sram3: memory@20020000 { + compatible = "mmio-sram"; + reg = <0x20020000 DT_SIZE_K(64)>; + }; + + sram4: memory@20030000 { + compatible = "mmio-sram"; + reg = <0x20030000 DT_SIZE_K(128)>; + }; + + sram5: memory@20050000 { + compatible = "mmio-sram"; + reg = <0x20050000 DT_SIZE_K(128)>; + }; + + sram6: memory@20070000 { + compatible = "mmio-sram"; + reg = <0x20070000 DT_SIZE_K(8)>; + }; + + sram7: memory@20072000 { + compatible = "mmio-sram"; + reg = <0x20072000 DT_SIZE_K(8)>; + }; + + sram8: memory@20074000 { + compatible = "mmio-sram"; + reg = <0x20074000 DT_SIZE_K(16)>; + }; + + sram9: memory@20078000 { + compatible = "mmio-sram"; + reg = <0x20078000 DT_SIZE_K(16)>; + }; + + sram10: memory@2007c000 { + compatible = "mmio-sram"; + reg = <0x2007c000 DT_SIZE_K(32)>; + }; + + sram11: memory@20084000 { + compatible = "mmio-sram"; + reg = <0x20084000 DT_SIZE_K(32)>; + }; + + flc1: flash_controller@40029400 { + compatible = "adi,max32-flash-controller"; + reg = <0x40029400 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + flash1: flash@10080000 { + compatible = "soc-nv-flash"; + reg = <0x10080000 DT_SIZE_K(512)>; + write-block-size = <16>; + erase-block-size = <8192>; + }; + }; + }; +}; diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig index ff597b95cc81b..80642dc339993 100644 --- a/soc/adi/max32/Kconfig +++ b/soc/adi/max32/Kconfig @@ -17,6 +17,9 @@ config SOC_MAX32655 config SOC_MAX32662 select CPU_CORTEX_M4 +config SOC_MAX32666 + select CPU_CORTEX_M4 + config SOC_MAX32670 select CPU_CORTEX_M4 diff --git a/soc/adi/max32/Kconfig.defconfig.max32666 b/soc/adi/max32/Kconfig.defconfig.max32666 new file mode 100644 index 0000000000000..25213269dbc8b --- /dev/null +++ b/soc/adi/max32/Kconfig.defconfig.max32666 @@ -0,0 +1,14 @@ +# Analog Devices MAX32666 MCU + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MAX32666 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency) + +config NUM_IRQS + default 95 + +endif # SOC_MAX32666 diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index d1db3d161b03b..e56456047fb29 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -21,6 +21,14 @@ config SOC_MAX32662 bool select SOC_FAMILY_MAX32 +config SOC_MAX32666 + bool + select SOC_FAMILY_MAX32 + +config SOC_MAX32666_CPU0 + bool + select SOC_MAX32666 + config SOC_MAX32670 bool select SOC_FAMILY_MAX32 @@ -52,6 +60,7 @@ config SOC_MAX32690_M4 config SOC default "max32655" if SOC_MAX32655 default "max32662" if SOC_MAX32662 + default "max32666" if SOC_MAX32666 default "max32670" if SOC_MAX32670 default "max32672" if SOC_MAX32672 default "max32675" if SOC_MAX32675 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index e8f36ee2d4c8b..701509dc15cfd 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -8,6 +8,9 @@ family: cpuclusters: - name: m4 - name: max32662 + - name: max32666 + cpuclusters: + - name: cpu0 - name: max32670 - name: max32672 - name: max32675 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32666evkit_max32666_cpu0.overlay new file mode 100644 index 0000000000000..fb94814fe391f --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32666evkit_max32666_cpu0.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 6 0>; + in-gpios = <&gpio0 7 0>; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32666fthr_max32666_cpu0.overlay new file mode 100644 index 0000000000000..224df12c8c1e4 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32666fthr_max32666_cpu0.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 2 0>; + in-gpios = <&gpio0 4 0>; + }; +};