diff --git a/boards/adi/max32675evkit/Kconfig.max32675evkit b/boards/adi/max32675evkit/Kconfig.max32675evkit new file mode 100644 index 0000000000000..25732ef6631e1 --- /dev/null +++ b/boards/adi/max32675evkit/Kconfig.max32675evkit @@ -0,0 +1,7 @@ +# MAX32675EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32675EVKIT + select SOC_MAX32675 diff --git a/boards/adi/max32675evkit/board.cmake b/boards/adi/max32675evkit/board.cmake new file mode 100644 index 0000000000000..42caa77e95b02 --- /dev/null +++ b/boards/adi/max32675evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32675.cfg]") +board_runner_args(jlink "--device=MAX32675" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32675evkit/board.yml b/boards/adi/max32675evkit/board.yml new file mode 100644 index 0000000000000..d51c7284c7f40 --- /dev/null +++ b/boards/adi/max32675evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32675evkit + vendor: adi + socs: + - name: max32675 diff --git a/boards/adi/max32675evkit/doc/img/max32675evkit.webp b/boards/adi/max32675evkit/doc/img/max32675evkit.webp new file mode 100644 index 0000000000000..c884836b2be37 Binary files /dev/null and b/boards/adi/max32675evkit/doc/img/max32675evkit.webp differ diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst new file mode 100644 index 0000000000000..1ed63d4994d77 --- /dev/null +++ b/boards/adi/max32675evkit/doc/index.rst @@ -0,0 +1,401 @@ +.. _max32675_evkit: + +MAX32675EVKIT +############# + +Overview +******** +The MAX32675 evaluation kit (EV kit) provides a platform for evaluation capabilities of +the MAX32675 microcontroller, which is a highly integrated, mixed-signal, ultralow-power +microcontroller designed for industrial and medical sensors. It contains an integrated, low-power +HART modem which enables the bidirectional transfer of digital data over a current loop, to/from +industrial sensors for configuration and diagnostics. + +The Zephyr port is running on the MAX32675 MCU. + +.. image:: img/max32675evkit.webp + :align: center + :alt: MAX32675EVKIT + +Hardware +******** + +- MAX32675 MCU: + + - Low-Power, High-Performance for IndustrialApplications + + - 100MHz Arm Cortex-M4 with FPU + - 384KB Internal Flash + - 160KB SRAM + - 128kB ECC Enabled + - 44.1μA/MHz ACTIVE Mode at 0.9V up to 12MHzCoremark® + - 64.5μA/MHz ACTIVE Mode at 1.1V up to 100MHzCoremark + - 2.84μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V + - Ultra-Low-Power Analog Peripherals + + - Optimal Peripheral Mix Provides Platform Scalability + + - Two Sigma-Delta ADCs + - 12 Channels, Assignable to Either ADC + - Flexible Resolution and Sample Rates (24 Bits at 0.4ksps, 16 Bits at 4ksps) + - 12-Bit DAC + - On-Die Temperature Sensor + - SPI (M/S) + - Up to Two I2C + - Up to Two UARTs + - Up to 23 GPIOs + - Up to Five 32-Bit Timers + - Two Windowed Watchdog Timers + - 8-Channel Standard DMA Controller + - One I2S Slave for Digital Audio Interface + + - Robust Security and Reliability + + - TRNG Compliant to SP800-90B + - Secure Nonvolatile Key Storage and AES-128/192/256 + - Secure Bootloader to Protect IP/Firmware + - Wide, -40°C to +105°C Operating TemperatureRange + + +- Benefits and Features of MAX32675EVKIT: + + - HART Compatible Secondary Master with the Ability to Connect to Existing 4-20mA Current Loop and Communicate with HART Enabled Devices + - USB 2.0 Micro B to Serial UART + - Two On-Board, High-Precision Voltage References + - All GPIOs Signals Accessed Through 0.1in Headers + - Access to 4 Analog Inputs Through SMA Connectors Configured as Differential + - Access to 8 Analog Inputs Through 0.1in Headers Configured as Single-Ended + - DAC Output Accessed Through SMA Connector or Test Point + - 10-Pin SWD and Connector + - Board Power Provided by USB Port + - On-Board 1.0V, 1.8V, and 3.3V LDO Regulators + - Individual Power Measurement on all IC Rails Through Jumpers + - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32675EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | P1_9 | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED D1 from P1_9. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects red LED D1 to P1_9. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | P1_10 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED D2 from P1_10. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects green LED D2 to P1_10. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C_SCLK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 from I2C_SCLK. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 3V3 to I2C0_SCLK. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 to I2C_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 3V3 to I2C_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | UART0_RX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects UART0_RX (P0.8) from the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects UART0_RX (P0.8) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | UART0_TX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disonnects UART0_TX (P0.9) from the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects UART0_TX (P0.9) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | REF0N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF0N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF0N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | REF1N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF1N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF1N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | Open | | | Disconnects TX of USB - serial bridge from HART_IN (P0.15). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.15). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | Open | | | Disconnects RX of USB - serial bridge from HART_OUT (P0.14). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | 3-4 | | | Connects RX of USB - serial bridge to HART_OUT (P0.14). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | Open | | | Disconnects RTS of USB - serial bridge from HART_RTS (P1.8). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | 4-5 | | | Connects TX of USB - serial bridge to HART_RTS (P1.8). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | Open | | | Disconnects RTS of USB - serial bridge from HART_OCD (P0.16). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | 7-8 | | | Connects TX of USB - serial bridge to HART_OCD (P0.16). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | SWD_CLK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects boot load enable circuit from SWD_CLK (P0.1). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects boot load enable circuit to SWD_CLK (P0.1). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | FSK_IN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_IN from HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_IN to HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | FSK_OUT | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_OUT from HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_OUT to HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | RCV_FSK | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from XFMR LOOP. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to XFMR LOOP. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249Ω resistor shunt from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249Ω resistor shunt to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | HART_RTS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Enables HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Bypasses HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249Ω resistor shunt from XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249Ω resistor shunt to XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | VDD18 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDD18. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDD18. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP24 | VCORE | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP25 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects OB_VREF to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects INT_VREF to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP26 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects OB_VREF to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects INT_VREF to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Detailed Description of Hardware +================================ + +HART Interface +************** +The HART circuitry acts as a secondary master with the ability to connect to an existing 4mA–20mA +current loop and communicates with HART-enabled devices. Connection to a capacitance coupled loop +through JH8 and a transformer loop is through JH9. HART communication to the MAX32675 is through +the USB connector CN1. + +USB-to-HART Interface +********************* +The EV kit provides a USB-to-HART bridge chip, FTDI FT231. This bridge eliminates the requirement +for a physical RS-232 COM port. Instead, the IC’s HART access is through the Micro-USB type-B +connector, CN1. Virtual COM port drivers and guides for installing Windows® drivers are available +at the FTDI chip website. + +Power Supply +************ +The EV kit is powered by +5V that is made available through VBUS on the Micro-USB type-B +connector CN1. A blue LED (D5) illuminates when the board is powered. Green LEDs (D6), (D7), +and (D8) illuminate when the 3V3, 1V8, and 1V0 LDOs are powered, respectively. + +Current Monitoring +****************** +Two pin headers provide convenient current monitoring points for VDDIO EN (JP21), +VDDA EN (JP22), VDD18 EN (JP23), and VCORE (JP24). +To accurately achieve the low-power current values, the EVkit needs to be configured +such that no outside influence (i.e., pullups, external clock, debugger connector, etc.) +causes a current source or sink on that GPIO. + +Clocking +******** +The MAX32675 clocking is provided by an external 16MHz crystal (Y1). + +Voltage Reference +***************** +The differential reference inputs REF0 and REF1 can be sourced by an internal reference (INT_VREF) +or a higher precision external reference source, MAX6071. +This is selected by jumpers JP25 and JP26. + +UART Interface +************** +The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates +the requirement for a physical RS-232 COM port. Instead, the IC’s UART access is through +the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0 +or LPUART0 with jumpers JP10 (RX0) and JP11 (TX0). Virtual COM port drivers and guides for +installing Windows® drivers are available on the FTDI Chip website. + +Boot Loader +*********** +Boot load is activated by boot load enable slide switch SW5. + +GPIO and Alternate Function Headers +*********************************** +GPIO and alternate function signals from the MAX32675 can be accessed through 0.1in +spaced headers JH1, JH2, JH3, and JH4. + +Analog Input Access +******************* +Analog inputs (AIN0–AIN3) can be accessed differentially from SMA connectors J2 and J3 or +separately from TP10, TP12, TP15, and TP16, respectively. Analog inputs (AIN4–AIN11) can be +accessed through 0.1in spaced headers JH5 and JH6. + +I2C Pullups +*********** +The I2C port can independently pulled up to 3V3 through JP3 (I2C_SCL) and JP4 (I2C_SDA). + +Reset Pushbutton +**************** +The IC can be reset by pushbutton SW3. + +Indicator LEDs +************** +General-purpose indicators LED D1 (red) is connected to GPIO P1.9 and LED D2 (green) is connected +to GPIO P1.10. + +GPIO Pushbutton Switches +************************ +The two general-purpose pushbuttons (SW1 and SW2) are connected to GPIO P1.11 and P1.12, +respectively. If the pushbutton is pressed, the attached port pin is pulled low. + + +Programming and Debugging +************************* + +Flashing +======== + +SWD debug can be accessed through an Arm Cortex 10-pin connector (J5). +Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT) +is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect +the 3.3V LDO if supplying VDD and VDDA externally. + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH2) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32675EVKIT web page`_ + +.. _MAX32675EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32675evkit.html diff --git a/boards/adi/max32675evkit/max32675evkit.dts b/boards/adi/max32675evkit/max32675evkit.dts new file mode 100644 index 0000000000000..b3b5b9d49f7e1 --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32675EVKIT"; + compatible = "adi,max32675evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram3; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW1"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml new file mode 100644 index 0000000000000..3ec16411c8390 --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit.yaml @@ -0,0 +1,15 @@ +identifier: max32675evkit +name: max32675evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng +ram: 160 +flash: 384 diff --git a/boards/adi/max32675evkit/max32675evkit_defconfig b/boards/adi/max32675evkit/max32675evkit_defconfig new file mode 100644 index 0000000000000..a048ab2608ff0 --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/dts/arm/adi/max32/max32675-pinctrl.dtsi b/dts/arm/adi/max32/max32675-pinctrl.dtsi new file mode 100644 index 0000000000000..28920ec0b184b --- /dev/null +++ b/dts/arm/adi/max32/max32675-pinctrl.dtsi @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + pinctrl: pin-controller@40008000 { + + /omit-if-no-ref/ swdio_p0_0: swdio_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_ia_p0_0: tmr0c_ia_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_oa_p0_1: tmr0c_oa_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0a_scl_p0_6: i2c0a_scl_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ lptmr0b_ia_p0_6: lptmr0b_ia_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3c_ia_p0_6: tmr3c_ia_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0a_sda_p0_7: i2c0a_sda_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ lptmr0b_oa_p0_7: lptmr0b_oa_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3c_oa_p0_7: tmr3c_oa_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_rx_p0_8: uart0a_rx_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0b_sdo_p0_8: i2s0b_sdo_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_ia_p0_8: tmr0c_ia_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_tx_p0_9: uart0a_tx_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0b_lrclk_p0_9: i2s0b_lrclk_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_oa_p0_9: tmr0c_oa_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_cts_p0_10: uart0a_cts_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0b_bclk_p0_10: i2s0b_bclk_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_ia_p0_10: tmr1c_ia_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ ext_clk_p0_10: ext_clk_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_rts_p0_11: uart0a_rts_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0b_sdi_p0_11: i2s0b_sdi_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_oa_p0_11: tmr1c_oa_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2c_oa_p0_13: tmr2c_oa_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1d_ss0_p0_13: spi1d_ss0_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1a_miso_p0_14: spi1a_miso_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2b_rx_p0_14: uart2b_rx_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3c_ia_p0_14: tmr3c_ia_p0_14 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1a_mosi_p0_15: spi1a_mosi_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2b_tx_p0_15: uart2b_tx_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3c_oa_p0_15: tmr3c_oa_p0_15 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1a_sck_p0_16: spi1a_sck_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2b_cts_p0_16: uart2b_cts_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_ia_p0_16: tmr0c_ia_p0_16 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1a_ss0_p0_17: spi1a_ss0_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2b_rts_p0_17: uart2b_rts_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_oa_p0_17: tmr0c_oa_p0_17 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c2a_scl_p0_18: i2c2a_scl_p0_18 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_ia_p0_18: tmr1c_ia_p0_18 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c2a_sda_p0_19: i2c2a_sda_p0_19 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_oa_p0_19: tmr1c_oa_p0_19 { + pinmux = ; + }; + + /omit-if-no-ref/ cm4_tx_p0_21: cm4_tx_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2c_oa_p0_21: tmr2c_oa_p0_21 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3c_oa_p0_31: tmr3c_oa_p0_31 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2a_rx_p1_8: uart2a_rx_p1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2b_rts_p1_8: uart2b_rts_p1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2a_tx_p1_9: uart2a_tx_p1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2a_cts_p1_10: uart2a_cts_p1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ uart2a_rts_p1_11: uart2a_rts_p1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2c_oa_p1_11: tmr2c_oa_p1_11 { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/adi/max32/max32675.dtsi b/dts/arm/adi/max32/max32675.dtsi new file mode 100644 index 0000000000000..8ab6a74f03547 --- /dev/null +++ b/dts/arm/adi/max32/max32675.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&flash0 { + reg = <0x10000000 DT_SIZE_K(384)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(16)>; +}; + +&clk_inro { + clock-frequency = ; +}; + +/delete-node/ &clk_iso; +/delete-node/ &uart1; + +/* MAX32675 extra peripherals. */ +/ { + soc { + sram1: memory@20004000 { + compatible = "mmio-sram"; + reg = <0x20004000 DT_SIZE_K(16)>; + }; + + sram2: memory@20008000 { + compatible = "mmio-sram"; + reg = <0x20008000 DT_SIZE_K(32)>; + }; + + sram3: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 DT_SIZE_K(64)>; + }; + + sram4: memory@20020000 { + compatible = "mmio-sram"; + reg = <0x20020000 DT_SIZE_K(4)>; + }; + + sram5: memory@20021000 { + compatible = "mmio-sram"; + reg = <0x20021000 DT_SIZE_K(4)>; + }; + + sram6: memory@20022000 { + compatible = "mmio-sram"; + reg = <0x20022000 DT_SIZE_K(8)>; + }; + + sram7: memory@20024000 { + compatible = "mmio-sram"; + reg = <0x20024000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig index a6e6d06d4324d..d612184349519 100644 --- a/soc/adi/max32/Kconfig +++ b/soc/adi/max32/Kconfig @@ -20,6 +20,9 @@ config SOC_MAX32670 config SOC_MAX32672 select CPU_CORTEX_M4 +config SOC_MAX32675 + select CPU_CORTEX_M4 + config SOC_MAX32680 select CPU_CORTEX_M4 diff --git a/soc/adi/max32/Kconfig.defconfig.max32675 b/soc/adi/max32/Kconfig.defconfig.max32675 new file mode 100644 index 0000000000000..3718cef954935 --- /dev/null +++ b/soc/adi/max32/Kconfig.defconfig.max32675 @@ -0,0 +1,14 @@ +# Analog Devices MAX32675 MCU + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MAX32675 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency) + +config NUM_IRQS + default 100 + +endif # SOC_MAX32675 diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index 19743fc1a0d16..2a1f5f0a9ccf0 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -25,6 +25,10 @@ config SOC_MAX32672 bool select SOC_FAMILY_MAX32 +config SOC_MAX32675 + bool + select SOC_FAMILY_MAX32 + config SOC_MAX32680 bool select SOC_FAMILY_MAX32 @@ -45,5 +49,6 @@ config SOC default "max32655" if SOC_MAX32655 default "max32670" if SOC_MAX32670 default "max32672" if SOC_MAX32672 + default "max32675" if SOC_MAX32675 default "max32680" if SOC_MAX32680 default "max32690" if SOC_MAX32690 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index 65c999cc35cbe..ba1d3d80016dc 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -9,6 +9,7 @@ family: - name: m4 - name: max32670 - name: max32672 + - name: max32675 - name: max32680 cpuclusters: - name: m4 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32675evkit.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32675evkit.overlay new file mode 100644 index 0000000000000..a26574b5cd14d --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32675evkit.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 19 0>; + in-gpios = <&gpio0 21 0>; + }; +};