diff --git a/boards/adi/max32662evkit/Kconfig.max32662evkit b/boards/adi/max32662evkit/Kconfig.max32662evkit new file mode 100644 index 0000000000000..341e421cd9c7a --- /dev/null +++ b/boards/adi/max32662evkit/Kconfig.max32662evkit @@ -0,0 +1,7 @@ +# MAX32662EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32662EVKIT + select SOC_MAX32662 diff --git a/boards/adi/max32662evkit/board.cmake b/boards/adi/max32662evkit/board.cmake new file mode 100644 index 0000000000000..48ee0fa505f8a --- /dev/null +++ b/boards/adi/max32662evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32662.cfg]") +board_runner_args(jlink "--device=MAX32662" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32662evkit/board.yml b/boards/adi/max32662evkit/board.yml new file mode 100644 index 0000000000000..628de9d766874 --- /dev/null +++ b/boards/adi/max32662evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32662evkit + vendor: adi + socs: + - name: max32662 diff --git a/boards/adi/max32662evkit/doc/img/max32662evkit.webp b/boards/adi/max32662evkit/doc/img/max32662evkit.webp new file mode 100644 index 0000000000000..6757d84654fbd Binary files /dev/null and b/boards/adi/max32662evkit/doc/img/max32662evkit.webp differ diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst new file mode 100644 index 0000000000000..04c868e050f0f --- /dev/null +++ b/boards/adi/max32662evkit/doc/index.rst @@ -0,0 +1,229 @@ +.. _max32662_evkit: + +MAX32662EVKIT +############# + +Overview +******** +The MAX32662 evaluation kit (EV kit) provides a platform for evaluating +the capabilities of the MAX32662 microcontroller, which is a cost-effective, +ultra-low power, highly integrated 32-bit microcontroller designed +for battery-powered edge devices. + +The Zephyr port is running on the MAX32662 MCU. + +.. image:: img/max32662evkit.webp + :align: center + :alt: MAX32662EVKIT + +Hardware +******** + +- MAX32662 MCU: + + - High-Efficiency Microcontroller for Low-Power High-Reliability Devices + + - 256KB Flash + - 80KB SRAM, Optionally Preserved in LowestPower BACKUP Mode + - 16KB Unified Cache + - Memory Protection Unit (MPU) + - Dual- or Single-Supply Operation: 1.7V to 3.6V + - Wide Operating Temperature: -40°C to +105°C + + - Flexible Clocking Schemes + + - Internal High-Speed 100MHz + - Internal Low-Power 7.3728MHz + - Ultra-Low-Power 80kHz + - 16MHz–32MHz (External Crystal Required) + - 32.768kHz (External Crystal Required) + - External Clock Inputs for CPU and Low-PowerTimer + + - Power Management Maximizes Uptime for Battery Applications + + - 50μA/MHz at 0.9V up to 12MHz (CoreMark®) inACTIVE Mode + - 44μA/MHz at 1.1V up to 100MHz (While(1)) inACTIVE Mode + - 2.15μA Full Memory Retention Current in BACKUPMode at VDDIO = 1.8V + - 2.4μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V + - 350nA Ultra-Low-Power RTC + - Wakeup from Low-Power Timer + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 21 General-Purpose I/O Pins + - 4-Channel, 12-Bit, 1Msps ADC + - Two SPI Controller/Target + - One I2S Controller/Target + - Two 4-Wire UART + - Two I2C Controller/Target + - One CAN 2.0B Controller + - 4-Channel Standard DMA Controller + - Three 32-Bit Timers + - One 32-Bit Low-Power Timer + - One Watchdog Timer + - CMOS-Level 32.768kHz Calibration Output + - AES-128/192/256 Hardware Accelerator + +- Benefits and Features of MAX32662EVKIT: + + - 3-Pin Terminal Block for CAN Bus 2.0B + - 128 x 128 (1.45in) Color TFT Display with SPI Interface + - Selectable On-Board High-Precision Voltage Reference + - USB 2.0 Micro-B to Serial UART + - All GPIOs Signals Accessed through 0.1in Headers + - Four Analog Inputs Accessed through 0.1in Header + - SWD 10-Pin Header + - Board Power Provided by USB Port + - On-Board LDO Regulators + - Individual Power Measurement on All IC Rails through Jumpers + - One General-Purpose LED + - One General-Purpose Pushbutton Switch + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32662EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VREF EN | | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the external voltage reference to the VREF pin; must be enabled in the software. | | +| | | | | | | See the External Voltage Reference (VREF) section for additional information. | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the external voltage reference. | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C1_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the pull-up to I2C1A_SCL (P0.6); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the pull-up from I2C1A_SCL (P0.6); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | N/A | N/A | Does not exist. | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C1_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the pull-up to I2C1A_SDA (P0.9); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Oepn | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables LED0. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disables LED0. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | CTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_CTS (P0.20). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_CTS (P0.20). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | RX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RX (P0.11). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RX (P0.11). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | TX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_TX (P0.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_TX (P0.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | RTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RTS (P0.19). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RTS (P0.19). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V1 to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V1 from VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | VDDIO/VDDASEL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects 1V8 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects 3V3 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the JP11 selected voltage to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the voltage from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +An Arm® debug access port (DAP) provides an external interface for debugging during application +development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial +interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J3). Logic levels are set +to V_AUX (1V8 or 3V3), which is determined by the shunt placement on JP11. In addition, +the UART1A port can also be accessed through J3. + + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32662EVKIT web page`_ + +.. _MAX32662EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32662evkit.html diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts new file mode 100644 index 0000000000000..124c39cda90b6 --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32662EVKIT"; + compatible = "adi,max32662evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + sw0 = &pb1; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_10 &uart0a_rx_p0_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml new file mode 100644 index 0000000000000..480e4805782f2 --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit.yaml @@ -0,0 +1,15 @@ +identifier: max32662evkit +name: max32662evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng +ram: 80 +flash: 256 diff --git a/boards/adi/max32662evkit/max32662evkit_defconfig b/boards/adi/max32662evkit/max32662evkit_defconfig new file mode 100644 index 0000000000000..a048ab2608ff0 --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/dts/arm/adi/max32/max32662-pinctrl.dtsi b/dts/arm/adi/max32/max32662-pinctrl.dtsi new file mode 100644 index 0000000000000..585b08f85c8b2 --- /dev/null +++ b/dts/arm/adi/max32/max32662-pinctrl.dtsi @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + pinctrl: pin-controller@40008000 { + + /omit-if-no-ref/ swdio_p0_0: swdio_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ pt0b_p0_0: pt0b_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_oa_p0_0: tmr0c_oa_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1d_oa_p0_0: tmr1d_oa_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_trig_e_p0_0: adc_trig_e_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ pt1b_p0_1: pt1b_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_ia_p0_1: tmr0c_ia_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1d_ia_p0_1: tmr1d_ia_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0a_cito_p0_2: spi0a_cito_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1b_tx_p0_2: uart1b_tx_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_ia_p0_2: tmr0c_ia_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ pt0d_p0_2: pt0d_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0e_sdo_p0_2: i2s0e_sdo_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0a_copi_p0_3: spi0a_copi_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1b_rx_p0_3: uart1b_rx_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0c_oa_p0_3: tmr0c_oa_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ pt1d_p0_3: pt1d_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0e_sdi_p0_3: i2s0e_sdi_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0a_sck_p0_4: spi0a_sck_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1b_cts_p0_4: uart1b_cts_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_ia_p0_4: tmr1c_ia_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ pt2d_p0_4: pt2d_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0e_bclk_p0_4: i2s0e_bclk_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0a_ts0_p0_5: spi0a_ts0_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1b_rts_p0_5: uart1b_rts_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1c_oa_p0_5: tmr1c_oa_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ pt3d_p0_5: pt3d_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0e_lrclk_p0_5: i2s0e_lrclk_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1a_scl_p0_6: i2c1a_scl_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ can0b_rx_p0_6: can0b_rx_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2c_ia_p0_6: tmr2c_ia_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ hf_ext_clk_p0_6: hf_ext_clk_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ pt2e_p0_6: pt2e_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1a_sda_p0_9: i2c1a_sda_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ can0b_tx_p0_9: can0b_tx_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2c_oa_p0_9: tmr2c_oa_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_trig_d_p0_9: adc_trig_d_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ pt3e_p0_9: pt3e_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_tx_p0_10: uart0a_tx_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1b_ts0_p0_10: spi1b_ts0_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ ain3_p0_10: ain3_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0a_rx_p0_11: uart0a_rx_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1b_sck_p0_11: spi1b_sck_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ cal32k_p0_11: cal32k_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ ain2_p0_11: ain2_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ lp_ext_clk_p0_11: lp_ext_clk_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0a_scl_p0_12: i2c0a_scl_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1b_coti_p0_12: spi1b_coti_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ lptmr0c_ia_p0_12: lptmr0c_ia_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ ain1_p0_12: ain1_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ lptmr0e_oan_p0_12: lptmr0e_oan_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0a_sda_p0_13: i2c0a_sda_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1b_cito_p0_13: spi1b_cito_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ lptmr0c_oa_p0_13: lptmr0c_oa_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ ain0_p0_13: ain0_p0_13 { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/adi/max32/max32662.dtsi b/dts/arm/adi/max32/max32662.dtsi new file mode 100644 index 0000000000000..5a3e22d0b7541 --- /dev/null +++ b/dts/arm/adi/max32/max32662.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&flash0 { + reg = <0x10000000 DT_SIZE_K(256)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(16)>; +}; + +/delete-node/ &clk_iso; + +/delete-node/ &gpio1; + +/delete-node/ &uart2; + +/* MAX32662 extra peripherals. */ +/ { + soc { + sram1: memory@20004000 { + compatible = "mmio-sram"; + reg = <0x20004000 DT_SIZE_K(16)>; + }; + + sram2: memory@20008000 { + compatible = "mmio-sram"; + reg = <0x20008000 DT_SIZE_K(16)>; + }; + + sram3: memory@2000c000 { + compatible = "mmio-sram"; + reg = <0x2000c000 DT_SIZE_K(16)>; + }; + + sram4: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 DT_SIZE_K(4)>; + }; + + sram5: memory@20011000 { + compatible = "mmio-sram"; + reg = <0x20011000 DT_SIZE_K(4)>; + }; + + sram6: memory@20012000 { + compatible = "mmio-sram"; + reg = <0x20012000 DT_SIZE_K(4)>; + }; + + sram7: memory@20013000 { + compatible = "mmio-sram"; + reg = <0x20013000 DT_SIZE_K(4)>; + }; + }; +}; diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig index d612184349519..ff597b95cc81b 100644 --- a/soc/adi/max32/Kconfig +++ b/soc/adi/max32/Kconfig @@ -14,6 +14,9 @@ config SOC_FAMILY_MAX32 config SOC_MAX32655 select CPU_CORTEX_M4 +config SOC_MAX32662 + select CPU_CORTEX_M4 + config SOC_MAX32670 select CPU_CORTEX_M4 diff --git a/soc/adi/max32/Kconfig.defconfig.max32662 b/soc/adi/max32/Kconfig.defconfig.max32662 new file mode 100644 index 0000000000000..997c0f2515ac3 --- /dev/null +++ b/soc/adi/max32/Kconfig.defconfig.max32662 @@ -0,0 +1,14 @@ +# Analog Devices MAX32662 MCU + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MAX32662 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency) + +config NUM_IRQS + default 108 + +endif # SOC_MAX32662 diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index 2a1f5f0a9ccf0..d1db3d161b03b 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -17,6 +17,10 @@ config SOC_MAX32655_M4 bool select SOC_MAX32655 +config SOC_MAX32662 + bool + select SOC_FAMILY_MAX32 + config SOC_MAX32670 bool select SOC_FAMILY_MAX32 @@ -47,6 +51,7 @@ config SOC_MAX32690_M4 config SOC default "max32655" if SOC_MAX32655 + default "max32662" if SOC_MAX32662 default "max32670" if SOC_MAX32670 default "max32672" if SOC_MAX32672 default "max32675" if SOC_MAX32675 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index ba1d3d80016dc..e8f36ee2d4c8b 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -7,6 +7,7 @@ family: - name: max32655 cpuclusters: - name: m4 + - name: max32662 - name: max32670 - name: max32672 - name: max32675 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32662evkit.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32662evkit.overlay new file mode 100644 index 0000000000000..cfe65202b81a3 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32662evkit.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 5 0>; + in-gpios = <&gpio0 7 0>; + }; +}; diff --git a/west.yml b/west.yml index 61b40799e8945..9180c6a6ee09e 100644 --- a/west.yml +++ b/west.yml @@ -137,7 +137,7 @@ manifest: groups: - fs - name: hal_adi - revision: dee9a7b1eff13a9da0560daf8842d61657f9d61e + revision: 1a700a62511c96d8c3d8b4e29c9503855fec50c5 path: modules/hal/adi groups: - hal