diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 078beb62d0150..ff458210bddfe 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3766,7 +3766,7 @@ Renesas RA Platforms: - thaoluonguw files: - boards/arduino/uno_r4/ - - boards/renesas/*ra8*/ + - boards/renesas/*ra*/ - drivers/*/*renesas_ra* - drivers/pinctrl/renesas/ra/ - dts/arm/renesas/ra/ diff --git a/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 new file mode 100644 index 0000000000000..06f6e754a0810 --- /dev/null +++ b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6E2 + select SOC_R7FA6E2BB3CFM diff --git a/boards/renesas/ek_ra6e2/board.cmake b/boards/renesas/ek_ra6e2/board.cmake new file mode 100644 index 0000000000000..368e10209f9c3 --- /dev/null +++ b/boards/renesas/ek_ra6e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E2BB") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6e2/board.yml b/boards/renesas/ek_ra6e2/board.yml new file mode 100644 index 0000000000000..972476c9b2ef9 --- /dev/null +++ b/boards/renesas/ek_ra6e2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6e2 + vendor: renesas + socs: + - name: r7fa6e2bb3cfm diff --git a/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp new file mode 100644 index 0000000000000..56ebb4c77e72c Binary files /dev/null and b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp differ diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst new file mode 100644 index 0000000000000..aad21a93ea435 --- /dev/null +++ b/boards/renesas/ek_ra6e2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra6e2: + +RA6E2 Evaluation Kit +#################### + +Overview +******** + +The EK-RA6E2, an Evaluation Kit for RA6E2 MCU Group, enables users to +seamlessly evaluate the features of the RA6E2 MCU group and develop +embedded systems applications using Flexible Software Package (FSP) +and e2 studio IDE. The users can use rich on-board features along with +their choice of popular ecosystems add-ons to bring their big ideas to life + +The key features of the EK-RA6E2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package +- 256 kB Code Flash, 40 kB SRAM +- Native pin access through 2 x 14-pin and 1 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals, + providing precision 20.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6E2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Three 5V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and J31 through holes) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD) + - Debug out (JTAG, SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I3C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- 16 Mb (128 Mb) External Quad-SPI Flash +- CAN (3-pin header) + +.. figure:: ek-ra6e2-board.webp + :align: center + :alt: RA6E2 Evaluation Kit + + EK-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ + +.. figure:: ra6e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E2 MCU group feature + + RA6E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E2BB +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6E2 Website`_ +- `RA6E2 MCU group Website`_ + +.. _EK-RA6E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6e2-evaluation-kit-ra6e2-mcu-group + +.. _RA6E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _EK-RA6E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6e2-v1-users-manual + +.. _RA6E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp new file mode 100644 index 0000000000000..7eeb1bc516f89 Binary files /dev/null and b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts new file mode 100644 index 0000000000000..682aafcd006b1 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6e2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6E2"; + compatible = "renesas,ra6e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 13 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + storage_partition: partition@20000 { + label = "storage"; + reg = <0x20000 DT_SIZE_K(128)>; + }; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml new file mode 100644 index 0000000000000..dcb71bda519a1 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6e2 +name: Renesas EK-RA6E2 +type: mcu +arch: arm +ram: 40 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig new file mode 100644 index 0000000000000..92bb425cfa8bb --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 new file mode 100644 index 0000000000000..c21e240aeaaff --- /dev/null +++ b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M1 + select SOC_R7FA6M1AD3CFP diff --git a/boards/renesas/ek_ra6m1/board.cmake b/boards/renesas/ek_ra6m1/board.cmake new file mode 100644 index 0000000000000..1a34ff999584c --- /dev/null +++ b/boards/renesas/ek_ra6m1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M1AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m1/board.yml b/boards/renesas/ek_ra6m1/board.yml new file mode 100644 index 0000000000000..db68eb8a0684e --- /dev/null +++ b/boards/renesas/ek_ra6m1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m1 + vendor: renesas + socs: + - name: r7fa6m1ad3cfp diff --git a/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp new file mode 100644 index 0000000000000..438d21dc19b53 Binary files /dev/null and b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp differ diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst new file mode 100644 index 0000000000000..955c87ac32bb6 --- /dev/null +++ b/boards/renesas/ek_ra6m1/doc/index.rst @@ -0,0 +1,161 @@ +.. _ek_ra6m1: + +RA6M1 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M1 microcontroller is the entry point to the Renesas RA6 product +series for applications that require a high-performance Arm® Cortex®-M4 core at +a very attractive price point. The RA6M1 is built on a highly efficient 40nm process +and is supported by an open and flexible ecosystem concept—the Flexible Software +Package (FSP), built on FreeRTOS—and is expandable to use other RTOSes and middleware. +The RA6M1 is suitable for IoT applications requiring security, large embedded RAM and +low power consumption. + +The key features of the EK-RA6M1 board are categorized in three groups as follow: + +**MCU Native Pin Access** +- R7FA6M1AD3CFP +- 100-pin LQFP package +- 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU) +- 256 KB SRAM +- 512 KB code flash memory +- 8 KB data flash memory + +**Connectivity** +- A Device USB connector for the Main MCU +- S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the +RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external +debuggers and programmers. +- Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for +rapid prototyping +- Pin headers for access to power and signals for the Main MCU + +**Multiple clock sources** +- Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference +clocks +- Additional low-precision clocks are available internal to the Main MCU + +**General purpose I/O ports** +- One jumper to allow measuring of Main MCU current +- Copper jumpers on PCB bottom side for configuration and access to selected MCU signals +**Operating voltage** +- External 5 V input through the Debug USB connector supplies the on-board power regulator to power +logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate +locations on the board. +- A two-color board status LED indicating availability of regulated power and connection status of the J-Link +interface. +- A red User LED, controlled by the Main MCU firmware +- A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer, +all of which are controlled by the Main MCU firmware +- MCU reset push-button switch +- MCU boot configuration jumper + +**Special Feature Access** + +- USB Full Speed Debug and Device (micro-AB connector) + +.. figure:: ek-ra6m1-board.webp + :align: center + :alt: RA6M1 Evaluation Kit + + EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_ + +.. figure:: ra6m1-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M1 MCU group feature + + RA6M1 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M1AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M1 Website`_ +- `RA6M1 MCU group Website`_ + +.. _EK-RA6M1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group + +.. _RA6M1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m1-32-bit-microcontrollers-120mhz-optimized-entry-point-ra6-series + +.. _EK-RA6M1 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m1-v1-users-manual + +.. _RA6M1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/renesas-ra6m1-group-users-manual-hardware?r=1054156 + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp new file mode 100644 index 0000000000000..2f9511bf9a51e Binary files /dev/null and b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi new file mode 100644 index 0000000000000..56fa3e26b6abb --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts new file mode 100644 index 0000000000000..013c7d4fa88e8 --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M1"; + compatible = "renesas,ra6m1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + status = "okay"; + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml new file mode 100644 index 0000000000000..92e8d569db224 --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra6m1 +name: Renesas EK-RA6M1 +type: mcu +arch: arm +ram: 256 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig new file mode 100644 index 0000000000000..00adc77146e5e --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 new file mode 100644 index 0000000000000..106137b4c4bc2 --- /dev/null +++ b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M2 + select SOC_R7FA6M2AF3CFB diff --git a/boards/renesas/ek_ra6m2/board.cmake b/boards/renesas/ek_ra6m2/board.cmake new file mode 100644 index 0000000000000..4ebea5664ca0b --- /dev/null +++ b/boards/renesas/ek_ra6m2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M2AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m2/board.yml b/boards/renesas/ek_ra6m2/board.yml new file mode 100644 index 0000000000000..325b1601c9a5b --- /dev/null +++ b/boards/renesas/ek_ra6m2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m2 + vendor: renesas + socs: + - name: r7fa6m2af3cfb diff --git a/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp new file mode 100644 index 0000000000000..e58a8a1191442 Binary files /dev/null and b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp differ diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst new file mode 100644 index 0000000000000..a3cb9f0e88754 --- /dev/null +++ b/boards/renesas/ek_ra6m2/doc/index.rst @@ -0,0 +1,155 @@ +.. _ek_ra6m2: + +RA6M2 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M2 microcontroller is the entry point to the Renesas RA6 product series +for applications that require a high-performance Arm® Cortex®-M4 core at a very attractive +price point. The RA6M2 is suitable for IoT applications requiring security, large embedded +RAM and low power consumption. + +The key features of the EK-RA6M2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 120MHz Arm Cortex-M4 based RA6M2 MCU in 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M2 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed device +- 5V input through USB debug + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - One User LEDs + - One User buttons + - One Reset button + +- Three most popular ecosystems expansions + + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- USB Full Speed Host and Device (micro-AB connector) + +.. figure:: ek-ra6m2-board.webp + :align: center + :alt: RA6M2 Evaluation Kit + + EK-RA6M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_ + +.. figure:: ra6m2-block-diagram.webp + :width: 871px + :align: center + :alt: RA6M2 MCU group feature + + RA6M2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M2AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M2 Website`_ +- `RA6M2 MCU group Website`_ + +.. _EK-RA6M2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m2-evaluation-kit-ra6m2-mcu-group + +.. _RA6M2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m2-32-bit-microcontrollers-120mhz-medium-size-memory-integration-and-ethernet + +.. _EK-RA6M2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m2-v1-users-manual-0 + +.. _RA6M2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/renesas-ra6m2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp new file mode 100644 index 0000000000000..5b7256380b5c3 Binary files /dev/null and b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi new file mode 100644 index 0000000000000..69d920e7edab6 --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci7_default: sci7_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts new file mode 100644 index 0000000000000..78407352e72d4 --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M2"; + compatible = "renesas,ra6m2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart7; + zephyr,shell-uart = &uart7; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + status = "okay"; + uart7: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml new file mode 100644 index 0000000000000..3f3c049c5e563 --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m2 +name: Renesas EK-RA6M2 +type: mcu +arch: arm +ram: 384 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig new file mode 100644 index 0000000000000..00adc77146e5e --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 new file mode 100644 index 0000000000000..eb3f5510d45b4 --- /dev/null +++ b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M3 + select SOC_R7FA6M3AH3CFC diff --git a/boards/renesas/ek_ra6m3/board.cmake b/boards/renesas/ek_ra6m3/board.cmake new file mode 100644 index 0000000000000..a395cf75494c4 --- /dev/null +++ b/boards/renesas/ek_ra6m3/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M3AH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m3/board.yml b/boards/renesas/ek_ra6m3/board.yml new file mode 100644 index 0000000000000..2bf115b0a184a --- /dev/null +++ b/boards/renesas/ek_ra6m3/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m3 + vendor: renesas + socs: + - name: r7fa6m3ah3cfc diff --git a/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp new file mode 100644 index 0000000000000..9aa1acf04da2d Binary files /dev/null and b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp differ diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst new file mode 100644 index 0000000000000..bb468d9d1f52f --- /dev/null +++ b/boards/renesas/ek_ra6m3/doc/index.rst @@ -0,0 +1,163 @@ +.. _ek_ra6m3: + +RA6M3 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M3 group uses the high-performance Arm® Cortex®-M4 core and +offers a TFT controller with 2D accelerator and JPEG decoder. The RA6M3 is +suitable for IoT applications requiring TFT, Ethernet, security, large +embedded RAM, and USB High Speed (HS). + +The key features of the EK-RA6M3 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M3 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Four most popular ecosystems expansions + + - Two Seeed Grove system (I2C) connectors + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 32 Mb (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra6m3-board.webp + :align: center + :alt: RA6M3 Evaluation Kit + + EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_ + +.. figure:: ra6m3-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M3 MCU group feature + + RA6M3 Block diagram (Credit: Renesas Electronics Corporation) + +Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M3 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m3`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M3 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M3AH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M3 Website`_ +- `RA6M3 MCU group Website`_ + +.. _EK-RA6M3 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m3-evaluation-kit-ra6m3-mcu-group + +.. _RA6M3 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m3-32-bit-microcontrollers-120mhz-usb-high-speed-ethernet-and-tft-controller + +.. _EK-RA6M3 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m3-v1-users-manual + +.. _RA6M3 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6m3-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp new file mode 100644 index 0000000000000..e95bf93ee05cd Binary files /dev/null and b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi new file mode 100644 index 0000000000000..56fa3e26b6abb --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts new file mode 100644 index 0000000000000..0cd4de22aa19d --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m3-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M3"; + compatible = "renesas,ra6m3", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 3 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + status = "okay"; + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml new file mode 100644 index 0000000000000..50cc8737e921f --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m3 +name: Renesas EK-RA6M3 +type: mcu +arch: arm +ram: 640 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig new file mode 100644 index 0000000000000..31c2fa759e481 --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 new file mode 100644 index 0000000000000..28ed45ff14b44 --- /dev/null +++ b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M4 + select SOC_R7FA6M4AF3CFB diff --git a/boards/renesas/ek_ra6m4/board.cmake b/boards/renesas/ek_ra6m4/board.cmake new file mode 100644 index 0000000000000..66f79828a34ad --- /dev/null +++ b/boards/renesas/ek_ra6m4/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M4AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m4/board.yml b/boards/renesas/ek_ra6m4/board.yml new file mode 100644 index 0000000000000..5c7e34ff1809c --- /dev/null +++ b/boards/renesas/ek_ra6m4/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m4 + vendor: renesas + socs: + - name: r7fa6m4af3cfb diff --git a/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp new file mode 100644 index 0000000000000..b146b233ba7d5 Binary files /dev/null and b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp differ diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst new file mode 100644 index 0000000000000..82549000d63c8 --- /dev/null +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -0,0 +1,168 @@ +.. _ek_ra6m4: + +RA6M4 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M4 group uses the high-performance Arm® Cortex®-M33 +core with TrustZone®. Secure element functionality providing better +performance, unlimited secure key storage, key management, and lower +BOM cost, as well as the integrated Ethernet MAC with individual DMA +ensures high data throughput. The RA6M4 is suitable for IoT applications +requiring Ethernet, future proof security, large embedded RAM, and low +active power consumption down to 99uA/MHz running the CoreMark® +algorithm from Flash. + +The key features of the EK-RA6M4 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6M4 MCU in 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M4 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M4 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- 32 Mb (256 Mb) External Quad-SPI Flash +- 64 Mb (512 Mb) External Octo-SPI Flash + +.. figure:: ek-ra6m4-board.webp + :align: center + :alt: RA6M4 Evaluation Kit + + EK-RA6M4 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_ + +.. figure:: ra6m4-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M4 MCU group feature + + RA6M4 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M4 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m4`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M4 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M4AF +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M4 Website`_ +- `RA6M4 MCU group Website`_ + +.. _EK-RA6M4 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m4-evaluation-kit-ra6m4-mcu-group + +.. _RA6M4 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m4-200mhz-arm-cortex-m33-trustzone-high-integration-ethernet-and-octaspi + +.. _EK-RA6M4 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra6m4-v1-users-manual + +.. _RA6M4 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra6m4-group-user-s-manual-hardware?r=1333976 + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp new file mode 100644 index 0000000000000..3bf83cf0a5983 Binary files /dev/null and b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts new file mode 100644 index 0000000000000..5fcb92a2b93a0 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m4-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M4"; + compatible = "renesas,ra6m4", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&pclka { + clk_src = ; + clk_div = ; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml new file mode 100644 index 0000000000000..d9488b99e8129 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m4 +name: Renesas EK-RA6M4 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig new file mode 100644 index 0000000000000..45a5a73366a55 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 new file mode 100644 index 0000000000000..fccd13875b9fa --- /dev/null +++ b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M5 + select SOC_R7FA6M5BH3CFC diff --git a/boards/renesas/ek_ra6m5/board.cmake b/boards/renesas/ek_ra6m5/board.cmake new file mode 100644 index 0000000000000..5aabef8bb75d7 --- /dev/null +++ b/boards/renesas/ek_ra6m5/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M5BH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m5/board.yml b/boards/renesas/ek_ra6m5/board.yml new file mode 100644 index 0000000000000..826e64f943e1d --- /dev/null +++ b/boards/renesas/ek_ra6m5/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m5 + vendor: renesas + socs: + - name: r7fa6m5bh3cfc diff --git a/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp new file mode 100644 index 0000000000000..073a0493daaf0 Binary files /dev/null and b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp differ diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst new file mode 100644 index 0000000000000..bc94a155e11d8 --- /dev/null +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -0,0 +1,166 @@ +.. _ek_ra6m5: + +RA6M5 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M5 group uses the high-performance Arm® Cortex®-M33 core with +TrustZone®. The RA6M5 is suitable for IoT applications requiring Ethernet, future +proof security, large embedded RAM, and low active power consumption down +to 107uA/MHz running the CoreMark® algorithm from Flash. + +The key features of the EK-RA6M5 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6M5 MCU in 176 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M5 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M5 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 32 Mb (256 Mb) External Quad-SPI Flash +- 64 Mb (512 Mb) External Octo-SPI Flash +- CAN (3-pin header) + +.. figure:: ek-ra6m5-board.webp + :align: center + :alt: RA6M5 Evaluation Kit + + EK-RA6M5 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_ + +.. figure:: ra6m5-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M5 MCU group feature + + RA6M5 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M5 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m5`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M5 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M5BH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M5 Website`_ +- `RA6M5 MCU group Website`_ + +.. _EK-RA6M5 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group + +.. _RA6M5 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m5-200mhz-arm-cortex-m33-trustzone-highest-integration-ethernet-and-can-fd + +.. _EK-RA6M5 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra6m5-v1-users-manual + +.. _RA6M5 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra6m5-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp new file mode 100644 index 0000000000000..456726a84461c Binary files /dev/null and b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts new file mode 100644 index 0000000000000..ad84e26a1678f --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m5-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M5"; + compatible = "renesas,ra6m5", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport0 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport0 7 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport0 8 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport0 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml new file mode 100644 index 0000000000000..2f65bfb229d83 --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m5 +name: Renesas EK-RA6M5 +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig new file mode 100644 index 0000000000000..4b5534eb1ff12 --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 new file mode 100644 index 0000000000000..03c2ffd080a98 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RA6E1 + select SOC_R7FA6E10F2CFP diff --git a/boards/renesas/fpb_ra6e1/board.cmake b/boards/renesas/fpb_ra6e1/board.cmake new file mode 100644 index 0000000000000..f4e7c1669a581 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E10F") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_ra6e1/board.yml b/boards/renesas/fpb_ra6e1/board.yml new file mode 100644 index 0000000000000..ed1e0a18bfdb3 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/board.yml @@ -0,0 +1,5 @@ +board: + name: fpb_ra6e1 + vendor: renesas + socs: + - name: r7fa6e10f2cfp diff --git a/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp new file mode 100644 index 0000000000000..f11bcf13039ba Binary files /dev/null and b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp differ diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst new file mode 100644 index 0000000000000..17332f0c5e296 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/doc/index.rst @@ -0,0 +1,150 @@ +.. _fpb_ra6e1: + +RA6E1 Fast Prototyping Board +############################ + +Overview +******** + +The Renesas RA6E1 group uses the high-performance Arm® Cortex®-M33 core with +TrustZone®. The RA6E1 is suitable for entry IoT applications requiring streamlined +feature and connectivity integration including Ethernet, and unprecedented performance +with 790.75 CoreMark, which are 3.95CoreMark / Mhz. + +The key features of the FPB-RA6E1 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E1 MCU in 100 pins, LQFP package +- Native pin access through 2 x 50-pin male headers (not fitted) +- MCU current measurement point for precision current consumption measurement +- Multiple clock sources - Low-precision (~1%) clocks are available internal to + the RA MCU. RA MCU oscillator and sub-clock oscillator crystals, providing + precision 24.000 MHz (not fitted) and 32,768 Hz reference clocks are also available + +**System Control and Ecosystem Access** + +- Two 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using 2-pin header) (not fitted) + +- Built-in SEGGER J-Link Emulator On-Board programmer/debugger (SWD) + +- User LEDs and buttons + + - Two User LEDs (green) + - Power LED (green) (not fitted) indicating availability of regulated power + - Debug/power LED (yellow) indicating power and the debug connection + - One User button + - One Reset button + +- Two popular ecosystems expansions + + - Two Digilent PmodTM (SPI, UART) connectors (not fitted) + - Arduino (Uno R3) connector + +- MCU boot configuration jumper + +.. figure:: fpb-ra6e1-board.webp + :align: center + :alt: RA6E1 Evaluation Kit + + FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_ + +.. figure:: ra6e1-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E1 MCU group feature + + RA6E1 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for FPB-RA6E1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``fpb_ra6e1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to FPB-RA6E1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E10F +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `FPB-RA6E1 Website`_ +- `RA6E1 MCU group Website`_ + +.. _FPB-RA6E1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e1-fast-prototyping-board-ra6e1-mcu-group#overview + +.. _RA6E1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e1-200mhz-arm-cortex-m33-entry-line-high-performance-streamlined-connectivity + +.. _FPB-RA6E1 - User's Manual: + https://www.renesas.com/us/en/document/mat/fpb-ra6e1-users-manual + +.. _RA6E1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp new file mode 100644 index 0000000000000..b6f70e68ab8a0 Binary files /dev/null and b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp differ diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi new file mode 100644 index 0000000000000..3c01cb6bec4cf --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts new file mode 100644 index 0000000000000..6f73498953965 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "fpb_ra6e1-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RA6E1"; + compatible = "renesas,ra6e1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + + storage_partition: partition@80000 { + label = "storage"; + reg = <0x80000 DT_SIZE_K(512)>; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml new file mode 100644 index 0000000000000..8942834aca56b --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml @@ -0,0 +1,11 @@ +identifier: fpb_ra6e1 +name: Renesas FPB-RA6E1 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig new file mode 100644 index 0000000000000..fa7ef716d3f62 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 new file mode 100644 index 0000000000000..d23cc0e3b6dcf --- /dev/null +++ b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RA6E2 + select SOC_R7FA6E2BB3CFM diff --git a/boards/renesas/fpb_ra6e2/board.cmake b/boards/renesas/fpb_ra6e2/board.cmake new file mode 100644 index 0000000000000..368e10209f9c3 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E2BB") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_ra6e2/board.yml b/boards/renesas/fpb_ra6e2/board.yml new file mode 100644 index 0000000000000..0d28094c404bc --- /dev/null +++ b/boards/renesas/fpb_ra6e2/board.yml @@ -0,0 +1,5 @@ +board: + name: fpb_ra6e2 + vendor: renesas + socs: + - name: r7fa6e2bb3cfm diff --git a/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp new file mode 100644 index 0000000000000..705203f3ec3e6 Binary files /dev/null and b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp differ diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst new file mode 100644 index 0000000000000..21acb93f86929 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/doc/index.rst @@ -0,0 +1,152 @@ +.. _fpb_ra6e2: + +RA6E2 Fast Prototyping Board +############################ + +Overview +******** + +The FPB-RA6E2, a Fast Prototyping Board for RA6E2 MCU Group, based on +the 200 MHz Arm® Cortex®-M33 core with TrustZone, enables users to +seamlessly evaluate the features of the RA6E2 MCU group and develop +embedded systems applications using Flexible Software Package (FSP) +and e2 studio IDE. The users can use rich on-board features along with +their choice of popular ecosystems add-ons to bring their big ideas to life. + +The key features of the FPB-RA6E2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package +- 256 kB Code Flash, 40 kB SRAM +- Native pin access through 2 x 32-pin male headers +- MCU current measurement point for precision current consumption measurement +- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6E2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Two 5V input sources + + - USB (Debug, Full Speed) + - External power supply (using 2-pin header) + +- On-board debugger (SWD) + +- User LEDs and buttons + + - Two User LEDs (green) + - Power LED (green) indicating availability of regulated power + - Debug/power LED (yellow) indicating power and the debug connection + - One User button + - One Reset button + +- Two popular ecosystem expansions + + - Two Digilent PmodTM (SPI, UART and I3C) connectors + - Arduino (Uno R3) connectors + +- MCU boot configuration jumper + +.. figure:: fpb-ra6e2-board.webp + :align: center + :alt: RA6E2 Fast Prototyping Board + + FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ + +.. figure:: ra6e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E2 MCU group feature + + RA6E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for FPB-RA6E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``fpb_ra6e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to fpb-RA6E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E2BB +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `FPB-RA6E2 Website`_ +- `RA6E2 MCU group Website`_ + +.. _FPB-RA6E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e2-fast-prototyping-board-ra6e2-mcu-group + +.. _RA6E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _FPB-RA6E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/fpb-ra6e2-v1-users-manual + +.. _RA6E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp new file mode 100644 index 0000000000000..7eeb1bc516f89 Binary files /dev/null and b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp differ diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts new file mode 100644 index 0000000000000..bc7baa6c5ceda --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "fpb_ra6e2-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RA6E2"; + compatible = "renesas,ra6e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport2 6 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport2 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + storage_partition: partition@20000 { + label = "storage"; + reg = <0x20000 DT_SIZE_K(128)>; + }; + }; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml new file mode 100644 index 0000000000000..edd2002b2a3fa --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml @@ -0,0 +1,11 @@ +identifier: fpb_ra6e2 +name: Renesas FPB-RA6E2 +type: mcu +arch: arm +ram: 40 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig new file mode 100644 index 0000000000000..92bb425cfa8bb --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 4c03ce49d5688..c7f4493ac0ae8 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -82,7 +82,7 @@ source "drivers/clock_control/Kconfig.agilex5" source "drivers/clock_control/Kconfig.renesas_ra" -source "drivers/clock_control/Kconfig.renesas_ra8" +source "drivers/clock_control/Kconfig.renesas_ra_cgc" source "drivers/clock_control/Kconfig.max32" diff --git a/drivers/clock_control/Kconfig.renesas_ra8 b/drivers/clock_control/Kconfig.renesas_ra_cgc similarity index 100% rename from drivers/clock_control/Kconfig.renesas_ra8 rename to drivers/clock_control/Kconfig.renesas_ra_cgc diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index e68c657bfd639..ebbae6ec816ee 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -77,7 +77,7 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { }; #define INIT_PCLK(node_id) \ - IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra8_cgc_pclk), \ + IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ {.clk_src = DT_PROP_OR(node_id, clk_src, RA_CLOCK_SOURCE_DISABLE), \ .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \ diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 8a8dd719d9d09..90579a9e9c124 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -66,7 +66,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCA95XX gpio_pca95xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL64XXA gpio_pcal64xxa.c) zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c) -zephyr_library_sources_ifdef(CONFIG_GPIO_RA8 gpio_renesas_ra8.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 16252b2108edc..54d45ef95fc3f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -155,7 +155,7 @@ source "drivers/gpio/Kconfig.pcf857x" source "drivers/gpio/Kconfig.psoc6" source "drivers/gpio/Kconfig.rcar" source "drivers/gpio/Kconfig.renesas_ra" -source "drivers/gpio/Kconfig.renesas_ra8" +source "drivers/gpio/Kconfig.renesas_ra_ioport" source "drivers/gpio/Kconfig.rpi_pico" source "drivers/gpio/Kconfig.rt1718s" source "drivers/gpio/Kconfig.rv32m1" diff --git a/drivers/gpio/Kconfig.renesas_ra8 b/drivers/gpio/Kconfig.renesas_ra8 deleted file mode 100644 index 81e5fbcec5a99..0000000000000 --- a/drivers/gpio/Kconfig.renesas_ra8 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_RA8 - bool "Renesas RA8 GPIO driver" - default y - depends on DT_HAS_RENESAS_RA8_GPIO_ENABLED - help - Enable the Renesas RA8 GPIO driver. diff --git a/drivers/gpio/Kconfig.renesas_ra_ioport b/drivers/gpio/Kconfig.renesas_ra_ioport new file mode 100644 index 0000000000000..c09361cb1cad9 --- /dev/null +++ b/drivers/gpio/Kconfig.renesas_ra_ioport @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_RA_IOPORT + bool "Renesas RA GPIO IO port driver" + default y + depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED + help + Enable the Renesas RA GPIO IO port driver. diff --git a/drivers/gpio/gpio_renesas_ra8.c b/drivers/gpio/gpio_renesas_ra_ioport.c similarity index 71% rename from drivers/gpio/gpio_renesas_ra8.c rename to drivers/gpio/gpio_renesas_ra_ioport.c index cdc24c1ad4b00..49cd28ac92f41 100644 --- a/drivers/gpio/gpio_renesas_ra8.c +++ b/drivers/gpio/gpio_renesas_ra_ioport.c @@ -4,29 +4,29 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT renesas_ra8_gpio +#define DT_DRV_COMPAT renesas_ra_gpio_ioport #include #include -#include +#include #include #include #include -struct gpio_ra8_config { +struct gpio_ra_config { struct gpio_driver_config common; uint8_t port_num; R_PORT0_Type *port; gpio_pin_t vbatt_pins[]; }; -struct gpio_ra8_data { +struct gpio_ra_data { struct gpio_driver_data common; }; -static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; struct ra_pinctrl_soc_pin pincfg = {0}; @@ -93,9 +93,9 @@ static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); } -static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value) +static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; R_PORT0_Type *port = config->port; *value = port->PIDR; @@ -103,10 +103,10 @@ static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value) return 0; } -static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) +static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; R_PORT0_Type *port = config->port; port->PODR = ((port->PODR & ~mask) | (value & mask)); @@ -114,9 +114,9 @@ static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins return 0; } -static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; R_PORT0_Type *port = config->port; port->PODR = (port->PODR | pins); @@ -124,9 +124,9 @@ static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t return 0; } -static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; R_PORT0_Type *port = config->port; port->PODR = (port->PODR & ~pins); @@ -134,9 +134,9 @@ static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins return 0; } -static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) { - const struct gpio_ra8_config *config = dev->config; + const struct gpio_ra_config *config = dev->config; R_PORT0_Type *port = config->port; port->PODR = (port->PODR ^ pins); @@ -144,19 +144,19 @@ static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t return 0; } -static const struct gpio_driver_api gpio_ra8_drv_api_funcs = { - .pin_configure = gpio_ra8_pin_configure, - .port_get_raw = gpio_ra8_port_get_raw, - .port_set_masked_raw = gpio_ra8_port_set_masked_raw, - .port_set_bits_raw = gpio_ra8_port_set_bits_raw, - .port_clear_bits_raw = gpio_ra8_port_clear_bits_raw, - .port_toggle_bits = gpio_ra8_port_toggle_bits, +static const struct gpio_driver_api gpio_ra_drv_api_funcs = { + .pin_configure = gpio_ra_pin_configure, + .port_get_raw = gpio_ra_port_get_raw, + .port_set_masked_raw = gpio_ra_port_set_masked_raw, + .port_set_bits_raw = gpio_ra_port_set_bits_raw, + .port_clear_bits_raw = gpio_ra_port_clear_bits_raw, + .port_toggle_bits = gpio_ra_port_toggle_bits, .pin_interrupt_configure = NULL, .manage_callback = NULL, }; -#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \ - static const struct gpio_ra8_config gpio_ra8_config_##suffix = { \ +#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \ + static const struct gpio_ra_config gpio_ra_config_##suffix = { \ .common = \ { \ .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \ @@ -165,60 +165,59 @@ static const struct gpio_driver_api gpio_ra8_drv_api_funcs = { .port = (R_PORT0_Type *)addr, \ .vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \ }; \ - static struct gpio_ra8_data gpio_ra8_data_##suffix; \ - DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra8_data_##suffix, \ - &gpio_ra8_config_##suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ - &gpio_ra8_drv_api_funcs) + static struct gpio_ra_data gpio_ra_data_##suffix; \ + DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra_data_##suffix, &gpio_ra_config_##suffix, \ + PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_drv_api_funcs) -#define GPIO_DEVICE_INIT_RA8(suffix) \ +#define GPIO_DEVICE_INIT_RA(suffix) \ GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \ DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \ DT_REG_ADDR(DT_NODELABEL(ioport##suffix))) #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) -GPIO_DEVICE_INIT_RA8(0); +GPIO_DEVICE_INIT_RA(0); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) -GPIO_DEVICE_INIT_RA8(1); +GPIO_DEVICE_INIT_RA(1); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) -GPIO_DEVICE_INIT_RA8(2); +GPIO_DEVICE_INIT_RA(2); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) -GPIO_DEVICE_INIT_RA8(3); +GPIO_DEVICE_INIT_RA(3); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) -GPIO_DEVICE_INIT_RA8(4); +GPIO_DEVICE_INIT_RA(4); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) -GPIO_DEVICE_INIT_RA8(5); +GPIO_DEVICE_INIT_RA(5); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) -GPIO_DEVICE_INIT_RA8(6); +GPIO_DEVICE_INIT_RA(6); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) -GPIO_DEVICE_INIT_RA8(7); +GPIO_DEVICE_INIT_RA(7); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) -GPIO_DEVICE_INIT_RA8(8); +GPIO_DEVICE_INIT_RA(8); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) -GPIO_DEVICE_INIT_RA8(9); +GPIO_DEVICE_INIT_RA(9); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) -GPIO_DEVICE_INIT_RA8(a); +GPIO_DEVICE_INIT_RA(a); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) -GPIO_DEVICE_INIT_RA8(b); +GPIO_DEVICE_INIT_RA(b); #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) */ diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt index 38347a8ed3eb3..f53523415baf9 100644 --- a/drivers/pinctrl/renesas/CMakeLists.txt +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA8 ra/pinctrl_renesas_ra8.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) diff --git a/drivers/pinctrl/renesas/ra/Kconfig b/drivers/pinctrl/renesas/ra/Kconfig index 2ffaa63d16a3c..3ca03057982a8 100644 --- a/drivers/pinctrl/renesas/ra/Kconfig +++ b/drivers/pinctrl/renesas/ra/Kconfig @@ -9,9 +9,9 @@ config PINCTRL_RENESAS_RA help Enable Renesas RA series pin controller driver. -config PINCTRL_RENESAS_RA8 - bool "Renesas RA8 pinctrl driver" +config PINCTRL_RENESAS_RA_PFS + bool "Renesas RA pinctrl driver" default y - depends on DT_HAS_RENESAS_RA8_PINCTRL_ENABLED + depends on DT_HAS_RENESAS_RA_PINCTRL_PFS_ENABLED help - Enable the Renesas RA8 pinctrl driver. + Enable the Renesas RA series pinctrl driver with PFS secure register. diff --git a/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c similarity index 100% rename from drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c rename to drivers/pinctrl/renesas/ra/pinctrl_ra.c diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 03b986aba9b90..bbb7da14a9936 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -77,6 +77,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB1200 uart_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) +zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c) if(CONFIG_UART_NATIVE_POSIX) zephyr_library_compile_definitions(NO_POSIX_CHEATS) diff --git a/drivers/serial/Kconfig.renesas_ra b/drivers/serial/Kconfig.renesas_ra index 14311f27fe4aa..37c6a127e5e94 100644 --- a/drivers/serial/Kconfig.renesas_ra +++ b/drivers/serial/Kconfig.renesas_ra @@ -1,4 +1,5 @@ # Copyright (c) 2023 TOKITA Hiroshi +# Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config UART_RENESAS_RA @@ -9,3 +10,25 @@ config UART_RENESAS_RA select SERIAL_SUPPORT_INTERRUPT help Enable Renesas RA series UART driver. + +config UART_SCI_RA + bool "Renesas RA SCI UART" + default y + depends on DT_HAS_RENESAS_RA_SCI_UART_ENABLED + select SERIAL_HAS_DRIVER + select SERIAL_SUPPORT_INTERRUPT + select SERIAL_SUPPORT_ASYNC + select USE_RA_FSP_SCI_UART + select USE_RA_FSP_DTC if UART_ASYNC_API + help + Enable Renesas RA SCI UART Driver. + +if UART_SCI_RA + +config UART_RA_SCI_UART_FIFO_ENABLE + bool "RA SCI UART FIFO usage enable" + default y + help + Enable RA SCI FIFO + +endif diff --git a/drivers/serial/uart_renesas_ra8_sci_b.c b/drivers/serial/uart_renesas_ra8_sci_b.c index 0f7ec056d696f..3db0c32314a0b 100644 --- a/drivers/serial/uart_renesas_ra8_sci_b.c +++ b/drivers/serial/uart_renesas_ra8_sci_b.c @@ -1038,14 +1038,10 @@ static void uart_ra_sci_b_eri_isr(const struct device *dev) #define UART_RA_SCI_B_DTC_INIT(index) \ do { \ - if (DT_INST_PROP_OR(index, rx_dtc, false)) { \ - uart_ra_sci_b_data_##index.fsp_config.p_transfer_rx = \ - &uart_ra_sci_b_data_##index.rx_transfer; \ - } \ - if (DT_INST_PROP_OR(index, tx_dtc, false)) { \ - uart_ra_sci_b_data_##index.fsp_config.p_transfer_tx = \ - &uart_ra_sci_b_data_##index.tx_transfer; \ - } \ + uart_ra_sci_b_data_##index.fsp_config.p_transfer_rx = \ + &uart_ra_sci_b_data_##index.rx_transfer; \ + uart_ra_sci_b_data_##index.fsp_config.p_transfer_tx = \ + &uart_ra_sci_b_data_##index.tx_transfer; \ } while (0) #define UART_RA_SCI_B_ASYNC_INIT(index) \ diff --git a/drivers/serial/uart_renesas_ra_sci.c b/drivers/serial/uart_renesas_ra_sci.c new file mode 100644 index 0000000000000..f1327c59fbd9e --- /dev/null +++ b/drivers/serial/uart_renesas_ra_sci.c @@ -0,0 +1,1212 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_ra_sci_uart + +#include +#include +#include +#include +#include +#include "r_sci_uart.h" +#include "r_dtc.h" + +#include +LOG_MODULE_REGISTER(ra_sci_uart); + +#define SCI_UART_SSR_FIFO_DR_RDF (R_SCI0_SSR_FIFO_DR_Msk | R_SCI0_SSR_FIFO_RDF_Msk) +#define SCI_UART_SSR_FIFO_TDFE_TEND (R_SCI0_SSR_FIFO_TDFE_Msk | R_SCI0_SSR_FIFO_TEND_Msk) +#define SCI_UART_SSR_TDRE_TEND (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk) +#define SCI_UART_SSR_ERR_MSK (R_SCI0_SSR_ORER_Msk | R_SCI0_SSR_FER_Msk | R_SCI0_SSR_PER_Msk) +#define SCI_UART_SSR_FIFO_ERR_MSK \ + (R_SCI0_SSR_FIFO_ORER_Msk | R_SCI0_SSR_FIFO_FER_Msk | R_SCI0_SSR_FIFO_PER_Msk) + +#if defined(CONFIG_UART_ASYNC_API) +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +#endif + +struct uart_ra_sci_config { + const struct pinctrl_dev_config *pcfg; + + R_SCI0_Type * const regs; +}; + +struct uart_ra_sci_data { + const struct device *dev; + struct st_sci_uart_instance_ctrl sci; + struct uart_config uart_config; + struct st_uart_cfg fsp_config; + struct st_sci_uart_extended_cfg fsp_config_extend; + struct st_baud_setting_t fsp_baud_setting; +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + uart_irq_callback_user_data_t user_cb; + void *user_cb_data; + uint32_t ssr; +#endif +#if defined(CONFIG_UART_ASYNC_API) + uart_callback_t async_user_cb; + void *async_user_cb_data; + + struct k_work_delayable rx_timeout_work; + size_t rx_timeout; + size_t rx_buf_len; + size_t rx_buf_offset; + size_t rx_buf_cap; + uint8_t *rx_buffer; + size_t rx_next_buf_cap; + uint8_t *rx_next_buf; + + struct st_transfer_instance rx_transfer; + struct st_dtc_instance_ctrl rx_transfer_ctrl; + struct st_transfer_info rx_transfer_info; + struct st_transfer_cfg rx_transfer_cfg; + struct st_dtc_extended_cfg rx_transfer_cfg_extend; + + struct k_work_delayable tx_timeout; + size_t tx_buf_cap; + + struct st_transfer_instance tx_transfer; + struct st_dtc_instance_ctrl tx_transfer_ctrl; + struct st_transfer_info tx_transfer_info; + struct st_transfer_cfg tx_transfer_cfg; + struct st_dtc_extended_cfg tx_transfer_cfg_extend; +#endif +}; + +static int uart_ra_sci_poll_in(const struct device *dev, unsigned char *c) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + + if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->SCR_b.RIE) { + /* This function cannot be used if async reception was enabled */ + return -EBUSY; + } + + if (IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0 + ? cfg->regs->FDR_b.R == 0U + : cfg->regs->SSR_b.RDRF == 0U) { + /* There are no characters available to read. */ + return -1; + } + + /* got a character */ + *c = IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0 + ? cfg->regs->FRDRL + : cfg->regs->RDR; + + return 0; +} + +static void uart_ra_sci_poll_out(const struct device *dev, unsigned char c) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth > 0) { + while (cfg->regs->FDR_b.T > 0x8) { + } + cfg->regs->FTDRL = c; + } else +#endif + { + while (cfg->regs->SSR_b.TDRE == 0U) { + } + cfg->regs->TDR = c; + } +} + +static int uart_ra_sci_err_check(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + int errors = 0; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth > 0) { + const uint8_t status = cfg->regs->SSR_FIFO; + uint8_t ssr_fifo = 0; + + if (status & R_SCI0_SSR_FIFO_ORER_Msk) { + errors |= UART_ERROR_OVERRUN; + ssr_fifo |= R_SCI0_SSR_FIFO_ORER_Msk; + } + if (status & R_SCI0_SSR_FIFO_PER_Msk) { + errors |= UART_ERROR_PARITY; + ssr_fifo |= R_SCI0_SSR_FIFO_PER_Msk; + } + if (status & R_SCI0_SSR_FIFO_FER_Msk) { + errors |= UART_ERROR_FRAMING; + ssr_fifo |= R_SCI0_SSR_FIFO_FER_Msk; + } + cfg->regs->SSR_FIFO &= ~ssr_fifo; + } else +#endif + { + const uint8_t status = cfg->regs->SSR; + uint8_t ssr = 0; + + if (status & R_SCI0_SSR_ORER_Msk) { + errors |= UART_ERROR_OVERRUN; + ssr |= R_SCI0_SSR_ORER_Msk; + } + if (status & R_SCI0_SSR_PER_Msk) { + errors |= UART_ERROR_PARITY; + ssr |= R_SCI0_SSR_PER_Msk; + } + if (status & R_SCI0_SSR_FER_Msk) { + errors |= UART_ERROR_FRAMING; + ssr |= R_SCI0_SSR_FER_Msk; + } + cfg->regs->SSR &= ~ssr; + } + + return errors; +} + +static int uart_ra_sci_apply_config(const struct uart_config *config, + struct st_uart_cfg *fsp_config, + struct st_sci_uart_extended_cfg *fsp_config_extend, + struct st_baud_setting_t *fsp_baud_setting) +{ + fsp_err_t fsp_err; + + fsp_err = R_SCI_UART_BaudCalculate(config->baudrate, true, 5000, fsp_baud_setting); + if (fsp_err != FSP_SUCCESS) { + LOG_DBG("drivers: uart: baud calculate error"); + return -EINVAL; + } + + switch (config->parity) { + case UART_CFG_PARITY_NONE: + fsp_config->parity = UART_PARITY_OFF; + break; + case UART_CFG_PARITY_ODD: + fsp_config->parity = UART_PARITY_ODD; + break; + case UART_CFG_PARITY_EVEN: + fsp_config->parity = UART_PARITY_EVEN; + break; + case UART_CFG_PARITY_MARK: + return -ENOTSUP; + case UART_CFG_PARITY_SPACE: + return -ENOTSUP; + default: + return -EINVAL; + } + + switch (config->stop_bits) { + case UART_CFG_STOP_BITS_0_5: + return -ENOTSUP; + case UART_CFG_STOP_BITS_1: + fsp_config->stop_bits = UART_STOP_BITS_1; + break; + case UART_CFG_STOP_BITS_1_5: + return -ENOTSUP; + case UART_CFG_STOP_BITS_2: + fsp_config->stop_bits = UART_STOP_BITS_2; + break; + default: + return -EINVAL; + } + + switch (config->data_bits) { + case UART_CFG_DATA_BITS_5: + return -ENOTSUP; + case UART_CFG_DATA_BITS_6: + return -ENOTSUP; + case UART_CFG_DATA_BITS_7: + fsp_config->data_bits = UART_DATA_BITS_7; + break; + case UART_CFG_DATA_BITS_8: + fsp_config->data_bits = UART_DATA_BITS_8; + break; + case UART_CFG_DATA_BITS_9: + fsp_config->data_bits = UART_DATA_BITS_9; + break; + default: + return -EINVAL; + } + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + fsp_config_extend->rx_fifo_trigger = 0x8; +#endif + + switch (config->flow_ctrl) { + case UART_CFG_FLOW_CTRL_NONE: + fsp_config_extend->flow_control = 0; + fsp_config_extend->rs485_setting.enable = false; + break; + case UART_CFG_FLOW_CTRL_RTS_CTS: + fsp_config_extend->flow_control = SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS; + fsp_config_extend->rs485_setting.enable = false; + break; + case UART_CFG_FLOW_CTRL_DTR_DSR: + return -ENOTSUP; + case UART_CFG_FLOW_CTRL_RS485: + /* TODO: implement this config */ + return -ENOTSUP; + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + +static int uart_ra_sci_configure(const struct device *dev, const struct uart_config *config) +{ + int err; + fsp_err_t fsp_err; + struct uart_ra_sci_data *data = dev->data; + + err = uart_ra_sci_apply_config(config, &data->fsp_config, &data->fsp_config_extend, + &data->fsp_baud_setting); + if (err) { + return err; + } + + fsp_err = R_SCI_UART_Close(&data->sci); + fsp_err |= R_SCI_UART_Open(&data->sci, &data->fsp_config); + if (fsp_err != FSP_SUCCESS) { + LOG_DBG("drivers: serial: uart configure failed"); + return -EIO; + } + memcpy(&data->uart_config, config, sizeof(*config)); + + return 0; +} + +static int uart_ra_sci_config_get(const struct device *dev, struct uart_config *cfg) +{ + struct uart_ra_sci_data *data = dev->data; + + memcpy(cfg, &data->uart_config, sizeof(*cfg)); + return 0; +} + +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + +static int uart_ra_sci_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + uint8_t num_tx = 0U; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + while ((size - num_tx > 0) && cfg->regs->FDR_b.T < data->sci.fifo_depth) { + /* Send a character (8bit , parity none) */ + cfg->regs->FTDRL = tx_data[num_tx++]; + } + cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND; + } else +#endif + { + if (size > 0 && cfg->regs->SSR_b.TDRE) { + /* Send a character (8bit , parity none) */ + cfg->regs->TDR = tx_data[num_tx++]; + } + }; + + return num_tx; +} + +static int uart_ra_sci_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + uint8_t num_rx = 0U; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + while ((size - num_rx > 0) && cfg->regs->FDR_b.R > 0) { + /* Receive a character (8bit , parity none) */ + rx_data[num_rx++] = cfg->regs->FRDRL; + } + cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF; + } else +#endif + { + if (size > 0 && cfg->regs->SSR_b.RDRF) { + /* Receive a character (8bit , parity none) */ + rx_data[num_rx++] = cfg->regs->RDR; + } + cfg->regs->SSR &= (uint8_t)~R_SCI0_SSR_RDRF_Msk; + } + + return num_rx; +} + +static void uart_ra_sci_irq_tx_enable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND; + } else +#endif + { + cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_TDRE_TEND; + } + + cfg->regs->SCR |= (R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); +} + +static void uart_ra_sci_irq_tx_disable(const struct device *dev) +{ + const struct uart_ra_sci_config *cfg = dev->config; + + cfg->regs->SCR &= ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); +} + +static int uart_ra_sci_irq_tx_ready(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + int ret; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_FIFO_TDFE_Msk); + } else +#endif + { + ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_TDRE_Msk); + } + + return ret; +} + +static int uart_ra_sci_irq_tx_complete(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + + return (cfg->regs->SCR_b.TEIE == 1U) && (data->ssr & BIT(R_SCI0_SSR_TEND_Pos)); +} + +static void uart_ra_sci_irq_rx_enable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_DR_RDF); + } else +#endif + { + cfg->regs->SSR_b.RDRF = 0U; + } + cfg->regs->SCR_b.RIE = 1U; +} + +static void uart_ra_sci_irq_rx_disable(const struct device *dev) +{ + const struct uart_ra_sci_config *cfg = dev->config; + + cfg->regs->SCR_b.RIE = 0U; +} + +static int uart_ra_sci_irq_rx_ready(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + int ret; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & SCI_UART_SSR_FIFO_DR_RDF); + } else +#endif + { + ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & R_SCI0_SSR_RDRF_Msk); + } + + return ret; +} + +static void uart_ra_sci_irq_err_enable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + + NVIC_EnableIRQ(data->fsp_config.eri_irq); +} + +static void uart_ra_sci_irq_err_disable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + + NVIC_DisableIRQ(data->fsp_config.eri_irq); +} + +static int uart_ra_sci_irq_is_pending(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + uint8_t scr; + uint8_t ssr; + int ret; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + scr = cfg->regs->SCR; + ssr = cfg->regs->SSR_FIFO; + ret = ((scr & R_SCI0_SCR_TIE_Msk) && + (ssr & (R_SCI0_SSR_FIFO_TEND_Msk | R_SCI0_SSR_FIFO_TDFE_Msk))) || + ((scr & R_SCI0_SCR_RIE_Msk) && + ((ssr & (R_SCI0_SSR_FIFO_RDF_Msk | R_SCI0_SSR_FIFO_DR_Msk | + R_SCI0_SSR_FIFO_FER_Msk | R_SCI0_SSR_FIFO_ORER_Msk | + R_SCI0_SSR_FIFO_PER_Msk)))); + } else +#endif + { + scr = cfg->regs->SCR; + ssr = cfg->regs->SSR; + ret = ((scr & R_SCI0_SCR_TIE_Msk) && + (ssr & (R_SCI0_SSR_TEND_Msk | R_SCI0_SSR_TDRE_Msk))) || + ((scr & R_SCI0_SCR_RIE_Msk) && + (ssr & (R_SCI0_SSR_RDRF_Msk | R_SCI0_SSR_PER_Msk | R_SCI0_SSR_FER_Msk | + R_SCI0_SSR_ORER_Msk))); + } + + return ret; +} + +static int uart_ra_sci_irq_update(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + data->ssr = cfg->regs->SSR_FIFO; + uint8_t ssr = data->ssr ^ (R_SCI0_SSR_FIFO_ORER_Msk | R_SCI0_SSR_FIFO_FER_Msk | + R_SCI0_SSR_FIFO_PER_Msk); + cfg->regs->SSR_FIFO &= ssr; + } else +#endif + { + data->ssr = cfg->regs->SSR; + uint8_t ssr = + data->ssr ^ (R_SCI0_SSR_ORER_Msk | R_SCI0_SSR_FER_Msk | R_SCI0_SSR_PER_Msk); + cfg->regs->SSR_FIFO &= ssr; + } + + return 1; +} + +static void uart_ra_sci_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, + void *cb_data) +{ + struct uart_ra_sci_data *data = dev->data; + + data->user_cb = cb; + data->user_cb_data = cb_data; + +#if CONFIG_UART_EXCLUSIVE_API_CALLBACKS + data->async_user_cb = NULL; + data->async_user_cb_data = NULL; +#endif +} + +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +#ifdef CONFIG_UART_ASYNC_API + +static int fsp_err_to_errno(fsp_err_t fsp_err) +{ + switch (fsp_err) { + case FSP_ERR_INVALID_ARGUMENT: + return -EINVAL; + case FSP_ERR_NOT_OPEN: + return -EIO; + case FSP_ERR_IN_USE: + return -EBUSY; + case FSP_ERR_UNSUPPORTED: + return -ENOTSUP; + case 0: + return 0; + default: + return -EINVAL; + } +} + +static int uart_ra_sci_async_callback_set(const struct device *dev, uart_callback_t cb, + void *cb_data) +{ + struct uart_ra_sci_data *data = dev->data; + + data->async_user_cb = cb; + data->async_user_cb_data = cb_data; + +#if CONFIG_UART_EXCLUSIVE_API_CALLBACKS + data->user_cb = NULL; + data->user_cb_data = NULL; +#endif + return 0; +} + +static int uart_ra_sci_async_tx(const struct device *dev, const uint8_t *buf, size_t len, + int32_t timeout) +{ + struct uart_ra_sci_data *data = dev->data; + int err; + + err = fsp_err_to_errno(R_SCI_UART_Write(&data->sci, buf, len)); + if (err) { + return err; + } + data->tx_buf_cap = len; + if (timeout != SYS_FOREVER_US && timeout != 0) { + k_work_reschedule(&data->tx_timeout, Z_TIMEOUT_US(timeout)); + } + + return 0; +} + +static inline void async_user_callback(const struct device *dev, struct uart_event *event) +{ + struct uart_ra_sci_data *data = dev->data; + + if (data->async_user_cb) { + data->async_user_cb(dev, event, data->async_user_cb_data); + } +} + +static inline void async_rx_release_buf(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + + struct uart_event event = { + .type = UART_RX_BUF_RELEASED, + .data.rx.buf = (uint8_t *)data->rx_buffer, + }; + async_user_callback(dev, &event); + data->rx_buffer = NULL; + data->rx_buf_offset = 0; + data->rx_buf_len = 0; + data->rx_buf_cap = 0; +} + +static inline void async_rx_release_next_buf(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + struct uart_event event = { + .type = UART_RX_BUF_RELEASED, + .data.rx.buf = (uint8_t *)data->rx_next_buf, + }; + async_user_callback(dev, &event); + data->rx_next_buf = NULL; +} + +static inline void async_rx_req_buf(const struct device *dev) +{ + struct uart_event event = { + .type = UART_RX_BUF_REQUEST, + }; + + async_user_callback(dev, &event); +} + +static inline void async_rx_disable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + struct uart_event event = { + .type = UART_RX_DISABLED, + }; + async_user_callback(dev, &event); + + /* Disable the RXI request and clear the status flag to be ready for the next reception */ + cfg->regs->SCR_b.RIE = 0; +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth != 0) { + cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF; + } else +#endif + { + cfg->regs->SSR_b.RDRF = 0; + } +} + +static inline void async_rx_ready(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + + if (!data->rx_buf_len) { + return; + } + + struct uart_event event = { + .type = UART_RX_RDY, + .data.rx.buf = (uint8_t *)data->rx_buffer, + .data.rx.offset = data->rx_buf_offset, + .data.rx.len = data->rx_buf_len, + }; + async_user_callback(data->dev, &event); + data->rx_buf_offset += data->rx_buf_len; + data->rx_buf_len = 0; +} + +static inline void disable_tx(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + + /* Transmit interrupts must be disabled to start with. */ + cfg->regs->SCR &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); + + /* + * Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND + * is 0 causes SCI peripheral to work abnormally. + */ + while (IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth + ? cfg->regs->SSR_FIFO_b.TEND != 1U + : cfg->regs->SSR_b.TEND != 1U) { + } + + cfg->regs->SCR_b.TE = 0; +} + +static inline void enable_tx(const struct device *dev) +{ + const struct uart_ra_sci_config *cfg = dev->config; + + cfg->regs->SCR_b.TE = 1; +} + +static int uart_ra_sci_async_tx_abort(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + int err = 0; + + if (!data->sci.p_tx_src) { + return -EFAULT; + } + + disable_tx(dev); + + if (FSP_SUCCESS != R_SCI_UART_Abort(&data->sci, UART_DIR_TX)) { + LOG_DBG("drivers: serial: uart abort tx failed"); + err = -EIO; + goto unlock; + } + transfer_properties_t tx_properties = {0}; + + if (FSP_SUCCESS != R_DTC_InfoGet(data->tx_transfer.p_ctrl, &tx_properties)) { + LOG_DBG("drivers: serial: uart abort tx failed"); + err = -EIO; + goto unlock; + } + struct uart_event event = { + .type = UART_TX_ABORTED, + .data.tx.buf = (uint8_t *)data->sci.p_tx_src, + .data.tx.len = data->tx_buf_cap - tx_properties.transfer_length_remaining, + }; + async_user_callback(dev, &event); + k_work_cancel_delayable(&data->tx_timeout); + +unlock: + enable_tx(dev); + return err; +} + +static int uart_ra_sci_async_rx_enable(const struct device *dev, uint8_t *buf, size_t len, + int32_t timeout) +{ + struct uart_ra_sci_data *data = dev->data; + const struct uart_ra_sci_config *cfg = dev->config; + int err = 0; + unsigned int key = irq_lock(); + + if (data->rx_buffer) { + err = -EAGAIN; + goto unlock; + } + +#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE + if (data->sci.fifo_depth) { + cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_ERR_MSK); + } else +#endif + { + cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_ERR_MSK; + } + + err = fsp_err_to_errno(R_SCI_UART_Read(&data->sci, buf, len)); + if (err) { + goto unlock; + } + + data->rx_timeout = timeout; + data->rx_buffer = buf; + data->rx_buf_cap = len; + data->rx_buf_len = 0; + data->rx_buf_offset = 0; + + /* Call buffer request user callback */ + async_rx_req_buf(dev); + cfg->regs->SCR_b.RIE = 1; + +unlock: + irq_unlock(key); + return err; +} + +static int uart_ra_sci_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len) +{ + struct uart_ra_sci_data *data = dev->data; + + data->rx_next_buf = buf; + data->rx_next_buf_cap = len; + + return 0; +} + +static int uart_ra_sci_async_rx_disable(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + uint32_t remaining_byte = 0; + int err = 0; + unsigned int key = irq_lock(); + + if (!data->rx_buffer) { + err = -EAGAIN; + goto unlock; + } + + k_work_cancel_delayable(&data->rx_timeout_work); + if (FSP_SUCCESS != R_SCI_UART_ReadStop(&data->sci, &remaining_byte)) { + LOG_DBG("drivers: serial: uart stop reading failed"); + err = -EIO; + goto unlock; + } + + async_rx_ready(dev); + async_rx_release_buf(dev); + async_rx_release_next_buf(dev); + async_rx_disable(dev); + +unlock: + irq_unlock(key); + return err; +} + +static inline void async_evt_rx_err(const struct device *dev, enum uart_rx_stop_reason reason) +{ + struct uart_ra_sci_data *data = dev->data; + + k_work_cancel_delayable(&data->rx_timeout_work); + struct uart_event event = { + .type = UART_RX_STOPPED, + .data.rx_stop.reason = reason, + .data.rx_stop.data.buf = (uint8_t *)data->sci.p_rx_dest, + .data.rx_stop.data.offset = 0, + .data.rx_stop.data.len = + data->rx_buf_cap - data->rx_buf_offset - data->sci.rx_dest_bytes, + }; + async_user_callback(dev, &event); +} + +static inline void async_evt_rx_complete(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + unsigned int key = irq_lock(); + + async_rx_ready(dev); + async_rx_release_buf(dev); + if (data->rx_next_buf) { + data->rx_buffer = data->rx_next_buf; + data->rx_buf_offset = 0; + data->rx_buf_cap = data->rx_next_buf_cap; + data->rx_next_buf = NULL; + R_SCI_UART_Read(&data->sci, data->rx_buffer, data->rx_buf_cap); + async_rx_req_buf(dev); + } else { + async_rx_disable(dev); + } + irq_unlock(key); +} + +static inline void async_evt_tx_done(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; + + k_work_cancel_delayable(&data->tx_timeout); + struct uart_event event = { + .type = UART_TX_DONE, + .data.tx.buf = (uint8_t *)data->sci.p_tx_src, + .data.tx.len = data->tx_buf_cap, + }; + async_user_callback(dev, &event); +} + +static void uart_ra_sci_callback_adapter(struct st_uart_callback_arg *fsp_args) +{ + const struct device *dev = fsp_args->p_context; + + switch (fsp_args->event) { + case UART_EVENT_TX_COMPLETE: + return async_evt_tx_done(dev); + case UART_EVENT_RX_COMPLETE: + async_evt_rx_complete(dev); + case UART_EVENT_ERR_PARITY: + return async_evt_rx_err(dev, UART_ERROR_PARITY); + case UART_EVENT_ERR_FRAMING: + return async_evt_rx_err(dev, UART_ERROR_FRAMING); + case UART_EVENT_ERR_OVERFLOW: + return async_evt_rx_err(dev, UART_ERROR_OVERRUN); + case UART_EVENT_BREAK_DETECT: + return async_evt_rx_err(dev, UART_BREAK); + case UART_EVENT_TX_DATA_EMPTY: + case UART_EVENT_RX_CHAR: + break; + } +} + +static void uart_ra_sci_rx_timeout_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct uart_ra_sci_data *data = + CONTAINER_OF(dwork, struct uart_ra_sci_data, rx_timeout_work); + unsigned int key = irq_lock(); + + async_rx_ready(data->dev); + irq_unlock(key); +} + +static void uart_ra_sci_tx_timeout_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct uart_ra_sci_data *data = CONTAINER_OF(dwork, struct uart_ra_sci_data, tx_timeout); + + uart_ra_sci_async_tx_abort(data->dev); +} + +#endif /* CONFIG_UART_ASYNC_API */ + +static const struct uart_driver_api uart_ra_sci_driver_api = { + .poll_in = uart_ra_sci_poll_in, + .poll_out = uart_ra_sci_poll_out, + .err_check = uart_ra_sci_err_check, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = uart_ra_sci_configure, + .config_get = uart_ra_sci_config_get, +#endif +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + .fifo_fill = uart_ra_sci_fifo_fill, + .fifo_read = uart_ra_sci_fifo_read, + .irq_tx_enable = uart_ra_sci_irq_tx_enable, + .irq_tx_disable = uart_ra_sci_irq_tx_disable, + .irq_tx_ready = uart_ra_sci_irq_tx_ready, + .irq_rx_enable = uart_ra_sci_irq_rx_enable, + .irq_rx_disable = uart_ra_sci_irq_rx_disable, + .irq_tx_complete = uart_ra_sci_irq_tx_complete, + .irq_rx_ready = uart_ra_sci_irq_rx_ready, + .irq_err_enable = uart_ra_sci_irq_err_enable, + .irq_err_disable = uart_ra_sci_irq_err_disable, + .irq_is_pending = uart_ra_sci_irq_is_pending, + .irq_update = uart_ra_sci_irq_update, + .irq_callback_set = uart_ra_sci_irq_callback_set, +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +#if CONFIG_UART_ASYNC_API + .callback_set = uart_ra_sci_async_callback_set, + .tx = uart_ra_sci_async_tx, + .tx_abort = uart_ra_sci_async_tx_abort, + .rx_enable = uart_ra_sci_async_rx_enable, + .rx_buf_rsp = uart_ra_sci_async_rx_buf_rsp, + .rx_disable = uart_ra_sci_async_rx_disable, +#endif /* CONFIG_UART_ASYNC_API */ +}; + +static int uart_ra_sci_init(const struct device *dev) +{ + const struct uart_ra_sci_config *config = dev->config; + struct uart_ra_sci_data *data = dev->data; + int ret; + fsp_err_t fsp_err; + + /* Configure dt provided device signals when available */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + /* Setup fsp sci_uart setting */ + ret = uart_ra_sci_apply_config(&data->uart_config, &data->fsp_config, + &data->fsp_config_extend, &data->fsp_baud_setting); + if (ret != 0) { + return ret; + } + + data->fsp_config_extend.p_baud_setting = &data->fsp_baud_setting; +#if defined(CONFIG_UART_ASYNC_API) + data->fsp_config.p_callback = uart_ra_sci_callback_adapter; + data->fsp_config.p_context = dev; + k_work_init_delayable(&data->tx_timeout, uart_ra_sci_tx_timeout_handler); + k_work_init_delayable(&data->rx_timeout_work, uart_ra_sci_rx_timeout_handler); +#endif /* defined(CONFIG_UART_ASYNC_API) */ + data->fsp_config.p_extend = &data->fsp_config_extend; + + fsp_err = R_SCI_UART_Open(&data->sci, &data->fsp_config); + if (fsp_err != FSP_SUCCESS) { + LOG_DBG("drivers: uart: initialize failed"); + return -EIO; + } + irq_disable(data->fsp_config.eri_irq); + return 0; +} + +#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API +static void uart_ra_sci_rxi_isr(const struct device *dev) +{ + struct uart_ra_sci_data *data = dev->data; +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + if (data->user_cb != NULL) { + data->user_cb(dev, data->user_cb_data); + goto out; + } +#endif + +#if defined(CONFIG_UART_ASYNC_API) + if (data->rx_timeout != SYS_FOREVER_US && data->rx_timeout != 0) { + k_work_reschedule(&data->rx_timeout_work, Z_TIMEOUT_US(data->rx_timeout)); + } + data->rx_buf_len++; + if (data->rx_buf_len + data->rx_buf_offset == data->rx_buf_cap) { + sci_uart_rxi_isr(); + } else { + goto out; + } +#endif +out: + R_ICU->IELSR_b[data->fsp_config.rxi_irq].IR = 0U; +} + +static void uart_ra_sci_txi_isr(const struct device *dev) +{ +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + struct uart_ra_sci_data *data = dev->data; + + if (data->user_cb != NULL) { + data->user_cb(dev, data->user_cb_data); + R_ICU->IELSR_b[data->fsp_config.txi_irq].IR = 0U; + return; + } +#endif + +#if defined(CONFIG_UART_ASYNC_API) + sci_uart_txi_isr(); +#endif +} + +static void uart_ra_sci_tei_isr(const struct device *dev) +{ +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + struct uart_ra_sci_data *data = dev->data; + + if (data->user_cb != NULL) { + data->user_cb(dev, data->user_cb_data); + R_ICU->IELSR_b[data->fsp_config.tei_irq].IR = 0U; + return; + } +#endif + +#if defined(CONFIG_UART_ASYNC_API) + sci_uart_tei_isr(); +#endif +} + +static void uart_ra_sci_eri_isr(const struct device *dev) +{ +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + struct uart_ra_sci_data *data = dev->data; + + if (data->user_cb != NULL) { + data->user_cb(dev, data->user_cb_data); + R_ICU->IELSR_b[data->fsp_config.eri_irq].IR = 0U; + return; + } +#endif + +#if defined(CONFIG_UART_ASYNC_API) + sci_uart_eri_isr(); +#endif +} +#endif + +#define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI +#define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI +#define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI +#define _ELC_EVENT_SCI_ERI(channel) ELC_EVENT_SCI##channel##_ERI + +#define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel) +#define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel) +#define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel) +#define ELC_EVENT_SCI_ERI(channel) _ELC_EVENT_SCI_ERI(channel) + +#if CONFIG_UART_ASYNC_API +#define UART_RA_SCI_ASYNC_INIT(index) \ + .rx_transfer_info = \ + { \ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, \ + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, \ + .transfer_settings_word_b.irq = TRANSFER_IRQ_EACH, \ + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, \ + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED, \ + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, \ + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, \ + .p_dest = (void *)NULL, \ + .p_src = (void const *)NULL, \ + .num_blocks = 0, \ + .length = 0, \ + }, \ + .rx_transfer_cfg_extend = {.activation_source = \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)}, \ + .rx_transfer_cfg = \ + { \ + .p_info = &uart_ra_sci_data_##index.rx_transfer_info, \ + .p_extend = &uart_ra_sci_data_##index.rx_transfer_cfg_extend, \ + }, \ + .rx_transfer = \ + { \ + .p_ctrl = &uart_ra_sci_data_##index.rx_transfer_ctrl, \ + .p_cfg = &uart_ra_sci_data_##index.rx_transfer_cfg, \ + .p_api = &g_transfer_on_dtc, \ + }, \ + .tx_transfer_info = \ + { \ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, \ + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, \ + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, \ + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, \ + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, \ + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, \ + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, \ + .p_dest = (void *)NULL, \ + .p_src = (void const *)NULL, \ + .num_blocks = 0, \ + .length = 0, \ + }, \ + .tx_transfer_cfg_extend = {.activation_source = \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)}, \ + .tx_transfer_cfg = \ + { \ + .p_info = &uart_ra_sci_data_##index.tx_transfer_info, \ + .p_extend = &uart_ra_sci_data_##index.tx_transfer_cfg_extend, \ + }, \ + .tx_transfer = { \ + .p_ctrl = &uart_ra_sci_data_##index.tx_transfer_ctrl, \ + .p_cfg = &uart_ra_sci_data_##index.tx_transfer_cfg, \ + .p_api = &g_transfer_on_dtc, \ + }, + +#define UART_RA_SCI_DTC_INIT(index) \ + { \ + uart_ra_sci_data_##index.fsp_config.p_transfer_rx = \ + &uart_ra_sci_data_##index.rx_transfer; \ + uart_ra_sci_data_##index.fsp_config.p_transfer_tx = \ + &uart_ra_sci_data_##index.tx_transfer; \ + } + +#else +#define UART_RA_SCI_ASYNC_INIT(index) +#define UART_RA_SCI_DTC_INIT(index) +#endif + +#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API +#define UART_RA_SCI_IRQ_INIT(index) \ + { \ + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] = \ + ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel)); \ + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] = \ + ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel)); \ + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] = \ + ELC_EVENT_SCI_TEI(DT_INST_PROP(index, channel)); \ + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] = \ + ELC_EVENT_SCI_ERI(DT_INST_PROP(index, channel)); \ + \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \ + uart_ra_sci_rxi_isr, DEVICE_DT_INST_GET(index), 0); \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \ + uart_ra_sci_txi_isr, DEVICE_DT_INST_GET(index), 0); \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \ + uart_ra_sci_tei_isr, DEVICE_DT_INST_GET(index), 0); \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, priority), \ + uart_ra_sci_eri_isr, DEVICE_DT_INST_GET(index), 0); \ + \ + irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)); \ + irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)); \ + irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)); \ + } +#else +#define UART_RA_SCI_IRQ_INIT(index) +#endif + +#define UART_RA_SCI_INIT(index) \ + PINCTRL_DT_DEFINE(DT_INST_PARENT(index)); \ + static const struct uart_ra_sci_config uart_ra_sci_config_##index = { \ + .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(index)), \ + .regs = (R_SCI0_Type *)DT_REG_ADDR(DT_INST_PARENT(index)), \ + }; \ + \ + static struct uart_ra_sci_data uart_ra_sci_data_##index = { \ + .uart_config = \ + { \ + .baudrate = DT_INST_PROP(index, current_speed), \ + .parity = UART_CFG_PARITY_NONE, \ + .stop_bits = UART_CFG_STOP_BITS_1, \ + .data_bits = UART_CFG_DATA_BITS_8, \ + .flow_ctrl = COND_CODE_1(DT_NODE_HAS_PROP(idx, hw_flow_control), \ + (UART_CFG_FLOW_CTRL_RTS_CTS), \ + (UART_CFG_FLOW_CTRL_NONE)), \ + }, \ + .fsp_config = \ + { \ + .channel = DT_INST_PROP(index, channel), \ + .rxi_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \ + .rxi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \ + .txi_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \ + .txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \ + .tei_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \ + .tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \ + .eri_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, priority), \ + .eri_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \ + }, \ + .fsp_config_extend = {}, \ + .fsp_baud_setting = {}, \ + .dev = DEVICE_DT_INST_GET(index), \ + UART_RA_SCI_ASYNC_INIT(index)}; \ + \ + static int uart_ra_sci_init##index(const struct device *dev) \ + { \ + UART_RA_SCI_IRQ_INIT(index); \ + UART_RA_SCI_DTC_INIT(index); \ + int err = uart_ra_sci_init(dev); \ + if (err != 0) { \ + return err; \ + } \ + return 0; \ + } \ + DEVICE_DT_INST_DEFINE(index, uart_ra_sci_init##index, NULL, &uart_ra_sci_data_##index, \ + &uart_ra_sci_config_##index, PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_sci_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(UART_RA_SCI_INIT) diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi new file mode 100644 index 0000000000000..f8a45b5b0e251 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(1)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi new file mode 100644 index 0000000000000..f4469132ad9e3 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(256)>; + }; + + ioport6: gpio@400800c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400800e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40118200 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118200 0x100>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL2 */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi new file mode 100644 index 0000000000000..8ccb1e3bb3a04 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi new file mode 100644 index 0000000000000..7110aebab9193 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(40)>; + }; + + ioport8: gpio@40080100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + id_code: id_code@100a120 { + compatible = "zephyr,memory-region"; + reg = <0x0100a120 0x10>; + zephyr,memory-region = "ID_CODE"; + status = "okay"; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <10 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + cecclk: cecclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + i3cclk: i3cclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi new file mode 100644 index 0000000000000..f281d5199fb15 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(256)>; + }; + + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(512)>; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <0>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi new file mode 100644 index 0000000000000..4a3320b2bbb9a --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + compatible = "renesas,ra6-flash-controller"; + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <4 1>, <5 1>; + interrupt-names = "frdyi", "fiferr"; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(1)>; + write-block-size = <128>; + erase-block-size = <8192>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi new file mode 100644 index 0000000000000..82a6333c293c8 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(384)>; + }; + + sci5: sci5@400700a0 { + compatible = "renesas,ra-sci"; + interrupts = <20 1>, <21 1>, <22 1>, <23 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700a0 0x20>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci6: sci6@400700c0 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700c0 0x20>; + clocks = <&pclka MSTPB 25>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <6>; + status = "disabled"; + }; + }; + + sci7: sci7@400700e0 { + compatible = "renesas,ra-sci"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700e0 0x20>; + clocks = <&pclka MSTPB 24>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <7>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <1>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi new file mode 100644 index 0000000000000..f6ed09902d460 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(2)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi new file mode 100644 index 0000000000000..b23a8fc2476fd --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(640)>; + }; + + ioport8: gpio@40040100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport9: gpio@40040120 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040120 0x20>; + port = <9>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioporta: gpio@40040140 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040140 0x20>; + port = <10>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioportb: gpio@40040160 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040160 0x20>; + port = <11>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci5: sci5@400700a0 { + compatible = "renesas,ra-sci"; + interrupts = <20 1>, <21 1>, <22 1>, <23 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700a0 0x20>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci6: sci6@400700c0 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700c0 0x20>; + clocks = <&pclka MSTPB 25>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <6>; + status = "disabled"; + }; + }; + + sci7: sci7@400700e0 { + compatible = "renesas,ra-sci"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700e0 0x20>; + clocks = <&pclka MSTPB 24>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <7>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <1>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi new file mode 100644 index 0000000000000..4ab1124d5f7b0 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(1)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi new file mode 100644 index 0000000000000..188f686bab918 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(256)>; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40118200 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118200 0x100>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + + sci5: sci5@40118500 { + compatible = "renesas,ra-sci"; + interrupts = <20 1>, <21 1>, <22 1>, <23 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118500 0x100>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci6: sci6@40118600 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118600 0x100>; + clocks = <&pclka MSTPB 25>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <6>; + status = "disabled"; + }; + }; + + sci7: sci7@40118700 { + compatible = "renesas,ra-sci"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118700 0x100>; + clocks = <&pclka MSTPB 24>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <7>; + status = "disabled"; + }; + }; + + sci8: sci8@40118800 { + compatible = "renesas,ra-sci"; + interrupts = <32 1>, <33 1>, <34 1>, <35 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118800 0x100>; + clocks = <&pclka MSTPB 23>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <8>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <25 0>; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL2 */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <0>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + octaspiclk: octaspiclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi new file mode 100644 index 0000000000000..cf75071f3ad4e --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(2)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi new file mode 100644 index 0000000000000..2097c1f322ad9 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(512)>; + }; + + ioport6: gpio@400800c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400800e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport8: gpio@40080100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport9: gpio@40080120 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080120 0x20>; + port = <9>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioporta: gpio@40080140 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080140 0x20>; + port = <10>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioportb: gpio@40080160 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080160 0x20>; + port = <11>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40118200 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118200 0x100>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + + sci5: sci5@40118500 { + compatible = "renesas,ra-sci"; + interrupts = <20 1>, <21 1>, <22 1>, <23 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118500 0x100>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci6: sci6@40118600 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118600 0x100>; + clocks = <&pclka MSTPB 25>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <6>; + status = "disabled"; + }; + }; + + sci7: sci7@40118700 { + compatible = "renesas,ra-sci"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118700 0x100>; + clocks = <&pclka MSTPB 24>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <7>; + status = "disabled"; + }; + }; + + sci8: sci8@40118800 { + compatible = "renesas,ra-sci"; + interrupts = <32 1>, <33 1>, <34 1>, <35 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118800 0x100>; + clocks = <&pclka MSTPB 23>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <8>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <25 0>; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL2 */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <0>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + u60clk: u60clk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + octaspiclk: octaspiclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + cecclk: cecclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi new file mode 100644 index 0000000000000..2f9a4f0364029 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + interrupt-parent = <&nvic>; + + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + ioport0: gpio@40080000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@40080020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@40080040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@40080060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@40080080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@400800a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-contrller@40080800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x40080800 0x3c0>; + status = "okay"; + }; + + sci0: sci0@40118000 { + compatible = "renesas,ra-sci"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118000 0x100>; + clocks = <&pclka MSTPB 31>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci9: sci9@40118900 { + compatible = "renesas,ra-sci"; + interrupts = <36 1>, <37 1>, <38 1>, <39 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118900 0x100>; + clocks = <&pclka MSTPB 22>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + option_setting_ofs: option_setting_ofs@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x18>; + zephyr,memory-region = "OPTION_SETTING_OFS"; + status = "okay"; + }; + + option_setting_sas: option_setting_sas@100a134 { + compatible = "zephyr,memory-region"; + reg = <0x0100a134 0xcc>; + zephyr,memory-region = "OPTION_SETTING_SAS"; + status = "okay"; + }; + + option_setting_s: option_setting_s@100a200 { + compatible = "zephyr,memory-region"; + reg = <0x0100a200 0x100>; + zephyr,memory-region = "OPTION_SETTING_S"; + status = "okay"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi new file mode 100644 index 0000000000000..f28cbaafa6ecd --- /dev/null +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + ioport0: gpio@40040000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@40040020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@40040040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@40040060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@40040080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@400400a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport6: gpio@400400c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400400e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-contrller@40040800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x40040800 0x3c0>; + status = "okay"; + }; + + sci0: sci0@40070000 { + compatible = "renesas,ra-sci"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070000 0x20>; + clocks = <&pclka MSTPB 31>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci1: sci1@40070020 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070020 0x20>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40070040 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070040 0x20>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40070060 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070060 0x20>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40070080 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070080 0x20>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + + sci8: sci8@40070100 { + compatible = "renesas,ra-sci"; + interrupts = <32 1>, <33 1>, <34 1>, <35 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070100 0x20>; + clocks = <&pclka MSTPB 23>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <8>; + status = "disabled"; + }; + }; + + sci9: sci9@40070120 { + compatible = "renesas,ra-sci"; + interrupts = <36 1>, <37 1>, <38 1>, <39 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070120 0x20>; + clocks = <&pclka MSTPB 22>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + id_code: id_code@100a150 { + compatible = "zephyr,memory-region"; + reg = <0x0100a150 0x10>; + zephyr,memory-region = "ID_CODE"; + status = "okay"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 1933e2ff3babf..ed1b5506419c9 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,62 +144,62 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; lcdclk: lcdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 53393b24942f5..21c2468dd8278 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,56 +144,56 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 7005dc22bf6db..59bda1f704caf 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,62 +144,62 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; lcdclk: lcdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index 19221efe2058c..3ae29ee7ab500 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include / { @@ -44,13 +44,13 @@ }; pinctrl: pin-controller@40400800 { - compatible = "renesas,ra8-pinctrl"; + compatible = "renesas,ra-pinctrl-pfs"; reg = <0x40400800 0x3c0>; status = "okay"; }; ioport0: gpio@40400000 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400000 0x20>; port = <0>; gpio-controller; @@ -60,7 +60,7 @@ }; ioport1: gpio@40400020 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400020 0x20>; port = <1>; gpio-controller; @@ -70,7 +70,7 @@ }; ioport2: gpio@40400040 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400040 0x20>; port = <2>; gpio-controller; @@ -80,7 +80,7 @@ }; ioport3: gpio@40400060 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400060 0x20>; port = <3>; gpio-controller; @@ -90,7 +90,7 @@ }; ioport4: gpio@40400080 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400080 0x20>; port = <4>; gpio-controller; @@ -101,7 +101,7 @@ }; ioport5: gpio@404000a0 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x404000a0 0x20>; port = <5>; gpio-controller; @@ -111,7 +111,7 @@ }; ioport6: gpio@404000c0 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x404000c0 0x20>; port = <6>; gpio-controller; @@ -121,7 +121,7 @@ }; ioport7: gpio@404000e0 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x404000e0 0x20>; port = <7>; gpio-controller; @@ -131,7 +131,7 @@ }; ioport8: gpio@40400100 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400100 0x20>; port = <8>; gpio-controller; @@ -141,7 +141,7 @@ }; ioport9: gpio@40400120 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400120 0x20>; port = <9>; gpio-controller; @@ -151,7 +151,7 @@ }; ioporta: gpio@40400140 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400140 0x20>; port = <10>; gpio-controller; @@ -161,7 +161,7 @@ }; ioportb: gpio@40400160 { - compatible = "renesas,ra8-gpio"; + compatible = "renesas,ra-gpio-ioport"; reg = <0x40400160 0x20>; port = <11>; gpio-controller; diff --git a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml similarity index 85% rename from dts/bindings/clock/renesas,ra8-cgc-busclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-busclk.yaml index 1d2ae985d4cf5..949a739f2d43a 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 External Bus Clock +description: Renesas RA External Bus Clock -compatible: "renesas,ra8-cgc-busclk" +compatible: "renesas,ra-cgc-busclk" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml similarity index 73% rename from dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml rename to dts/bindings/clock/renesas,ra-cgc-external-clock.yaml index cdbefd91b69c1..3981894c860dd 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Generation Circuit external clock configuration +description: Renesas RA Clock Generation Circuit external clock configuration -compatible: "renesas,ra8-cgc-external-clock" +compatible: "renesas,ra-cgc-external-clock" include: [fixed-clock.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml similarity index 67% rename from dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml rename to dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml index 9ad2542ba2157..6380b712984d4 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 clock control node pclk block +description: Renesas RA Clock Control node pclk block -compatible: "renesas,ra8-cgc-pclk-block" +compatible: "renesas,ra-cgc-pclk-block" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml similarity index 81% rename from dts/bindings/clock/renesas,ra8-cgc-pclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-pclk.yaml index aece92b25705e..cc001c1717593 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Control Peripheral Clock +description: Renesas RA Clock Control Peripheral Clock -compatible: "renesas,ra8-cgc-pclk" +compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml similarity index 77% rename from dts/bindings/clock/renesas,ra8-cgc-pll.yaml rename to dts/bindings/clock/renesas,ra-cgc-pll.yaml index a18f6cf15d923..a974f54c075b9 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Generation Circuit PLL Clock +description: Renesas RA Clock Generation Circuit PLL Clock -compatible: "renesas,ra8-cgc-pll" +compatible: "renesas,ra-cgc-pll" include: [clock-controller.yaml, base.yaml] @@ -18,10 +18,8 @@ properties: required: true type: array divp: - required: true type: int freqp: - required: true type: int divq: type: int diff --git a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml similarity index 88% rename from dts/bindings/clock/renesas,ra8-cgc-subclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-subclk.yaml index 7ed083be7c13f..afb98c5fea116 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Sub-Clock +description: Renesas RA Sub-Clock -compatible: "renesas,ra8-cgc-subclk" +compatible: "renesas,ra-cgc-subclk" include: fixed-clock.yaml diff --git a/dts/bindings/gpio/renesas,ra8-gpio.yaml b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml similarity index 82% rename from dts/bindings/gpio/renesas,ra8-gpio.yaml rename to dts/bindings/gpio/renesas,ra-gpio-ioport.yaml index 9f6df08140171..bdf53054ec1d8 100644 --- a/dts/bindings/gpio/renesas,ra8-gpio.yaml +++ b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 GPIO +description: Renesas RA GPIO IO port -compatible: "renesas,ra8-gpio" +compatible: "renesas,ra-gpio-ioport" include: [gpio-controller.yaml, base.yaml] diff --git a/dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml b/dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml similarity index 97% rename from dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml rename to dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml index e4240dbc18a93..c3782162b8489 100644 --- a/dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml +++ b/dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml @@ -21,7 +21,7 @@ description: | */ /* include pre-defined combinations for the SoC variant used by the board */ - #include + #include &pinctrl { /* configuration for the sci0 "default" state */ @@ -67,7 +67,7 @@ description: | pinctrl-names = "default", "sleep"; }; -compatible: "renesas,ra8-pinctrl" +compatible: "renesas,ra-pinctrl-pfs" include: base.yaml diff --git a/dts/bindings/serial/renesas,ra-sci-uart.yaml b/dts/bindings/serial/renesas,ra-sci-uart.yaml new file mode 100644 index 0000000000000..55faae5a66f5c --- /dev/null +++ b/dts/bindings/serial/renesas,ra-sci-uart.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA SCI UART controller + +compatible: "renesas,ra-sci-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + channel: + type: int + required: true diff --git a/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml b/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml index 80717d8f7dce6..68490c4caa14f 100644 --- a/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml +++ b/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml @@ -11,11 +11,3 @@ properties: channel: type: int required: true - - tx-dtc: - type: boolean - description: Enable dtc support for transmit - - rx-dtc: - type: boolean - description: Enable dtc support for receive diff --git a/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h b/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h new file mode 100644 index 0000000000000..335f4b1c76cd8 --- /dev/null +++ b/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ + +#define RENESAS_GPIO_DS_POS (8) +#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS) +/* GPIO Drive strength */ +#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h deleted file mode 100644 index aa511e9fa47b1..0000000000000 --- a/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_ - -#define RENESAS_GPIO_DS_POS (8) -#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS) -/* GPIO Drive strength */ -#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS) -#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS) -#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS) -#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS) - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h similarity index 100% rename from include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h rename to include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas_fsp index d46bbf9ee4d02..c5f9b26bfe474 100644 --- a/modules/Kconfig.renesas_fsp +++ b/modules/Kconfig.renesas_fsp @@ -22,3 +22,8 @@ config USE_RA_FSP_I2C_IIC bool help Enable Renesas RA I2C IIC Master driver + +config USE_RA_FSP_SCI_UART + bool + help + Enable RA FSP SCI UART driver diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h index 7390202a24cb6..1b347f2bd2320 100644 --- a/soc/renesas/ra/common_fsp/pinctrl_soc.h +++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h @@ -10,7 +10,7 @@ #include #include -#include +#include /** * @brief Type to hold a renesas ra pin's pinctrl configuration. diff --git a/soc/renesas/ra/ra6e1/CMakeLists.txt b/soc/renesas/ra/ra6e1/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra6e1/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6e1/Kconfig b/soc/renesas/ra/ra6e1/Kconfig new file mode 100644 index 0000000000000..e67c9f66dc2b5 --- /dev/null +++ b/soc/renesas/ra/ra6e1/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6E1 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6e1/Kconfig.defconfig b/soc/renesas/ra/ra6e1/Kconfig.defconfig new file mode 100644 index 0000000000000..07ec796a33fb2 --- /dev/null +++ b/soc/renesas/ra/ra6e1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6E1 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6E1 diff --git a/soc/renesas/ra/ra6e1/Kconfig.soc b/soc/renesas/ra/ra6e1/Kconfig.soc new file mode 100644 index 0000000000000..979e11808418c --- /dev/null +++ b/soc/renesas/ra/ra6e1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6E1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6E1 series + +config SOC_R7FA6E10F2CFP + bool + select SOC_SERIES_RA6E1 + help + R7FA6E10F2CFP + +config SOC_SERIES + default "ra6e1" if SOC_SERIES_RA6E1 + +config SOC + default "r7fa6e10f2cfp" if SOC_R7FA6E10F2CFP diff --git a/soc/renesas/ra/ra6e1/sections.ld b/soc/renesas/ra/ra6e1/sections.ld new file mode 100644 index 0000000000000..cfc81aeec00b5 --- /dev/null +++ b/soc/renesas/ra/ra6e1/sections.ld @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF diff --git a/soc/renesas/ra/ra6e1/soc.c b/soc/renesas/ra/ra6e1/soc.c new file mode 100644 index 0000000000000..5ca796f5bbe58 --- /dev/null +++ b/soc/renesas/ra/ra6e1/soc.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6E1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6e1_init(void) +{ + uint32_t key; + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6e1_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6e1/soc.h b/soc/renesas/ra/ra6e1/soc.h new file mode 100644 index 0000000000000..0d3eb2c16fcc7 --- /dev/null +++ b/soc/renesas/ra/ra6e1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6E1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ */ diff --git a/soc/renesas/ra/ra6e2/CMakeLists.txt b/soc/renesas/ra/ra6e2/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra6e2/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6e2/Kconfig b/soc/renesas/ra/ra6e2/Kconfig new file mode 100644 index 0000000000000..9ac1ba7dd4211 --- /dev/null +++ b/soc/renesas/ra/ra6e2/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6E2 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6e2/Kconfig.defconfig b/soc/renesas/ra/ra6e2/Kconfig.defconfig new file mode 100644 index 0000000000000..e08fb2e13563d --- /dev/null +++ b/soc/renesas/ra/ra6e2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6E2 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6E2 diff --git a/soc/renesas/ra/ra6e2/Kconfig.soc b/soc/renesas/ra/ra6e2/Kconfig.soc new file mode 100644 index 0000000000000..3a0feff296e9a --- /dev/null +++ b/soc/renesas/ra/ra6e2/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6E2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6E2 series + +config SOC_R7FA6E2BB3CFM + bool + select SOC_SERIES_RA6E2 + help + R7FA6E2BB3CFM + +config SOC_SERIES + default "ra6e2" if SOC_SERIES_RA6E2 + +config SOC + default "r7fa6e2bb3cfm" if SOC_R7FA6E2BB3CFM diff --git a/soc/renesas/ra/ra6e2/sections.ld b/soc/renesas/ra/ra6e2/sections.ld new file mode 100644 index 0000000000000..511ad0854a26a --- /dev/null +++ b/soc/renesas/ra/ra6e2/sections.ld @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra6e2/soc.c b/soc/renesas/ra/ra6e2/soc.c new file mode 100644 index 0000000000000..2249db628e4bd --- /dev/null +++ b/soc/renesas/ra/ra6e2/soc.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6E2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6e2_init(void) +{ + uint32_t key; + + key = irq_lock(); + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6e2_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6e2/soc.h b/soc/renesas/ra/ra6e2/soc.h new file mode 100644 index 0000000000000..a40324087cdbe --- /dev/null +++ b/soc/renesas/ra/ra6e2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6E2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_ */ diff --git a/soc/renesas/ra/ra6m1/CMakeLists.txt b/soc/renesas/ra/ra6m1/CMakeLists.txt new file mode 100644 index 0000000000000..ccc5f9899ae8c --- /dev/null +++ b/soc/renesas/ra/ra6m1/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(ROM_START opt_set_mem.ld) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m1/Kconfig b/soc/renesas/ra/ra6m1/Kconfig new file mode 100644 index 0000000000000..e2520fc456947 --- /dev/null +++ b/soc/renesas/ra/ra6m1/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M1 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m1/Kconfig.defconfig b/soc/renesas/ra/ra6m1/Kconfig.defconfig new file mode 100644 index 0000000000000..4f61b47586958 --- /dev/null +++ b/soc/renesas/ra/ra6m1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M1 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M1 diff --git a/soc/renesas/ra/ra6m1/Kconfig.soc b/soc/renesas/ra/ra6m1/Kconfig.soc new file mode 100644 index 0000000000000..b979a8b609756 --- /dev/null +++ b/soc/renesas/ra/ra6m1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M1 series + +config SOC_R7FA6M1AD3CFP + bool + select SOC_SERIES_RA6M1 + help + R7FA6M1AD3CFP + +config SOC_SERIES + default "ra6m1" if SOC_SERIES_RA6M1 + +config SOC + default "r7fa6m1ad3cfp" if SOC_R7FA6M1AD3CFP diff --git a/soc/renesas/ra/ra6m1/opt_set_mem.ld b/soc/renesas/ra/ra6m1/opt_set_mem.ld new file mode 100644 index 0000000000000..07aef9e92d838 --- /dev/null +++ b/soc/renesas/ra/ra6m1/opt_set_mem.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra6m1/sections.ld b/soc/renesas/ra/ra6m1/sections.ld new file mode 100644 index 0000000000000..b850a64f64374 --- /dev/null +++ b/soc/renesas/ra/ra6m1/sections.ld @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra6m1/soc.c b/soc/renesas/ra/ra6m1/soc.c new file mode 100644 index 0000000000000..d56bde197e639 --- /dev/null +++ b/soc/renesas/ra/ra6m1/soc.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m1_init(void) +{ + uint32_t key; + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m1_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m1/soc.h b/soc/renesas/ra/ra6m1/soc.h new file mode 100644 index 0000000000000..b341280870ec8 --- /dev/null +++ b/soc/renesas/ra/ra6m1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_ */ diff --git a/soc/renesas/ra/ra6m2/CMakeLists.txt b/soc/renesas/ra/ra6m2/CMakeLists.txt new file mode 100644 index 0000000000000..ccc5f9899ae8c --- /dev/null +++ b/soc/renesas/ra/ra6m2/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(ROM_START opt_set_mem.ld) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m2/Kconfig b/soc/renesas/ra/ra6m2/Kconfig new file mode 100644 index 0000000000000..89c951a9db9ea --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M2 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m2/Kconfig.defconfig b/soc/renesas/ra/ra6m2/Kconfig.defconfig new file mode 100644 index 0000000000000..33ada2c756e89 --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M2 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M2 diff --git a/soc/renesas/ra/ra6m2/Kconfig.soc b/soc/renesas/ra/ra6m2/Kconfig.soc new file mode 100644 index 0000000000000..6c8b47e20cf23 --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M2 series + +config SOC_R7FA6M2AF3CFB + bool + select SOC_SERIES_RA6M2 + help + R7FA6M2AF3CFB + +config SOC_SERIES + default "ra6m2" if SOC_SERIES_RA6M2 + +config SOC + default "r7fa6m2af3cfb" if SOC_R7FA6M2AF3CFB diff --git a/soc/renesas/ra/ra6m2/opt_set_mem.ld b/soc/renesas/ra/ra6m2/opt_set_mem.ld new file mode 100644 index 0000000000000..07aef9e92d838 --- /dev/null +++ b/soc/renesas/ra/ra6m2/opt_set_mem.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra6m2/sections.ld b/soc/renesas/ra/ra6m2/sections.ld new file mode 100644 index 0000000000000..b850a64f64374 --- /dev/null +++ b/soc/renesas/ra/ra6m2/sections.ld @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra6m2/soc.c b/soc/renesas/ra/ra6m2/soc.c new file mode 100644 index 0000000000000..4b10f2123e644 --- /dev/null +++ b/soc/renesas/ra/ra6m2/soc.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m2_init(void) +{ + uint32_t key; + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m2_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m2/soc.h b/soc/renesas/ra/ra6m2/soc.h new file mode 100644 index 0000000000000..8ad75a1efea57 --- /dev/null +++ b/soc/renesas/ra/ra6m2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ */ diff --git a/soc/renesas/ra/ra6m3/CMakeLists.txt b/soc/renesas/ra/ra6m3/CMakeLists.txt new file mode 100644 index 0000000000000..ccc5f9899ae8c --- /dev/null +++ b/soc/renesas/ra/ra6m3/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(ROM_START opt_set_mem.ld) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m3/Kconfig b/soc/renesas/ra/ra6m3/Kconfig new file mode 100644 index 0000000000000..c91e5284022dc --- /dev/null +++ b/soc/renesas/ra/ra6m3/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M3 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m3/Kconfig.defconfig b/soc/renesas/ra/ra6m3/Kconfig.defconfig new file mode 100644 index 0000000000000..f1d9a2998d3e4 --- /dev/null +++ b/soc/renesas/ra/ra6m3/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M3 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M3 diff --git a/soc/renesas/ra/ra6m3/Kconfig.soc b/soc/renesas/ra/ra6m3/Kconfig.soc new file mode 100644 index 0000000000000..af57f34f5c8f8 --- /dev/null +++ b/soc/renesas/ra/ra6m3/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M3 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M3 series + +config SOC_R7FA6M3AH3CFC + bool + select SOC_SERIES_RA6M3 + help + R7FA6M3AH3CFC + +config SOC_SERIES + default "ra6m3" if SOC_SERIES_RA6M3 + +config SOC + default "r7fa6m3ah3cfc" if SOC_R7FA6M3AH3CFC diff --git a/soc/renesas/ra/ra6m3/opt_set_mem.ld b/soc/renesas/ra/ra6m3/opt_set_mem.ld new file mode 100644 index 0000000000000..07aef9e92d838 --- /dev/null +++ b/soc/renesas/ra/ra6m3/opt_set_mem.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra6m3/sections.ld b/soc/renesas/ra/ra6m3/sections.ld new file mode 100644 index 0000000000000..b850a64f64374 --- /dev/null +++ b/soc/renesas/ra/ra6m3/sections.ld @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra6m3/soc.c b/soc/renesas/ra/ra6m3/soc.c new file mode 100644 index 0000000000000..b2d87b50f0aa9 --- /dev/null +++ b/soc/renesas/ra/ra6m3/soc.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M3 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m3_init(void) +{ + uint32_t key; + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m3_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m3/soc.h b/soc/renesas/ra/ra6m3/soc.h new file mode 100644 index 0000000000000..9fa414f0b6474 --- /dev/null +++ b/soc/renesas/ra/ra6m3/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M3 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_ */ diff --git a/soc/renesas/ra/ra6m4/CMakeLists.txt b/soc/renesas/ra/ra6m4/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra6m4/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m4/Kconfig b/soc/renesas/ra/ra6m4/Kconfig new file mode 100644 index 0000000000000..b74ea6807dc64 --- /dev/null +++ b/soc/renesas/ra/ra6m4/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M4 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m4/Kconfig.defconfig b/soc/renesas/ra/ra6m4/Kconfig.defconfig new file mode 100644 index 0000000000000..672c88d9aa3b2 --- /dev/null +++ b/soc/renesas/ra/ra6m4/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M4 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M4 diff --git a/soc/renesas/ra/ra6m4/Kconfig.soc b/soc/renesas/ra/ra6m4/Kconfig.soc new file mode 100644 index 0000000000000..d0e9adda2d236 --- /dev/null +++ b/soc/renesas/ra/ra6m4/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M4 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M4 series + +config SOC_R7FA6M4AF3CFB + bool + select SOC_SERIES_RA6M4 + help + R7FA6M4AF3CFB + +config SOC_SERIES + default "ra6m4" if SOC_SERIES_RA6M4 + +config SOC + default "r7fa6m4af3cfb" if SOC_R7FA6M4AF3CFB diff --git a/soc/renesas/ra/ra6m4/sections.ld b/soc/renesas/ra/ra6m4/sections.ld new file mode 100644 index 0000000000000..cfc81aeec00b5 --- /dev/null +++ b/soc/renesas/ra/ra6m4/sections.ld @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF diff --git a/soc/renesas/ra/ra6m4/soc.c b/soc/renesas/ra/ra6m4/soc.c new file mode 100644 index 0000000000000..1d61e5f40c7a4 --- /dev/null +++ b/soc/renesas/ra/ra6m4/soc.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M4 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m4_init(void) +{ + uint32_t key; + + key = irq_lock(); + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m4_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m4/soc.h b/soc/renesas/ra/ra6m4/soc.h new file mode 100644 index 0000000000000..13344b76e84a0 --- /dev/null +++ b/soc/renesas/ra/ra6m4/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M4 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_ */ diff --git a/soc/renesas/ra/ra6m5/CMakeLists.txt b/soc/renesas/ra/ra6m5/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra6m5/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m5/Kconfig b/soc/renesas/ra/ra6m5/Kconfig new file mode 100644 index 0000000000000..f7fdc083bc21f --- /dev/null +++ b/soc/renesas/ra/ra6m5/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M5 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m5/Kconfig.defconfig b/soc/renesas/ra/ra6m5/Kconfig.defconfig new file mode 100644 index 0000000000000..ca09319ed2a0c --- /dev/null +++ b/soc/renesas/ra/ra6m5/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M5 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M5 diff --git a/soc/renesas/ra/ra6m5/Kconfig.soc b/soc/renesas/ra/ra6m5/Kconfig.soc new file mode 100644 index 0000000000000..169511ecfc98a --- /dev/null +++ b/soc/renesas/ra/ra6m5/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M5 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M5 series + +config SOC_R7FA6M5BH3CFC + bool + select SOC_SERIES_RA6M5 + help + R7FA6M5BH3CFC + +config SOC_SERIES + default "ra6m5" if SOC_SERIES_RA6M5 + +config SOC + default "r7fa6m5bh3cfc" if SOC_R7FA6M5BH3CFC diff --git a/soc/renesas/ra/ra6m5/sections.ld b/soc/renesas/ra/ra6m5/sections.ld new file mode 100644 index 0000000000000..cfc81aeec00b5 --- /dev/null +++ b/soc/renesas/ra/ra6m5/sections.ld @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF diff --git a/soc/renesas/ra/ra6m5/soc.c b/soc/renesas/ra/ra6m5/soc.c new file mode 100644 index 0000000000000..fda381f0f0d88 --- /dev/null +++ b/soc/renesas/ra/ra6m5/soc.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M5 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m5_init(void) +{ + uint32_t key; + + key = irq_lock(); + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m5_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m5/soc.h b/soc/renesas/ra/ra6m5/soc.h new file mode 100644 index 0000000000000..2774723147c1f --- /dev/null +++ b/soc/renesas/ra/ra6m5/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M5 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index 87d7237e8a7a4..7e2bfeeb6334b 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -4,6 +4,27 @@ family: - name: ra4m1 socs: - name: r7fa4m1ab3cfm + - name: ra6m1 + socs: + - name: r7fa6m1ad3cfp + - name: ra6m2 + socs: + - name: r7fa6m2af3cfb + - name: ra6m3 + socs: + - name: r7fa6m3ah3cfc + - name: ra6m4 + socs: + - name: r7fa6m4af3cfb + - name: ra6m5 + socs: + - name: r7fa6m5bh3cfc + - name: ra6e1 + socs: + - name: r7fa6e10f2cfp + - name: ra6e2 + socs: + - name: r7fa6e2bb3cfm - name: ra8m1 socs: - name: r7fa8m1ahecbd diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay new file mode 100644 index 0000000000000..10121b5ad9ee9 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay new file mode 100644 index 0000000000000..e73ba999f6604 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay new file mode 100644 index 0000000000000..dbef642d32d9e --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay new file mode 100644 index 0000000000000..dbef642d32d9e --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay new file mode 100644 index 0000000000000..eafbefdaf62b8 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci7_default: sci7_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay new file mode 100644 index 0000000000000..eafbefdaf62b8 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci7_default: sci7_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay new file mode 100644 index 0000000000000..c80fe08563968 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay new file mode 100644 index 0000000000000..10121b5ad9ee9 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +};