diff --git a/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 b/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 new file mode 100644 index 0000000000000..418e3597cd7d6 --- /dev/null +++ b/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4E2 + select SOC_R7FA4E2B93CFM diff --git a/boards/renesas/ek_ra4e2/board.cmake b/boards/renesas/ek_ra4e2/board.cmake new file mode 100644 index 0000000000000..18c2bdf71e930 --- /dev/null +++ b/boards/renesas/ek_ra4e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4E2B9") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4e2/board.yml b/boards/renesas/ek_ra4e2/board.yml new file mode 100644 index 0000000000000..8baa0819ff2d5 --- /dev/null +++ b/boards/renesas/ek_ra4e2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4e2 + vendor: renesas + socs: + - name: r7fa4e2b93cfm diff --git a/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp b/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp new file mode 100644 index 0000000000000..4b3e56075c339 Binary files /dev/null and b/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp differ diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst new file mode 100644 index 0000000000000..0bf90ed5464e0 --- /dev/null +++ b/boards/renesas/ek_ra4e2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra4e2: + +RA4E2 Evaluation Kit +#################### + +Overview +******** + +The RA4E2 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core +with 128 KB of code flash memory, 4 KB of data flash memory, and 40 KB of SRAM. RA4E2 MCUs +offer high-performance and optimized peripheral functions along with the smallest package +options, including space-saving 36-pin BGA and 32-pin QFN packages. The RA4E2 +Group offers a wide set of peripherals, including USB Full Speed, CANFD, I3C, and ADC. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**MCU Native Pin Access** +- R7FA4E2B93CFM MCU (referred to as RA MCU) +- 100 MHz, Arm® Cortex®-M33 core +- 128 kB Code Flash, 40 kB SRAM +- 64 pins, LQFP package +- Native pin access through 2 x 14-pin and 1 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision +20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the +RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Device (micro-AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and J31 through holes) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD) + - Debug out (JTAG, SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I3C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- CAN FD (3-pin header) + +.. figure:: ek-ra4e2-board.webp + :align: center + :alt: RA4E2 Evaluation Kit + + EK-RA4E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_ + +.. figure:: ra4e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA4E2 MCU group feature + + RA4E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4E2B9 +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4E2 Website`_ +- `RA4E2 MCU group Website`_ + +.. _EK-RA4E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4e2-evaluation-kit-ra4e2-mcu-group + +.. _RA4E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4e2-entry-line-100mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _EK-RA4E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4e2-v1-users-manual + +.. _RA4E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra4e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp b/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp new file mode 100644 index 0000000000000..d214ac7dba802 Binary files /dev/null and b/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts new file mode 100644 index 0000000000000..e371198e6ed53 --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4e2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4E2"; + compatible = "renesas,ra4e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport1 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml new file mode 100644 index 0000000000000..bceab6ca960ac --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4e2 +name: Renesas EK-RA4E2 +type: mcu +arch: arm +ram: 40 +flash: 128 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig new file mode 100644 index 0000000000000..ceaa9b32580a3 --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 b/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 new file mode 100644 index 0000000000000..bd762fb2bd9a5 --- /dev/null +++ b/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4M2 + select SOC_R7FA4M2AD3CFP diff --git a/boards/renesas/ek_ra4m2/board.cmake b/boards/renesas/ek_ra4m2/board.cmake new file mode 100644 index 0000000000000..f0faf6c179ab1 --- /dev/null +++ b/boards/renesas/ek_ra4m2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4M2AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4m2/board.yml b/boards/renesas/ek_ra4m2/board.yml new file mode 100644 index 0000000000000..c19484eff8a9f --- /dev/null +++ b/boards/renesas/ek_ra4m2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4m2 + vendor: renesas + socs: + - name: r7fa4m2ad3cfp diff --git a/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp b/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp new file mode 100644 index 0000000000000..6f83ef7274aff Binary files /dev/null and b/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp differ diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst new file mode 100644 index 0000000000000..833768d6d16f7 --- /dev/null +++ b/boards/renesas/ek_ra4m2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra4m2: + +RA4M2 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4M2 group of 32-bit microcontrollers (MCUs) uses the high-performance Arm +Cortex®-M33 core. In concert with the secure crypto engine, it offers secure element +functionality. The RA4M2 is built on a highly efficient 40nm process, built on FreeRTOS—and +is expandable to use other RTOSes and middleware. The RA4M2 is suitable for IoT applications +requiring vast communication options, future proof security, large embedded RAM, and low +active power consumption down to 81µA/MHz running the CoreMark® algorithm from Flash. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**Renesas RA4M2 Microcontroller Group** +- R7FA4M2AD3CFP +- 100-pin LQFP package +- 100 MHz Arm® Cortex®-M33 core +- 512 kB Code Flash, 128 KB SRAM +- Native pin access through 4 x 28-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing +precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are +available internal to the RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Host and Device (micro AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD, and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I2C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** +- 32 MB (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra4m2-board.webp + :align: center + :alt: RA4M2 Evaluation Kit + + EK-RA4M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_ + +.. figure:: ra4m2-block-diagram.webp + :width: 442px + :align: center + :alt: RA4M2 MCU group feature + + RA4M2 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4M2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4m2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4M2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4M2AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4M2 Website`_ +- `RA4M2 MCU group Website`_ + +.. _EK-RA4M2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m2-evaluation-kit-ra4m2-mcu-group + +.. _RA4M2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m2-100mhz-arm-cortex-m33-trustzone-high-integration-lowest-active-power-consumption + +.. _EK-RA4M2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4m2-v1-users-manual + +.. _RA4M2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra4m2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp b/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp new file mode 100644 index 0000000000000..c902d3d4d3fbb Binary files /dev/null and b/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts new file mode 100644 index 0000000000000..49f35db2e8340 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4m2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4M2"; + compatible = "renesas,ra4m2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 5 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml new file mode 100644 index 0000000000000..d61c6bf05fe82 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4m2 +name: Renesas EK-RA4M2 +type: mcu +arch: arm +ram: 128 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig new file mode 100644 index 0000000000000..ceaa9b32580a3 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 b/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 new file mode 100644 index 0000000000000..5060f6a325e4a --- /dev/null +++ b/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4M3 + select SOC_R7FA4M3AF3CFB diff --git a/boards/renesas/ek_ra4m3/board.cmake b/boards/renesas/ek_ra4m3/board.cmake new file mode 100644 index 0000000000000..98f1f87f5b721 --- /dev/null +++ b/boards/renesas/ek_ra4m3/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4M3AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4m3/board.yml b/boards/renesas/ek_ra4m3/board.yml new file mode 100644 index 0000000000000..30b3b39ac4e34 --- /dev/null +++ b/boards/renesas/ek_ra4m3/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4m3 + vendor: renesas + socs: + - name: r7fa4m3af3cfb diff --git a/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp b/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp new file mode 100644 index 0000000000000..998092d81716a Binary files /dev/null and b/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp differ diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst new file mode 100644 index 0000000000000..07db2061617b7 --- /dev/null +++ b/boards/renesas/ek_ra4m3/doc/index.rst @@ -0,0 +1,167 @@ +.. _ek_ra4m3: + +RA4M3 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4M3 group of 32-bit microcontrollers (MCUs) uses the high-performance +Arm® Cortex®-M33 core with TrustZone. In concert with the secure crypto engine, it +offers secure element functionality. The RA4M3 is built on a highly efficient 40nm +process, built on FreeRTOS—and is expandable to use other RTOSes and middleware. +The RA4M3 is suitable for IoT applications requiring vast communication options, future +proof security, large embedded RAM, and low active power consumption down to 119µA/MHz +running the CoreMark® algorithm from Flash. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**MCU Native Pin Access** +- R7FA4M3AF3CFB +- 100-pin LQFP package +- 100 MHz Arm® Cortex®-M33 core +- 1 MB Code Flash, 128 KB SRAM +- 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision +24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the +RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Host and Device (micro AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + + Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD, and JTAG) + - Debug out (SWD) + + User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I2C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** +- 32 MB (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra4m3-board.webp + :align: center + :alt: RA4M3 Evaluation Kit + + EK-RA4M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_ + +.. figure:: ra4m3-block-diagram.webp + :width: 442px + :align: center + :alt: RA4M3 MCU group feature + + RA4M3 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4M3 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4m3`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4M3 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M3 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4M3AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4M3 Website`_ +- `RA4M3 MCU group Website`_ + +.. _EK-RA4M3 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group + +.. _RA4M3 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m3-100mhz-arm-cortex-m33-trustzone-high-integration-rich-connectivity + +.. _EK-RA4M3 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4m3-v1-users-manual + +.. _RA4M3 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra4m3-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp b/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp new file mode 100644 index 0000000000000..d3d70ebcd38bb Binary files /dev/null and b/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi new file mode 100644 index 0000000000000..851d8543beea0 --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts new file mode 100644 index 0000000000000..f076510018e93 --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4m3-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4M3"; + compatible = "renesas,ra4m3", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml new file mode 100644 index 0000000000000..e05b8e804da78 --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4m3 +name: Renesas EK-RA4M3 +type: mcu +arch: arm +ram: 128 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig new file mode 100644 index 0000000000000..ceaa9b32580a3 --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 b/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 new file mode 100644 index 0000000000000..a2f855a2b3c6f --- /dev/null +++ b/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4W1 + select SOC_R7FA4W1AD2CNG diff --git a/boards/renesas/ek_ra4w1/board.cmake b/boards/renesas/ek_ra4w1/board.cmake new file mode 100644 index 0000000000000..6a1b1617cb802 --- /dev/null +++ b/boards/renesas/ek_ra4w1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4W1AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4w1/board.yml b/boards/renesas/ek_ra4w1/board.yml new file mode 100644 index 0000000000000..709a8435475f3 --- /dev/null +++ b/boards/renesas/ek_ra4w1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4w1 + vendor: renesas + socs: + - name: r7fa4w1ad2cng diff --git a/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp b/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp new file mode 100644 index 0000000000000..9a1e2b9be439b Binary files /dev/null and b/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp differ diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst new file mode 100644 index 0000000000000..d20c5c27390bc --- /dev/null +++ b/boards/renesas/ek_ra4w1/doc/index.rst @@ -0,0 +1,157 @@ +.. _ek_ra4w1: + +RA4W1 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4W1 is the first Bluetooth® 5.0 Low Energy fully compliant with 2Mbit High-Throughput +(HT) and Long Range support in a single chip MCU of Renesas RA4 product series for IoT applications +that require a high-performance Arm® Cortex®-M4 core at a very attractive price point. The RA4W1 MCU +has full function support for Bluetooth 5.0 Low Energy long-range and mesh networking, and provides +excellent reception performance. RA4W1 is geared towards IoT application requiring Security, large +embedded RAM and low power consumption. + +**MCU Native Pin Access** +- R7FA4W1AD2CNG +- QFN-56 package +- On-chip memory: 512-KB ROM, 96-KB RAM, 8-KB data flash memory + +**Power-supply voltage** +- USB connector: 5-V input +- Power-supply IC: 5-V input, 3.3-V output +- External power-supply header*1: 3.3-V input, 2 pins x 1 + +**Main clock** +- Crystal oscillator (surface-mount technology (SMT)) for the main system clock +- Crystal oscillator or ceramic resonator (lead type) for the main system clock + +**Sub-clock** +- Crystal oscillator (SMT) for the sub-clock + +**Bluetooth Low Energy** +- Bluetooth Low Energy (BLE) circuit x1 +- Range of frequency: 2402 to 2480 MHz +- Maximum transmission output power: 4 dBm (in 4-dBm output mode) +- Output variation: +2 dB + +**Push switches** +- Reset switch x 1 +- User switch x 1 + +**LED** +- Power indicator: green x 1 +- User: green x 2 +- ACT LED: green x 1 + +**Conetivity** +- Connector for an on-board emulator: USB Micro-B +- Connector for a USB serial-conversion interface: USB Micro-B +- Pmod™ connector: Angle type, 12 pins +- Arduino™ UNO connectors + +- Emulator reset switch + +.. figure:: ek-ra4w1-board.webp + :align: center + :alt: RA4W1 Evaluation Kit + + EK-RA4W1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_ + +.. figure:: ra4w1-block-diagram.webp + :width: 442px + :align: center + :alt: RA4W1 MCU group feature + + RA4W1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4W1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4w1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4W1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4W1AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4W1 Website`_ +- `RA4W1 MCU group Website`_ + +.. _EK-RA4W1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4w1-evaluation-kit-ra4w1-mcu-group + +.. _RA4W1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4w1-low-energy-single-chip-32-bit-microcontrollers-48mhz-bluetooth-50 + +.. _EK-RA4W1 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra4w1-users-manual + +.. _RA4W1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/renesas-ra4w1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp b/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp new file mode 100644 index 0000000000000..d569b021488f1 Binary files /dev/null and b/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi new file mode 100644 index 0000000000000..3c01cb6bec4cf --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts new file mode 100644 index 0000000000000..7d764631e034b --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4w1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4W1"; + compatible = "renesas,ra4w1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&subclk { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml new file mode 100644 index 0000000000000..f31bcd0a7bc88 --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4w1 +name: Renesas EK-RA4W1 +type: mcu +arch: arm +ram: 96 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig new file mode 100644 index 0000000000000..92542b8ab9c11 --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi new file mode 100644 index 0000000000000..f6f3074a005b3 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(40)>; + }; + + ioport8: gpio@40080100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(128)>; + }; + }; + + id_code: id_code@100a120 { + compatible = "zephyr,memory-region"; + reg = <0x0100a120 0x10>; + zephyr,memory-region = "ID_CODE"; + status = "okay"; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <10 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + i3cclk: i3cclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + cecclk: cecclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ad3cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ad3cfp.dtsi new file mode 100644 index 0000000000000..37b1961111c73 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ad3cfp.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi new file mode 100644 index 0000000000000..8ce2e86e7a46a --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(128)>; + }; + + ioport6: gpio@400800c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400800e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40118200 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118200 0x100>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <25 0>; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3af3cfb.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3af3cfb.dtsi new file mode 100644 index 0000000000000..7d0d8b908d51c --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4m3af3cfb.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@407e0000 { + reg = <0x407e0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(1)>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi new file mode 100644 index 0000000000000..116e1f5b05f80 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(128)>; + }; + + ioport6: gpio@400800c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@400800e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport8: gpio@40080100 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080100 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci2: sci2@40118200 { + compatible = "renesas,ra-sci"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118200 0x100>; + clocks = <&pclka MSTPB 29>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <2>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <25 0>; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi new file mode 100644 index 0000000000000..d485e4c1f76d4 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(96)>; + }; + + flash-controller@407e0000 { + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(512)>; + }; + }; + + sci4: sci4@40070080 { + compatible = "renesas,ra-sci"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070080 0x20>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <12 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi new file mode 100644 index 0000000000000..f7959fc898d9e --- /dev/null +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + interrupt-parent = <&nvic>; + + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ioport0: gpio@40080000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@40080020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@40080040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@40080060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@40080080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40080080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@400800a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400800a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-controller@40080800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x40080800 0x3c0>; + status = "okay"; + }; + + sci0: sci0@40118000 { + compatible = "renesas,ra-sci"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118000 0x100>; + clocks = <&pclka MSTPB 31>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci9: sci9@40118900 { + compatible = "renesas,ra-sci"; + interrupts = <36 1>, <37 1>, <38 1>, <39 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40118900 0x100>; + clocks = <&pclka MSTPB 22>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + option_setting_ofs: option_setting_ofs@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x18>; + zephyr,memory-region = "OPTION_SETTING_OFS"; + status = "okay"; + }; + + option_setting_sas: option_setting_sas@100a134 { + compatible = "zephyr,memory-region"; + reg = <0x0100a134 0xcc>; + zephyr,memory-region = "OPTION_SETTING_SAS"; + status = "okay"; + }; + + option_setting_s: option_setting_s@100a200 { + compatible = "zephyr,memory-region"; + reg = <0x0100a200 0x100>; + zephyr,memory-region = "OPTION_SETTING_S"; + status = "okay"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi new file mode 100644 index 0000000000000..69a90813f1e53 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + }; + + }; + }; + + soc { + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + flash-controller@407e0000 { + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ioport0: gpio@40040000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@40040020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@40040040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@40040060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@40040080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@400400a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x400400a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport9: gpio@40040120 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x40040120 0x20>; + port = <9>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-controller@40040800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x40040800 0x3c0>; + status = "okay"; + }; + + sci0: sci0@40070000 { + compatible = "renesas,ra-sci"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070000 0x20>; + clocks = <&pclka MSTPB 31>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci1: sci1@40070020 { + compatible = "renesas,ra-sci"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070020 0x20>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci9: sci9@40070120 { + compatible = "renesas,ra-sci"; + interrupts = <36 1>, <37 1>, <38 1>, <39 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x40070120 0x20>; + clocks = <&pclka MSTPB 22>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + id_code: id_code@1010018 { + compatible = "zephyr,memory-region"; + reg = <0x01010018 0x20>; + zephyr,memory-region = "ID_CODE"; + status = "okay"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/soc/renesas/ra/ra4e2/CMakeLists.txt b/soc/renesas/ra/ra4e2/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra4e2/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4e2/Kconfig b/soc/renesas/ra/ra4e2/Kconfig new file mode 100644 index 0000000000000..6c3c2b8746865 --- /dev/null +++ b/soc/renesas/ra/ra4e2/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4E2 + select ARM + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M33 + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra4e2/Kconfig.defconfig b/soc/renesas/ra/ra4e2/Kconfig.defconfig new file mode 100644 index 0000000000000..985e17502d705 --- /dev/null +++ b/soc/renesas/ra/ra4e2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4E2 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA4E2 diff --git a/soc/renesas/ra/ra4e2/Kconfig.soc b/soc/renesas/ra/ra4e2/Kconfig.soc new file mode 100644 index 0000000000000..38ec2b3af06e8 --- /dev/null +++ b/soc/renesas/ra/ra4e2/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4E2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4E2 series + +config SOC_R7FA4E2B93CFM + bool + select SOC_SERIES_RA4E2 + help + R7FA4E2B93CFM + +config SOC_SERIES + default "ra4e2" if SOC_SERIES_RA4E2 + +config SOC + default "r7fa4e2b93cfm" if SOC_R7FA4E2B93CFM diff --git a/soc/renesas/ra/ra4e2/sections.ld b/soc/renesas/ra/ra4e2/sections.ld new file mode 100644 index 0000000000000..511ad0854a26a --- /dev/null +++ b/soc/renesas/ra/ra4e2/sections.ld @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra4e2/soc.c b/soc/renesas/ra/ra4e2/soc.c new file mode 100644 index 0000000000000..74b0e8c76410a --- /dev/null +++ b/soc/renesas/ra/ra4e2/soc.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA4E2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra4e2_init(void) +{ + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + return 0; +} + +SYS_INIT(renesas_ra4e2_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra4e2/soc.h b/soc/renesas/ra/ra4e2/soc.h new file mode 100644 index 0000000000000..cdf8331dac62a --- /dev/null +++ b/soc/renesas/ra/ra4e2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA4E2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ */ diff --git a/soc/renesas/ra/ra4m2/CMakeLists.txt b/soc/renesas/ra/ra4m2/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra4m2/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m2/Kconfig b/soc/renesas/ra/ra4m2/Kconfig new file mode 100644 index 0000000000000..1231924935df5 --- /dev/null +++ b/soc/renesas/ra/ra4m2/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M2 + select ARM + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M33 + select HAS_RENESAS_RA_FSP + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select ARMV8_M_DSP + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra4m2/Kconfig.defconfig b/soc/renesas/ra/ra4m2/Kconfig.defconfig new file mode 100644 index 0000000000000..4d0b12330b0c5 --- /dev/null +++ b/soc/renesas/ra/ra4m2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4M2 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA4M2 diff --git a/soc/renesas/ra/ra4m2/Kconfig.soc b/soc/renesas/ra/ra4m2/Kconfig.soc new file mode 100644 index 0000000000000..9878de8da67a6 --- /dev/null +++ b/soc/renesas/ra/ra4m2/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4M2 series + +config SOC_R7FA4M2AD3CFP + bool + select SOC_SERIES_RA4M2 + help + R7FA4M2AD3CFP + +config SOC_SERIES + default "ra4m2" if SOC_SERIES_RA4M2 + +config SOC + default "r7fa4m2ad3cfp" if SOC_R7FA4M2AD3CFP diff --git a/soc/renesas/ra/ra4m2/sections.ld b/soc/renesas/ra/ra4m2/sections.ld new file mode 100644 index 0000000000000..cfc81aeec00b5 --- /dev/null +++ b/soc/renesas/ra/ra4m2/sections.ld @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF diff --git a/soc/renesas/ra/ra4m2/soc.c b/soc/renesas/ra/ra4m2/soc.c new file mode 100644 index 0000000000000..e6e846ab088f1 --- /dev/null +++ b/soc/renesas/ra/ra4m2/soc.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA4M2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra4m2_init(void) +{ + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + return 0; +} + +SYS_INIT(renesas_ra4m2_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra4m2/soc.h b/soc/renesas/ra/ra4m2/soc.h new file mode 100644 index 0000000000000..99cefaf34758c --- /dev/null +++ b/soc/renesas/ra/ra4m2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA4M2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4M2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4M2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4M2_SOC_H_ */ diff --git a/soc/renesas/ra/ra4m3/CMakeLists.txt b/soc/renesas/ra/ra4m3/CMakeLists.txt new file mode 100644 index 0000000000000..1c7457569ef3e --- /dev/null +++ b/soc/renesas/ra/ra4m3/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m3/Kconfig b/soc/renesas/ra/ra4m3/Kconfig new file mode 100644 index 0000000000000..00eb8c9a7abe6 --- /dev/null +++ b/soc/renesas/ra/ra4m3/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M3 + select ARM + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M33 + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra4m3/Kconfig.defconfig b/soc/renesas/ra/ra4m3/Kconfig.defconfig new file mode 100644 index 0000000000000..a93ed41ee240f --- /dev/null +++ b/soc/renesas/ra/ra4m3/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4M3 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA4M3 diff --git a/soc/renesas/ra/ra4m3/Kconfig.soc b/soc/renesas/ra/ra4m3/Kconfig.soc new file mode 100644 index 0000000000000..7b32bdd622555 --- /dev/null +++ b/soc/renesas/ra/ra4m3/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M3 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4M3 series + +config SOC_R7FA4M3AF3CFB + bool + select SOC_SERIES_RA4M3 + help + R7FA4M3AF3CFB + +config SOC_SERIES + default "ra4m3" if SOC_SERIES_RA4M3 + +config SOC + default "r7fa4m3af3cfb" if SOC_R7FA4M3AF3CFB diff --git a/soc/renesas/ra/ra4m3/sections.ld b/soc/renesas/ra/ra4m3/sections.ld new file mode 100644 index 0000000000000..cfc81aeec00b5 --- /dev/null +++ b/soc/renesas/ra/ra4m3/sections.ld @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF diff --git a/soc/renesas/ra/ra4m3/soc.c b/soc/renesas/ra/ra4m3/soc.c new file mode 100644 index 0000000000000..f62cd1da28cfb --- /dev/null +++ b/soc/renesas/ra/ra4m3/soc.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA4M3 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra4m3_init(void) +{ + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + return 0; +} + +SYS_INIT(renesas_ra4m3_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra4m3/soc.h b/soc/renesas/ra/ra4m3/soc.h new file mode 100644 index 0000000000000..7910a06c96a78 --- /dev/null +++ b/soc/renesas/ra/ra4m3/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA4M3 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4M3_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4M3_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4M3_SOC_H_ */ diff --git a/soc/renesas/ra/ra4w1/CMakeLists.txt b/soc/renesas/ra/ra4w1/CMakeLists.txt new file mode 100644 index 0000000000000..ccc5f9899ae8c --- /dev/null +++ b/soc/renesas/ra/ra4w1/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(ROM_START opt_set_mem.ld) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4w1/Kconfig b/soc/renesas/ra/ra4w1/Kconfig new file mode 100644 index 0000000000000..358633bb8950d --- /dev/null +++ b/soc/renesas/ra/ra4w1/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4W1 + select ARM + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M4 + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra4w1/Kconfig.defconfig b/soc/renesas/ra/ra4w1/Kconfig.defconfig new file mode 100644 index 0000000000000..c73bab8b0975f --- /dev/null +++ b/soc/renesas/ra/ra4w1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4W1 + +config NUM_IRQS + default 32 + +config PINCTRL + default y + +endif # SOC_SERIES_RA4W1 diff --git a/soc/renesas/ra/ra4w1/Kconfig.soc b/soc/renesas/ra/ra4w1/Kconfig.soc new file mode 100644 index 0000000000000..a406dd97eaecc --- /dev/null +++ b/soc/renesas/ra/ra4w1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4W1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4W1 series + +config SOC_R7FA4W1AD2CNG + bool + select SOC_SERIES_RA4W1 + help + R7FA4W1AD2CNG + +config SOC_SERIES + default "ra4w1" if SOC_SERIES_RA4W1 + +config SOC + default "r7fa4w1ad2cng" if SOC_R7FA4W1AD2CNG diff --git a/soc/renesas/ra/ra4w1/opt_set_mem.ld b/soc/renesas/ra/ra4w1/opt_set_mem.ld new file mode 100644 index 0000000000000..07aef9e92d838 --- /dev/null +++ b/soc/renesas/ra/ra4w1/opt_set_mem.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra4w1/sections.ld b/soc/renesas/ra/ra4w1/sections.ld new file mode 100644 index 0000000000000..b850a64f64374 --- /dev/null +++ b/soc/renesas/ra/ra4w1/sections.ld @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra4w1/soc.c b/soc/renesas/ra/ra4w1/soc.c new file mode 100644 index 0000000000000..d3f9b351d24ba --- /dev/null +++ b/soc/renesas/ra/ra4w1/soc.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA4W1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra4w1_init(void) +{ + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + return 0; +} + +SYS_INIT(renesas_ra4w1_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra4w1/soc.h b/soc/renesas/ra/ra4w1/soc.h new file mode 100644 index 0000000000000..7646360c58bbf --- /dev/null +++ b/soc/renesas/ra/ra4w1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA4W1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index cf3c90523bc07..6e7887b098a3c 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -4,9 +4,21 @@ family: - name: ra2a1 socs: - name: r7fa2a1ab3cfm + - name: ra4e2 + socs: + - name: r7fa4e2b93cfm - name: ra4m1 socs: - name: r7fa4m1ab3cfm + - name: ra4m2 + socs: + - name: r7fa4m2ad3cfp + - name: ra4m3 + socs: + - name: r7fa4m3af3cfb + - name: ra4w1 + socs: + - name: r7fa4w1ad2cng - name: ra6m1 socs: - name: r7fa6m1ad3cfp diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay new file mode 100644 index 0000000000000..10121b5ad9ee9 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay new file mode 100644 index 0000000000000..21e0f0f9141cc --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci2_default: sci2_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci2 { + pinctrl-0 = <&sci2_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay new file mode 100644 index 0000000000000..dbef642d32d9e --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay new file mode 100644 index 0000000000000..238c284fa2d9b --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci1_default: sci1_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci1 { + pinctrl-0 = <&sci1_default>; + pinctrl-names = "default"; + status = "okay"; + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +};