diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi index 6a81cec8b7d58..f9fff37eaabfa 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi @@ -64,12 +64,30 @@ clock-frequency = <48000000>; }; -&cgc { - clock-source = <&hoco>; - iclk-div = <1>; - pclka-div = <1>; - pclkb-div = <2>; - pclkc-div = <1>; - pclkd-div = <1>; - fclk-div = <2>; +&pclkblock { + clocks = <&hoco>; +}; + +&iclk { + div = <1>; +}; + +&pclka { + div = <1>; +}; + +&pclkb { + div = <2>; +}; + +&pclkc { + div = <1>; +}; + +&pclkd { + div = <1>; +}; + +&fclk { + div = <2>; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi index c9538829a480b..863d9e6030af4 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { sci2_default: sci2_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig index bcd05338d4445..3c655ea376e89 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig @@ -16,8 +16,6 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y - CONFIG_CLOCK_CONTROL=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi index 093d4e4cdf989..9add47e472363 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { sci2_default: sci2_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig index 76f5a5fb85446..48137e86d7ac2 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig @@ -16,8 +16,6 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y - CONFIG_CLOCK_CONTROL=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts index b15242c5fea89..cd71c38f14c02 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts @@ -6,9 +6,9 @@ /dts-v1/; #include -#include #include #include +#include / { model = "Mikroe Clicker RA4M1"; @@ -52,7 +52,12 @@ &pinctrl { sci0_default: sci0_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + }; + group2 { + /* rx */ + psels = ; }; }; }; @@ -79,17 +84,35 @@ status = "okay"; }; -&mosc { +&xtal { status = "okay"; clock-frequency = <12000000>; }; -&cgc { - clock-source = <&mosc>; - iclk-div = <1>; - pclka-div = <1>; - pclkb-div = <2>; - pclkc-div = <1>; - pclkd-div = <1>; - fclk-div = <2>; +&pclkblock { + clocks = <&xtal>; +}; + +&iclk { + div = <1>; +}; + +&pclka { + div = <1>; +}; + +&pclkb { + div = <2>; +}; + +&pclkc { + div = <1>; +}; + +&pclkd { + div = <1>; +}; + +&fclk { + div = <2>; }; diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 79079867e5dd8..684345729dddf 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -32,7 +32,6 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_control_smartbond.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA clock_control_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index ca4db637014a3..307e01ba81fbb 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -82,8 +82,6 @@ source "drivers/clock_control/Kconfig.nxp_s32" source "drivers/clock_control/Kconfig.agilex5" -source "drivers/clock_control/Kconfig.renesas_ra" - source "drivers/clock_control/Kconfig.renesas_ra_cgc" source "drivers/clock_control/Kconfig.max32" diff --git a/drivers/clock_control/Kconfig.renesas_ra b/drivers/clock_control/Kconfig.renesas_ra deleted file mode 100644 index 5a14f593f9b40..0000000000000 --- a/drivers/clock_control/Kconfig.renesas_ra +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config CLOCK_CONTROL_RENESAS_RA - bool "Renesas RA series clock generation circuit driver" - default y - depends on DT_HAS_RENESAS_RA_CLOCK_GENERATION_CIRCUIT_ENABLED - help - Enable Renesas RA series clock generation circuit driver. diff --git a/drivers/clock_control/clock_control_renesas_ra.c b/drivers/clock_control/clock_control_renesas_ra.c deleted file mode 100644 index 3065c94e785a9..0000000000000 --- a/drivers/clock_control/clock_control_renesas_ra.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#define DT_DRV_COMPAT renesas_ra_clock_generation_circuit - -#include -#include -#include -#include - -#if DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, pll)) -#define SYSCLK_SRC pll -#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, mosc)) -#define SYSCLK_SRC mosc -#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, sosc)) -#define SYSCLK_SRC sosc -#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, hoco)) -#define SYSCLK_SRC hoco -#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, moco)) -#define SYSCLK_SRC moco -#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, loco)) -#define SYSCLK_SRC loco -#else -#error Unknown clock source -#endif - -#define FREQ_iclk (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, iclk_div)) -#define FREQ_pclka (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclka_div)) -#define FREQ_pclkb (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkb_div)) -#define FREQ_pclkc (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkc_div)) -#define FREQ_pclkd (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkd_div)) -#define FREQ_fclk (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, fclk_div)) - -#define CLKSRC_FREQ(clk) DT_PROP(DT_PATH(clocks, clk), clock_frequency) - -#define IS_CLKSRC_ENABLED(clk) DT_NODE_HAS_STATUS_OKAY(DT_PATH(clocks, clk)) - -#define SCKSCR_INIT_VALUE _CONCAT(CLKSRC_, SYSCLK_SRC) - -#define SCKDIV_ENABLED(clk) DT_INST_NODE_HAS_PROP(0, clk##_div) -#define SCKDIV_VAL(clk) _CONCAT(SCKDIV_, DT_INST_PROP(0, clk##_div)) -#define SCKDIV_POS(clk) _CONCAT(SCKDIV_POS_, clk) - -#define SCKDIVCR_BITS(clk) \ - COND_CODE_1(SCKDIV_ENABLED(clk), ((SCKDIV_VAL(clk) & 0xFU) << SCKDIV_POS(clk)), (0U)) - -#define SCKDIVCR_INIT_VALUE \ - (SCKDIVCR_BITS(iclk) | SCKDIVCR_BITS(pclka) | SCKDIVCR_BITS(pclkb) | \ - SCKDIVCR_BITS(pclkc) | SCKDIVCR_BITS(pclkd) | SCKDIVCR_BITS(bclk) | SCKDIVCR_BITS(fclk)) - -#define HOCOWTCR_INIT_VALUE (6) - -/* - * Required cycles for sub-clokc stabilizing. - */ -#define SUBCLK_STABILIZE_CYCLES 5 - -extern int z_clock_hw_cycles_per_sec; - -enum { - CLKSRC_hoco = 0, - CLKSRC_moco, - CLKSRC_loco, - CLKSRC_mosc, - CLKSRC_sosc, - CLKSRC_pll, -}; - -enum { - SCKDIV_1 = 0, - SCKDIV_2, - SCKDIV_4, - SCKDIV_8, - SCKDIV_16, - SCKDIV_32, - SCKDIV_64, - SCKDIV_128, - SCKDIV_3, - SCKDIV_6, - SCKDIV_12 -}; - -enum { - SCKDIV_POS_pclkd = 0x0U, - SCKDIV_POS_pclkc = 0x4U, - SCKDIV_POS_pclkb = 0x8U, - SCKDIV_POS_pclka = 0xcU, - SCKDIV_POS_bclk = 0x10U, - SCKDIV_POS_pclke = 0x14U, - SCKDIV_POS_iclk = 0x18U, - SCKDIV_POS_fclk = 0x1cU -}; - -enum { - OSCSF_HOCOSF_POS = 0, - OSCSF_MOSCSF_POS = 3, - OSCSF_PLLSF_POS = 5, -}; - -enum { - OPCCR_OPCMTSF_POS = 4, -}; - -static const uint32_t PRCR_KEY = 0xA500U; -static const uint32_t PRCR_CLOCKS = 0x1U; -static const uint32_t PRCR_LOW_POWER = 0x2U; - -enum { -#if DT_INST_REG_SIZE_BY_NAME(0, mstp) == 16 - MSTPCRA_OFFSET = -0x4, -#else - MSTPCRA_OFFSET = 0x0, -#endif - MSTPCRB_OFFSET = (MSTPCRA_OFFSET + 0x4), - MSTPCRC_OFFSET = (MSTPCRB_OFFSET + 0x4), - MSTPCRD_OFFSET = (MSTPCRC_OFFSET + 0x4), - MSTPCRE_OFFSET = (MSTPCRD_OFFSET + 0x4), -}; - -enum { - SCKDIVCR_OFFSET = 0x020, - SCKSCR_OFFSET = 0x026, - MEMWAIT_OFFSET = 0x031, - MOSCCR_OFFSET = 0x032, - HOCOCR_OFFSET = 0x036, - OSCSF_OFFSET = 0x03C, - CKOCR_OFFSET = 0x03E, - OPCCR_OFFSET = 0x0A0, - HOCOWTCR_OFFSET = 0x0A5, - PRCR_OFFSET = 0x3FE, - SOSCCR_OFFSET = 0x480, -}; - -enum { - SCRSCK_hoco, - SCRSCK_moco, - SCRSCK_loco, - SCRSCK_mosc, - SCRSCK_sosc, - SCRSCK_pll, -}; - -static const int clock_freqs[] = { - COND_CODE_1(IS_CLKSRC_ENABLED(hoco), (CLKSRC_FREQ(hoco)), (0)), - COND_CODE_1(IS_CLKSRC_ENABLED(moco), (CLKSRC_FREQ(moco)), (0)), - COND_CODE_1(IS_CLKSRC_ENABLED(loco), (CLKSRC_FREQ(loco)), (0)), - COND_CODE_1(IS_CLKSRC_ENABLED(mosc), (CLKSRC_FREQ(mosc)), (0)), - COND_CODE_1(IS_CLKSRC_ENABLED(sosc), (CLKSRC_FREQ(sosc)), (0)), - COND_CODE_1(IS_CLKSRC_ENABLED(pll), - (DT_PROP(DT_PHANDLE_BY_IDX(DT_PATH(clocks, pll), clocks, 0), clock_frequency) * - DT_PROP(DT_PATH(clocks, pll), clock_mult) / - DT_PROP(DT_PATH(clocks, pll), clock_div)), - (0)), -}; - -static uint32_t MSTP_read(size_t offset) -{ - return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, mstp) + offset); -} - -static void MSTP_write(size_t offset, uint32_t value) -{ - sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, mstp) + offset); -} - -static uint8_t SYSTEM_read8(size_t offset) -{ - return sys_read8(DT_INST_REG_ADDR_BY_NAME(0, system) + offset); -} - -static void SYSTEM_write8(size_t offset, uint8_t value) -{ - sys_write8(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset); -} - -static void SYSTEM_write16(size_t offset, uint16_t value) -{ - sys_write16(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset); -} - -static void SYSTEM_write32(size_t offset, uint32_t value) -{ - sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset); -} - -static int clock_control_ra_on(const struct device *dev, clock_control_subsys_t subsys) -{ - uint32_t clkid = (uint32_t)subsys; - int lock = irq_lock(); - - MSTP_write(MSTPCRA_OFFSET + RA_CLOCK_GROUP(clkid), - MSTP_read(MSTPCRB_OFFSET) & ~RA_CLOCK_BIT(clkid)); - irq_unlock(lock); - - return 0; -} - -static int clock_control_ra_off(const struct device *dev, clock_control_subsys_t subsys) -{ - uint32_t clkid = (uint32_t)subsys; - int lock = irq_lock(); - - MSTP_write(MSTPCRA_OFFSET + RA_CLOCK_GROUP(clkid), - MSTP_read(MSTPCRB_OFFSET) | RA_CLOCK_BIT(clkid)); - irq_unlock(lock); - - return 0; -} - -static int clock_control_ra_get_rate(const struct device *dev, clock_control_subsys_t subsys, - uint32_t *rate) -{ - uint32_t clkid = (uint32_t)subsys; - - switch (clkid & 0xFFFFFF00) { - case RA_CLOCK_SCI(0): - *rate = FREQ_pclka; - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct clock_control_driver_api ra_clock_control_driver_api = { - .on = clock_control_ra_on, - .off = clock_control_ra_off, - .get_rate = clock_control_ra_get_rate, -}; - -static void crude_busy_loop_impl(uint32_t cycles) -{ - __asm__ volatile(".align 8\n" - "busy_loop:\n" - " sub r0, r0, #1\n" - " cmp r0, #0\n" - " bne.n busy_loop\n"); -} - -static inline void crude_busy_loop(uint32_t wait_us) -{ - static const uint64_t cycles_per_loop = 4; - - crude_busy_loop_impl(sys_clock_hw_cycles_per_sec() * wait_us / USEC_PER_SEC / - cycles_per_loop); -} - -static int clock_control_ra_init(const struct device *dev) -{ - uint8_t sysclk = SYSTEM_read8(SCKSCR_OFFSET); - - z_clock_hw_cycles_per_sec = clock_freqs[sysclk]; - - SYSTEM_write16(PRCR_OFFSET, PRCR_KEY | PRCR_CLOCKS | PRCR_LOW_POWER); - - if (clock_freqs[SCRSCK_hoco] == 64000000) { - SYSTEM_write8(HOCOWTCR_OFFSET, HOCOWTCR_INIT_VALUE); - } - - SYSTEM_write8(SOSCCR_OFFSET, !IS_CLKSRC_ENABLED(sosc)); - SYSTEM_write8(MOSCCR_OFFSET, !IS_CLKSRC_ENABLED(mosc)); - SYSTEM_write8(HOCOCR_OFFSET, !IS_CLKSRC_ENABLED(hoco)); - - if (IS_CLKSRC_ENABLED(sosc)) { - crude_busy_loop(z_clock_hw_cycles_per_sec / clock_freqs[CLKSRC_sosc] * - SUBCLK_STABILIZE_CYCLES); - } - - if (IS_CLKSRC_ENABLED(mosc)) { - while ((SYSTEM_read8(OSCSF_OFFSET) & BIT(OSCSF_MOSCSF_POS)) != - BIT(OSCSF_MOSCSF_POS)) { - ; - } - } - - if (IS_CLKSRC_ENABLED(hoco)) { - while ((SYSTEM_read8(OSCSF_OFFSET) & BIT(OSCSF_HOCOSF_POS)) != - BIT(OSCSF_HOCOSF_POS)) { - ; - } - } - - SYSTEM_write8(OPCCR_OFFSET, 0); - while ((SYSTEM_read8(OPCCR_OFFSET) & BIT(OPCCR_OPCMTSF_POS)) != 0) { - ; - } - - SYSTEM_write8(MEMWAIT_OFFSET, 1); - - SYSTEM_write32(SCKDIVCR_OFFSET, SCKDIVCR_INIT_VALUE); - SYSTEM_write8(SCKSCR_OFFSET, SCKSCR_INIT_VALUE); - - /* re-read system clock setting and apply to hw_cycles */ - sysclk = SYSTEM_read8(SCKSCR_OFFSET); - z_clock_hw_cycles_per_sec = clock_freqs[sysclk]; - - SYSTEM_write16(PRCR_OFFSET, PRCR_KEY); - - return 0; -} - -DEVICE_DT_INST_DEFINE(0, clock_control_ra_init, NULL, NULL, NULL, PRE_KERNEL_1, - CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &ra_clock_control_driver_api); diff --git a/drivers/gpio/Kconfig.renesas_ra b/drivers/gpio/Kconfig.renesas_ra index bd6f536ee80f1..2f6fb3c38c44e 100644 --- a/drivers/gpio/Kconfig.renesas_ra +++ b/drivers/gpio/Kconfig.renesas_ra @@ -5,6 +5,7 @@ config GPIO_RENESAS_RA bool "Renesas RA Series GPIO driver" default y select GPIO_GET_CONFIG + select PINCTRL depends on DT_HAS_RENESAS_RA_GPIO_ENABLED help Enable Renesas RA series GPIO driver. diff --git a/drivers/gpio/gpio_renesas_ra.c b/drivers/gpio/gpio_renesas_ra.c index 9f4fe59c83b1f..8da6f593e667c 100644 --- a/drivers/gpio/gpio_renesas_ra.c +++ b/drivers/gpio/gpio_renesas_ra.c @@ -144,7 +144,7 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1); const struct gpio_ra_config *config = dev->config; struct gpio_ra_data *data = dev->data; - struct pinctrl_ra_pin pincfg = {0}; + struct ra_pinctrl_soc_pin pincfg = {0}; if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) { /* Pin cannot be configured as input and output */ @@ -155,25 +155,25 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ } if (flags & GPIO_OUTPUT) { - pincfg.config |= BIT(PmnPFS_PDR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos); } if (flags & GPIO_PULL_UP) { - pincfg.config |= BIT(PmnPFS_PCR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos); } if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) { - pincfg.config |= BIT(PmnPFS_NCODR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos); } if (flags & GPIO_INT_ENABLE) { - pincfg.config |= BIT(PmnPFS_ISEL_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos); } - pincfg.config &= ~BIT(PmnPFS_PMR_POS); + pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos); - pincfg.pin = pin; - pincfg.port = config->port; + pincfg.pin_num = pin; + pincfg.port_num = config->port; if (flags & GPIO_INT_ENABLE) { const struct gpio_ra_irq_info *irq_info; @@ -230,7 +230,7 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio { const struct gpio_ra_config *config = dev->config; const struct gpio_ra_irq_info *irq_info; - struct pinctrl_ra_pin pincfg; + struct ra_pinctrl_soc_pin pincfg; ra_isr_handler cb; const void *cbarg; uint32_t intcfg; @@ -239,22 +239,22 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio memset(flags, 0, sizeof(gpio_flags_t)); - err = pinctrl_ra_query_config(config->port, pin, &pincfg); + err = ra_pinctrl_query_config(config->port, pin, &pincfg); if (err < 0) { return err; } - if (pincfg.config & BIT(PmnPFS_PDR_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) { *flags |= GPIO_OUTPUT; } else { *flags |= GPIO_INPUT; } - if (pincfg.config & BIT(PmnPFS_ISEL_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos)) { *flags |= GPIO_INT_ENABLE; } - if (pincfg.config & BIT(PmnPFS_PCR_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) { *flags |= GPIO_PULL_UP; } diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt index f53523415baf9..80e4c95ec14ea 100644 --- a/drivers/pinctrl/renesas/CMakeLists.txt +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -2,7 +2,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) diff --git a/drivers/pinctrl/renesas/ra/Kconfig b/drivers/pinctrl/renesas/ra/Kconfig index 3ca03057982a8..4c0077d3b84f3 100644 --- a/drivers/pinctrl/renesas/ra/Kconfig +++ b/drivers/pinctrl/renesas/ra/Kconfig @@ -2,13 +2,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -config PINCTRL_RENESAS_RA - bool "Renesas RA series pin controller driver" - default y - depends on DT_HAS_RENESAS_RA_PINCTRL_ENABLED - help - Enable Renesas RA series pin controller driver. - config PINCTRL_RENESAS_RA_PFS bool "Renesas RA pinctrl driver" default y diff --git a/drivers/pinctrl/renesas/ra/pinctrl_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c index efaac2f34f740..0f2bc85bd6005 100644 --- a/drivers/pinctrl/renesas/ra/pinctrl_ra.c +++ b/drivers/pinctrl/renesas/ra/pinctrl_ra.c @@ -26,3 +26,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp return 0; } + +int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg) +{ + if (port >= RA_PINCTRL_PORT_NUM || pin >= RA_PINCTRL_PIN_NUM) { + return -EINVAL; + } + + pincfg->port_num = port; + pincfg->pin_num = pin; + + pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS; + return 0; +} diff --git a/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c deleted file mode 100644 index 89f8a41d51982..0000000000000 --- a/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#define DT_DRV_COMPAT renesas_ra_pinctrl - -#define PORT_NUM 15 -#define PIN_NUM 16 - -enum { - PWPR_PFSWE_POS = 6, - PWPR_B0WI_POS = 7, -}; - -static inline uint32_t pinctrl_ra_read_PmnFPS(size_t port, size_t pin) -{ - return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4); -} - -static inline void pinctrl_ra_write_PmnFPS(size_t port, size_t pin, uint32_t value) -{ - sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4); -} - -static inline uint8_t pinctrl_ra_read_PMISC_PWPR(size_t port, size_t pin) -{ - return sys_read8(DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr)); -} - -static inline void pinctrl_ra_write_PMISC_PWPR(uint8_t value) -{ - sys_write8(value, DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr)); -} - -static void pinctrl_ra_configure_pfs(const pinctrl_soc_pin_t *pinc) -{ - pinctrl_soc_pin_t pincfg; - - memcpy(&pincfg, pinc, sizeof(pinctrl_soc_pin_t)); - pincfg.pin = 0; - pincfg.port = 0; - - /* Clear PMR bits before configuring */ - if ((pincfg.config & PmnPFS_PMR_POS)) { - uint32_t val = pinctrl_ra_read_PmnFPS(pinc->port, pinc->pin); - - pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, val & ~(BIT(PmnPFS_PMR_POS))); - pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config & ~PmnPFS_PMR_POS); - } - - pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config); -} - -int pinctrl_ra_query_config(uint32_t port, uint32_t pin, struct pinctrl_ra_pin *const pincfg) -{ - if (port >= PORT_NUM || pin >= PIN_NUM) { - return -EINVAL; - } - - pincfg->config = pinctrl_ra_read_PmnFPS(port, pin); - return 0; -} - -int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) -{ - pinctrl_ra_write_PMISC_PWPR(0); - pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_PFSWE_POS)); - - for (int i = 0; i < pin_cnt; i++) { - pinctrl_ra_configure_pfs(&pins[i]); - } - - pinctrl_ra_write_PMISC_PWPR(0); - pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_B0WI_POS)); - - return 0; -} diff --git a/drivers/serial/uart_renesas_ra.c b/drivers/serial/uart_renesas_ra.c index 81f6c567c84cd..269a26a59f515 100644 --- a/drivers/serial/uart_renesas_ra.c +++ b/drivers/serial/uart_renesas_ra.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -27,7 +28,7 @@ enum { struct uart_ra_cfg { mem_addr_t regs; const struct device *clock_dev; - clock_control_subsys_t clock_id; + const struct clock_control_ra_subsys_cfg clock_id; const struct pinctrl_dev_config *pcfg; #ifdef CONFIG_UART_INTERRUPT_DRIVEN int (*irq_config_func)(const struct device *dev); @@ -389,12 +390,13 @@ static int uart_ra_init(const struct device *dev) return -ENODEV; } - ret = clock_control_on(config->clock_dev, config->clock_id); + ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id); if (ret < 0) { return ret; } - ret = clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_rate); + ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_id, + &data->clk_rate); if (ret < 0) { return ret; } @@ -659,12 +661,13 @@ static const struct uart_driver_api uart_ra_driver_api = { .regs = DT_REG_ADDR(DT_INST_PARENT(n)), \ .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \ .clock_id = \ - (clock_control_subsys_t)DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, id), \ + { \ + .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \ + .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \ + }, \ .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \ - IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ - .irq_config_func = irq_config_func_##n, \ - )) \ - } + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ + (.irq_config_func = irq_config_func_##n,))} #ifdef CONFIG_UART_INTERRUPT_DRIVEN diff --git a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi b/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi index 4836a58a0afe6..8a1702d785afc 100644 --- a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi +++ b/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi @@ -8,5 +8,4 @@ #define RA_SOC_HAS_MSTPCRE 1 #define RA_SOC_MSTPD5_CHANNELS 1 -#include #include diff --git a/dts/arm/renesas/ra/ra-cm4-common.dtsi b/dts/arm/renesas/ra/ra-cm4-common.dtsi index 4ef18141e6c44..8be1fc555618c 100644 --- a/dts/arm/renesas/ra/ra-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra-cm4-common.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { cpus { @@ -21,36 +22,36 @@ }; }; - clocks { - mosc: mosc { - compatible = "fixed-clock"; + clocks: clocks { + xtal: clock-main-osc { + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = <1200000>; status = "disabled"; #clock-cells = <0>; }; - sosc: sosc { - compatible = "fixed-clock"; + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; status = "disabled"; #clock-cells = <0>; }; - hoco: hoco { + hoco: clock-hoco { compatible = "fixed-clock"; clock-frequency = <24000000>; status = "okay"; #clock-cells = <0>; }; - moco: moco { + moco: clock-moco { compatible = "fixed-clock"; clock-frequency = <8000000>; status = "okay"; #clock-cells = <0>; }; - loco: loco { + loco: clock-loco { compatible = "fixed-clock"; clock-frequency = <32768>; status = "okay"; @@ -58,12 +59,14 @@ }; pll: pll { - compatible = "fixed-factor-clock"; - status = "disabled"; - clocks = <&mosc>; - clock-div = <2>; - clock-mult = <8>; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; + + /* PLL */ + clocks = <&xtal>; + div = <2>; + mul = <8 0>; + status = "disabled"; }; }; @@ -82,19 +85,64 @@ #interrupt-cells = <3>; }; - cgc: cgc@4001e000 { - compatible = "renesas,ra-clock-generation-circuit"; - reg = <0x4001e000 0x40 0x40047000 0x10>; - reg-names = "system", "mstp"; - #clock-cells = <1>; + pclkblock: pclkblock@4001e01c { + compatible = "renesas,ra-cgc-pclk-block"; + reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, + <0x40047008 4>; + reg-names = "MSTPA", "MSTPB","MSTPC", + "MSTPD"; + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + clocks = <&moco>; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; - clock-source = <&moco>; - iclk-div = <16>; - pclka-div = <16>; - pclkb-div = <16>; - pclkc-div = <16>; - pclkd-div = <16>; - fclk-div = <16>; + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; }; fcu: flash-controller@4001c000 { @@ -240,7 +288,7 @@ }; pinctrl: pinctrl@40040800 { - compatible = "renesas,ra-pinctrl"; + compatible = "renesas,ra-pinctrl-pfs"; reg = <0x40040800 0x500 0x40040d03 0x1>; reg-names = "pfs", "pmisc_pwpr"; status = "okay"; @@ -256,7 +304,7 @@ , ; interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri"; - clocks = <&cgc RA_CLOCK_SCI(0)>; + clocks = <&pclka MSTPB 31>; #clock-cells = <1>; status = "disabled"; uart { @@ -274,7 +322,7 @@ , ; interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&cgc RA_CLOCK_SCI(1)>; + clocks = <&pclka MSTPB 30>; #clock-cells = <1>; status = "disabled"; uart { @@ -292,7 +340,7 @@ , ; interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&cgc RA_CLOCK_SCI(9)>; + clocks = <&pclka MSTPB 22>; #clock-cells = <1>; status = "disabled"; uart { diff --git a/dts/arm/renesas/ra/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4-cm4-common.dtsi index 1d2397f85dec1..e49b9bc766e2d 100644 --- a/dts/arm/renesas/ra/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4-cm4-common.dtsi @@ -53,7 +53,7 @@ , ; interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&cgc RA_CLOCK_SCI(2)>; + clocks = <&pclka MSTPB 29>; #clock-cells = <1>; status = "disabled"; uart { diff --git a/dts/bindings/clock/renesas,ra-clock-generation-circuit.yaml b/dts/bindings/clock/renesas,ra-clock-generation-circuit.yaml deleted file mode 100644 index 2769a02ce2dfb..0000000000000 --- a/dts/bindings/clock/renesas,ra-clock-generation-circuit.yaml +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -description: Renesas RA series Clock Generation Circuit - -compatible: "renesas,ra-clock-generation-circuit" - -include: [clock-controller.yaml, base.yaml] - -properties: - reg: - required: true - - iclk-div: - type: int - description: Division factor for ICLK - - fclk-div: - type: int - description: Division factor for FCLK - - pclka-div: - type: int - description: Division factor for PCLKA - - pclkb-div: - type: int - description: Division factor for PCLKB - - pclkc-div: - type: int - description: Division factor for PCLKC - - pclkd-div: - type: int - description: Division factor for PCLKD - - clock-source: - type: phandle - description: System clock source - - "#clock-cells": - const: 1 - -clock-cells: - - id diff --git a/dts/bindings/pinctrl/renesas,ra-pinctrl.yaml b/dts/bindings/pinctrl/renesas,ra-pinctrl.yaml deleted file mode 100644 index 6a48dedf37e77..0000000000000 --- a/dts/bindings/pinctrl/renesas,ra-pinctrl.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -description: | - Renesas RA series pin controller - -compatible: "renesas,ra-pinctrl" - -include: base.yaml - -child-binding: - description: | - Definitions for a pinctrl state. - child-binding: - - properties: - pinmux: - required: true - type: array - description: | - An array of pins sharing the same group properties. Each - element of the array is an integer constructed from the - pin number and the alternative function of the pin. diff --git a/include/zephyr/dt-bindings/clock/renesas-ra-cgc.h b/include/zephyr/dt-bindings/clock/renesas-ra-cgc.h deleted file mode 100644 index 31bb65ecc4593..0000000000000 --- a/include/zephyr/dt-bindings/clock/renesas-ra-cgc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ -#define ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ - -#define RA_CLOCK(grp, func, ch) ((grp << 28) | (func << 20) | ch) - -#define RA_CLOCK_GROUP(mod) (((mod >> 28) & 0xF) * 4) -#define RA_CLOCK_BIT(mod) BIT(((mod >> 20) & 0xFF) - ((mod >> 0) & 0xF)) - -#define RA_CLOCK_DMAC(channel) RA_CLOCK(0, 22, channel) -#define RA_CLOCK_DTC(channel) RA_CLOCK(0, 22, channel) -#define RA_CLOCK_CAN(channel) RA_CLOCK(1, 2, channel) -#define RA_CLOCK_CEC(channel) RA_CLOCK(1, 3U, channel) -#define RA_CLOCK_I3C(channel) RA_CLOCK(1, 4U, channel) -#define RA_CLOCK_IRDA(channel) RA_CLOCK(1, 5U, channel) -#define RA_CLOCK_QSPI(channel) RA_CLOCK(1, 6U, channel) -#define RA_CLOCK_IIC(channel) RA_CLOCK(1, 9U, channel) -#define RA_CLOCK_USBFS(channel) RA_CLOCK(1, 11U, channel) -#define RA_CLOCK_USBHS(channel) RA_CLOCK(1, 12U, channel) -#define RA_CLOCK_EPTPC(channel) RA_CLOCK(1, 13U, channel) -#define RA_CLOCK_ETHER(channel) RA_CLOCK(1, 15U, channel) -#define RA_CLOCK_OSPI(channel) RA_CLOCK(1, 16U, channel) -#define RA_CLOCK_SPI(channel) RA_CLOCK(1, 19U, channel) -#define RA_CLOCK_SCI(channel) RA_CLOCK(1, 31U, channel) -#define RA_CLOCK_CAC(channel) RA_CLOCK(2, 0U, channel) -#define RA_CLOCK_CRC(channel) RA_CLOCK(2, 1U, channel) -#define RA_CLOCK_PDC(channel) RA_CLOCK(2, 2U, channel) -#define RA_CLOCK_CTSU(channel) RA_CLOCK(2, 3U, channel) -#define RA_CLOCK_SLCDC(channel) RA_CLOCK(2, 4U, channel) -#define RA_CLOCK_GLCDC(channel) RA_CLOCK(2, 4U, channel) -#define RA_CLOCK_JPEG(channel) RA_CLOCK(2, 5U, channel) -#define RA_CLOCK_DRW(channel) RA_CLOCK(2, 6U, channel) -#define RA_CLOCK_SSI(channel) RA_CLOCK(2, 8U, channel) -#define RA_CLOCK_SRC(channel) RA_CLOCK(2, 9U, channel) -#define RA_CLOCK_SDHIMMC(channel) RA_CLOCK(2, 12U, channel) -#define RA_CLOCK_DOC(channel) RA_CLOCK(2, 13U, channel) -#define RA_CLOCK_ELC(channel) RA_CLOCK(2, 14U, channel) -#define RA_CLOCK_CEU(channel) RA_CLOCK(2, 16U, channel) -#define RA_CLOCK_TFU(channel) RA_CLOCK(2, 20U, channel) -#define RA_CLOCK_IIRFA(channel) RA_CLOCK(2, 21U, channel) -#define RA_CLOCK_CANFD(channel) RA_CLOCK(2, 27U, channel) -#define RA_CLOCK_TRNG(channel) RA_CLOCK(2, 28U, channel) -#define RA_CLOCK_SCE(channel) RA_CLOCK(2, 31U, channel) -#define RA_CLOCK_AES(channel) RA_CLOCK(2, 31U, channel) -#define RA_CLOCK_POEG(channel) RA_CLOCK(3, 14U, channel) -#define RA_CLOCK_ADC(channel) RA_CLOCK(3, 16U, channel) -#define RA_CLOCK_SDADC(channel) RA_CLOCK(3, 17U, channel) -#define RA_CLOCK_DAC8(channel) RA_CLOCK(3, 19U, channel) -#define RA_CLOCK_DAC(channel) RA_CLOCK(3, 20U, channel) -#define RA_CLOCK_TSN(channel) RA_CLOCK(3, 22U, channel) -#define RA_CLOCK_ACMPHS(channel) RA_CLOCK(3, 28U, channel) -#define RA_CLOCK_ACMPLP(channel) RA_CLOCK(3, 29U, channel) -#define RA_CLOCK_OPAMP(channel) RA_CLOCK(3, 31U, channel) -#define RA_CLOCK_AGT(channel) RA_CLOCK(4, 3U, channel) -#define RA_CLOCK_KEY(channel) RA_CLOCK(4, 4U, channel) -#define RA_CLOCK_ULPT(channel) RA_CLOCK(4, 9U, channel) -#define RA_CLOCK_GPT(channel) RA_CLOCK(5, 31U, channel) - -#endif /* ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r7fa4m1xxxxxx.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r7fa4m1xxxxxx.h deleted file mode 100644 index e54667576533d..0000000000000 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r7fa4m1xxxxxx.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R7FA4M1XXXXXX_H_ -#define ZEPHYR_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R7FA4M1XXXXXX_H_ - -#include - -#define P000_AMP0P RA_PINCFG__40(0, 0, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P000_AN000 RA_PINCFG__40(0, 0, 0x01, RA_PINCFG_ANALOG) -#define P000_TS21 RA_PINCFG__40(0, 0, 0x0C, RA_PINCFG_FUNC) -#define P001_AMP0M RA_PINCFG__40(0, 1, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P001_AN001 RA_PINCFG__40(0, 1, 0x01, RA_PINCFG_ANALOG) -#define P001_TS22 RA_PINCFG__40(0, 1, 0x0C, RA_PINCFG_FUNC) -#define P002_AMP0O RA_PINCFG__48(0, 2, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P002_AN002 RA_PINCFG__48(0, 2, 0x01, RA_PINCFG_ANALOG) -#define P003_AMP1O RA_PINCFG__64(0, 3, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P003_AN003 RA_PINCFG__64(0, 3, 0x01, RA_PINCFG_ANALOG) -#define P004_AMP2O RA_PINCFG__64(0, 4, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P004_AN004 RA_PINCFG__64(0, 4, 0x01, RA_PINCFG_ANALOG) -#define P005_AMP3P RA_PINCFG_100(0, 5, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P005_AN011 RA_PINCFG_100(0, 5, 0x01, RA_PINCFG_ANALOG) -#define P006_AMP3M RA_PINCFG_100(0, 6, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P006_AN012 RA_PINCFG_100(0, 6, 0x01, RA_PINCFG_ANALOG) -#define P007_AMP3O RA_PINCFG_100(0, 7, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P007_AN013 RA_PINCFG_100(0, 7, 0x01, RA_PINCFG_ANALOG) -#define P008_AN014 RA_PINCFG_100(0, 8, 0x01, RA_PINCFG_ANALOG) -#define P010_AMP2M RA_PINCFG__40(0, 10, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P010_AN005 RA_PINCFG__40(0, 10, 0x01, RA_PINCFG_ANALOG) -#define P010_TS30 RA_PINCFG__40(0, 10, 0x0C, RA_PINCFG_FUNC) -#define P010_VREFH0 RA_PINCFG__40(0, 10, 0x03, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P011_AN006 RA_PINCFG__40(0, 11, 0x01, RA_PINCFG_ANALOG) -#define P011_TS31 RA_PINCFG__40(0, 11, 0x0C, RA_PINCFG_FUNC) -#define P011_VREFL0 RA_PINCFG__40(0, 11, 0x03, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P012_AN007 RA_PINCFG__40(0, 12, 0x01, RA_PINCFG_ANALOG) -#define P012_VREFH RA_PINCFG__40(0, 12, 0x03, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P013_AN008 RA_PINCFG__40(0, 13, 0x01, RA_PINCFG_ANALOG) -#define P013_VREFL RA_PINCFG__40(0, 13, 0x03, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P014_AN009 RA_PINCFG__40(0, 14, 0x01, RA_PINCFG_ANALOG) -#define P014_DA0 RA_PINCFG__40(0, 14, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P015_AN010 RA_PINCFG__40(0, 15, 0x01, RA_PINCFG_ANALOG) -#define P015_TS28 RA_PINCFG__40(0, 15, 0x0C, RA_PINCFG_FUNC) -#define P100_AGTIO0 RA_PINCFG__40(1, 0, 0x01, RA_PINCFG_FUNC) -#define P100_AN022 RA_PINCFG__40(1, 0, 0x01, RA_PINCFG_ANALOG) -#define P100_CMPIN0 RA_PINCFG__40(1, 0, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P100_GTETRGA RA_PINCFG__40(1, 0, 0x02, RA_PINCFG_FUNC) -#define P100_GTIOC5B RA_PINCFG__40(1, 0, 0x03, RA_PINCFG_FUNC) -#define P100_KR00 RA_PINCFG__40(1, 0, 0x08, RA_PINCFG_FUNC) -#define P100_MISO0 RA_PINCFG__40(1, 0, 0x04, RA_PINCFG_FUNC) -#define P100_MISOA RA_PINCFG__40(1, 0, 0x06, RA_PINCFG_FUNC) -#define P100_RXD0 RA_PINCFG__40(1, 0, 0x04, RA_PINCFG_FUNC) -#define P100_SCK1 RA_PINCFG__40(1, 0, 0x05, RA_PINCFG_FUNC) -#define P100_SCL0 RA_PINCFG__40(1, 0, 0x04, RA_PINCFG_FUNC) -#define P100_SCL1 RA_PINCFG__40(1, 0, 0x07, RA_PINCFG_FUNC) -#define P100_VL1 RA_PINCFG__40(1, 0, 0x0D, RA_PINCFG_FUNC) -#define P101_AGTEE0 RA_PINCFG__40(1, 1, 0x01, RA_PINCFG_FUNC) -#define P101_AN021 RA_PINCFG__40(1, 1, 0x01, RA_PINCFG_ANALOG) -#define P101_CMPREF0 RA_PINCFG__40(1, 1, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P101_CTS1_RTS1 RA_PINCFG__40(1, 1, 0x05, RA_PINCFG_FUNC) -#define P101_GTETRGB RA_PINCFG__40(1, 1, 0x02, RA_PINCFG_FUNC) -#define P101_GTIOC5A RA_PINCFG__40(1, 1, 0x03, RA_PINCFG_FUNC) -#define P101_KR01 RA_PINCFG__40(1, 1, 0x08, RA_PINCFG_FUNC) -#define P101_MOSI0 RA_PINCFG__40(1, 1, 0x04, RA_PINCFG_FUNC) -#define P101_MOSIA RA_PINCFG__40(1, 1, 0x06, RA_PINCFG_FUNC) -#define P101_SDA0 RA_PINCFG__40(1, 1, 0x04, RA_PINCFG_FUNC) -#define P101_SDA1 RA_PINCFG__40(1, 1, 0x07, RA_PINCFG_FUNC) -#define P101_SS1 RA_PINCFG__40(1, 1, 0x05, RA_PINCFG_FUNC) -#define P101_TXD0 RA_PINCFG__40(1, 1, 0x04, RA_PINCFG_FUNC) -#define P101_VL2 RA_PINCFG__40(1, 1, 0x0D, RA_PINCFG_FUNC) -#define P102_ADTRG0 RA_PINCFG__40(1, 2, 0x0A, RA_PINCFG_FUNC) -#define P102_AGTO0 RA_PINCFG__40(1, 2, 0x01, RA_PINCFG_FUNC) -#define P102_AN020 RA_PINCFG__40(1, 2, 0x01, RA_PINCFG_ANALOG) -#define P102_CMPIN1 RA_PINCFG__40(1, 2, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P102_CRX0 RA_PINCFG__40(1, 2, 0x10, RA_PINCFG_FUNC) -#define P102_GTIOC2B RA_PINCFG__40(1, 2, 0x03, RA_PINCFG_FUNC) -#define P102_GTOWLO RA_PINCFG__40(1, 2, 0x02, RA_PINCFG_FUNC) -#define P102_KR02 RA_PINCFG__40(1, 2, 0x08, RA_PINCFG_FUNC) -#define P102_MOSI2 RA_PINCFG__40(1, 2, 0x05, RA_PINCFG_FUNC) -#define P102_RSPCKA RA_PINCFG__40(1, 2, 0x06, RA_PINCFG_FUNC) -#define P102_SCK0 RA_PINCFG__40(1, 2, 0x04, RA_PINCFG_FUNC) -#define P102_SDA2 RA_PINCFG__40(1, 2, 0x05, RA_PINCFG_FUNC) -#define P102_TXD2 RA_PINCFG__40(1, 2, 0x05, RA_PINCFG_FUNC) -#define P102_VL3 RA_PINCFG__40(1, 2, 0x0D, RA_PINCFG_FUNC) -#define P103_AN019 RA_PINCFG__48(1, 3, 0x01, RA_PINCFG_ANALOG) -#define P103_CMPREF1 RA_PINCFG__48(1, 3, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P103_CTS0_RTS0 RA_PINCFG__48(1, 3, 0x04, RA_PINCFG_FUNC) -#define P103_CTX0 RA_PINCFG__48(1, 3, 0x10, RA_PINCFG_FUNC) -#define P103_GTIOC2A RA_PINCFG__48(1, 3, 0x03, RA_PINCFG_FUNC) -#define P103_GTOWUP RA_PINCFG__48(1, 3, 0x02, RA_PINCFG_FUNC) -#define P103_KR03 RA_PINCFG__48(1, 3, 0x08, RA_PINCFG_FUNC) -#define P103_SS0 RA_PINCFG__48(1, 3, 0x04, RA_PINCFG_FUNC) -#define P103_SSLA0 RA_PINCFG__48(1, 3, 0x06, RA_PINCFG_FUNC) -#define P103_VL4 RA_PINCFG__48(1, 3, 0x0D, RA_PINCFG_FUNC) -#define P104_COM0 RA_PINCFG__48(1, 4, 0x0D, RA_PINCFG_FUNC) -#define P104_GTETRGB RA_PINCFG__48(1, 4, 0x02, RA_PINCFG_FUNC) -#define P104_GTIOC1B RA_PINCFG__48(1, 4, 0x03, RA_PINCFG_FUNC) -#define P104_KR04 RA_PINCFG__48(1, 4, 0x08, RA_PINCFG_FUNC) -#define P104_MISO0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC) -#define P104_RXD0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC) -#define P104_SCL0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC) -#define P104_SSLA1 RA_PINCFG__48(1, 4, 0x06, RA_PINCFG_FUNC) -#define P104_TS13 RA_PINCFG__48(1, 4, 0x0C, RA_PINCFG_FUNC) -#define P105_COM1 RA_PINCFG__64(1, 5, 0x0D, RA_PINCFG_FUNC) -#define P105_GTETRGA RA_PINCFG__64(1, 5, 0x02, RA_PINCFG_FUNC) -#define P105_GTIOC1A RA_PINCFG__64(1, 5, 0x03, RA_PINCFG_FUNC) -#define P105_KR05 RA_PINCFG__64(1, 5, 0x08, RA_PINCFG_FUNC) -#define P105_SSLA2 RA_PINCFG__64(1, 5, 0x06, RA_PINCFG_FUNC) -#define P105_TS34 RA_PINCFG__64(1, 5, 0x0C, RA_PINCFG_FUNC) -#define P106_COM2 RA_PINCFG__64(1, 6, 0x0D, RA_PINCFG_FUNC) -#define P106_GTIOC0B RA_PINCFG__64(1, 6, 0x03, RA_PINCFG_FUNC) -#define P106_KR06 RA_PINCFG__64(1, 6, 0x08, RA_PINCFG_FUNC) -#define P106_SSLA3 RA_PINCFG__64(1, 6, 0x06, RA_PINCFG_FUNC) -#define P107_COM3 RA_PINCFG__64(1, 7, 0x0D, RA_PINCFG_FUNC) -#define P107_GTIOC0A RA_PINCFG__64(1, 7, 0x03, RA_PINCFG_FUNC) -#define P107_KR07 RA_PINCFG__64(1, 7, 0x08, RA_PINCFG_FUNC) -#define P108_CTS9_RTS9 RA_PINCFG__40(1, 8, 0x05, RA_PINCFG_FUNC) -#define P108_GTIOC0B RA_PINCFG__40(1, 8, 0x03, RA_PINCFG_FUNC) -#define P108_GTOULO RA_PINCFG__40(1, 8, 0x02, RA_PINCFG_FUNC) -#define P108_SS9 RA_PINCFG__40(1, 8, 0x05, RA_PINCFG_FUNC) -#define P108_SSLB0 RA_PINCFG__40(1, 8, 0x06, RA_PINCFG_FUNC) -#define P109_CLKOUT RA_PINCFG__40(1, 9, 0x09, RA_PINCFG_FUNC) -#define P109_CTX0 RA_PINCFG__40(1, 9, 0x10, RA_PINCFG_FUNC) -#define P109_GTIOC1A RA_PINCFG__40(1, 9, 0x03, RA_PINCFG_FUNC) -#define P109_GTOVUP RA_PINCFG__40(1, 9, 0x02, RA_PINCFG_FUNC) -#define P109_MOSI9 RA_PINCFG__40(1, 9, 0x05, RA_PINCFG_FUNC) -#define P109_MOSIB RA_PINCFG__40(1, 9, 0x06, RA_PINCFG_FUNC) -#define P109_SCK1 RA_PINCFG__40(1, 9, 0x04, RA_PINCFG_FUNC) -#define P109_SDA9 RA_PINCFG__40(1, 9, 0x05, RA_PINCFG_FUNC) -#define P109_SEG23 RA_PINCFG__40(1, 9, 0x0D, RA_PINCFG_FUNC) -#define P109_TS10 RA_PINCFG__40(1, 9, 0x0C, RA_PINCFG_FUNC) -#define P109_TXD9 RA_PINCFG__40(1, 9, 0x05, RA_PINCFG_FUNC) -#define P110_CRX0 RA_PINCFG__40(1, 10, 0x10, RA_PINCFG_FUNC) -#define P110_CTS2_RTS2 RA_PINCFG__40(1, 10, 0x04, RA_PINCFG_FUNC) -#define P110_GTIOC1B RA_PINCFG__40(1, 10, 0x03, RA_PINCFG_FUNC) -#define P110_GTOVLO RA_PINCFG__40(1, 10, 0x02, RA_PINCFG_FUNC) -#define P110_MISO9 RA_PINCFG__40(1, 10, 0x05, RA_PINCFG_FUNC) -#define P110_MISOB RA_PINCFG__40(1, 10, 0x06, RA_PINCFG_FUNC) -#define P110_RXD9 RA_PINCFG__40(1, 10, 0x05, RA_PINCFG_FUNC) -#define P110_SCL9 RA_PINCFG__40(1, 10, 0x05, RA_PINCFG_FUNC) -#define P110_SEG24 RA_PINCFG__40(1, 10, 0x0D, RA_PINCFG_FUNC) -#define P110_SS2 RA_PINCFG__40(1, 10, 0x04, RA_PINCFG_FUNC) -#define P110_VCOUT RA_PINCFG__40(1, 10, 0x09, RA_PINCFG_FUNC) -#define P111_CAPH RA_PINCFG__40(1, 11, 0x0D, RA_PINCFG_FUNC) -#define P111_GTIOC3A RA_PINCFG__40(1, 11, 0x03, RA_PINCFG_FUNC) -#define P111_RSPCKB RA_PINCFG__40(1, 11, 0x06, RA_PINCFG_FUNC) -#define P111_SCK2 RA_PINCFG__40(1, 11, 0x04, RA_PINCFG_FUNC) -#define P111_SCK9 RA_PINCFG__40(1, 11, 0x05, RA_PINCFG_FUNC) -#define P111_TS12 RA_PINCFG__40(1, 11, 0x0C, RA_PINCFG_FUNC) -#define P112_CAPL RA_PINCFG__40(1, 12, 0x0D, RA_PINCFG_FUNC) -#define P112_GTIOC3B RA_PINCFG__40(1, 12, 0x03, RA_PINCFG_FUNC) -#define P112_MOSI2 RA_PINCFG__40(1, 12, 0x04, RA_PINCFG_FUNC) -#define P112_SCK1 RA_PINCFG__40(1, 12, 0x05, RA_PINCFG_FUNC) -#define P112_SDA2 RA_PINCFG__40(1, 12, 0x04, RA_PINCFG_FUNC) -#define P112_SSIBCK0 RA_PINCFG__40(1, 12, 0x12, RA_PINCFG_FUNC) -#define P112_SSLB0 RA_PINCFG__40(1, 12, 0x06, RA_PINCFG_FUNC) -#define P112_TSCAP RA_PINCFG__40(1, 12, 0x0C, RA_PINCFG_FUNC) -#define P112_TXD2 RA_PINCFG__40(1, 12, 0x04, RA_PINCFG_FUNC) -#define P113_GTIOC2A RA_PINCFG__64(1, 13, 0x03, RA_PINCFG_FUNC) -#define P113_SEG00COM4 RA_PINCFG__64(1, 13, 0x0D, RA_PINCFG_FUNC) -#define P113_SSIFS0 RA_PINCFG__64(1, 13, 0x12, RA_PINCFG_FUNC) -#define P113_SSILRCK0 RA_PINCFG__64(1, 13, 0x12, RA_PINCFG_FUNC) -#define P113_TS27 RA_PINCFG__64(1, 13, 0x0C, RA_PINCFG_FUNC) -#define P114_GTIOC2B RA_PINCFG_100(1, 14, 0x03, RA_PINCFG_FUNC) -#define P114_SEG25 RA_PINCFG_100(1, 14, 0x0D, RA_PINCFG_FUNC) -#define P114_SSIRXD0 RA_PINCFG_100(1, 14, 0x12, RA_PINCFG_FUNC) -#define P114_TS29 RA_PINCFG_100(1, 14, 0x0C, RA_PINCFG_FUNC) -#define P115_GTIOC4A RA_PINCFG_100(1, 15, 0x03, RA_PINCFG_FUNC) -#define P115_SEG26 RA_PINCFG_100(1, 15, 0x0D, RA_PINCFG_FUNC) -#define P115_SSITXD0 RA_PINCFG_100(1, 15, 0x12, RA_PINCFG_FUNC) -#define P115_TS35 RA_PINCFG_100(1, 15, 0x0C, RA_PINCFG_FUNC) -#define P202_GTIOC5B RA_PINCFG_100(2, 2, 0x03, RA_PINCFG_FUNC) -#define P202_MISO9 RA_PINCFG_100(2, 2, 0x05, RA_PINCFG_FUNC) -#define P202_MISOB RA_PINCFG_100(2, 2, 0x06, RA_PINCFG_FUNC) -#define P202_RXD9 RA_PINCFG_100(2, 2, 0x05, RA_PINCFG_FUNC) -#define P202_SCK2 RA_PINCFG_100(2, 2, 0x04, RA_PINCFG_FUNC) -#define P202_SCL9 RA_PINCFG_100(2, 2, 0x05, RA_PINCFG_FUNC) -#define P202_SEG16 RA_PINCFG_100(2, 2, 0x0D, RA_PINCFG_FUNC) -#define P203_CTS2_RTS2 RA_PINCFG_100(2, 3, 0x04, RA_PINCFG_FUNC) -#define P203_GTIOC5A RA_PINCFG_100(2, 3, 0x03, RA_PINCFG_FUNC) -#define P203_MOSI9 RA_PINCFG_100(2, 3, 0x05, RA_PINCFG_FUNC) -#define P203_MOSIB RA_PINCFG_100(2, 3, 0x06, RA_PINCFG_FUNC) -#define P203_SDA9 RA_PINCFG_100(2, 3, 0x05, RA_PINCFG_FUNC) -#define P203_SEG15 RA_PINCFG_100(2, 3, 0x0D, RA_PINCFG_FUNC) -#define P203_SS2 RA_PINCFG_100(2, 3, 0x04, RA_PINCFG_FUNC) -#define P203_TSCAP RA_PINCFG_100(2, 3, 0x0C, RA_PINCFG_FUNC) -#define P203_TXD9 RA_PINCFG_100(2, 3, 0x05, RA_PINCFG_FUNC) -#define P204_AGTIO1 RA_PINCFG__64(2, 4, 0x01, RA_PINCFG_FUNC) -#define P204_CACREF RA_PINCFG__64(2, 4, 0x0A, RA_PINCFG_FUNC) -#define P204_GTIOC4B RA_PINCFG__64(2, 4, 0x03, RA_PINCFG_FUNC) -#define P204_GTIW RA_PINCFG__64(2, 4, 0x02, RA_PINCFG_FUNC) -#define P204_RSPCKB RA_PINCFG__64(2, 4, 0x06, RA_PINCFG_FUNC) -#define P204_SCK0 RA_PINCFG__64(2, 4, 0x04, RA_PINCFG_FUNC) -#define P204_SCK9 RA_PINCFG__64(2, 4, 0x05, RA_PINCFG_FUNC) -#define P204_SCL0 RA_PINCFG__64(2, 4, 0x07, RA_PINCFG_FUNC) -#define P204_SEG14 RA_PINCFG__64(2, 4, 0x0D, RA_PINCFG_FUNC) -#define P204_TS00 RA_PINCFG__64(2, 4, 0x0C, RA_PINCFG_FUNC) -#define P204_USB_OVRCUR_B RA_PINCFG__64(2, 4, 0x13, RA_PINCFG_FUNC) -#define P205_AGTO1 RA_PINCFG__64(2, 5, 0x01, RA_PINCFG_FUNC) -#define P205_CLKOUT RA_PINCFG__64(2, 5, 0x09, RA_PINCFG_FUNC) -#define P205_CTS9_RTS9 RA_PINCFG__64(2, 5, 0x05, RA_PINCFG_FUNC) -#define P205_GTIOC4A RA_PINCFG__64(2, 5, 0x03, RA_PINCFG_FUNC) -#define P205_GTIV RA_PINCFG__64(2, 5, 0x02, RA_PINCFG_FUNC) -#define P205_MOSI0 RA_PINCFG__64(2, 5, 0x04, RA_PINCFG_FUNC) -#define P205_SCL1 RA_PINCFG__64(2, 5, 0x07, RA_PINCFG_FUNC) -#define P205_SDA0 RA_PINCFG__64(2, 5, 0x04, RA_PINCFG_FUNC) -#define P205_SEG13 RA_PINCFG__64(2, 5, 0x0D, RA_PINCFG_FUNC) -#define P205_SS9 RA_PINCFG__64(2, 5, 0x05, RA_PINCFG_FUNC) -#define P205_SSLB0 RA_PINCFG__64(2, 5, 0x06, RA_PINCFG_FUNC) -#define P205_TSCAP RA_PINCFG__64(2, 5, 0x0C, RA_PINCFG_FUNC) -#define P205_TXD0 RA_PINCFG__64(2, 5, 0x04, RA_PINCFG_FUNC) -#define P205_USB_OVRCUR_A RA_PINCFG__64(2, 5, 0x13, RA_PINCFG_FUNC) -#define P206_GTIU RA_PINCFG__48(2, 6, 0x02, RA_PINCFG_FUNC) -#define P206_MISO0 RA_PINCFG__48(2, 6, 0x04, RA_PINCFG_FUNC) -#define P206_RXD0 RA_PINCFG__48(2, 6, 0x04, RA_PINCFG_FUNC) -#define P206_SCL0 RA_PINCFG__48(2, 6, 0x04, RA_PINCFG_FUNC) -#define P206_SDA1 RA_PINCFG__48(2, 6, 0x07, RA_PINCFG_FUNC) -#define P206_SEG12 RA_PINCFG__48(2, 6, 0x0D, RA_PINCFG_FUNC) -#define P206_SSLB1 RA_PINCFG__48(2, 6, 0x06, RA_PINCFG_FUNC) -#define P206_TS01 RA_PINCFG__48(2, 6, 0x0C, RA_PINCFG_FUNC) -#define P206_USB_VBUSEN RA_PINCFG__48(2, 6, 0x13, RA_PINCFG_FUNC) -#define P212_AGTEE1 RA_PINCFG__40(2, 12, 0x01, RA_PINCFG_FUNC) -#define P212_GTETRGB RA_PINCFG__40(2, 12, 0x02, RA_PINCFG_FUNC) -#define P212_GTIOC0B RA_PINCFG__40(2, 12, 0x03, RA_PINCFG_FUNC) -#define P212_MISO1 RA_PINCFG__40(2, 12, 0x05, RA_PINCFG_FUNC) -#define P212_RXD1 RA_PINCFG__40(2, 12, 0x05, RA_PINCFG_FUNC) -#define P212_SCL1 RA_PINCFG__40(2, 12, 0x05, RA_PINCFG_FUNC) -#define P213_GTETRGA RA_PINCFG__40(2, 13, 0x02, RA_PINCFG_FUNC) -#define P213_GTIOC0A RA_PINCFG__40(2, 13, 0x03, RA_PINCFG_FUNC) -#define P213_MOSI1 RA_PINCFG__40(2, 13, 0x05, RA_PINCFG_FUNC) -#define P213_SDA1 RA_PINCFG__40(2, 13, 0x05, RA_PINCFG_FUNC) -#define P213_TXD1 RA_PINCFG__40(2, 13, 0x05, RA_PINCFG_FUNC) -#define P300_GTIOC0A RA_PINCFG__40(3, 0, 0x03, RA_PINCFG_FUNC) -#define P300_GTOUUP RA_PINCFG__40(3, 0, 0x02, RA_PINCFG_FUNC) -#define P300_SSLB1 RA_PINCFG__40(3, 0, 0x06, RA_PINCFG_FUNC) -#define P301_AGTIO0 RA_PINCFG__40(3, 1, 0x01, RA_PINCFG_FUNC) -#define P301_COM5 RA_PINCFG__40(3, 1, 0x10, RA_PINCFG_FUNC) -#define P301_CTS9_RTS9 RA_PINCFG__40(3, 1, 0x05, RA_PINCFG_FUNC) -#define P301_GTIOC4B RA_PINCFG__40(3, 1, 0x03, RA_PINCFG_FUNC) -#define P301_GTOULO RA_PINCFG__40(3, 1, 0x02, RA_PINCFG_FUNC) -#define P301_MISO2 RA_PINCFG__40(3, 1, 0x04, RA_PINCFG_FUNC) -#define P301_RXD2 RA_PINCFG__40(3, 1, 0x04, RA_PINCFG_FUNC) -#define P301_SCL2 RA_PINCFG__40(3, 1, 0x04, RA_PINCFG_FUNC) -#define P301_SEG01 RA_PINCFG__40(3, 1, 0x0D, RA_PINCFG_FUNC) -#define P301_SS9 RA_PINCFG__40(3, 1, 0x05, RA_PINCFG_FUNC) -#define P301_SSLB2 RA_PINCFG__40(3, 1, 0x06, RA_PINCFG_FUNC) -#define P301_TS09 RA_PINCFG__40(3, 1, 0x0C, RA_PINCFG_FUNC) -#define P302_COM6 RA_PINCFG__48(3, 2, 0x10, RA_PINCFG_FUNC) -#define P302_GTIOC4A RA_PINCFG__48(3, 2, 0x03, RA_PINCFG_FUNC) -#define P302_GTOUUP RA_PINCFG__48(3, 2, 0x02, RA_PINCFG_FUNC) -#define P302_MOSI2 RA_PINCFG__48(3, 2, 0x04, RA_PINCFG_FUNC) -#define P302_SDA2 RA_PINCFG__48(3, 2, 0x04, RA_PINCFG_FUNC) -#define P302_SEG02 RA_PINCFG__48(3, 2, 0x0D, RA_PINCFG_FUNC) -#define P302_SSLB3 RA_PINCFG__48(3, 2, 0x06, RA_PINCFG_FUNC) -#define P302_TS08 RA_PINCFG__48(3, 2, 0x0C, RA_PINCFG_FUNC) -#define P302_TXD2 RA_PINCFG__48(3, 2, 0x04, RA_PINCFG_FUNC) -#define P303_COM7 RA_PINCFG__64(3, 3, 0x10, RA_PINCFG_FUNC) -#define P303_GTIOC7B RA_PINCFG__64(3, 3, 0x03, RA_PINCFG_FUNC) -#define P303_SEG03 RA_PINCFG__64(3, 3, 0x0D, RA_PINCFG_FUNC) -#define P303_TS02 RA_PINCFG__64(3, 3, 0x0C, RA_PINCFG_FUNC) -#define P304_GTIOC7A RA_PINCFG__64(3, 4, 0x03, RA_PINCFG_FUNC) -#define P304_SEG20 RA_PINCFG__64(3, 4, 0x0D, RA_PINCFG_FUNC) -#define P304_TS11 RA_PINCFG__64(3, 4, 0x0C, RA_PINCFG_FUNC) -#define P305_SEG19 RA_PINCFG_100(3, 5, 0x0D, RA_PINCFG_FUNC) -#define P306_SEG18 RA_PINCFG_100(3, 6, 0x0D, RA_PINCFG_FUNC) -#define P307_SEG17 RA_PINCFG_100(3, 7, 0x0D, RA_PINCFG_FUNC) -#define P400_AGTIO1 RA_PINCFG__48(4, 0, 0x01, RA_PINCFG_FUNC) -#define P400_AUDIO_CLK RA_PINCFG__48(4, 0, 0x12, RA_PINCFG_FUNC) -#define P400_CACREF RA_PINCFG__48(4, 0, 0x0A, RA_PINCFG_FUNC) -#define P400_GTIOC6A RA_PINCFG__48(4, 0, 0x04, RA_PINCFG_FUNC) -#define P400_SCK0 RA_PINCFG__48(4, 0, 0x04, RA_PINCFG_FUNC) -#define P400_SCK1 RA_PINCFG__48(4, 0, 0x05, RA_PINCFG_FUNC) -#define P400_SCL0 RA_PINCFG__48(4, 0, 0x07, RA_PINCFG_FUNC) -#define P400_SEG04 RA_PINCFG__48(4, 0, 0x0D, RA_PINCFG_FUNC) -#define P400_TS20 RA_PINCFG__48(4, 0, 0x0C, RA_PINCFG_FUNC) -#define P401_CTS0_RTS0 RA_PINCFG__64(4, 1, 0x04, RA_PINCFG_FUNC) -#define P401_CTX0 RA_PINCFG__64(4, 1, 0x10, RA_PINCFG_FUNC) -#define P401_GTETRGA RA_PINCFG__64(4, 1, 0x03, RA_PINCFG_FUNC) -#define P401_GTIOC6B RA_PINCFG__64(4, 1, 0x04, RA_PINCFG_FUNC) -#define P401_MOSI1 RA_PINCFG__64(4, 1, 0x05, RA_PINCFG_FUNC) -#define P401_SDA0 RA_PINCFG__64(4, 1, 0x07, RA_PINCFG_FUNC) -#define P401_SDA1 RA_PINCFG__64(4, 1, 0x05, RA_PINCFG_FUNC) -#define P401_SEG05 RA_PINCFG__64(4, 1, 0x0D, RA_PINCFG_FUNC) -#define P401_SS0 RA_PINCFG__64(4, 1, 0x04, RA_PINCFG_FUNC) -#define P401_TS19 RA_PINCFG__64(4, 1, 0x0C, RA_PINCFG_FUNC) -#define P401_TXD1 RA_PINCFG__64(4, 1, 0x05, RA_PINCFG_FUNC) -#define P402_AGTIO0 RA_PINCFG__64(4, 2, 0x01, RA_PINCFG_FUNC) -#define P402_AGTIO1 RA_PINCFG__64(4, 2, 0x02, RA_PINCFG_FUNC) -#define P402_CRX0 RA_PINCFG__64(4, 2, 0x10, RA_PINCFG_FUNC) -#define P402_MISO1 RA_PINCFG__64(4, 2, 0x05, RA_PINCFG_FUNC) -#define P402_RTCIC0 RA_PINCFG__64(4, 2, 0x00, RA_PINCFG_GPIO) -#define P402_RXD1 RA_PINCFG__64(4, 2, 0x05, RA_PINCFG_FUNC) -#define P402_SCL1 RA_PINCFG__64(4, 2, 0x05, RA_PINCFG_FUNC) -#define P402_SEG06 RA_PINCFG__64(4, 2, 0x0D, RA_PINCFG_FUNC) -#define P402_TS18 RA_PINCFG__64(4, 2, 0x0C, RA_PINCFG_FUNC) -#define P403_AGTIO0 RA_PINCFG_100(4, 3, 0x01, RA_PINCFG_FUNC) -#define P403_AGTIO1 RA_PINCFG_100(4, 3, 0x02, RA_PINCFG_FUNC) -#define P403_CTS1_RTS1 RA_PINCFG_100(4, 3, 0x05, RA_PINCFG_FUNC) -#define P403_GTIOC3A RA_PINCFG_100(4, 3, 0x04, RA_PINCFG_FUNC) -#define P403_RTCIC1 RA_PINCFG_100(4, 3, 0x00, RA_PINCFG_GPIO) -#define P403_SS1 RA_PINCFG_100(4, 3, 0x05, RA_PINCFG_FUNC) -#define P403_SSIBCK0 RA_PINCFG_100(4, 3, 0x12, RA_PINCFG_FUNC) -#define P403_TS17 RA_PINCFG_100(4, 3, 0x0C, RA_PINCFG_FUNC) -#define P404_GTIOC3B RA_PINCFG_100(4, 4, 0x04, RA_PINCFG_FUNC) -#define P404_RTCIC2 RA_PINCFG_100(4, 4, 0x00, RA_PINCFG_GPIO) -#define P404_SSIFS0 RA_PINCFG_100(4, 4, 0x12, RA_PINCFG_FUNC) -#define P404_SSILRCK0 RA_PINCFG_100(4, 4, 0x12, RA_PINCFG_FUNC) -#define P405_GTIOC1A RA_PINCFG_100(4, 5, 0x04, RA_PINCFG_FUNC) -#define P405_SSITXD0 RA_PINCFG_100(4, 5, 0x12, RA_PINCFG_FUNC) -#define P406_GTIOC1B RA_PINCFG_100(4, 6, 0x04, RA_PINCFG_FUNC) -#define P406_SSIRXD0 RA_PINCFG_100(4, 6, 0x12, RA_PINCFG_FUNC) -#define P407_ADTRG0 RA_PINCFG__40(4, 7, 0x0A, RA_PINCFG_FUNC) -#define P407_AGTIO0 RA_PINCFG__40(4, 7, 0x01, RA_PINCFG_FUNC) -#define P407_CTS0_RTS0 RA_PINCFG__40(4, 7, 0x04, RA_PINCFG_FUNC) -#define P407_RTCOUT RA_PINCFG__40(4, 7, 0x09, RA_PINCFG_FUNC) -#define P407_SDA0 RA_PINCFG__40(4, 7, 0x07, RA_PINCFG_FUNC) -#define P407_SEG11 RA_PINCFG__40(4, 7, 0x0D, RA_PINCFG_FUNC) -#define P407_SS0 RA_PINCFG__40(4, 7, 0x04, RA_PINCFG_FUNC) -#define P407_SSLB3 RA_PINCFG__40(4, 7, 0x06, RA_PINCFG_FUNC) -#define P407_TS03 RA_PINCFG__40(4, 7, 0x0C, RA_PINCFG_FUNC) -#define P407_USB_VBUS RA_PINCFG__40(4, 7, 0x13, RA_PINCFG_FUNC) -#define P408_CTS1_RTS1 RA_PINCFG__40(4, 8, 0x04, RA_PINCFG_FUNC) -#define P408_GTIOC5B RA_PINCFG__40(4, 8, 0x04, RA_PINCFG_FUNC) -#define P408_GTOWLO RA_PINCFG__40(4, 8, 0x03, RA_PINCFG_FUNC) -#define P408_MISO9 RA_PINCFG__40(4, 8, 0x05, RA_PINCFG_FUNC) -#define P408_RXD9 RA_PINCFG__40(4, 8, 0x05, RA_PINCFG_FUNC) -#define P408_SCL0 RA_PINCFG__40(4, 8, 0x07, RA_PINCFG_FUNC) -#define P408_SCL9 RA_PINCFG__40(4, 8, 0x05, RA_PINCFG_FUNC) -#define P408_SEG10 RA_PINCFG__40(4, 8, 0x0D, RA_PINCFG_FUNC) -#define P408_SS1 RA_PINCFG__40(4, 8, 0x04, RA_PINCFG_FUNC) -#define P408_TS04 RA_PINCFG__40(4, 8, 0x0C, RA_PINCFG_FUNC) -#define P408_USB_ID RA_PINCFG__40(4, 8, 0x13, RA_PINCFG_FUNC) -#define P409_GTIOC5A RA_PINCFG__48(4, 9, 0x04, RA_PINCFG_FUNC) -#define P409_GTOWUP RA_PINCFG__48(4, 9, 0x03, RA_PINCFG_FUNC) -#define P409_MOSI9 RA_PINCFG__48(4, 9, 0x05, RA_PINCFG_FUNC) -#define P409_SDA9 RA_PINCFG__48(4, 9, 0x05, RA_PINCFG_FUNC) -#define P409_SEG09 RA_PINCFG__48(4, 9, 0x0D, RA_PINCFG_FUNC) -#define P409_TS05 RA_PINCFG__48(4, 9, 0x0C, RA_PINCFG_FUNC) -#define P409_TXD9 RA_PINCFG__48(4, 9, 0x05, RA_PINCFG_FUNC) -#define P409_USB_EXICEN RA_PINCFG__48(4, 9, 0x13, RA_PINCFG_FUNC) -#define P410_AGTOB1 RA_PINCFG__64(4, 10, 0x01, RA_PINCFG_FUNC) -#define P410_GTIOC6B RA_PINCFG__64(4, 10, 0x04, RA_PINCFG_FUNC) -#define P410_GTOVLO RA_PINCFG__64(4, 10, 0x03, RA_PINCFG_FUNC) -#define P410_MISO0 RA_PINCFG__64(4, 10, 0x04, RA_PINCFG_FUNC) -#define P410_MISOA RA_PINCFG__64(4, 10, 0x06, RA_PINCFG_FUNC) -#define P410_RXD0 RA_PINCFG__64(4, 10, 0x04, RA_PINCFG_FUNC) -#define P410_SCL0 RA_PINCFG__64(4, 10, 0x04, RA_PINCFG_FUNC) -#define P410_SEG08 RA_PINCFG__64(4, 10, 0x0D, RA_PINCFG_FUNC) -#define P410_TS06 RA_PINCFG__64(4, 10, 0x0C, RA_PINCFG_FUNC) -#define P411_AGTOA1 RA_PINCFG__64(4, 11, 0x01, RA_PINCFG_FUNC) -#define P411_GTIOC6A RA_PINCFG__64(4, 11, 0x04, RA_PINCFG_FUNC) -#define P411_GTOVUP RA_PINCFG__64(4, 11, 0x03, RA_PINCFG_FUNC) -#define P411_MOSI0 RA_PINCFG__64(4, 11, 0x04, RA_PINCFG_FUNC) -#define P411_MOSIA RA_PINCFG__64(4, 11, 0x06, RA_PINCFG_FUNC) -#define P411_SDA0 RA_PINCFG__64(4, 11, 0x04, RA_PINCFG_FUNC) -#define P411_SEG07 RA_PINCFG__64(4, 11, 0x0D, RA_PINCFG_FUNC) -#define P411_TS07 RA_PINCFG__64(4, 11, 0x0C, RA_PINCFG_FUNC) -#define P411_TXD0 RA_PINCFG__64(4, 11, 0x04, RA_PINCFG_FUNC) -#define P412_RSPCKA RA_PINCFG_100(4, 12, 0x06, RA_PINCFG_FUNC) -#define P412_SCK0 RA_PINCFG_100(4, 12, 0x04, RA_PINCFG_FUNC) -#define P413_CTS0_RTS0 RA_PINCFG_100(4, 13, 0x04, RA_PINCFG_FUNC) -#define P413_SS0 RA_PINCFG_100(4, 13, 0x04, RA_PINCFG_FUNC) -#define P413_SSLA0 RA_PINCFG_100(4, 13, 0x06, RA_PINCFG_FUNC) -#define P414_GTIOC0B RA_PINCFG_100(4, 14, 0x04, RA_PINCFG_FUNC) -#define P414_SSLA1 RA_PINCFG_100(4, 14, 0x06, RA_PINCFG_FUNC) -#define P415_GTIOC0A RA_PINCFG_100(4, 15, 0x04, RA_PINCFG_FUNC) -#define P415_SSLA2 RA_PINCFG_100(4, 15, 0x06, RA_PINCFG_FUNC) -#define P500_AGTOA0 RA_PINCFG__48(5, 0, 0x01, RA_PINCFG_FUNC) -#define P500_AN016 RA_PINCFG__48(5, 0, 0x01, RA_PINCFG_ANALOG) -#define P500_CMPREF1 RA_PINCFG__48(5, 0, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P500_GTIOC2A RA_PINCFG__48(5, 0, 0x04, RA_PINCFG_FUNC) -#define P500_GTIU RA_PINCFG__48(5, 0, 0x03, RA_PINCFG_FUNC) -#define P500_SEG34 RA_PINCFG__48(5, 0, 0x0D, RA_PINCFG_FUNC) -#define P500_USB_VBUSEN RA_PINCFG__48(5, 0, 0x13, RA_PINCFG_FUNC) -#define P501_AGTOB0 RA_PINCFG__64(5, 1, 0x01, RA_PINCFG_FUNC) -#define P501_AN017 RA_PINCFG__64(5, 1, 0x01, RA_PINCFG_ANALOG) -#define P501_CMPIN1 RA_PINCFG__64(5, 1, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P501_GTIOC2B RA_PINCFG__64(5, 1, 0x04, RA_PINCFG_FUNC) -#define P501_GTIV RA_PINCFG__64(5, 1, 0x03, RA_PINCFG_FUNC) -#define P501_MOSI1 RA_PINCFG__64(5, 1, 0x05, RA_PINCFG_FUNC) -#define P501_SDA1 RA_PINCFG__64(5, 1, 0x05, RA_PINCFG_FUNC) -#define P501_SEG35 RA_PINCFG__64(5, 1, 0x0D, RA_PINCFG_FUNC) -#define P501_TXD1 RA_PINCFG__64(5, 1, 0x05, RA_PINCFG_FUNC) -#define P501_USB_OVRCUR_A RA_PINCFG__64(5, 1, 0x13, RA_PINCFG_FUNC) -#define P502_AN018 RA_PINCFG__64(5, 2, 0x01, RA_PINCFG_ANALOG) -#define P502_CMPREF0 RA_PINCFG__64(5, 2, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P502_GTIOC3B RA_PINCFG__64(5, 2, 0x04, RA_PINCFG_FUNC) -#define P502_GTIW RA_PINCFG__64(5, 2, 0x03, RA_PINCFG_FUNC) -#define P502_MISO1 RA_PINCFG__64(5, 2, 0x05, RA_PINCFG_FUNC) -#define P502_RXD1 RA_PINCFG__64(5, 2, 0x05, RA_PINCFG_FUNC) -#define P502_SCL1 RA_PINCFG__64(5, 2, 0x05, RA_PINCFG_FUNC) -#define P502_SEG36 RA_PINCFG__64(5, 2, 0x0D, RA_PINCFG_FUNC) -#define P502_USB_OVRCUR_B RA_PINCFG__64(5, 2, 0x13, RA_PINCFG_FUNC) -#define P503_AN023 RA_PINCFG_100(5, 3, 0x01, RA_PINCFG_ANALOG) -#define P503_CMPIN0 RA_PINCFG_100(5, 3, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG) -#define P503_SCK1 RA_PINCFG_100(5, 3, 0x05, RA_PINCFG_FUNC) -#define P503_SEG37 RA_PINCFG_100(5, 3, 0x0D, RA_PINCFG_FUNC) -#define P503_USB_EXICEN RA_PINCFG_100(5, 3, 0x13, RA_PINCFG_FUNC) -#define P504_AN024 RA_PINCFG_100(5, 4, 0x01, RA_PINCFG_ANALOG) -#define P504_CTS1_RTS1 RA_PINCFG_100(5, 4, 0x05, RA_PINCFG_FUNC) -#define P504_SS1 RA_PINCFG_100(5, 4, 0x05, RA_PINCFG_FUNC) -#define P504_USB_ID RA_PINCFG_100(5, 4, 0x13, RA_PINCFG_FUNC) -#define P505_AN025 RA_PINCFG_100(5, 5, 0x01, RA_PINCFG_ANALOG) -#define P600_GTIOC6B RA_PINCFG_100(6, 0, 0x01, RA_PINCFG_FUNC) -#define P600_SCK9 RA_PINCFG_100(6, 0, 0x05, RA_PINCFG_FUNC) -#define P600_SEG33 RA_PINCFG_100(6, 0, 0x0D, RA_PINCFG_FUNC) -#define P601_GTIOC6A RA_PINCFG_100(6, 1, 0x01, RA_PINCFG_FUNC) -#define P601_MISO9 RA_PINCFG_100(6, 1, 0x05, RA_PINCFG_FUNC) -#define P601_RXD9 RA_PINCFG_100(6, 1, 0x05, RA_PINCFG_FUNC) -#define P601_SCL9 RA_PINCFG_100(6, 1, 0x05, RA_PINCFG_FUNC) -#define P601_SEG32 RA_PINCFG_100(6, 1, 0x0D, RA_PINCFG_FUNC) -#define P602_GTIOC7B RA_PINCFG_100(6, 2, 0x01, RA_PINCFG_FUNC) -#define P602_MOSI9 RA_PINCFG_100(6, 2, 0x05, RA_PINCFG_FUNC) -#define P602_SDA9 RA_PINCFG_100(6, 2, 0x05, RA_PINCFG_FUNC) -#define P602_SEG31 RA_PINCFG_100(6, 2, 0x0D, RA_PINCFG_FUNC) -#define P602_TXD9 RA_PINCFG_100(6, 2, 0x05, RA_PINCFG_FUNC) -#define P603_CTS9_RTS9 RA_PINCFG_100(6, 3, 0x05, RA_PINCFG_FUNC) -#define P603_GTIOC7A RA_PINCFG_100(6, 3, 0x01, RA_PINCFG_FUNC) -#define P603_SEG30 RA_PINCFG_100(6, 3, 0x0D, RA_PINCFG_FUNC) -#define P603_SS9 RA_PINCFG_100(6, 3, 0x05, RA_PINCFG_FUNC) -#define P608_GTIOC4B RA_PINCFG_100(6, 8, 0x01, RA_PINCFG_FUNC) -#define P608_SEG27 RA_PINCFG_100(6, 8, 0x0D, RA_PINCFG_FUNC) -#define P609_GTIOC5A RA_PINCFG_100(6, 9, 0x01, RA_PINCFG_FUNC) -#define P609_SEG28 RA_PINCFG_100(6, 9, 0x0D, RA_PINCFG_FUNC) -#define P610_GTIOC5B RA_PINCFG_100(6, 10, 0x01, RA_PINCFG_FUNC) -#define P610_SEG29 RA_PINCFG_100(6, 10, 0x0D, RA_PINCFG_FUNC) -#define P708_MISO1 RA_PINCFG_100(7, 8, 0x05, RA_PINCFG_FUNC) -#define P708_RXD1 RA_PINCFG_100(7, 8, 0x05, RA_PINCFG_FUNC) -#define P708_SCL1 RA_PINCFG_100(7, 8, 0x05, RA_PINCFG_FUNC) -#define P708_SSLA3 RA_PINCFG_100(7, 8, 0x06, RA_PINCFG_FUNC) -#define P808_SEG21 RA_PINCFG_100(8, 8, 0x0D, RA_PINCFG_FUNC) -#define P809_SEG22 RA_PINCFG_100(8, 9, 0x0D, RA_PINCFG_FUNC) -#define P914_USB_DP RA_PINCFG__40(9, 14, 0x00, RA_PINCFG_GPIO) -#define P915_USB_DM RA_PINCFG__40(9, 15, 0x00, RA_PINCFG_GPIO) -#endif diff --git a/soc/renesas/ra/common/pinctrl_ra.h b/soc/renesas/ra/common/pinctrl_ra.h deleted file mode 100644 index ed80b3fda1856..0000000000000 --- a/soc/renesas/ra/common/pinctrl_ra.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_ - -enum { - PmnPFS_PODR_POS, - PmnPFS_PIDR_POS, - PmnPFS_PDR_POS, - PmnPFS_RSV3_POS, - PmnPFS_PCR_POS, - PmnPFS_RSV5_POS, - PmnPFS_NCODR_POS, - PmnPFS_RSV7_POS, - PmnPFS_RSV8_POS, - PmnPFS_RSV9_POS, - PmnPFS_DSCR_POS, - PmnPFS_DSCR1_POS, - PmnPFS_EOR_POS, - PmnPFS_EOF_POS, - PmnPFS_ISEL_POS, - PmnPFS_ASEL_POS, - PmnPFS_PMR_POS, -}; - -struct pinctrl_ra_pin { - union { - uint32_t config; - struct { - uint8_t PODR: 1; - uint8_t PIDR: 1; - uint8_t PDR: 1; - uint8_t RESERVED3: 1; - uint8_t PCR: 1; - uint8_t RESERVED5: 1; - uint8_t NCODR: 1; - uint8_t RESERVED7: 1; - uint8_t RESERVED8: 1; - uint8_t RESERVED9: 1; - uint8_t DSCR: 2; - uint8_t EOFR: 2; - uint8_t ISEL: 1; - uint8_t ASEL: 1; - uint8_t PMR: 1; - uint8_t RESERVED17: 7; - uint8_t PSEL: 5; - uint8_t RESERVED29: 3; - }; - /* Using RESERVED fields for store pin and port info. */ - struct { - uint32_t UNUSED0: 17; - uint8_t pin: 4; - uint8_t port: 3; - uint32_t UNUSED24: 5; - uint8_t port4: 1; - uint32_t UNUSED30: 2; - }; - }; -}; - -typedef struct pinctrl_ra_pin pinctrl_soc_pin_t; - -extern int pinctrl_ra_query_config(uint32_t port, uint32_t pin, - struct pinctrl_ra_pin *const pincfg); - -/** - * @brief Utility macro to initialize each pin. - * - * @param node_id Node identifier. - * @param prop Property name. - * @param idx Property entry index. - */ -#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ - { \ - .config = DT_PROP_BY_IDX(node_id, prop, idx), \ - }, - -/** - * @brief Utility macro to initialize state pins contained in a given property. - * - * @param node_id Node identifier. - * @param prop Property name describing state pins. - */ -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { \ - DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ - Z_PINCTRL_STATE_PIN_INIT) \ - } - -#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/ra/common/ra_common_soc.h b/soc/renesas/ra/common/ra_common_soc.h deleted file mode 100644 index f76c4c26fc0d4..0000000000000 --- a/soc/renesas/ra/common/ra_common_soc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ -#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ */ diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h index 0df9ec39111cb..dc08dc3db10f5 100644 --- a/soc/renesas/ra/common_fsp/pinctrl_soc.h +++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h @@ -12,6 +12,8 @@ #include +#define RA_PINCTRL_PORT_NUM ARRAY_SIZE(((R_PFS_Type *)0)->PORT) +#define RA_PINCTRL_PIN_NUM ARRAY_SIZE(((R_PFS_PORT_Type *)0)->PIN) /** * @brief Type to hold a renesas ra pin's pinctrl configuration. */ @@ -26,6 +28,8 @@ struct ra_pinctrl_soc_pin { typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t; +int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg); + /** * @brief Utility macro to initialize each pin. * diff --git a/soc/renesas/ra/ra4m1/CMakeLists.txt b/soc/renesas/ra/ra4m1/CMakeLists.txt index 00cdd96aa1876..e9637ecd9e69b 100644 --- a/soc/renesas/ra/ra4m1/CMakeLists.txt +++ b/soc/renesas/ra/ra4m1/CMakeLists.txt @@ -3,13 +3,11 @@ zephyr_include_directories(.) -zephyr_library_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY - soc.c -) - -zephyr_linker_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY - ROM_START - ${CMAKE_CURRENT_SOURCE_DIR}/opt_set_mem.ld -) +zephyr_library_sources(soc.c) + +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(DATA_SECTIONS data_sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) +zephyr_linker_sources(ROM_START rom_start.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m1/Kconfig b/soc/renesas/ra/ra4m1/Kconfig index 9096855e987b6..798725677bbd9 100644 --- a/soc/renesas/ra/ra4m1/Kconfig +++ b/soc/renesas/ra/ra4m1/Kconfig @@ -5,10 +5,15 @@ config SOC_SERIES_RA4M1 select ARM select CPU_CORTEX_M4 select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_SYSTICK - select DYNAMIC_INTERRUPTS - select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME + select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO select XIP + select SOC_EARLY_INIT_HOOK + select DYNAMIC_INTERRUPTS if SOC_SERIES_RA4M1 diff --git a/soc/renesas/ra/ra4m1/Kconfig.soc b/soc/renesas/ra/ra4m1/Kconfig.soc index e83c7bf3629ab..cb3cbe60a8f58 100644 --- a/soc/renesas/ra/ra4m1/Kconfig.soc +++ b/soc/renesas/ra/ra4m1/Kconfig.soc @@ -5,7 +5,7 @@ config SOC_SERIES_RA4M1 bool select SOC_FAMILY_RENESAS_RA help - Renesas RA4M1 + Renesas RA4M1 series config SOC_R7FA4M1AB3CFM bool diff --git a/soc/renesas/ra/ra4m1/data_sections.ld b/soc/renesas/ra/ra4m1/data_sections.ld new file mode 100644 index 0000000000000..84cb7c088e838 --- /dev/null +++ b/soc/renesas/ra/ra4m1/data_sections.ld @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION diff --git a/soc/renesas/ra/ra4m1/opt_set_mem.ld b/soc/renesas/ra/ra4m1/opt_set_mem.ld deleted file mode 100644 index c05238789af71..0000000000000 --- a/soc/renesas/ra/ra4m1/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Ian Morris - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -. = 0x400; -FILL(0xFF) -KEEP(*(.opt_set_mem*)) -. = 0x500; diff --git a/soc/renesas/ra/ra4m1/ram_sections.ld b/soc/renesas/ra/ra4m1/ram_sections.ld new file mode 100644 index 0000000000000..46ad2cc8b9339 --- /dev/null +++ b/soc/renesas/ra/ra4m1/ram_sections.ld @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) diff --git a/soc/renesas/ra/ra4m1/rom_start.ld b/soc/renesas/ra/ra4m1/rom_start.ld new file mode 100644 index 0000000000000..64eb3c891e043 --- /dev/null +++ b/soc/renesas/ra/ra4m1/rom_start.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra4m1/sections.ld b/soc/renesas/ra/ra4m1/sections.ld new file mode 100644 index 0000000000000..e3034adb244ea --- /dev/null +++ b/soc/renesas/ra/ra4m1/sections.ld @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay) + +SECTION_PROLOGUE(.option_setting_ofs,,) +{ + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = __OPTION_SETTING_OFS_Start + 0x04; + KEEP(*(.option_setting_ofs2)) + . = __OPTION_SETTING_OFS_Start + 0x10; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay) + +SECTION_PROLOGUE(.option_setting_sas,,) +{ + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; +} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay) + +SECTION_PROLOGUE(.option_setting_ns,,) +{ + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = __OPTION_SETTING_NS_Start + 0x04; + KEEP(*(.option_setting_ofs3)) + . = __OPTION_SETTING_NS_Start + 0x10; + KEEP(*(.option_setting_banksel)) + . = __OPTION_SETTING_NS_Start + 0x40; + KEEP(*(.option_setting_bps0)) + . = __OPTION_SETTING_NS_Start + 0x44; + KEEP(*(.option_setting_bps1)) + . = __OPTION_SETTING_NS_Start + 0x48; + KEEP(*(.option_setting_bps2)) + . = __OPTION_SETTING_NS_Start + 0x4C; + KEEP(*(.option_setting_bps3)) + . = __OPTION_SETTING_NS_Start + 0x60; + KEEP(*(.option_setting_pbps0)) + . = __OPTION_SETTING_NS_Start + 0x64; + KEEP(*(.option_setting_pbps1)) + . = __OPTION_SETTING_NS_Start + 0x68; + KEEP(*(.option_setting_pbps2)) + . = __OPTION_SETTING_NS_Start + 0x6C; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; +} GROUP_LINK_IN(OPTION_SETTING) = 0xFF + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay) + +SECTION_PROLOGUE(.option_setting_s,,) +{ + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = __OPTION_SETTING_S_Start + 0x04; + KEEP(*(.option_setting_ofs3_sec)) + . = __OPTION_SETTING_S_Start + 0x10; + KEEP(*(.option_setting_banksel_sec)) + . = __OPTION_SETTING_S_Start + 0x40; + KEEP(*(.option_setting_bps_sec0)) + . = __OPTION_SETTING_S_Start + 0x44; + KEEP(*(.option_setting_bps_sec1)) + . = __OPTION_SETTING_S_Start + 0x48; + KEEP(*(.option_setting_bps_sec2)) + . = __OPTION_SETTING_S_Start + 0x4C; + KEEP(*(.option_setting_bps_sec3)) + . = __OPTION_SETTING_S_Start + 0x60; + KEEP(*(.option_setting_pbps_sec0)) + . = __OPTION_SETTING_S_Start + 0x64; + KEEP(*(.option_setting_pbps_sec1)) + . = __OPTION_SETTING_S_Start + 0x68; + KEEP(*(.option_setting_pbps_sec2)) + . = __OPTION_SETTING_S_Start + 0x6C; + KEEP(*(.option_setting_pbps_sec3)) + . = __OPTION_SETTING_S_Start + 0x80; + KEEP(*(.option_setting_ofs1_sel)) + . = __OPTION_SETTING_S_Start + 0x84; + KEEP(*(.option_setting_ofs3_sel)) + . = __OPTION_SETTING_S_Start + 0x90; + KEEP(*(.option_setting_banksel_sel)) + . = __OPTION_SETTING_S_Start + 0xC0; + KEEP(*(.option_setting_bps_sel0)) + . = __OPTION_SETTING_S_Start + 0xC4; + KEEP(*(.option_setting_bps_sel1)) + . = __OPTION_SETTING_S_Start + 0xC8; + KEEP(*(.option_setting_bps_sel2)) + . = __OPTION_SETTING_S_Start + 0xCC; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; +} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF + +#endif diff --git a/soc/renesas/ra/ra4m1/soc.c b/soc/renesas/ra/ra4m1/soc.c index 7d8f27449141a..06202352c518d 100644 --- a/soc/renesas/ra/ra4m1/soc.c +++ b/soc/renesas/ra/ra4m1/soc.c @@ -1,11 +1,29 @@ /* * Copyright (c) 2024 Ian Morris + * Copyright (c) 2024 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @brief System/hardware module for Renesas RA4M1 family processor + */ + +#include +#include #include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include -#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency) +#define HOCO_FREQ DT_PROP(DT_PATH(clocks, clock_hoco), clock_frequency) #if HOCO_FREQ == MHZ(24) #define OFS1_HOCO_FREQ 0 @@ -75,43 +93,31 @@ struct opt_set_mem { }; #ifdef CONFIG_SOC_OPTION_SETTING_MEMORY -const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = { +const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = { .ofs0 = { - /* - * Initial settings for watchdog timers. Set all fields to 1, - * disabling watchdog functionality as config options have not - * yet been implemented. - */ - .RSVD1 = 0x1, - .IWDTSTRT = 0x1, /* Disable independent watchdog timer */ - .IWDTTOPS = 0x3, - .IWDTCKS = 0xf, - .IWDTRPES = 0x3, - .IWDTRPSS = 0x3, - .IWDTRSTIRQS = 0x1, - .RSVD2 = 0x1, - .IWDTSTPCTL = 0x1, - .RSVD3 = 0x3, - .WDTSTRT = 0x1, /* Stop watchdog timer following reset */ - .WDTTOPS = 0x3, - .WDTCKS = 0xf, - .WDTRPES = 0x3, - .WDTRPSS = 0x3, - .WDTRSTIRQS = 0x1, - .RSVD4 = 0x1, - .WDTSTPCTL = 0x1, - .RSVD5 = 0x1, - }, + /* + * Initial settings for watchdog timers. Set all fields to 1, + * disabling watchdog functionality as config options have not + * yet been implemented. + */ + .RSVD1 = 0x1, .IWDTSTRT = 0x1, /* Disable independent watchdog timer + */ + .IWDTTOPS = 0x3, .IWDTCKS = 0xf, .IWDTRPES = 0x3, .IWDTRPSS = 0x3, + .IWDTRSTIRQS = 0x1, .RSVD2 = 0x1, .IWDTSTPCTL = 0x1, .RSVD3 = 0x3, + .WDTSTRT = 0x1, /* Stop watchdog timer following reset */ + .WDTTOPS = 0x3, .WDTCKS = 0xf, .WDTRPES = 0x3, .WDTRPSS = 0x3, + .WDTRSTIRQS = 0x1, .RSVD4 = 0x1, .WDTSTPCTL = 0x1, .RSVD5 = 0x1, + }, .ofs1 = { - .RSVD1 = 0x3, - .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */ - .VDSEL1 = 0x3, - .RSVD2 = 0x3, - .HOCOEN = !DT_NODE_HAS_STATUS_OKAY(DT_PATH(clocks, hoco)), - .RSVD3 = 0x7, - .HOCOFRQ1 = OFS1_HOCO_FREQ, - .RSVD4 = 0x1ffff, - }, + .RSVD1 = 0x3, + .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */ + .VDSEL1 = 0x3, + .RSVD2 = 0x3, + .HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay), + .RSVD3 = 0x7, + .HOCOFRQ1 = OFS1_HOCO_FREQ, + .RSVD4 = 0x1ffff, + }, .mpu = { /* * Initial settings for MPU. Set all areas to maximum values @@ -131,6 +137,26 @@ const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = { .SECMPUS3 = 0x40dffffc, .SECMPUE3 = 0x40dfffff, .SECMPUAC = 0xffffffff, - } -}; + }}; #endif + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + uint32_t key; + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + irq_unlock(key); +} diff --git a/soc/renesas/ra/ra4m1/soc.h b/soc/renesas/ra/ra4m1/soc.h index 127ee9ab44477..0476e2ba816ac 100644 --- a/soc/renesas/ra/ra4m1/soc.h +++ b/soc/renesas/ra/ra4m1/soc.h @@ -4,4 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "../common/ra_common_soc.h" +/** + * @file SoC configuration macros for the Renesas RA4M1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_ */