From 9c8fa3389dc1d98bf2bdf8fed2e511f5f773177e Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 13:30:25 +0800 Subject: [PATCH 1/5] clock: driver/clock_control: Add sai clock support for syscon. Add sai clock support for syscon. Signed-off-by: Qiang Zhang --- drivers/clock_control/clock_control_mcux_syscon.c | 15 +++++++++++++++ .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index d26565b1a941e..d9af2574fbf10 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -412,6 +412,21 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de #endif #endif /* CONFIG_MEMC_MCUX_FLEXSPI */ +#if defined(CONFIG_I2S_MCUX_SAI) + case MCUX_SAI0_CLK: +#if (FSL_FEATURE_SOC_I2S_COUNT == 1) + *rate = CLOCK_GetSaiClkFreq(); +#else + *rate = CLOCK_GetSaiClkFreq(0); +#endif + break; +#if (FSL_FEATURE_SOC_I2S_COUNT == 2) + case MCUX_SAI1_CLK: + *rate = CLOCK_GetSaiClkFreq(1); + break; +#endif +#endif /* CONFIG_I2S_MCUX_SAI */ + #ifdef CONFIG_ETH_NXP_ENET_QOS case MCUX_ENET_QOS_CLK: *rate = CLOCK_GetFreq(kCLOCK_BusClk); diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 32e0e228653a6..274d0632fa098 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -115,4 +115,7 @@ #define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01) #define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02) +#define MCUX_SAI0_CLK MCUX_LPC_CLK_ID(0x16, 0x00) +#define MCUX_SAI1_CLK MCUX_LPC_CLK_ID(0x16, 0x01) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ From 55ffc95c8fa3cb619da504b3e06be6d03b433abe Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 11:06:33 +0800 Subject: [PATCH 2/5] drivers: drivers/i2s: fix sai issue for support frdm_mcxn497 i2s driver have not suooprt frdm_mcxn947 pll clk set. so add macro CONFIG_I2S_HAS_PLL_SETTING to control pll init. Signed-off-by: Qiang Zhang --- drivers/i2s/Kconfig.mcux | 6 +++++- drivers/i2s/i2s_mcux_sai.c | 29 ++++++++++++++++------------- dts/bindings/i2s/nxp,mcux-i2s.yaml | 1 - 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/i2s/Kconfig.mcux b/drivers/i2s/Kconfig.mcux index 4a7ef1b1eef69..7a6889db61741 100644 --- a/drivers/i2s/Kconfig.mcux +++ b/drivers/i2s/Kconfig.mcux @@ -1,6 +1,6 @@ # MCUX I2S driver configuration options -# Copyright (c) 2021, NXP +# Copyright 2021,2024 NXP # SPDX-License-Identifier: Apache-2.0 menuconfig I2S_MCUX_SAI @@ -28,4 +28,8 @@ config I2S_EDMA_BURST_SIZE help I2S EDMA burst size in bytes. +config I2S_HAS_PLL_SETTING + bool "I2S will setting pll in driver" + default y + endif # I2S_MCUX_SAI diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c index 468dce37dfba0..ae0ddb2bcffa8 100644 --- a/drivers/i2s/i2s_mcux_sai.c +++ b/drivers/i2s/i2s_mcux_sai.c @@ -94,7 +94,7 @@ struct i2s_mcux_config { uint32_t pll_pd; uint32_t pll_num; uint32_t pll_den; - uint32_t *mclk_control_base; + uint32_t mclk_control_base; uint32_t mclk_pin_mask; uint32_t mclk_pin_offset; uint32_t tx_channel; @@ -400,9 +400,10 @@ static void i2s_dma_rx_callback(const struct device *dma_dev, void *arg, uint32_ static void enable_mclk_direction(const struct device *dev, bool dir) { const struct i2s_mcux_config *dev_cfg = dev->config; + uint32_t control_base = dev_cfg->mclk_control_base; uint32_t offset = dev_cfg->mclk_pin_offset; uint32_t mask = dev_cfg->mclk_pin_mask; - uint32_t *base = (uint32_t *)(dev_cfg->mclk_control_base + offset); + uint32_t *base = (uint32_t *)(control_base + offset); if (dir) { *base |= mask; @@ -1030,6 +1031,7 @@ static void i2s_mcux_isr(void *arg) static void audio_clock_settings(const struct device *dev) { +#ifdef CONFIG_I2S_HAS_PLL_SETTING clock_audio_pll_config_t audioPllConfig; const struct i2s_mcux_config *dev_cfg = dev->config; uint32_t clock_name = (uint32_t)dev_cfg->clk_sub_sys; @@ -1055,6 +1057,7 @@ static void audio_clock_settings(const struct device *dev) #endif /* CONFIG_SOC_SERIES */ CLOCK_InitAudioPll(&audioPllConfig); +#endif } static int i2s_mcux_initialize(const struct device *dev) @@ -1113,7 +1116,8 @@ static int i2s_mcux_initialize(const struct device *dev) /* master clock configurations */ #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) mclkConfig.mclkHz = mclk; mclkConfig.mclkSourceClkHz = mclk; #endif @@ -1140,16 +1144,15 @@ static DEVICE_API(i2s, i2s_mcux_driver_api) = { \ static const struct i2s_mcux_config i2s_##i2s_id##_config = { \ .base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \ - .clk_src = DT_INST_PROP(i2s_id, clock_mux), \ - .clk_pre_div = DT_INST_PROP(i2s_id, pre_div), \ - .clk_src_div = DT_INST_PROP(i2s_id, podf), \ - .pll_src = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, src, value), \ - .pll_lp = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, lp, value), \ - .pll_pd = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, pd, value), \ - .pll_num = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, num, value), \ - .pll_den = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, den, value), \ - .mclk_control_base = \ - (uint32_t *)DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)), \ + .clk_src = DT_INST_PROP_OR(i2s_id, clock_mux, 0), \ + .clk_pre_div = DT_INST_PROP_OR(i2s_id, pre_div, 0), \ + .clk_src_div = DT_INST_PROP_OR(i2s_id, podf, 0), \ + .pll_src = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, src, value, 0), \ + .pll_lp = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, lp, value, 0), \ + .pll_pd = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, pd, value, 0), \ + .pll_num = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, num, value, 0), \ + .pll_den = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, den, value, 0), \ + .mclk_control_base = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)), \ .mclk_pin_mask = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, function), \ .mclk_pin_offset = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, pin), \ .clk_sub_sys = \ diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml index 25295432874a7..6aed4a4bf3451 100644 --- a/dts/bindings/i2s/nxp,mcux-i2s.yaml +++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml @@ -62,6 +62,5 @@ properties: description: tx channel the maximum number is SOC dependent clock-mux: - required: true type: int description: Clock mux source for SAI root clock From aebbd9ffe43efb4a53da5f14690ff9509cfca5f2 Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 11:24:13 +0800 Subject: [PATCH 3/5] dts: arm/nxp/mcxn94x: Add sai nodes for NXP mcxn94x Add sai nodes for NXP mcxn94x Signed-off-by: Qiang Zhang --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 33 +++++++++++++++++++++++++++++ dts/bindings/i2s/nxp,mcux-i2s.yaml | 6 +++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 1b9ef18153e52..48e99586de55f 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -1040,6 +1040,39 @@ clock-src = <0>; alarms-count = <1>; }; + + sai0: sai@106000 { + compatible = "nxp,mcux-i2s"; + #address-cells = <1>; + #size-cells = <0>; + #pinmux-cells = <2>; + reg = < 0x106000 0x1000>; + clocks = <&syscon MCUX_SAI0_CLK>; + pinmuxes = <&sai0 0x100 0x40000000>; + interrupts = <59 0>; + dmas = <&edma0 0 99>, <&edma0 0 100>; + dma-names = "rx", "tx"; + nxp,tx-channel = <1>; + nxp,tx-dma-channel = <0>; + nxp,rx-dma-channel = <1>; + status = "disabled"; + }; + sai1: sai@107000 { + compatible = "nxp,mcux-i2s"; + #address-cells = <1>; + #size-cells = <0>; + #pinmux-cells = <2>; + reg = < 0x107000 0x1000>; + clocks = <&syscon MCUX_SAI1_CLK>; + pinmuxes = <&sai1 0x100 0x40000000>; + interrupts = <60 0>; + dmas = <&edma0 0 101>, <&edma0 0 102>; + dma-names = "rx", "tx"; + nxp,tx-channel = <1>; + nxp,tx-dma-channel = <2>; + nxp,rx-dma-channel = <3>; + status = "disabled"; + }; }; &systick { diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml index 6aed4a4bf3451..56239140e9a5b 100644 --- a/dts/bindings/i2s/nxp,mcux-i2s.yaml +++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml @@ -1,4 +1,4 @@ -# Copyright 2021,2023 NXP +# Copyright 2021,2023-2024 NXP # SPDX-License-Identifier: Apache-2.0 description: NXP mcux SAI-I2S controller @@ -64,3 +64,7 @@ properties: clock-mux: type: int description: Clock mux source for SAI root clock + +pinmux-cells: + - pin + - function From a2a3d70fd4c0da50fedd1eeb1b76b20c3a97d8f4 Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 11:29:46 +0800 Subject: [PATCH 4/5] boards: nxp/frdm_mcxn947: Support sai for NXP frdm_mcxn947 Support sai for NXP frdm_mcxn947. Signed-off-by: Qiang Zhang --- boards/nxp/frdm_mcxn947/board.c | 37 ++++++++++++------- boards/nxp/frdm_mcxn947/doc/index.rst | 2 + .../frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 25 +++++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 10 +++++ .../frdm_mcxn947_mcxn947_cpu0.dtsi | 7 ++++ .../frdm_mcxn947_mcxn947_cpu0.yaml | 1 + soc/nxp/mcx/mcxn/Kconfig.defconfig | 5 +++ 7 files changed, 73 insertions(+), 14 deletions(-) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 7bf3f8999cc82..fafaf3e406824 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -131,21 +131,18 @@ static int frdm_mcxn947_init(void) CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ); -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) - /* Set up PLL1 for 80 MHz FlexCAN clock */ - const pll_setup_t pll1Setup = { - .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) | - SCG_SPLLCTRL_SELP(13U), - .pllndiv = SCG_SPLLNDIV_NDIV(3U), - .pllpdiv = SCG_SPLLPDIV_PDIV(1U), - .pllmdiv = SCG_SPLLMDIV_MDIV(10U), - .pllRate = 80000000U - }; +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) + /* < Set up PLL1 */ + const pll_setup_t pll1_Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) | + SCG_SPLLCTRL_SELP(1U), + .pllndiv = SCG_SPLLNDIV_NDIV(25U), + .pllpdiv = SCG_SPLLPDIV_PDIV(10U), + .pllmdiv = SCG_SPLLMDIV_MDIV(256U), + .pllRate = 24576000U}; /* Configure PLL1 to the desired values */ - CLOCK_SetPLL1Freq(&pll1Setup); - /* PLL1 Monitor is disabled */ - CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); + CLOCK_SetPLL1Freq(&pll1_Setup); /* Set PLL1 CLK0 divider to value 1 */ CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U); #endif @@ -250,7 +247,7 @@ static int frdm_mcxn947_init(void) #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U); - CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0); + CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) @@ -383,6 +380,18 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kFRO_HF_to_SCT); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) + CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u); + CLOCK_AttachClk(kPLL1_CLK0_to_SAI0); + CLOCK_EnableClock(kCLOCK_Sai0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) + CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u); + CLOCK_AttachClk(kPLL1_CLK0_to_SAI1); + CLOCK_EnableClock(kCLOCK_Sai1); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 4cbc2d5ad9369..871c5c035d490 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -97,6 +97,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | FLEXIO | on-chip | flexio | +-----------+------------+-------------------------------------+ +| SAI | on-chip | i2s | ++-----------+------------+-------------------------------------+ | DISPLAY | on-chip | flexio; MIPI-DBI. Tested with | | | | :ref:`lcd_par_s035` | +-----------+------------+-------------------------------------+ diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index ce4995b6d1cd4..83b496c635d26 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -92,6 +92,31 @@ }; }; + pinmux_sai1: pinmux_sai1 { + group0 { + pinmux = , + , + , + , + , + ; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_sai0: pinmux_sai0 { + group0 { + pinmux = , + , + ; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + pinmux_enet_qos: pinmux_enet_qos { mdio_group { pinmux = , diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index d96f6c3ca253e..9c13cb95a9dd7 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -206,6 +206,16 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-names = "default"; }; +&sai1 { + pinctrl-0 = <&pinmux_sai1>; + pinctrl-names = "default"; +}; + +&sai0 { + pinctrl-0 = <&pinmux_sai0>; + pinctrl-names = "default"; +}; + &enet { pinctrl-0 = <&pinmux_enet_qos>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi index 08c13f5ddf66c..ec2880077b34b 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi @@ -233,3 +233,10 @@ zephyr_udc0: &usb1 { &sc_timer { status = "okay"; }; + +&sai1 { + status = "okay"; +}; +&sai0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 8578e55b9310f..919a6b7058398 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -23,6 +23,7 @@ supported: - flash - gpio - i2c + - i2s - i3c - pwm - regulator diff --git a/soc/nxp/mcx/mcxn/Kconfig.defconfig b/soc/nxp/mcx/mcxn/Kconfig.defconfig index ada924c897c48..1668cfad798a7 100644 --- a/soc/nxp/mcx/mcxn/Kconfig.defconfig +++ b/soc/nxp/mcx/mcxn/Kconfig.defconfig @@ -27,4 +27,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config FLASH_FILL_BUFFER_SIZE default 128 +# The existing SAI diver cannot initialize the PLL on the board, +# so the PLL settings will not be performed in the driver. +config I2S_HAS_PLL_SETTING + default n + endif # SOC_SERIES_MCXN From a959efd00009ca9d8a52ee64d0671ebf1bd2e631 Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 11:31:46 +0800 Subject: [PATCH 5/5] samples: drivers/i2s: Support i2s example for NXP frdm_mcxn947 Support i2s example for NXP frdm_mcxn947 Signed-off-by: Qiang Zhang --- tests/drivers/i2s/i2s_api/testcase.yaml | 2 ++ tests/drivers/i2s/i2s_speed/Readme.txt | 7 ++++++ .../boards/frdm_mcxn947_mcxn947_cpu0.conf | 25 +++++++++++++++++++ .../boards/frdm_mcxn947_mcxn947_cpu0.overlay | 11 ++++++++ 4 files changed, 45 insertions(+) create mode 100644 tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf create mode 100644 tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay diff --git a/tests/drivers/i2s/i2s_api/testcase.yaml b/tests/drivers/i2s/i2s_api/testcase.yaml index b039b41358554..315f8edd9aaa3 100644 --- a/tests/drivers/i2s/i2s_api/testcase.yaml +++ b/tests/drivers/i2s/i2s_api/testcase.yaml @@ -6,6 +6,7 @@ tests: - userspace filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK platform_exclude: + - frdm_mcxn947/mcxn947/cpu0 - mimxrt595_evk/mimxrt595s/cm33 - mimxrt685_evk/mimxrt685s/cm33 drivers.i2s.gpio_loopback: @@ -18,6 +19,7 @@ tests: filter: CONFIG_I2S_TEST_USE_GPIO_LOOPBACK harness: ztest platform_exclude: + - frdm_mcxn947/mcxn947/cpu0 - mimxrt595_evk/mimxrt595s/cm33 - mimxrt685_evk/mimxrt685s/cm33 harness_config: diff --git a/tests/drivers/i2s/i2s_speed/Readme.txt b/tests/drivers/i2s/i2s_speed/Readme.txt index 4d5816996c5cf..a578ed9a39aa1 100644 --- a/tests/drivers/i2s/i2s_speed/Readme.txt +++ b/tests/drivers/i2s/i2s_speed/Readme.txt @@ -10,3 +10,10 @@ signals externally on the EVK. These are the HW changes required to run this te - Short BCLK J9-pin1 (SAI1_RX_BCLK) to J66-pin1 (SAI4_TX_BCLK) - Short SYNC J9-pin5 (SAI1_RX_SYNC) to J64-pin1 (SAI4_TX_SYNC) - Short Data J61-pin1 (SAI1_RX_DATA) to J63-pin1 (SAI4_TX_DATA) + +FRDM-MCXN947: +This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=y and connects two SAI peripherals by shorting +signals externally on the EVK. These are the HW changes required to run this test: + - Short BCLK J1-pin9 (SAI1_RX_BCLK/P3_18) to J3-pin15 (SAI0_TX_BCLK/P2_6) + - Short SYNC J1-pin13 (SAI1_RX_FS/P3_19) to J3-pin13 (SAI0_TX_FS/P2_7) + - Short Data J1-pin15 (SAI1_RXD0/P3_21) to J3-pin7 (SAI0_TXD0/P2_2) diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf new file mode 100644 index 0000000000000..b44f2e381fc02 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf @@ -0,0 +1,25 @@ +# +# Copyright (c) 2024, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# SAI peripheral does not have loopback mode. Use 2 SAI peripherals connected +# together externally. +CONFIG_I2S_TEST_SEPARATE_DEVICES=y + +# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs) +# together, and should be sized as needed by the application. If not large +# enough, the DMA may starve. Symptoms of this issue include transmit blocks +# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3. +CONFIG_DMA_TCD_QUEUE_SIZE=4 + +# Repeat test continually to help find intermittent issues +CONFIG_ZTEST_RETEST_IF_PASSED=y + +# I2S and DMA logging can occur in interrupt context, and interfere with I2S +# stream timing. If using either logging, set logging to deferred +# CONFIG_LOG_MODE_DEFERRED=y + +CONFIG_DMA_LOG_LEVEL_OFF=y +CONFIG_I2S_LOG_LEVEL_OFF=y diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay new file mode 100644 index 0000000000000..d6f34fc2e5f14 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -0,0 +1,11 @@ +/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=y uses two I2S peripherals: + * i2s-node0 is the receiver + * i2s-node1 is the transmitter + */ + +/ { + aliases { + i2s-node0 = &sai1; + i2s-node1 = &sai0; + }; +};