diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index cb216bc59e565..3e31661b58966 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -160,10 +160,6 @@
 #error "APB4 frequency is too high!"
 #endif
 
-#if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
-#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC"
-#endif
-
 /* end of clock feasibility check */
 #endif /* CONFIG_CPU_CORTEX_M7 */
 
@@ -800,8 +796,11 @@ static int set_up_plls(void)
 
 	LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
 
-	/* FRACN disable DIVP,DIVQ,DIVR enable*/
 	LL_RCC_PLL1FRACN_Disable();
+	if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
+		LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
+		LL_RCC_PLL1FRACN_Enable();
+	}
 
 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
 		LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
@@ -846,6 +845,10 @@ static int set_up_plls(void)
 	LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
 
 	LL_RCC_PLL2FRACN_Disable();
+	if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {
+		LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE);
+		LL_RCC_PLL2FRACN_Enable();
+	}
 
 	if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
 		LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
@@ -896,6 +899,10 @@ static int set_up_plls(void)
 	LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
 
 	LL_RCC_PLL3FRACN_Disable();
+	if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {
+		LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE);
+		LL_RCC_PLL3FRACN_Enable();
+	}
 
 	if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
 		LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
index ab6afacb880c0..2e441876116ea 100644
--- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
@@ -65,3 +65,9 @@ properties:
     description: |
         PLL division factor for pllx_r_ck
         Valid range: 1 - 128
+
+  fracn:
+    type: int
+    description: |
+        PLLx FRACN value
+        Valid range: 0 - 8191
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay
new file mode 100644
index 0000000000000..21ba087efbf2b
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Kickmaker
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	hsi-div = <1>;		/* HSI RC: 64MHz, hsi_clk = 64MHz */
+	status = "okay";
+};
+
+&pll {
+	div-m = <4>;
+	mul-n = <34>;
+	div-p = <1>;
+	div-q = <4>;
+	div-r = <2>;
+	clocks = <&clk_hsi>;
+	fracn = <3072>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(550)>;
+	d1cpre = <1>;
+	hpre = <2>;
+	d1ppre = <2>;
+	d2ppre1 = <2>;
+	d2ppre2 = <2>;
+	d3ppre = <2>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml
index 8b868d3618a82..795de1a64bb5b 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml
@@ -46,3 +46,10 @@ tests:
       - stm32h735g_disco
     integration_platforms:
       - nucleo_h723zg
+  drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_fracn_550:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_550.overlay"
+    platform_allow:
+      - nucleo_h723zg
+      - stm32h735g_disco
+    integration_platforms:
+      - nucleo_h723zg