From 412acce1e758eacedb80854ba23e79f615462b8f Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Thu, 22 Aug 2024 23:22:11 +0200 Subject: [PATCH 1/4] dts: add fracn to STM32H7 PLL clocks add fracn to STM32H7 pll clock binding Signed-off-by: Nathan Olff --- dts/bindings/clock/st,stm32h7-pll-clock.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml index ab6afacb880c0..2e441876116ea 100644 --- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml @@ -65,3 +65,9 @@ properties: description: | PLL division factor for pllx_r_ck Valid range: 1 - 128 + + fracn: + type: int + description: | + PLLx FRACN value + Valid range: 0 - 8191 From 16d7c67e32bded5ee0395cd331756b9d8764c21c Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Thu, 22 Aug 2024 23:28:33 +0200 Subject: [PATCH 2/4] drivers: use fracn in clock stm32h7 driver use fracn value if defined for each PLL 1, 2 and 3 based on stm32u5 code Signed-off-by: Nathan Olff --- drivers/clock_control/clock_stm32_ll_h7.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index cb216bc59e565..658796385e27c 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -800,8 +800,11 @@ static int set_up_plls(void) LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER); - /* FRACN disable DIVP,DIVQ,DIVR enable*/ LL_RCC_PLL1FRACN_Disable(); + if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) { + LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE); + LL_RCC_PLL1FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL_P_ENABLED)) { LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); @@ -846,6 +849,10 @@ static int set_up_plls(void) LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER); LL_RCC_PLL2FRACN_Disable(); + if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) { + LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE); + LL_RCC_PLL2FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR); @@ -896,6 +903,10 @@ static int set_up_plls(void) LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER); LL_RCC_PLL3FRACN_Disable(); + if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) { + LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE); + LL_RCC_PLL3FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL3_P_ENABLED)) { LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); From 00474a61b2b75f9b65e96368387daa92fd27ae51 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Mon, 9 Sep 2024 09:09:05 +0200 Subject: [PATCH 3/4] drivers: clocks: remove check for sysclock in h7 clocks remove check for system clock frequency in clock_stm32_ll_h7 because of addition of fracn (difficult to handle) Signed-off-by: Nathan Olff --- drivers/clock_control/clock_stm32_ll_h7.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 658796385e27c..3e31661b58966 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -160,10 +160,6 @@ #error "APB4 frequency is too high!" #endif -#if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC" -#endif - /* end of clock feasibility check */ #endif /* CONFIG_CPU_CORTEX_M7 */ From 68d1418994034f93a54b9a1e69f9a43aa15746d2 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Mon, 9 Sep 2024 13:38:16 +0200 Subject: [PATCH 4/4] tests: drivers: add fracn test for stm32h7 clock configuration tests add overlay to use fracn with HSI in clock configuration tests for stm32h7 Signed-off-by: Nathan Olff --- .../boards/pll_hsi_fracn_550.overlay | 37 +++++++++++++++++++ .../stm32h7_core/testcase.yaml | 7 ++++ 2 files changed, 44 insertions(+) create mode 100644 tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay new file mode 100644 index 0000000000000..21ba087efbf2b --- /dev/null +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Kickmaker + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Warning: This overlay performs configuration from clean sheet. + * It is assumed that it is applied after clear_clocks.overlay file. + */ + +&clk_hsi { + hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ + status = "okay"; +}; + +&pll { + div-m = <4>; + mul-n = <34>; + div-p = <1>; + div-q = <4>; + div-r = <2>; + clocks = <&clk_hsi>; + fracn = <3072>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml index 8b868d3618a82..795de1a64bb5b 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml @@ -46,3 +46,10 @@ tests: - stm32h735g_disco integration_platforms: - nucleo_h723zg + drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_fracn_550: + extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_550.overlay" + platform_allow: + - nucleo_h723zg + - stm32h735g_disco + integration_platforms: + - nucleo_h723zg