From 0a47f17031222f62b3f587c44586dfa34c88c9ff Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 12 Sep 2024 15:05:52 +0300 Subject: [PATCH 1/3] west.yml: hal_nxp: update hash Update hal_nxp hash to point to the latest version. Signed-off-by: Laurentiu Mihalcea --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 49bc40e1e4f75..d75878bf083c6 100644 --- a/west.yml +++ b/west.yml @@ -198,7 +198,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 77815705c465627b8436cbac51f0bf0594bbeba2 + revision: 17aac63df44266c4ea0e111c731ca7664fe51e70 path: modules/hal/nxp groups: - hal From 44b05a272178226c25df903779ae4460bb4f9813 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 14 Aug 2024 16:15:11 +0300 Subject: [PATCH 2/3] drivers: dma: dma_nxp_edma: support MUX register in MP space Some EDMA versions may have the channel MUX register in the MP region. To support this scenario, use the `EDMA_HAS_MP_MUX_FLAG` flag to figure out which channel MUX register to use (TCD or MP). Signed-off-by: Laurentiu Mihalcea --- drivers/dma/dma_nxp_edma.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dma_nxp_edma.h b/drivers/dma/dma_nxp_edma.h index 6f4ac66948394..c96630a7186b8 100644 --- a/drivers/dma/dma_nxp_edma.h +++ b/drivers/dma/dma_nxp_edma.h @@ -417,6 +417,8 @@ static inline int edma_chan_cyclic_produce(struct edma_channel *chan, static inline void edma_dump_channel_registers(struct edma_data *data, uint32_t chan_id) { + uint32_t mux_reg; + LOG_DBG("dumping channel data for channel %d", chan_id); LOG_DBG("CH_CSR: 0x%x", @@ -431,8 +433,13 @@ static inline void edma_dump_channel_registers(struct edma_data *data, EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_PRI)); if (EDMA_HAS_MUX(data->hal_cfg)) { - LOG_DBG("CH_MUX: 0x%x", - EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_MUX)); + if (data->hal_cfg->flags & EDMA_HAS_MP_MUX_FLAG) { + mux_reg = EDMA_MP_CH_MUX; + } else { + mux_reg = EDMA_TCD_CH_MUX; + } + + LOG_DBG("CH_MUX: 0x%x", EDMA_ChannelRegRead(data->hal_cfg, chan_id, mux_reg)); } LOG_DBG("TCD_SADDR: 0x%x", From 7ab808e92391ae71df05167e4679522ad135af9d Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 14 Aug 2024 16:19:36 +0300 Subject: [PATCH 3/3] drivers: dma: dma_nxp_edma: support 64-bit TCD On some EDMA versions, some TCD registers (e.g: SADDR, DADDR, SLAST, DLAST, etc...) are extended to 64 bits via adding a new HIGH register holding the value of bits [63:32]. Since, for now, the driver doesn't support 64-bit addresses, this scenario is supported by sign-extending the 32-bit value written to SLAST/DLAST. SADDR and DADDR are taken care of on HAL side. Signed-off-by: Laurentiu Mihalcea --- drivers/dma/dma_nxp_edma.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/dma_nxp_edma.h b/drivers/dma/dma_nxp_edma.h index c96630a7186b8..ca345ad3fbe1e 100644 --- a/drivers/dma/dma_nxp_edma.h +++ b/drivers/dma/dma_nxp_edma.h @@ -514,6 +514,13 @@ static inline int set_slast_dlast(struct dma_config *dma_cfg, EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA, slast); EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA, dlast); + if (data->hal_cfg->flags & EDMA_HAS_64BIT_TCD_FLAG) { + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA_HIGH, + slast >= 0x0 ? 0x0 : 0xffffffff); + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA_HIGH, + dlast >= 0x0 ? 0x0 : 0xffffffff); + } + return 0; }