diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index e371198e6ed53..aa1e8f9435d3c 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -53,8 +53,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 49f35db2e8340..9ccde6acd8a38 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -53,8 +53,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index f076510018e93..21867f1dbe493 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -53,8 +53,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 682aafcd006b1..6e068eb55bd83 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -94,8 +94,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index f82d065911260..53fc329b0481f 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -60,8 +60,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 78407352e72d4..d498d6448e5fc 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -60,8 +60,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index 0cd4de22aa19d..141292d9f7e06 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -72,8 +72,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index f0f447eede7b5..866232d5c7fab 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -68,14 +68,14 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; &pclka { - clk-src = ; - clk-div = ; + clocks = <&pll>; + div = <2>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index ad84e26a1678f..3cb4ebe3ba59c 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -68,8 +68,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 698e90e631cd0..4449e566c2dc2 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -56,21 +56,21 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pll>; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index de64b9ecf252b..0e3b6ec3cd514 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -79,21 +79,21 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pll>; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 6f73498953965..2efab7438b50d 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -57,8 +57,8 @@ }; &pll { - source = ; - div = ; + clocks = <&hoco>; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index bc7baa6c5ceda..fbde0caf01395 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -76,8 +76,8 @@ }; &pll { - source = ; - div = ; + clocks = <&hoco>; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index f7046d4914901..6cd4cf53eb82e 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -60,21 +60,21 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pll>; + div = <4>; status = "okay"; }; diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index b03852fc86e1f..33d2f3e82d275 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -90,10 +90,11 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { #define INIT_PCLK(node_id) \ IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ - {.clk_src = DT_PROP_OR(node_id, clk_src, \ - DT_PROP_OR(DT_PARENT(node_id), sysclock_src, \ - RA_CLOCK_SOURCE_DISABLE)), \ - .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \ + {.clk_src = COND_CODE_1( \ + DT_NODE_HAS_PROP(node_id, clocks), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \ + .clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \ DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \ &node_id##_cfg, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 57d2c9201a1cc..8c60af4b83d87 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -25,7 +25,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -64,33 +64,33 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&hoco>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index ce2185e097cdf..3f403525ada59 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -83,8 +83,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -96,47 +96,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index d3e763b6e9ad1..6abfa96b0c85b 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -95,7 +95,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -132,8 +132,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -143,8 +143,7 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -156,47 +155,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 524ac63224106..fbfe3b5e36c5b 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -105,7 +105,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -142,8 +142,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -151,8 +151,7 @@ pll2: pll2 { compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - source = ; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -164,47 +163,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 2be6da132529b..4603b53044d22 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -40,7 +40,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -77,8 +77,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <12 0>; status = "disabled"; }; @@ -90,47 +90,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&hoco>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; @@ -143,7 +143,7 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index b92f8a3ead602..d8d31ceb55af1 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -95,7 +95,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -132,8 +132,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&hoco>; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -143,8 +143,7 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -156,47 +155,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 6af6db001f4df..d1d9bfad58d26 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -73,8 +73,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -86,47 +86,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index f8bbb0e154de0..2415350363beb 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -67,8 +67,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -80,47 +80,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -133,14 +133,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 5843d6c7ce899..db5488f79f2a0 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -98,8 +98,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -111,47 +111,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -164,14 +164,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index cf3d8e97bce71..0e233cd7d6fe4 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -101,7 +101,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -138,8 +138,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -151,47 +151,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -204,14 +204,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 3c5c308fb8162..da8000713620f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -131,7 +131,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -168,8 +168,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -179,8 +179,7 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -192,47 +191,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -245,7 +244,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 2b1fe78cbd21c..e266560fb5ff1 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -191,7 +191,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -228,8 +228,8 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -239,8 +239,7 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -252,47 +251,47 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -305,7 +304,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 89beb25bc7bf3..3db4898ccb2f7 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -49,14 +49,14 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,14 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -85,61 +84,61 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -152,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 164928c4cd4b6..cb22fd3357a51 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -49,14 +49,14 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,14 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -85,61 +84,61 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -152,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 51a07401b23d8..de851f6bf47e4 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -49,14 +49,14 @@ #clock-cells = <0>; /* PLL */ - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,14 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - source = ; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -85,61 +84,61 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -152,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml index 6380b712984d4..d455a1e83f74c 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml @@ -8,6 +8,5 @@ compatible: "renesas,ra-cgc-pclk-block" include: [clock-controller.yaml, base.yaml] properties: - sysclock-src: + clocks: required: true - type: int diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml index 5ea4d708894fe..798b1d3569f52 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -8,10 +8,7 @@ compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] properties: - clk-src: - type: int - - clk-div: + div: type: int required: true description: Prescale divider to calculate the subclock frequency from the diff --git a/dts/bindings/clock/renesas,ra-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml index a974f54c075b9..7c959b6a01db5 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pll.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml @@ -8,9 +8,8 @@ compatible: "renesas,ra-cgc-pll" include: [clock-controller.yaml, base.yaml] properties: - source: + clocks: required: true - type: int div: required: true type: int diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index b675b42ec7a61..917369c632c60 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -523,6 +523,92 @@ */ #define DT_NODE_FULL_NAME(node_id) DT_CAT(node_id, _FULL_NAME) +/** + * @brief Get the node's full name, including the unit-address, as an unquoted + * sequence of tokens + * + * This macro returns removed "the quotes" from the node's full name. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UNQUOTED(DT_NODELABEL(node)) // my-node@12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a sequence of tokens, + * with no quotes + */ +#define DT_NODE_FULL_NAME_UNQUOTED(node_id) DT_CAT(node_id, _FULL_NAME_UNQUOTED) + +/** + * @brief Get the node's full name, including the unit-address, as a token. + * + * This macro returns removed "the quotes" from the node's full name and + * converting any non-alphanumeric characters to underscores. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_TOKEN(DT_NODELABEL(node)) // my_node_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a token, i.e. without any quotes + * and with special characters converted to underscores + */ +#define DT_NODE_FULL_NAME_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_TOKEN) + +/** + * @brief Like DT_NODE_FULL_NAME_TOKEN(), but uppercased. + * + * This macro returns removed "the quotes" from the node's full name, + * converting any non-alphanumeric characters to underscores, and + * capitalizing the result. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UPPER_TOKEN(DT_NODELABEL(node)) // MY_NODE_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as an uppercased token, + * i.e. without any quotes and with special characters converted + * to underscores + */ +#define DT_NODE_FULL_NAME_UPPER_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_UPPER_TOKEN) + /** * @brief Get a devicetree node's index into its parent's list of children * diff --git a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h index 2e551256e8502..a7f147382fdc0 100644 --- a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h @@ -9,6 +9,52 @@ #include #include +#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) + +#define RA_CGC_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (BSP_CLOCKS_CLOCK_DISABLED)) + +#define RA_CGC_CLK_DIV(clk, prop, default_value) \ + UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ + (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value)) + +#define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n) +#define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n) +#define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n) +#define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n) +#define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n) +#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) +#define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) +#define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) +#define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) + +#define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL + +#define BSP_CLOCKS_CLKOUT_DIV_1 (0) +#define BSP_CLOCKS_CLKOUT_DIV_2 (1) +#define BSP_CLOCKS_CLKOUT_DIV_4 (2) +#define BSP_CLOCKS_CLKOUT_DIV_8 (3) +#define BSP_CLOCKS_CLKOUT_DIV_16 (4) +#define BSP_CLOCKS_CLKOUT_DIV_32 (5) +#define BSP_CLOCKS_CLKOUT_DIV_64 (6) +#define BSP_CLOCKS_CLKOUT_DIV_128 (7) + struct clock_control_ra_pclk_cfg { uint32_t clk_src; uint32_t clk_div; diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h index d88b1b93646b7..97fc2e41b5600 100644 --- a/include/zephyr/dt-bindings/clock/ra_clock.h +++ b/include/zephyr/dt-bindings/clock/ra_clock.h @@ -7,136 +7,6 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ -#define RA_PLL_SOURCE_HOCO 0 -#define RA_PLL_SOURCE_MOCO 1 -#define RA_PLL_SOURCE_LOCO 2 -#define RA_PLL_SOURCE_MAIN_OSC 3 -#define RA_PLL_SOURCE_SUBCLOCK 4 -#define RA_PLL_SOURCE_DISABLE 0xff - -#define RA_CLOCK_SOURCE_HOCO 0 -#define RA_CLOCK_SOURCE_MOCO 1 -#define RA_CLOCK_SOURCE_LOCO 2 -#define RA_CLOCK_SOURCE_MAIN_OSC 3 -#define RA_CLOCK_SOURCE_SUBCLOCK 4 -#define RA_CLOCK_SOURCE_PLL 5 -#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL -#define RA_CLOCK_SOURCE_PLL2 6 -#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2 -#define RA_CLOCK_SOURCE_PLL1Q 7 -#define RA_CLOCK_SOURCE_PLL1R 8 -#define RA_CLOCK_SOURCE_PLL2Q 9 -#define RA_CLOCK_SOURCE_PLL2R 10 -#define RA_CLOCK_SOURCE_DISABLE 0xff - -#define RA_SYS_CLOCK_DIV_1 0 -#define RA_SYS_CLOCK_DIV_2 1 -#define RA_SYS_CLOCK_DIV_4 2 -#define RA_SYS_CLOCK_DIV_8 3 -#define RA_SYS_CLOCK_DIV_16 4 -#define RA_SYS_CLOCK_DIV_32 5 -#define RA_SYS_CLOCK_DIV_64 6 -#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */ -#define RA_SYS_CLOCK_DIV_3 8 -#define RA_SYS_CLOCK_DIV_6 9 -#define RA_SYS_CLOCK_DIV_12 10 - -/* PLL divider options. */ -#define RA_PLL_DIV_1 0 -#define RA_PLL_DIV_2 1 -#define RA_PLL_DIV_3 2 -#define RA_PLL_DIV_4 3 -#define RA_PLL_DIV_5 4 -#define RA_PLL_DIV_6 5 -#define RA_PLL_DIV_8 7 -#define RA_PLL_DIV_9 8 -#define RA_PLL_DIV_16 15 - -/* USB clock divider options. */ -#define RA_USB_CLOCK_DIV_1 0 -#define RA_USB_CLOCK_DIV_2 1 -#define RA_USB_CLOCK_DIV_3 2 -#define RA_USB_CLOCK_DIV_4 3 -#define RA_USB_CLOCK_DIV_5 4 -#define RA_USB_CLOCK_DIV_6 5 -#define RA_USB_CLOCK_DIV_8 7 - -/* USB60 clock divider options. */ -#define RA_USB60_CLOCK_DIV_1 0 -#define RA_USB60_CLOCK_DIV_2 1 -#define RA_USB60_CLOCK_DIV_3 5 -#define RA_USB60_CLOCK_DIV_4 2 -#define RA_USB60_CLOCK_DIV_5 6 -#define RA_USB60_CLOCK_DIV_6 3 -#define RA_USB60_CLOCK_DIV_8 4 - -/* OCTA clock divider options. */ -#define RA_OCTA_CLOCK_DIV_1 0 -#define RA_OCTA_CLOCK_DIV_2 1 -#define RA_OCTA_CLOCK_DIV_4 2 -#define RA_OCTA_CLOCK_DIV_6 3 -#define RA_OCTA_CLOCK_DIV_8 4 - -/* CANFD clock divider options. */ -#define RA_CANFD_CLOCK_DIV_1 0 -#define RA_CANFD_CLOCK_DIV_2 1 -#define RA_CANFD_CLOCK_DIV_3 5 -#define RA_CANFD_CLOCK_DIV_4 2 -#define RA_CANFD_CLOCK_DIV_5 6 -#define RA_CANFD_CLOCK_DIV_6 3 -#define RA_CANFD_CLOCK_DIV_8 4 - -/* SCI clock divider options. */ -#define RA_SCI_CLOCK_DIV_1 0 -#define RA_SCI_CLOCK_DIV_2 1 -#define RA_SCI_CLOCK_DIV_3 5 -#define RA_SCI_CLOCK_DIV_4 2 -#define RA_SCI_CLOCK_DIV_5 6 -#define RA_SCI_CLOCK_DIV_6 3 -#define RA_SCI_CLOCK_DIV_8 4 - -/* SPI clock divider options. */ -#define RA_SPI_CLOCK_DIV_1 0 -#define RA_SPI_CLOCK_DIV_2 1 -#define RA_SPI_CLOCK_DIV_3 5 -#define RA_SPI_CLOCK_DIV_4 2 -#define RA_SPI_CLOCK_DIV_5 6 -#define RA_SPI_CLOCK_DIV_6 3 -#define RA_SPI_CLOCK_DIV_8 4 - -/* CEC clock divider options. */ -#define RA_CEC_CLOCK_DIV_1 0 -#define RA_CEC_CLOCK_DIV_2 1 - -/* I3C clock divider options. */ -#define RA_I3C_CLOCK_DIV_1 0 -#define RA_I3C_CLOCK_DIV_2 1 -#define RA_I3C_CLOCK_DIV_3 5 -#define RA_I3C_CLOCK_DIV_4 2 -#define RA_I3C_CLOCK_DIV_5 6 -#define RA_I3C_CLOCK_DIV_6 3 -#define RA_I3C_CLOCK_DIV_8 4 - -/* LCD clock divider options. */ -#define RA_LCD_CLOCK_DIV_1 0 -#define RA_LCD_CLOCK_DIV_2 1 -#define RA_LCD_CLOCK_DIV_3 5 -#define RA_LCD_CLOCK_DIV_4 2 -#define RA_LCD_CLOCK_DIV_5 6 -#define RA_LCD_CLOCK_DIV_6 3 -#define RA_LCD_CLOCK_DIV_8 4 - -/* SDADC clock divider options. */ -#define RA_SDADC_CLOCK_DIV_1 0 -#define RA_SDADC_CLOCK_DIV_2 1 -#define RA_SDADC_CLOCK_DIV_3 2 -#define RA_SDADC_CLOCK_DIV_4 3 -#define RA_SDADC_CLOCK_DIV_5 4 -#define RA_SDADC_CLOCK_DIV_6 5 -#define RA_SDADC_CLOCK_DIV_8 6 -#define RA_SDADC_CLOCK_DIV_12 7 -#define RA_SDADC_CLOCK_DIV_16 8 - #define MSTPA 0 #define MSTPB 1 #define MSTPC 2 diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py index fda61526dc85c..555c3c7e54e6a 100755 --- a/scripts/dts/gen_defines.py +++ b/scripts/dts/gen_defines.py @@ -74,6 +74,12 @@ def main(): out_comment("Node's name with unit-address:") out_dt_define(f"{node.z_path_id}_FULL_NAME", f'"{escape(node.name)}"') + out_dt_define(f"{node.z_path_id}_FULL_NAME_UNQUOTED", + f'{escape(node.name)}') + out_dt_define(f"{node.z_path_id}_FULL_NAME_TOKEN", + f'{edtlib.str_as_token(escape(node.name))}') + out_dt_define(f"{node.z_path_id}_FULL_NAME_UPPER_TOKEN", + f'{edtlib.str_as_token(escape(node.name)).upper()}') if node.parent is not None: out_comment(f"Node parent ({node.parent.path}) identifier:") diff --git a/west.yml b/west.yml index 34825f3557909..9ab47ac517987 100644 --- a/west.yml +++ b/west.yml @@ -214,7 +214,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 1ec88911defaba8aebe265d57497cacfbb6afeb8 + revision: 3dafd030046f8d6f8a26080e9b9c1bcc92d45999 groups: - hal - name: hal_rpi_pico