From 528f6a1b8d8c1d3882a0a7c3f56edab4a3c7f5dd Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Fri, 13 Sep 2024 06:52:58 +0900 Subject: [PATCH 1/6] west.yml: Update revision of hal_renesas Update HAL to improve the BSP clock setting process. Signed-off-by: TOKITA Hiroshi --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 34825f3557909..9ab47ac517987 100644 --- a/west.yml +++ b/west.yml @@ -214,7 +214,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 1ec88911defaba8aebe265d57497cacfbb6afeb8 + revision: 3dafd030046f8d6f8a26080e9b9c1bcc92d45999 groups: - hal - name: hal_rpi_pico From 0206c843b02b6d3737d9f135f2fb84627ddc3e97 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 12 Sep 2024 22:58:53 +0900 Subject: [PATCH 2/6] devicetree: Adding UNQUOTED, TOKEN, and UPPERTOKEN variants of FULL_NAME Like some other string properties, I will add a derived form to FULL_NAME to make it easier to reference from macros. Signed-off-by: TOKITA Hiroshi --- include/zephyr/devicetree.h | 86 +++++++++++++++++++++++++++++++++++++ scripts/dts/gen_defines.py | 6 +++ 2 files changed, 92 insertions(+) diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index b675b42ec7a61..917369c632c60 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -523,6 +523,92 @@ */ #define DT_NODE_FULL_NAME(node_id) DT_CAT(node_id, _FULL_NAME) +/** + * @brief Get the node's full name, including the unit-address, as an unquoted + * sequence of tokens + * + * This macro returns removed "the quotes" from the node's full name. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UNQUOTED(DT_NODELABEL(node)) // my-node@12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a sequence of tokens, + * with no quotes + */ +#define DT_NODE_FULL_NAME_UNQUOTED(node_id) DT_CAT(node_id, _FULL_NAME_UNQUOTED) + +/** + * @brief Get the node's full name, including the unit-address, as a token. + * + * This macro returns removed "the quotes" from the node's full name and + * converting any non-alphanumeric characters to underscores. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_TOKEN(DT_NODELABEL(node)) // my_node_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a token, i.e. without any quotes + * and with special characters converted to underscores + */ +#define DT_NODE_FULL_NAME_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_TOKEN) + +/** + * @brief Like DT_NODE_FULL_NAME_TOKEN(), but uppercased. + * + * This macro returns removed "the quotes" from the node's full name, + * converting any non-alphanumeric characters to underscores, and + * capitalizing the result. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UPPER_TOKEN(DT_NODELABEL(node)) // MY_NODE_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as an uppercased token, + * i.e. without any quotes and with special characters converted + * to underscores + */ +#define DT_NODE_FULL_NAME_UPPER_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_UPPER_TOKEN) + /** * @brief Get a devicetree node's index into its parent's list of children * diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py index fda61526dc85c..555c3c7e54e6a 100755 --- a/scripts/dts/gen_defines.py +++ b/scripts/dts/gen_defines.py @@ -74,6 +74,12 @@ def main(): out_comment("Node's name with unit-address:") out_dt_define(f"{node.z_path_id}_FULL_NAME", f'"{escape(node.name)}"') + out_dt_define(f"{node.z_path_id}_FULL_NAME_UNQUOTED", + f'{escape(node.name)}') + out_dt_define(f"{node.z_path_id}_FULL_NAME_TOKEN", + f'{edtlib.str_as_token(escape(node.name))}') + out_dt_define(f"{node.z_path_id}_FULL_NAME_UPPER_TOKEN", + f'{edtlib.str_as_token(escape(node.name)).upper()}') if node.parent is not None: out_comment(f"Node parent ({node.parent.path}) identifier:") From 3358e07d246f97c28c6466ba7a4839564803bdf2 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 11 Sep 2024 20:07:20 +0900 Subject: [PATCH 3/6] dts: renesas_ra: Rename dts node path Changes the path name of a DTS node so that it can be used as the stem of a BSP macro. All nodes to be changed are referenced via labels, so only the name is changed. Signed-off-by: TOKITA Hiroshi --- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 2 +- dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 2 +- dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 2 +- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 57d2c9201a1cc..9139417ea2824 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -25,7 +25,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index ce2185e097cdf..df7ee812a6919 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index d3e763b6e9ad1..333d70db07820 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -95,7 +95,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 524ac63224106..5bb6a46e5650b 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -105,7 +105,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 2be6da132529b..a6cd0df5edc9f 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -40,7 +40,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index b92f8a3ead602..9e3dfe76ba6f7 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -95,7 +95,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 6af6db001f4df..963ba9a468044 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index f8bbb0e154de0..cb849f005c91f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 5843d6c7ce899..ab689fd8f7896 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index cf3d8e97bce71..0870f6d42bb1d 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -101,7 +101,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 3c5c308fb8162..8f39ca62bf545 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -131,7 +131,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 2b1fe78cbd21c..12a95cef6248f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -191,7 +191,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 89beb25bc7bf3..2bd14bd072373 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 51a07401b23d8..621239f85b625 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; From 20d359f922732146039819a634c8d84b564b8048 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 12 Sep 2024 23:04:31 +0900 Subject: [PATCH 4/6] dts: renesas_ra: Referencing clocks change to DeviceTree's standard. DeviceTree typically references the clock source using the `clocks` property defined in `base.yaml`, so we'll change it to this. Also delete the custom clock source definitions in `renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and `renesas,ra-cgc-pll.yaml`. Signed-off-by: TOKITA Hiroshi --- boards/renesas/ek_ra4e2/ek_ra4e2.dts | 2 +- boards/renesas/ek_ra4m2/ek_ra4m2.dts | 2 +- boards/renesas/ek_ra4m3/ek_ra4m3.dts | 2 +- boards/renesas/ek_ra6e2/ek_ra6e2.dts | 2 +- boards/renesas/ek_ra6m1/ek_ra6m1.dts | 2 +- boards/renesas/ek_ra6m2/ek_ra6m2.dts | 2 +- boards/renesas/ek_ra6m3/ek_ra6m3.dts | 2 +- boards/renesas/ek_ra6m4/ek_ra6m4.dts | 4 ++-- boards/renesas/ek_ra6m5/ek_ra6m5.dts | 2 +- boards/renesas/ek_ra8d1/ek_ra8d1.dts | 4 ++-- boards/renesas/ek_ra8m1/ek_ra8m1.dts | 4 ++-- boards/renesas/fpb_ra6e1/fpb_ra6e1.dts | 2 +- boards/renesas/fpb_ra6e2/fpb_ra6e2.dts | 2 +- boards/renesas/mck_ra8t1/mck_ra8t1.dts | 4 ++-- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 4 ++-- dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 5 ++--- dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 5 ++--- dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 4 ++-- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 5 ++--- dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 4 ++-- dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 4 ++-- dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 4 ++-- dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 4 ++-- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 5 ++--- dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 5 ++--- dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 5 ++--- dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi | 5 ++--- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 5 ++--- dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml | 3 +-- dts/bindings/clock/renesas,ra-cgc-pclk.yaml | 3 --- dts/bindings/clock/renesas,ra-cgc-pll.yaml | 3 +-- 32 files changed, 49 insertions(+), 62 deletions(-) diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index e371198e6ed53..2bf7a9d3ff0e6 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -53,7 +53,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <10 0>; status = "okay"; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 49f35db2e8340..9cb8d8b77bb95 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -53,7 +53,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "okay"; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index f076510018e93..09701ac99236f 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -53,7 +53,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "okay"; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 682aafcd006b1..29571eb28a20e 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -94,7 +94,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <10 0>; status = "okay"; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index f82d065911260..631f2d1384c9d 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -60,7 +60,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "okay"; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 78407352e72d4..19721a46a2019 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -60,7 +60,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "okay"; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index 0cd4de22aa19d..db9031340a99c 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -72,7 +72,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "okay"; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index f0f447eede7b5..b156f6f1e52bb 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -68,14 +68,14 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "okay"; }; &pclka { - clk-src = ; + clocks = <&pll>; clk-div = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index ad84e26a1678f..902e281984ec9 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -68,7 +68,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "okay"; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 698e90e631cd0..e17bf02718cf1 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -56,7 +56,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <96 0>; divp = ; @@ -69,7 +69,7 @@ }; &sciclk { - clk-src = ; + clocks = <&pll>; clk-div = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index de64b9ecf252b..df94f202a15b0 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -79,7 +79,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <96 0>; divp = ; @@ -92,7 +92,7 @@ }; &sciclk { - clk-src = ; + clocks = <&pll>; clk-div = ; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 6f73498953965..b0aa5b48f0844 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -57,7 +57,7 @@ }; &pll { - source = ; + clocks = <&hoco>; div = ; mul = <20 0>; status = "okay"; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index bc7baa6c5ceda..847f55288132d 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -76,7 +76,7 @@ }; &pll { - source = ; + clocks = <&hoco>; div = ; mul = <10 0>; status = "okay"; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index f7046d4914901..ea06022287937 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -60,7 +60,7 @@ }; &pll { - source = ; + clocks = <&xtal>; div = ; mul = <80 0>; divp = ; @@ -73,7 +73,7 @@ }; &sciclk { - clk-src = ; + clocks = <&pll>; clk-div = ; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 9139417ea2824..bb23016381609 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -64,7 +64,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&hoco>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index df7ee812a6919..6feb69d4a43da 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -83,7 +83,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <10 0>; status = "disabled"; @@ -96,7 +96,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 333d70db07820..7ed9fdabd78b9 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -132,7 +132,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "disabled"; @@ -143,7 +143,6 @@ #clock-cells = <0>; /* PLL */ - source = ; div = ; mul = <20 0>; status = "disabled"; @@ -156,7 +155,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 5bb6a46e5650b..1277844b1b8e2 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -142,7 +142,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "disabled"; @@ -151,7 +151,6 @@ pll2: pll2 { compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - source = ; div = ; mul = <20 0>; status = "disabled"; @@ -164,7 +163,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index a6cd0df5edc9f..93ea6751e9ca8 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -77,7 +77,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <12 0>; status = "disabled"; @@ -90,7 +90,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&hoco>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 9e3dfe76ba6f7..b070022ee5f4a 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -132,7 +132,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&hoco>; div = ; mul = <20 0>; status = "disabled"; @@ -143,7 +143,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <20 0>; status = "disabled"; @@ -156,7 +155,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 963ba9a468044..7576bb0dcd332 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -73,7 +73,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <10 0>; status = "disabled"; @@ -86,7 +86,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index cb849f005c91f..af17716832164 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -67,7 +67,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "disabled"; @@ -80,7 +80,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index ab689fd8f7896..a06241a95b3f4 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -98,7 +98,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "disabled"; @@ -111,7 +111,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index 0870f6d42bb1d..197be43a3fc2b 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -138,7 +138,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <20 0>; status = "disabled"; @@ -151,7 +151,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 8f39ca62bf545..0310f61e65db8 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -168,7 +168,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "disabled"; @@ -179,7 +179,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <20 0>; status = "disabled"; @@ -192,7 +191,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 12a95cef6248f..91d95e288d83b 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -228,7 +228,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <25 0>; status = "disabled"; @@ -239,7 +239,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <20 0>; status = "disabled"; @@ -252,7 +251,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 2bd14bd072373..5b00642bae339 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -49,7 +49,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <96 0>; divp = ; @@ -66,7 +66,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <96 0>; divp = ; @@ -85,7 +84,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 164928c4cd4b6..c184c1432e208 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -49,7 +49,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <96 0>; divp = ; @@ -66,7 +66,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <96 0>; divp = ; @@ -85,7 +84,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 621239f85b625..3f4fb717f354f 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -49,7 +49,7 @@ #clock-cells = <0>; /* PLL */ - source = ; + clocks = <&xtal>; div = ; mul = <80 0>; divp = ; @@ -66,7 +66,6 @@ #clock-cells = <0>; /* PLL2 */ - source = ; div = ; mul = <96 0>; divp = ; @@ -85,7 +84,7 @@ reg-names = "MSTPA", "MSTPB","MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; cpuclk: cpuclk { diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml index 6380b712984d4..d455a1e83f74c 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml @@ -8,6 +8,5 @@ compatible: "renesas,ra-cgc-pclk-block" include: [clock-controller.yaml, base.yaml] properties: - sysclock-src: + clocks: required: true - type: int diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml index 5ea4d708894fe..1aac515882d74 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -8,9 +8,6 @@ compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] properties: - clk-src: - type: int - clk-div: type: int required: true diff --git a/dts/bindings/clock/renesas,ra-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml index a974f54c075b9..7c959b6a01db5 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pll.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml @@ -8,9 +8,8 @@ compatible: "renesas,ra-cgc-pll" include: [clock-controller.yaml, base.yaml] properties: - source: + clocks: required: true - type: int div: required: true type: int From 45a141f1c6c3681b645068ef872c932e9e5a1f46 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 12 Sep 2024 23:15:27 +0900 Subject: [PATCH 5/6] dts: renesas_ra: Change to describe the division ratio in a numeric Move the process of replacing numerical values with macros to the header, and set the division ratio in a numeric without using macros in the device tree. Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`. Signed-off-by: TOKITA Hiroshi --- boards/renesas/ek_ra4e2/ek_ra4e2.dts | 2 +- boards/renesas/ek_ra4m2/ek_ra4m2.dts | 2 +- boards/renesas/ek_ra4m3/ek_ra4m3.dts | 2 +- boards/renesas/ek_ra6e2/ek_ra6e2.dts | 2 +- boards/renesas/ek_ra6m1/ek_ra6m1.dts | 2 +- boards/renesas/ek_ra6m2/ek_ra6m2.dts | 2 +- boards/renesas/ek_ra6m3/ek_ra6m3.dts | 2 +- boards/renesas/ek_ra6m4/ek_ra6m4.dts | 4 +-- boards/renesas/ek_ra6m5/ek_ra6m5.dts | 2 +- boards/renesas/ek_ra8d1/ek_ra8d1.dts | 10 +++--- boards/renesas/ek_ra8m1/ek_ra8m1.dts | 10 +++--- boards/renesas/fpb_ra6e1/fpb_ra6e1.dts | 2 +- boards/renesas/fpb_ra6e2/fpb_ra6e2.dts | 2 +- boards/renesas/mck_ra8t1/mck_ra8t1.dts | 10 +++--- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 8 ++--- dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 14 ++++---- dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 16 ++++----- dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 16 ++++----- dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 16 ++++----- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 16 ++++----- dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 14 ++++---- dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 18 +++++------ dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 18 +++++------ dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 18 +++++------ dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 18 +++++------ dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 18 +++++------ dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 34 +++++++++---------- dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi | 36 ++++++++++----------- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 34 +++++++++---------- dts/bindings/clock/renesas,ra-cgc-pclk.yaml | 2 +- 30 files changed, 175 insertions(+), 175 deletions(-) diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 2bf7a9d3ff0e6..aa1e8f9435d3c 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 9cb8d8b77bb95..9ccde6acd8a38 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index 09701ac99236f..21867f1dbe493 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 29571eb28a20e..6e068eb55bd83 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -95,7 +95,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index 631f2d1384c9d..53fc329b0481f 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -61,7 +61,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 19721a46a2019..d498d6448e5fc 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -61,7 +61,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index db9031340a99c..141292d9f7e06 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -73,7 +73,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index b156f6f1e52bb..866232d5c7fab 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -69,13 +69,13 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; &pclka { clocks = <&pll>; - clk-div = ; + div = <2>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index 902e281984ec9..3cb4ebe3ba59c 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -69,7 +69,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index e17bf02718cf1..4449e566c2dc2 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -57,20 +57,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index df94f202a15b0..0e3b6ec3cd514 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -80,20 +80,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index b0aa5b48f0844..2efab7438b50d 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -58,7 +58,7 @@ &pll { clocks = <&hoco>; - div = ; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index 847f55288132d..fbde0caf01395 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -77,7 +77,7 @@ &pll { clocks = <&hoco>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index ea06022287937..6cd4cf53eb82e 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -61,20 +61,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index bb23016381609..8c60af4b83d87 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -69,28 +69,28 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 6feb69d4a43da..3f403525ada59 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -84,7 +84,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -101,42 +101,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 7ed9fdabd78b9..6abfa96b0c85b 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -133,7 +133,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -143,7 +143,7 @@ #clock-cells = <0>; /* PLL */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -160,42 +160,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 1277844b1b8e2..fbfe3b5e36c5b 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -143,7 +143,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -151,7 +151,7 @@ pll2: pll2 { compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -168,42 +168,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 93ea6751e9ca8..4603b53044d22 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -78,7 +78,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <12 0>; status = "disabled"; }; @@ -95,42 +95,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; @@ -143,7 +143,7 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index b070022ee5f4a..d8d31ceb55af1 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -133,7 +133,7 @@ /* PLL */ clocks = <&hoco>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -143,7 +143,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -160,42 +160,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 7576bb0dcd332..d1d9bfad58d26 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -74,7 +74,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -91,42 +91,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index af17716832164..2415350363beb 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -68,7 +68,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -85,42 +85,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -133,14 +133,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index a06241a95b3f4..db5488f79f2a0 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -99,7 +99,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -116,42 +116,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -164,14 +164,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index 197be43a3fc2b..0e233cd7d6fe4 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -139,7 +139,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -156,42 +156,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -204,14 +204,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 0310f61e65db8..da8000713620f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -169,7 +169,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -179,7 +179,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -196,42 +196,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -244,7 +244,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 91d95e288d83b..e266560fb5ff1 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -229,7 +229,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -239,7 +239,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -256,42 +256,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -304,7 +304,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 5b00642bae339..3db4898ccb2f7 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index c184c1432e208..cb22fd3357a51 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 3f4fb717f354f..de851f6bf47e4 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml index 1aac515882d74..798b1d3569f52 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -8,7 +8,7 @@ compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] properties: - clk-div: + div: type: int required: true description: Prescale divider to calculate the subclock frequency from the From 9c5ef6b5e8304aa446a1d6c6e007c50166ed46b3 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 12 Sep 2024 23:23:33 +0900 Subject: [PATCH 6/6] drivers: clock_control: renesas_ra: Adding macros to convert DT values Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive the BSP clock settings from the DeviceTree node settings. I also define some aliases to fill in the gaps with the BSP naming conventions. Signed-off-by: TOKITA Hiroshi --- .../clock_control_renesas_ra_cgc.c | 9 +- .../drivers/clock_control/renesas_ra_cgc.h | 46 +++++++ include/zephyr/dt-bindings/clock/ra_clock.h | 130 ------------------ 3 files changed, 51 insertions(+), 134 deletions(-) diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index b03852fc86e1f..33d2f3e82d275 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -90,10 +90,11 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { #define INIT_PCLK(node_id) \ IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ - {.clk_src = DT_PROP_OR(node_id, clk_src, \ - DT_PROP_OR(DT_PARENT(node_id), sysclock_src, \ - RA_CLOCK_SOURCE_DISABLE)), \ - .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \ + {.clk_src = COND_CODE_1( \ + DT_NODE_HAS_PROP(node_id, clocks), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \ + (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \ + .clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \ DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \ &node_id##_cfg, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ diff --git a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h index 2e551256e8502..a7f147382fdc0 100644 --- a/include/zephyr/drivers/clock_control/renesas_ra_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_ra_cgc.h @@ -9,6 +9,52 @@ #include #include +#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) + +#define RA_CGC_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (BSP_CLOCKS_CLOCK_DISABLED)) + +#define RA_CGC_CLK_DIV(clk, prop, default_value) \ + UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ + (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value)) + +#define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n) +#define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n) +#define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n) +#define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n) +#define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n) +#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) +#define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) +#define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) +#define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) + +#define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL + +#define BSP_CLOCKS_CLKOUT_DIV_1 (0) +#define BSP_CLOCKS_CLKOUT_DIV_2 (1) +#define BSP_CLOCKS_CLKOUT_DIV_4 (2) +#define BSP_CLOCKS_CLKOUT_DIV_8 (3) +#define BSP_CLOCKS_CLKOUT_DIV_16 (4) +#define BSP_CLOCKS_CLKOUT_DIV_32 (5) +#define BSP_CLOCKS_CLKOUT_DIV_64 (6) +#define BSP_CLOCKS_CLKOUT_DIV_128 (7) + struct clock_control_ra_pclk_cfg { uint32_t clk_src; uint32_t clk_div; diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h index d88b1b93646b7..97fc2e41b5600 100644 --- a/include/zephyr/dt-bindings/clock/ra_clock.h +++ b/include/zephyr/dt-bindings/clock/ra_clock.h @@ -7,136 +7,6 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ -#define RA_PLL_SOURCE_HOCO 0 -#define RA_PLL_SOURCE_MOCO 1 -#define RA_PLL_SOURCE_LOCO 2 -#define RA_PLL_SOURCE_MAIN_OSC 3 -#define RA_PLL_SOURCE_SUBCLOCK 4 -#define RA_PLL_SOURCE_DISABLE 0xff - -#define RA_CLOCK_SOURCE_HOCO 0 -#define RA_CLOCK_SOURCE_MOCO 1 -#define RA_CLOCK_SOURCE_LOCO 2 -#define RA_CLOCK_SOURCE_MAIN_OSC 3 -#define RA_CLOCK_SOURCE_SUBCLOCK 4 -#define RA_CLOCK_SOURCE_PLL 5 -#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL -#define RA_CLOCK_SOURCE_PLL2 6 -#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2 -#define RA_CLOCK_SOURCE_PLL1Q 7 -#define RA_CLOCK_SOURCE_PLL1R 8 -#define RA_CLOCK_SOURCE_PLL2Q 9 -#define RA_CLOCK_SOURCE_PLL2R 10 -#define RA_CLOCK_SOURCE_DISABLE 0xff - -#define RA_SYS_CLOCK_DIV_1 0 -#define RA_SYS_CLOCK_DIV_2 1 -#define RA_SYS_CLOCK_DIV_4 2 -#define RA_SYS_CLOCK_DIV_8 3 -#define RA_SYS_CLOCK_DIV_16 4 -#define RA_SYS_CLOCK_DIV_32 5 -#define RA_SYS_CLOCK_DIV_64 6 -#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */ -#define RA_SYS_CLOCK_DIV_3 8 -#define RA_SYS_CLOCK_DIV_6 9 -#define RA_SYS_CLOCK_DIV_12 10 - -/* PLL divider options. */ -#define RA_PLL_DIV_1 0 -#define RA_PLL_DIV_2 1 -#define RA_PLL_DIV_3 2 -#define RA_PLL_DIV_4 3 -#define RA_PLL_DIV_5 4 -#define RA_PLL_DIV_6 5 -#define RA_PLL_DIV_8 7 -#define RA_PLL_DIV_9 8 -#define RA_PLL_DIV_16 15 - -/* USB clock divider options. */ -#define RA_USB_CLOCK_DIV_1 0 -#define RA_USB_CLOCK_DIV_2 1 -#define RA_USB_CLOCK_DIV_3 2 -#define RA_USB_CLOCK_DIV_4 3 -#define RA_USB_CLOCK_DIV_5 4 -#define RA_USB_CLOCK_DIV_6 5 -#define RA_USB_CLOCK_DIV_8 7 - -/* USB60 clock divider options. */ -#define RA_USB60_CLOCK_DIV_1 0 -#define RA_USB60_CLOCK_DIV_2 1 -#define RA_USB60_CLOCK_DIV_3 5 -#define RA_USB60_CLOCK_DIV_4 2 -#define RA_USB60_CLOCK_DIV_5 6 -#define RA_USB60_CLOCK_DIV_6 3 -#define RA_USB60_CLOCK_DIV_8 4 - -/* OCTA clock divider options. */ -#define RA_OCTA_CLOCK_DIV_1 0 -#define RA_OCTA_CLOCK_DIV_2 1 -#define RA_OCTA_CLOCK_DIV_4 2 -#define RA_OCTA_CLOCK_DIV_6 3 -#define RA_OCTA_CLOCK_DIV_8 4 - -/* CANFD clock divider options. */ -#define RA_CANFD_CLOCK_DIV_1 0 -#define RA_CANFD_CLOCK_DIV_2 1 -#define RA_CANFD_CLOCK_DIV_3 5 -#define RA_CANFD_CLOCK_DIV_4 2 -#define RA_CANFD_CLOCK_DIV_5 6 -#define RA_CANFD_CLOCK_DIV_6 3 -#define RA_CANFD_CLOCK_DIV_8 4 - -/* SCI clock divider options. */ -#define RA_SCI_CLOCK_DIV_1 0 -#define RA_SCI_CLOCK_DIV_2 1 -#define RA_SCI_CLOCK_DIV_3 5 -#define RA_SCI_CLOCK_DIV_4 2 -#define RA_SCI_CLOCK_DIV_5 6 -#define RA_SCI_CLOCK_DIV_6 3 -#define RA_SCI_CLOCK_DIV_8 4 - -/* SPI clock divider options. */ -#define RA_SPI_CLOCK_DIV_1 0 -#define RA_SPI_CLOCK_DIV_2 1 -#define RA_SPI_CLOCK_DIV_3 5 -#define RA_SPI_CLOCK_DIV_4 2 -#define RA_SPI_CLOCK_DIV_5 6 -#define RA_SPI_CLOCK_DIV_6 3 -#define RA_SPI_CLOCK_DIV_8 4 - -/* CEC clock divider options. */ -#define RA_CEC_CLOCK_DIV_1 0 -#define RA_CEC_CLOCK_DIV_2 1 - -/* I3C clock divider options. */ -#define RA_I3C_CLOCK_DIV_1 0 -#define RA_I3C_CLOCK_DIV_2 1 -#define RA_I3C_CLOCK_DIV_3 5 -#define RA_I3C_CLOCK_DIV_4 2 -#define RA_I3C_CLOCK_DIV_5 6 -#define RA_I3C_CLOCK_DIV_6 3 -#define RA_I3C_CLOCK_DIV_8 4 - -/* LCD clock divider options. */ -#define RA_LCD_CLOCK_DIV_1 0 -#define RA_LCD_CLOCK_DIV_2 1 -#define RA_LCD_CLOCK_DIV_3 5 -#define RA_LCD_CLOCK_DIV_4 2 -#define RA_LCD_CLOCK_DIV_5 6 -#define RA_LCD_CLOCK_DIV_6 3 -#define RA_LCD_CLOCK_DIV_8 4 - -/* SDADC clock divider options. */ -#define RA_SDADC_CLOCK_DIV_1 0 -#define RA_SDADC_CLOCK_DIV_2 1 -#define RA_SDADC_CLOCK_DIV_3 2 -#define RA_SDADC_CLOCK_DIV_4 3 -#define RA_SDADC_CLOCK_DIV_5 4 -#define RA_SDADC_CLOCK_DIV_6 5 -#define RA_SDADC_CLOCK_DIV_8 6 -#define RA_SDADC_CLOCK_DIV_12 7 -#define RA_SDADC_CLOCK_DIV_16 8 - #define MSTPA 0 #define MSTPB 1 #define MSTPC 2