dts: infineon: cat1b: cyw20829: Reduce the default interrupt priority #79399
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Having the lowest possible interrupt priority is causing the tests\arch\arm\arm_irq_zero_latency_levels test to fail. This test reserves 2 priority levels for the low latency interrupts. Since CYW20829 supports 3 interrupt bits, 6 becomes an invalid value when 2 levels are reserved for the low latency interrupts. Signed-off-by: Sreeram Tatapudi <[email protected]>
npal-cy
approved these changes
Oct 4, 2024
ifyall
approved these changes
Oct 4, 2024
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Having the lowest possible interrupt priority is causing the tests\arch\arm\arm_irq_zero_latency_levels test to fail. This test reserves 2 priority levels for the low latency interrupts. Since CYW20829 supports 3 interrupt bits, 6 becomes an invalid value when 2 levels are reserved for the low latency interrupts.