diff --git a/boards/m5stack/m5stack_cores3/Kconfig b/boards/m5stack/m5stack_cores3/Kconfig index 26f6eed3551af..8cef5ae03edd6 100644 --- a/boards/m5stack/m5stack_cores3/Kconfig +++ b/boards/m5stack/m5stack_cores3/Kconfig @@ -3,5 +3,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int - default 4096 if BOARD_M5STACK_CORES3_ESP32S3_PROCPU + default 4096 if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || \ + BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE default 256 if BOARD_M5STACK_CORES3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 b/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 index 990925a96bb90..59a5912341703 100644 --- a/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 +++ b/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 @@ -5,5 +5,6 @@ config BOARD_M5STACK_CORES3 select SOC_ESP32S3 - select SOC_ESP32S3_PROCPU if BOARD_M5STACK_CORES3_ESP32S3_PROCPU + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || \ + BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE select SOC_ESP32S3_APPCPU if BOARD_M5STACK_CORES3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_cores3/board.yml b/boards/m5stack/m5stack_cores3/board.yml index 64479891d23d8..765c6b9eba232 100644 --- a/boards/m5stack/m5stack_cores3/board.yml +++ b/boards/m5stack/m5stack_cores3/board.yml @@ -4,3 +4,6 @@ board: vendor: m5stack socs: - name: esp32s3 + variants: + - name: se + cpucluster: procpu diff --git a/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp new file mode 100644 index 0000000000000..90e4450a8e7ff Binary files /dev/null and b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp differ diff --git a/boards/m5stack/m5stack_cores3/doc/index.rst b/boards/m5stack/m5stack_cores3/doc/index.rst index 4ee0d8461b697..d9025e3f6d8af 100644 --- a/boards/m5stack/m5stack_cores3/doc/index.rst +++ b/boards/m5stack/m5stack_cores3/doc/index.rst @@ -4,25 +4,27 @@ Overview ******** M5Stack CoreS3 is an ESP32-based development board from M5Stack. It is the third generation of the M5Stack Core series. +M5Stack CoreS3 SE is the compact version of CoreS3. It has the same form factor as the original M5Stack, +and some features were reduced from CoreS3. -M5Stack CoreS3 features consist of: +M5Stack CoreS3/CoreS3 SE features consist of: - ESP32-S3 chip (dual-core Xtensa LX7 processor @240MHz, WIFI, OTG and CDC functions) - PSRAM 8MB - Flash 16MB - LCD ISP 2", 320x240 pixel ILI9342C - Capacitive multi touch FT6336U -- Camera 30W pixel GC0308 - Speaker 1W AW88298 - Dual Microphones ES7210 Audio decoder - RTC BM8563 - USB-C - SD-Card slot -- Geomagnetic sensor BMM150 -- Proximity sensor LTR-553ALS-WA -- 6-Axis IMU BMI270 - PMIC AXP2101 -- Battery 500mAh 3.7 V +- Battery 500mAh 3.7 V (Not available for CoreS3 SE) +- Camera 30W pixel GC0308 (Not available for CoreS3 SE) +- Geomagnetic sensor BMM150 (Not available for CoreS3 SE) +- Proximity sensor LTR-553ALS-WA (Not available for CoreS3 SE) +- 6-Axis IMU BMI270 (Not available for CoreS3 SE) Start Application Development ***************************** @@ -48,24 +50,145 @@ below to retrieve those files. It is recommended running the command above after :file:`west update`. Building & Flashing -------------------- +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_cores3/esp32s3/procpu - :goals: build +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: build + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: build The usual ``flash`` target will work with the ``m5stack_cores3/esp32s3/procpu`` board configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_cores3/esp32s3/procpu - :goals: flash +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: flash + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: flash The baud rate of 921600bps is set by default. If experiencing issues when flashing, try using different values by using ``--esp-baud-rate `` option during @@ -85,9 +208,8 @@ message in the monitor: *** Booting Zephyr OS build vx.x.x-xxx-gxxxxxxxxxxxx *** Hello World! m5stack_cores3/esp32s3/procpu - Debugging ---------- +********* ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. @@ -95,6 +217,42 @@ ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additiona Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: debug + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: debug + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: debug + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: debug + References ********** @@ -102,5 +260,7 @@ References .. _`M5Stack CoreS3 Documentation`: http://docs.m5stack.com/en/core/CoreS3 .. _`M5Stack CoreS3 Schematic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/K128%20CoreS3/Sch_M5_CoreS3_v1.0.pdf +.. _`M5Stack CoreS3 SE Documentation`: https://docs.m5stack.com/en/core/M5CoreS3%20SE +.. _`M5Stack CoreS3 SE Schematic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/products/core/M5CORES3%20SE/M5_CoreS3SE.pdf .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases .. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/m5stack/m5stack_cores3/grove_connectors.dtsi b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi new file mode 100644 index 0000000000000..4139a48b86732 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header: grove_header { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 1 0>, + <1 0 &gpio0 2 0>; + }; +}; + +grove_i2c: &i2c1 {}; +grove_uart: &uart2 {}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi index a759fbc3c7794..78f4c841147a8 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi @@ -20,6 +20,28 @@ }; }; + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart2_default: uart2_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , @@ -40,4 +62,21 @@ output-high; }; }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; }; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts index 2042ca2422a49..1def598cdec76 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts @@ -1,53 +1,24 @@ /* - * Copyright (c) 2024 Zhang Xingtao + * Copyright (c) 2024 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include -#include -#include "m5stack_cores3-pinctrl.dtsi" +#include "m5stack_cores3_procpu_common.dtsi" / { model = "M5Stack CoreS3 PROCPU"; compatible = "m5stack,cores3"; - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; accel0 = &bmi270; magn0 = &bmm150; }; }; -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - &i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - bmi270: bmi270@69 { compatible = "bosch,bmi270"; reg = <0x69>; @@ -59,24 +30,3 @@ reg = <0x10>; }; }; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&wdt0 { - status = "okay"; -}; - -&psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; -}; - -&esp32_bt_hci { - status = "okay"; -}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml index e0e1f9c32cb7d..1db3de005d229 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml @@ -5,17 +5,15 @@ arch: xtensa toolchain: - zephyr supported: - - dma + - gpio + - uart - i2c - spi - - uart + - can + - counter - watchdog -testing: - ignore_tags: - - bluetooth - - gpio - - net - - pinmux - - pwm - - regulator + - entropy + - pwm + - dma + - pinmux vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi new file mode 100644 index 0000000000000..474da0931435a --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2024 Zhang Xingtao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "m5stack_cores3-pinctrl.dtsi" +#include "m5stack_mbus_connectors.dtsi" +#include "grove_connectors.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + i2c-0 = &i2c0; + i2c-1 = &i2c1; + watchdog0 = &wdt0; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&twai { + status = "disabled"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts new file mode 100644 index 0000000000000..93cdeda68cbcb --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "m5stack_cores3_procpu_common.dtsi" + +/ { + model = "M5Stack CoreS3 SE PROCPU"; + compatible = "m5stack,cores3-se"; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml new file mode 100644 index 0000000000000..0427aa4f12089 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml @@ -0,0 +1,19 @@ +identifier: m5stack_cores3/esp32s3/procpu/se +name: M5Stack CoreS3 SE PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - pinmux +vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig new file mode 100644 index 0000000000000..6539bd42e5947 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi b/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi new file mode 100644 index 0000000000000..c91d0b372d0b4 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + m5stack_mbus_header: m5stack_mbus_connector { + compatible = "m5stack,mbus-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = /* GND */ <1 0 &gpio 10 0>, /* ADC */ + /* GND */ <3 0 &gpio 8 0>, /* PB_IN */ + /* GND */ /* RESET/EN */ + /* MOSI */ <6 0 &gpio 37 0>, <7 0 &gpio 5 0>, /* GPIO */ + /* MISO */ <8 0 &gpio 35 0>, <9 0 &gpio 9 0>, /* PB_OUT */ + /* SCK */ <10 0 &gpio 36 0>, /* 3.3V */ + /* RXD0 */ <12 0 &gpio 44 0>, <13 0 &gpio 43 0>, /* TXD0 */ + /* PC_RX */ <14 0 &gpio 18 0>, <15 0 &gpio 17 0>, /* PC_TX */ + /* intSDA */ <16 0 &gpio 12 0>, <17 0 &gpio 11 0>, /* intSCL */ + /* PA_SDA */ <18 0 &gpio 2 0>, <19 0 &gpio 1 0>, /* PA_SCL */ + /* GPIO */ <20 0 &gpio 6 0>, <21 0 &gpio 7 0>, /* GPIO */ + /* I2S_DOUT */ <22 0 &gpio 13 0>, <23 0 &gpio 0 0>, /* I2S_LRCK */ + /* NC */ <25 0 &gpio 3 0>; /* I2S_DIN */ + /* NC */ /* 5V */ + /* NC */ /* BAT */ + }; +}; + +m5stack_mbus_i2c0: &i2c0 {}; +m5stack_mbus_i2c1: &i2c1 {}; +m5stack_mbus_uart0: &uart0 {}; +m5stack_mbus_uart1: &uart1 {}; +m5stack_mbus_spi: &spi2 {};