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Merged
nashif merged 3 commits into from
Nov 16, 2024
Merged

boards: ambiq: add ITM node to Apollo boards #80604

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e84864a
dts: arm: ambiq: add ITM node for Apollo series
aaronyegx Oct 30, 2024
1d44fa3
boards: ambiq: enable the ITM in Ambiq boards
aaronyegx Oct 30, 2024
6391297
soc: ambiq: enable the TPIU clock source
aaronyegx Oct 30, 2024
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11 changes: 11 additions & 0 deletions boards/ambiq/apollo3_evb/Kconfig.defconfig
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@@ -0,0 +1,11 @@
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com>

if BOARD_APOLLO3_EVB

config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

endif # BOARD_APOLLO3_EVB
5 changes: 5 additions & 0 deletions boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
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Expand Up @@ -17,6 +17,11 @@
input-enable;
};
};
itm_default: itm_default {
group1 {
pinmux = <SWO_P41>;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
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6 changes: 6 additions & 0 deletions boards/ambiq/apollo3_evb/apollo3_evb.dts
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Expand Up @@ -98,6 +98,12 @@
status = "okay";
};

&itm {
pinctrl-0 = <&itm_default>;
pinctrl-names = "default";
status = "okay";
};

&wdt0 {
status = "okay";
};
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11 changes: 11 additions & 0 deletions boards/ambiq/apollo3p_evb/Kconfig.defconfig
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@@ -0,0 +1,11 @@
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com>

if BOARD_APOLLO3P_EVB

config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

endif # BOARD_APOLLO3P_EVB
5 changes: 5 additions & 0 deletions boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
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Expand Up @@ -17,6 +17,11 @@
input-enable;
};
};
itm_default: itm_default {
group1 {
pinmux = <SWO_P41>;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
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6 changes: 6 additions & 0 deletions boards/ambiq/apollo3p_evb/apollo3p_evb.dts
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Expand Up @@ -98,6 +98,12 @@
status = "okay";
};

&itm {
pinctrl-0 = <&itm_default>;
pinctrl-names = "default";
status = "okay";
};

&wdt0 {
status = "okay";
};
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4 changes: 4 additions & 0 deletions boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig
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Expand Up @@ -4,6 +4,10 @@

if BOARD_APOLLO4P_BLUE_KXR_EVB

config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

if BT

config MAIN_STACK_SIZE
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5 changes: 5 additions & 0 deletions boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi
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Expand Up @@ -16,6 +16,11 @@
input-enable;
};
};
itm_default: itm_default {
group1 {
pinmux = <SWO_P28>;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
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6 changes: 6 additions & 0 deletions boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts
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Expand Up @@ -63,6 +63,12 @@
status = "okay";
};

&itm {
pinctrl-0 = <&itm_default>;
pinctrl-names = "default";
status = "okay";
};

&counter0 {
status = "okay";
};
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11 changes: 11 additions & 0 deletions boards/ambiq/apollo4p_evb/Kconfig.defconfig
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@@ -0,0 +1,11 @@
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com>

if BOARD_APOLLO4P_EVB

config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

endif # BOARD_APOLLO4P_EVB
5 changes: 5 additions & 0 deletions boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi
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Expand Up @@ -17,6 +17,11 @@
input-enable;
};
};
itm_default: itm_default {
group1 {
pinmux = <SWO_P28>;
};
};
adc0_default: adc0_default{
group1 {
pinmux = <ADCSE4_P15>, <ADCSE7_P12>;
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6 changes: 6 additions & 0 deletions boards/ambiq/apollo4p_evb/apollo4p_evb.dts
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Expand Up @@ -63,6 +63,12 @@
status = "okay";
};

&itm {
pinctrl-0 = <&itm_default>;
pinctrl-names = "default";
status = "okay";
};

&adc0 {
compatible = "ambiq,adc";
pinctrl-0 = <&adc0_default>;
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8 changes: 8 additions & 0 deletions dts/arm/ambiq/ambiq_apollo3_blue.dtsi
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Expand Up @@ -24,6 +24,14 @@
compatible = "arm,cortex-m4f";
reg = <0>;
cpu-power-states = <&idle &suspend_to_ram>;
#address-cells = <1>;
#size-cells = <1>;

itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <DT_FREQ_M(6)>;
};
};

power-states {
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8 changes: 8 additions & 0 deletions dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
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Expand Up @@ -24,6 +24,14 @@
compatible = "arm,cortex-m4f";
reg = <0>;
cpu-power-states = <&idle &suspend_to_ram>;
#address-cells = <1>;
#size-cells = <1>;

itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <DT_FREQ_M(6)>;
};
};

power-states {
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8 changes: 8 additions & 0 deletions dts/arm/ambiq/ambiq_apollo4p.dtsi
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Expand Up @@ -24,6 +24,14 @@
compatible = "arm,cortex-m4f";
reg = <0>;
cpu-power-states = <&idle &suspend_to_ram>;
#address-cells = <1>;
#size-cells = <1>;

itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <DT_FREQ_M(48)>;
};
};
power-states {
idle: idle {
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8 changes: 8 additions & 0 deletions dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
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Expand Up @@ -32,6 +32,14 @@
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;

itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <DT_FREQ_M(48)>;
};
};
};

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6 changes: 6 additions & 0 deletions soc/ambiq/apollo3x/soc.c
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Expand Up @@ -28,4 +28,10 @@ void soc_early_init_hook(void)
#ifdef CONFIG_PM
ambiq_power_init();
#endif

#ifdef CONFIG_LOG_BACKEND_SWO
/* Select HFRC/8 (6MHz) for the TPIU clock source */
MCUCTRL->TPIUCTRL_b.CLKSEL = MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8;
MCUCTRL->TPIUCTRL_b.ENABLE = MCUCTRL_TPIUCTRL_ENABLE_EN;
#endif
}
6 changes: 6 additions & 0 deletions soc/ambiq/apollo4x/soc.c
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Expand Up @@ -23,4 +23,10 @@ void soc_early_init_hook(void)
#ifdef CONFIG_PM
ambiq_power_init();
#endif

#ifdef CONFIG_LOG_BACKEND_SWO
/* Select HFRC 48MHz for the TPIU clock source */
MCUCTRL->DBGCTRL_b.CM4CLKSEL = MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC48;
MCUCTRL->DBGCTRL_b.CM4TPIUENABLE = MCUCTRL_DBGCTRL_CM4TPIUENABLE_EN;
#endif
}
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