diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/Kconfig.cv64a6_genesysII_cispa b/boards/openhwgroup/cv64a6_genesysII_cispa/Kconfig.cv64a6_genesysII_cispa new file mode 100644 index 0000000000000..86f9550d61032 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/Kconfig.cv64a6_genesysII_cispa @@ -0,0 +1,5 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +config BOARD_CV64A6_GENESYSII_CISPA + select SOC_CV64A6_IMAFDC + select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/board.cmake b/boards/openhwgroup/cv64a6_genesysII_cispa/board.cmake new file mode 100644 index 0000000000000..fffa2bed09562 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/board.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") +board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--verify") +board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/board.yml b/boards/openhwgroup/cv64a6_genesysII_cispa/board.yml new file mode 100644 index 0000000000000..027bd39bbf864 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/board.yml @@ -0,0 +1,7 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board: + name: cv64a6_genesysII_cispa + vendor: openhwgroup + socs: + - name: cv64a6 \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa.dts b/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa.dts new file mode 100644 index 0000000000000..88f299c9c39ec --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "CV64A6 on Genesys II (CISPA fork with Xilinx AXI Ethernet, https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet/tree/main)"; + compatible = "ariane,cv64a6_genesysII"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &memory0; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&clint{ + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + + + +&mdio0{ + status = "okay"; + + phy0: phy@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ethernet-phy"; + reg = <1 1>; + status="okay"; + }; +}; + +ð0 { + status = "okay"; + phy-handle=<&phy0>; +}; diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa_defconfig b/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa_defconfig new file mode 100644 index 0000000000000..85a88d40e88cd --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/cv64a6_genesysII_cispa_defconfig @@ -0,0 +1,69 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y +CONFIG_CONSOLE_HANDLER=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000 +CONFIG_FPU=y +CONFIG_POWEROFF=y + +# RNG +CONFIG_TIMER_RANDOM_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y + +# IRQs +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +# 1 PLIC +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1 +CONFIG_PLIC=y +CONFIG_3RD_LEVEL_INTERRUPTS=n + +# Ethernet / Networking +CONFIG_DMA=y +CONFIG_DMA_64BIT=y +CONFIG_DMA_XILINX_AXI_DMA=y +CONFIG_ETH_DRIVER=y +CONFIG_NET_L2_ETHERNET=y +CONFIG_ETH_XILINX_AXIENET=y +CONFIG_MDIO=y +CONFIG_PHY_GENERIC_MII=y +CONFIG_MDIO_XILINX_AXI_ENET=y +CONFIG_NET_IPV4=y +CONFIG_NET_TCP=y +CONFIG_NETWORKING=y +CONFIG_NET_PKT_RX_COUNT=64 +CONFIG_NET_TC_RX_COUNT=1 +CONFIG_NET_TC_TX_COUNT=1 + +# this is the choice that is safe in all scenarios +# overwrite in project if you know a less restrictive choice works for your project +CONFIG_DMA_XILINX_AXI_DMA_LOCK_ALL_IRQS=y +CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX=16 +CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX=16 +CONFIG_DMA_LOG_LEVEL_INF=y + +# required for the DMA, as no cache coherency in this configuration +CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS=y +CONFIG_DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS=y + +# logging +CONFIG_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_THREAD_NAME=y + +# increased stack sizes +CONFIG_ISR_STACK_SIZE=524288 +CONFIG_MAIN_STACK_SIZE=524288 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288 +CONFIG_IDLE_STACK_SIZE=524288 +CONFIG_NET_TCP_WORKQ_STACK_SIZE=524288 +CONFIG_NET_TX_STACK_SIZE=524288 +CONFIG_NET_RX_STACK_SIZE=524288 \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII_cispa/support/ariane.cfg b/boards/openhwgroup/cv64a6_genesysII_cispa/support/ariane.cfg new file mode 100644 index 0000000000000..9bece8fca9c55 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII_cispa/support/ariane.cfg @@ -0,0 +1,49 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +# Based on the ariane.cfg from the cva6 project: +# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg +adapter_khz 1000 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +# Channel 1 is taken by Xilinx JTAG +ftdi_channel 0 + +# links: +# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html +# +# Bit MPSSE FT2232 JTAG Type Description +# Bit0 TCK ADBUS0 TCK Out Clock Signal Output +# Bit1 TDI ADBUS1 TDI Out Serial Data Out +# Bit2 TDO ADBUS2 TDO In Serial Data In +# Bit3 TMS ADBUS3 TMS Out Select Signal Out +# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O +# this corresponds to the following in/out layout, with TMS initially set to 1 +ftdi_layout_init 0x0018 0x001b +# we only have to specify nTRST, the others are assigned correctly by default +ftdi_layout_signal nTRST -ndata 0x0010 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +# Try enabling address translation (only works for newer versions) +if { [catch {riscv set_enable_virtual on} ] } { + echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +init +halt +echo "Ready for Remote Connections"