diff --git a/doc/releases/migration-guide-4.1.rst b/doc/releases/migration-guide-4.1.rst index d35ab96073c73..2740e116a55a7 100644 --- a/doc/releases/migration-guide-4.1.rst +++ b/doc/releases/migration-guide-4.1.rst @@ -39,6 +39,27 @@ LVGL Device Drivers and Devicetree ***************************** +* The :dtcompatible: ``nxp,lpc-iocon`` and ``nxp,rt-iocon-pinctrl`` driver won't be used + for RT 3 digital platforms. + New :dtcompatible:`nxp,iopctl` and :dtcompatible:`nxp,rt-iopctl-pinctrl` have been created + for iopctl IP on RT 3 digital platforms. Change iocon node to iopctl0 node on RT500/600 + platforms. New pinctrl model add instance index parameter in pin header files, however, + for the application layer, the pin macro name will not change. So it means application + layer won't be affected by changes in the driver layer.(:github:`81086`) + example: + + .. code-block:: devicetree + + / { + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; + reg = <0x4000 0x1000>; + status = "okay"; + pinctrl: pinctrl { + compatible = "nxp,rt-iopctl-pinctrl"; + }; + }; + Controller Area Network (CAN) ============================= diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 99cb8d6b9e5f9..30ce7286ce370 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOPCTL pinctrl_iopctl.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 511a8a22cb9ca..25a32ec0342ca 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -49,6 +49,7 @@ source "drivers/pinctrl/Kconfig.xec" source "drivers/pinctrl/Kconfig.imx" source "drivers/pinctrl/Kconfig.sifive" source "drivers/pinctrl/Kconfig.lpc_iocon" +source "drivers/pinctrl/Kconfig.iopctl" source "drivers/pinctrl/Kconfig.cc13xx_cc26xx" source "drivers/pinctrl/Kconfig.esp32" source "drivers/pinctrl/Kconfig.rv32m1" diff --git a/drivers/pinctrl/Kconfig.iopctl b/drivers/pinctrl/Kconfig.iopctl new file mode 100644 index 0000000000000..e057ab4e77646 --- /dev/null +++ b/drivers/pinctrl/Kconfig.iopctl @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_NXP_IOPCTL + bool "IOPCTL Pin controller driver for NXP MCUs" + default y + depends on DT_HAS_NXP_RT_IOPCTL_PINCTRL_ENABLED + help + Enable pin controller driver for NXP MCUs diff --git a/drivers/pinctrl/Kconfig.lpc_iocon b/drivers/pinctrl/Kconfig.lpc_iocon index fdf101d93ebd3..9e8838ea5f9a5 100644 --- a/drivers/pinctrl/Kconfig.lpc_iocon +++ b/drivers/pinctrl/Kconfig.lpc_iocon @@ -1,11 +1,10 @@ -# Copyright 2022, NXP +# Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 config PINCTRL_NXP_IOCON bool "IOCON Pin controller driver for NXP LPC MCUs" default y depends on DT_HAS_NXP_LPC_IOCON_PINCTRL_ENABLED || \ - DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED || \ - DT_HAS_NXP_RT_IOCON_PINCTRL_ENABLED + DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED help Enable pin controller driver for NXP LPC MCUs diff --git a/drivers/pinctrl/pinctrl_iopctl.c b/drivers/pinctrl/pinctrl_iopctl.c new file mode 100644 index 0000000000000..cdea81b5ce809 --- /dev/null +++ b/drivers/pinctrl/pinctrl_iopctl.c @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_iopctl + +#include +#include + +#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) +#define INDEX(mux) (((mux) & 0xF0000) >> 16) +#define Z_PINCTRL_IOPCTL_PIN_MASK 0xFFF + +/* IOPCTL register addresses. */ +static uint32_t *iopctl[] = { +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl0))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl0)), +#else + NULL, +#endif +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl1))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl1)), +#else + NULL, +#endif +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl2))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl2)), +#else + NULL, +#endif +}; + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + for (uint8_t i = 0; i < pin_cnt; i++) { + uint32_t pin_mux = pins[i]; + uint32_t index = INDEX(pin_mux); + uint32_t offset = OFFSET(pin_mux); + + if (index < ARRAY_SIZE(iopctl)) { + /* Set pinmux */ + *(iopctl[index] + offset) = (pin_mux & Z_PINCTRL_IOPCTL_PIN_MASK); + } else { + return -EINVAL; + } + } + + return 0; +} diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi index aa9db51f12552..31001f73f8ca3 100644 --- a/dts/arm/nxp/nxp_rt5xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt5xx_common.dtsi @@ -130,11 +130,12 @@ #clock-cells = <1>; }; - iocon: iocon@4000 { - compatible = "nxp,lpc-iocon"; + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; reg = <0x4000 0x1000>; + status = "okay"; pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; + compatible = "nxp,rt-iopctl-pinctrl"; }; }; diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index bf2dc2daccd91..c39c6847eb62b 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -110,11 +110,12 @@ #clock-cells = <1>; }; - iocon: iocon@4000 { - compatible = "nxp,lpc-iocon"; + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; reg = <0x4000 0x1000>; + status = "okay"; pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; + compatible = "nxp,rt-iopctl-pinctrl"; }; }; diff --git a/dts/bindings/pinctrl/nxp,iopctl.yaml b/dts/bindings/pinctrl/nxp,iopctl.yaml new file mode 100644 index 0000000000000..72289cc23a5de --- /dev/null +++ b/dts/bindings/pinctrl/nxp,iopctl.yaml @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: IO PAD Controller (IOPCTL) + +compatible: "nxp,iopctl" + +include: base.yaml + +properties: + reg: + required: true diff --git a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml b/dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml similarity index 76% rename from dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml rename to dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml index e98eeaea42070..e87d5ec9b62ea 100644 --- a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml @@ -1,8 +1,8 @@ -# Copyright 2022, NXP +# Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 description: | - RT600/RT500 pin control node. This node defines pin configurations in pin + RT700/RT600/RT500 pin control node. This node defines pin configurations in pin groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each group within the pin configuration defines a peripheral's pin configuration. Each numbered subgroup represents pins with shared configuration for that @@ -21,31 +21,31 @@ description: | If only the required properties are supplied, the ICON_PIO register will be assigned the following values: - IOCON_FUNC=, - IOCON_PUPDENA = 0, - IOCON_PUPDSEL = 0, - IOCON_IBENA = 0, - IOCON_SLEWRATE = , - IOCON_FULLDRIVE = , - IOCON_AMENA = 0, - IOCON_ODENA = 0, - IOCON_IIENA = 0, + IOPCTL_FUNC=, + IOPCTL_PUPDENA = 0, + IOPCTL_PUPDSEL = 0, + IOPCTL_IBENA = 0, + IOPCTL_SLEWRATE = , + IOPCTL_FULLDRIVE = , + IOPCTL_AMENA = 0, + IOPCTL_ODENA = 0, + IOPCTL_IIENA = 0, Note the inherited pinctrl properties defined below have the following effects: - drive-open-drain: IOCON_ODENA=1 - bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1 - bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0 - input-enable: IOCON_IBENA=1 + drive-open-drain: IOPCTL_ODENA=1 + bias-pull-up: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=1 + bias-pull-down: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=0 + input-enable: IOPCTL_IBENA=1 -compatible: "nxp,rt-iocon-pinctrl" +compatible: "nxp,rt-iopctl-pinctrl" include: base.yaml child-binding: - description: iMX RT IOCON pin controller pin group + description: iMX RT IOPCTL pin controller pin group child-binding: description: | - iMX RT IOCON pin controller pin configuration node + iMX RT IOPCTL pin controller pin configuration node include: - name: pincfg-node.yaml @@ -69,7 +69,7 @@ child-binding: - "normal" - "slow" description: | - Pin output slew rate. Sets the SLEWRATE field in the IOCON register. + Pin output slew rate. Sets the SLEWRATE field in the IOPCTL register. 0 SLEWRATE_0- normal mode, output slew rate is standard 1 SLEWRATE_1- slow mode, output slew rate is slower drive-strength: @@ -80,7 +80,7 @@ child-binding: - "high" description: | Pin output drive strength. Sets the FULLDRIVE field in the - IOCON register. + IOPCTL register. 0 FULLDRIVE_0- Normal output drive mode 1 FULLDRIVE_1- Full output drive mode, output strength is twice the drive strength of normal drive mode. diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h index 3389073bd09a6..c60d888b5b2fc 100644 --- a/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h +++ b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,11 +31,6 @@ typedef uint32_t pinctrl_soc_pin_t; IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ -/* MCUX RT parts only have one pin type */ -#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF) -#define Z_PINCTRL_IOCON_A_PIN_MASK (0) -#define Z_PINCTRL_IOCON_I_PIN_MASK (0) - #define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group), diff --git a/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h index 445bd1a873b94..ba2a042de18ce 100644 --- a/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h +++ b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,11 +31,6 @@ typedef uint32_t pinctrl_soc_pin_t; IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ -/* MCUX RT parts only have one pin type */ -#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF) -#define Z_PINCTRL_IOCON_A_PIN_MASK (0) -#define Z_PINCTRL_IOCON_I_PIN_MASK (0) - #define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group), diff --git a/west.yml b/west.yml index 87657ebf6df36..d87cdf5192b2f 100644 --- a/west.yml +++ b/west.yml @@ -198,7 +198,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 3c64cd63125c86870802a561ce79dc33697b005c + revision: pull/460/head path: modules/hal/nxp groups: - hal