diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 2ee3c945644d0..409968ca6c7cf 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -111,6 +111,32 @@ config CPU_CORTEX_R52 help This option signifies the use of a Cortex-R52 CPU +config CPU_CORTEX_R52_CACHE_SEGREGATION + bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM" + depends on CPU_CORTEX_R52 + help + Control segregation of L1 I/D-Cache ways between Flash and AXIM. + Updates to the cache segregation controls are only permitted before the caches + have ever been enabled, following a system reset, otherwise the update is ignored. + +config CPU_CORTEX_R52_ICACHE_FLASH_WAY + int "L1 I-Cache Flash way" + depends on CPU_CORTEX_R52_CACHE_SEGREGATION + range 0 4 + default 0 + help + Configure L1 I-Cache ways for Flash interface. Default is reset value, all + I-Cache ways are allocated for AXIM interface. + +config CPU_CORTEX_R52_DCACHE_FLASH_WAY + int "L1 D-Cache Flash way" + depends on CPU_CORTEX_R52_CACHE_SEGREGATION + range 0 4 + default 0 + help + Configure L1 D-Cache ways for Flash interface. Default is reset value, + all D-Cache ways are allocated for AXIM interface. + if CPU_AARCH32_CORTEX_R config ARMV7_R diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index 591973e24e4b5..b5b899194e008 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -56,9 +56,12 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) cmp r0, #MODE_HYP bne EL1_Reset_Handler - /* Init HSCTLR see Armv8-R AArch32 architecture profile */ - ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT) - mcr p15, 4, r0, c1, c0, 0 + /* + * The HSCTLR register provides top-level control of system operation in Hyp mode. + * Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32 + * architecture profile, there's no need to modify HSCTLR configuration unless + * Fast Interrupts need to be enabled. + */ /* Init HACTLR: Enable EL1 access to all IMP DEF registers */ ldr r0, =HACTLR_INIT @@ -200,6 +203,12 @@ EL1_Reset_Handler: #endif /* CONFIG_DCLS */ +#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION) + ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY, + CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY) + mcr p15, 1, r0, c9, c1, 0 +#endif + ldr r0, =arm_cpu_boot_params #if CONFIG_MP_MAX_NUM_CPUS > 1 diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig index 2b5dffc89335a..4e0448afc1efc 100644 --- a/boards/nxp/s32z2xxdc2/Kconfig.defconfig +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -30,4 +30,20 @@ config NET_L2_ETHERNET endif # NETWORKING +if XIP +# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded +# over AXIM interface +config BUILD_OUTPUT_ADJUST_LMA + default "-0x47800000" + +config CPU_CORTEX_R52_CACHE_SEGREGATION + default y + +config CPU_CORTEX_R52_ICACHE_FLASH_WAY + default 4 + +config CPU_CORTEX_R52_DCACHE_FLASH_WAY + default 1 +endif # XIP + endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts index 3db4df08388ff..da6b964561420 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -13,7 +13,8 @@ compatible = "nxp,s32z270"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &dram0; + zephyr,flash = &cram0; zephyr,canbus = &canxl0; }; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig index c9a84cc2dfebd..e498ea9854305 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig @@ -1,7 +1,7 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts index 4aadfbebb1d60..286fd8d094c87 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -13,9 +13,8 @@ compatible = "nxp,s32z270"; chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; + zephyr,sram = &dram1; + zephyr,flash = &cram1; zephyr,canbus = &flexcan0; }; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig index c9a84cc2dfebd..e498ea9854305 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig @@ -1,7 +1,7 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 diff --git a/boards/nxp/s32z2xxdc2/support/startup.cmm b/boards/nxp/s32z2xxdc2/support/startup.cmm index a0cbca67470e9..ca26d84ae08d0 100644 --- a/boards/nxp/s32z2xxdc2/support/startup.cmm +++ b/boards/nxp/s32z2xxdc2/support/startup.cmm @@ -20,20 +20,17 @@ ; - Core0 and Core2 (redundancy) operate as a lockstep pair * ; - Core1 and Core3 (redundancy) operate as a lockstep pair * ; default: yes * -; - thumb set to "yes" to select the T32 instruction set at reset * -; default: no * ; * ;******************************************************************************* ENTRY %LINE &args -LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit +LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit &command=STRing.SCANAndExtract("&args","command=","debug") &elfFile=STRing.SCANAndExtract("&args","elfFile=","") &rtu=STRing.SCANAndExtract("&args","rtu=","0") &core=STRing.SCANAndExtract("&args","core=","0") &lockstep=STRing.SCANAndExtract("&args","lockstep=","yes") -&thumb=STRing.SCANAndExtract("&args","thumb=","no") IF ("&elfFile"=="") ( @@ -59,12 +56,6 @@ IF (&core<0||&core>3) ENDDO ) -; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit) -IF ("&thumb"=="yes") - &thumbBit="1" -ELSE - &thumbBit="0" - ; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit) IF ("&lockstep"=="yes") &spltLckBit="0" @@ -126,8 +117,8 @@ GOSUB EnableRTU1 ; Init RTU SRAM DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm -; Set reset value for TE bit and split-lock mode -Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit) ; CFG_CORE +; Set reset value for split-lock mode +Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit) ; CFG_CORE ; Write loop to self instruction Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index a04d5a01022d1..5d168173304f3 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -110,12 +110,12 @@ status = "okay"; }; - sram0: memory@31780000 { + dram0: memory@31780000 { compatible = "mmio-sram"; reg = <0x31780000 DT_SIZE_M(1)>; }; - sram1: memory@35780000 { + dram1: memory@35780000 { compatible = "mmio-sram"; reg = <0x35780000 DT_SIZE_M(1)>; }; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi index 03428c80db054..6f7dc687d1705 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,12 @@ }; soc { + /* Accessing code RAM over AXIF - a read-only flash memory bus */ + cram0: memory@79900000 { + compatible = "mmio-sram"; + reg = <0x79900000 DT_SIZE_M(7)>; + }; + stm0: stm@76200000 { compatible = "nxp,s32-sys-timer"; reg = <0x76200000 0x10000>; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi index 811fdfe5149bf..91b8de432075e 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi @@ -16,6 +16,12 @@ }; soc { + /* Accessing code RAM over AXIF - a read-only flash memory bus */ + cram1: memory@7d900000 { + compatible = "mmio-sram"; + reg = <0x7d900000 DT_SIZE_M(7)>; + }; + stm0: stm@76a00000 { compatible = "nxp,s32-sys-timer"; reg = <0x76a00000 0x10000>; diff --git a/include/zephyr/arch/arm/cortex_a_r/cpu.h b/include/zephyr/arch/arm/cortex_a_r/cpu.h index 954633ec43be7..74021eba6d010 100644 --- a/include/zephyr/arch/arm/cortex_a_r/cpu.h +++ b/include/zephyr/arch/arm/cortex_a_r/cpu.h @@ -56,6 +56,12 @@ #define SCTLR_C_BIT BIT(2) #define SCTLR_I_BIT BIT(12) +/* Armv8-R Cortex-R52 Cache Segregation Control Register */ +#define IMP_CSCTLR_DFLW_SHIFT (0) +#define IMP_CSCTLR_IFLW_SHIFT (8) +#define IMP_CSCTLR(iway, dway) ((iway << IMP_CSCTLR_IFLW_SHIFT) | \ + ((dway << IMP_CSCTLR_DFLW_SHIFT))) + /* Hyp System Control Register */ #define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \ BIT(22) | BIT(18) | BIT(16) | \ diff --git a/soc/nxp/s32/s32ze/Kconfig.defconfig b/soc/nxp/s32/s32ze/Kconfig.defconfig index 7f6269ca06d06..b6df44f00f624 100644 --- a/soc/nxp/s32/s32ze/Kconfig.defconfig +++ b/soc/nxp/s32/s32ze/Kconfig.defconfig @@ -18,6 +18,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config MAIN_STACK_SIZE default 1024 +config CACHE_MANAGEMENT + default y + if ETH_DRIVER && NET_L2_ETHERNET # NETC drops TCP/UDP packets with invalid checksum diff --git a/soc/nxp/s32/s32ze/mpu_regions.c b/soc/nxp/s32/s32ze/mpu_regions.c index 33c41d362b5da..bfdee2a67b7ad 100644 --- a/soc/nxp/s32/s32ze/mpu_regions.c +++ b/soc/nxp/s32/s32ze/mpu_regions.c @@ -11,20 +11,25 @@ #define DEVICE_REGION_END 0x76FFFFFFUL static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("vector", - (uintptr_t)_vector_start, - REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)), - MPU_REGION_ENTRY("SRAM_TEXT", - (uintptr_t)__text_region_start, + (uintptr_t)__rom_region_start, REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)), MPU_REGION_ENTRY("SRAM_RODATA", (uintptr_t)__rodata_region_start, - REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)), +#ifdef CONFIG_XIP + REGION_RAM_RO_ATTR(CONFIG_FLASH_BASE_ADDRESS + KB(CONFIG_FLASH_SIZE)) +#else + REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end) +#endif + ), MPU_REGION_ENTRY("SRAM_DATA", +#ifdef CONFIG_XIP + (uintptr_t)_image_ram_start, +#else (uintptr_t)__rom_region_end, +#endif REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)), MPU_REGION_ENTRY("DEVICE", diff --git a/soc/nxp/s32/s32ze/soc.c b/soc/nxp/s32/s32ze/soc.c index da05a2085b7c3..9d78881d27b64 100644 --- a/soc/nxp/s32/s32ze/soc.c +++ b/soc/nxp/s32/s32ze/soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include #include +#include #include @@ -27,21 +28,8 @@ void soc_reset_hook(void) */ __set_SCTLR(__get_SCTLR() & ~SCTLR_TE_Msk); - if (IS_ENABLED(CONFIG_ICACHE)) { - if (!(__get_SCTLR() & SCTLR_I_Msk)) { - L1C_InvalidateICacheAll(); - __set_SCTLR(__get_SCTLR() | SCTLR_I_Msk); - barrier_isync_fence_full(); - } - } - - if (IS_ENABLED(CONFIG_DCACHE)) { - if (!(__get_SCTLR() & SCTLR_C_Msk)) { - L1C_InvalidateDCacheAll(); - __set_SCTLR(__get_SCTLR() | SCTLR_C_Msk); - barrier_dsync_fence_full(); - } - } + sys_cache_instr_enable(); + sys_cache_data_enable(); } void soc_early_init_hook(void) diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay index e0fcca61f9b93..13f1c87a01b18 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -17,7 +17,7 @@ }; }; -&sram0 { +&dram0 { compatible = "mmio-sram"; reg = <0x31780000 DT_SIZE_K(960)>; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay index cc6211a9edcaa..c828ef591ed10 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -17,7 +17,7 @@ }; }; -&sram1 { +&dram1 { compatible = "mmio-sram"; reg = <0x35780000 DT_SIZE_K(960)>; }; diff --git a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay index e0fcca61f9b93..13f1c87a01b18 100644 --- a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -17,7 +17,7 @@ }; }; -&sram0 { +&dram0 { compatible = "mmio-sram"; reg = <0x31780000 DT_SIZE_K(960)>; }; diff --git a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay index 2d644fc681716..b9bcb12135107 100644 --- a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -17,7 +17,7 @@ }; }; -&sram1 { +&dram1 { compatible = "mmio-sram"; reg = <0x35780000 DT_SIZE_K(960)>; };