From d9f065845d91fef456c38cbdbf90b3d31ba8ad8b Mon Sep 17 00:00:00 2001 From: Nazar Palamar Date: Fri, 15 Nov 2024 21:04:34 +0200 Subject: [PATCH 1/2] Infineon: board: Add CONFIG_GPIO to defconfigs Add CONFIG_GPIO from defconfigs for Infineon boards. Revert pull/81377, which affect some ble samples which used GPIO. Signed-off-by: Nazar Palamar (cherry picked from commit 697efe8b5054a98010835a1b49384dfe06467549) --- .../infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig | 3 +++ boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig | 3 +++ boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig | 3 +++ 3 files changed, 9 insertions(+) diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 2bda7847628ab..221643eca2791 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -17,6 +17,9 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y +# Enable GPIO driver +CONFIG_GPIO=y + # Enable clock controller CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index 98136255552ab..7d0d29ea39cc9 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -18,6 +18,9 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y +# Enable GPIO +CONFIG_GPIO=y + # Enable clock controller CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig index 14c8035580030..426cd85d30f37 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -18,6 +18,9 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y +# Enable GPIO driver +CONFIG_GPIO=y + # Enable clock controller CONFIG_CLOCK_CONTROL=y From 60b62953299423ea4b2d59f2959d641cdcdf9e60 Mon Sep 17 00:00:00 2001 From: Nazar Palamar Date: Fri, 15 Nov 2024 21:12:13 +0200 Subject: [PATCH 2/2] test: arm: irq: Add overlays files for Infineon boards Changed interrupt priority for GPIO, default 6 is not suitable for for the ZERO_LATENCY_IRQS function used in this test. used in this test. Fixes for problem with arm_irq_zero_latency_levels refer to pull/81377 Signed-off-by: Nazar Palamar (cherry picked from commit 6172092730a88f93696f48983e65a18a9cabff00) --- .../boards/cy8cproto_062_4343w.overlay | 37 +++++++++++++++++++ .../boards/cy8cproto_063_ble.overlay | 33 +++++++++++++++++ .../boards/cyw920829m2evk_02.overlay | 21 +++++++++++ .../boards/cy8cproto_062_4343w.overlay | 37 +++++++++++++++++++ .../boards/cy8cproto_063_ble.overlay | 33 +++++++++++++++++ .../boards/cyw920829m2evk_02.overlay | 21 +++++++++++ 6 files changed, 182 insertions(+) create mode 100644 tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_062_4343w.overlay create mode 100644 tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_063_ble.overlay create mode 100644 tests/arch/arm/arm_irq_advanced_features/boards/cyw920829m2evk_02.overlay create mode 100644 tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_062_4343w.overlay create mode 100644 tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_063_ble.overlay create mode 100644 tests/arch/arm/arm_irq_zero_latency_levels/boards/cyw920829m2evk_02.overlay diff --git a/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_062_4343w.overlay b/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_062_4343w.overlay new file mode 100644 index 0000000000000..bd164a6bf2885 --- /dev/null +++ b/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_062_4343w.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt2 { + interrupts = <2 4>; +}; + +&gpio_prt3 { + interrupts = <3 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +}; + +&gpio_prt6 { + interrupts = <6 4>; +}; + +&gpio_prt9 { + interrupts = <9 4>; +}; + +&gpio_prt12 { + interrupts = <12 4>; +}; + +&gpio_prt13 { + interrupts = <13 4>; +}; diff --git a/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_063_ble.overlay b/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_063_ble.overlay new file mode 100644 index 0000000000000..155992e9cc52f --- /dev/null +++ b/tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_063_ble.overlay @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +}; + +&gpio_prt6 { + interrupts = <6 4>; +}; + +&gpio_prt7 { + interrupts = <7 4>; +}; + +&gpio_prt9 { + interrupts = <9 4>; +}; + +&gpio_prt10 { + interrupts = <10 4>; +}; + +&gpio_prt12 { + interrupts = <12 4>; +}; diff --git a/tests/arch/arm/arm_irq_advanced_features/boards/cyw920829m2evk_02.overlay b/tests/arch/arm/arm_irq_advanced_features/boards/cyw920829m2evk_02.overlay new file mode 100644 index 0000000000000..6ddd801888659 --- /dev/null +++ b/tests/arch/arm/arm_irq_advanced_features/boards/cyw920829m2evk_02.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt1 { + interrupts = <1 4>; +}; + +&gpio_prt3 { + interrupts = <3 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +}; diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_062_4343w.overlay b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_062_4343w.overlay new file mode 100644 index 0000000000000..bd164a6bf2885 --- /dev/null +++ b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_062_4343w.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt2 { + interrupts = <2 4>; +}; + +&gpio_prt3 { + interrupts = <3 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +}; + +&gpio_prt6 { + interrupts = <6 4>; +}; + +&gpio_prt9 { + interrupts = <9 4>; +}; + +&gpio_prt12 { + interrupts = <12 4>; +}; + +&gpio_prt13 { + interrupts = <13 4>; +}; diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_063_ble.overlay b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_063_ble.overlay new file mode 100644 index 0000000000000..155992e9cc52f --- /dev/null +++ b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_063_ble.overlay @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +}; + +&gpio_prt6 { + interrupts = <6 4>; +}; + +&gpio_prt7 { + interrupts = <7 4>; +}; + +&gpio_prt9 { + interrupts = <9 4>; +}; + +&gpio_prt10 { + interrupts = <10 4>; +}; + +&gpio_prt12 { + interrupts = <12 4>; +}; diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/boards/cyw920829m2evk_02.overlay b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cyw920829m2evk_02.overlay new file mode 100644 index 0000000000000..6ddd801888659 --- /dev/null +++ b/tests/arch/arm/arm_irq_zero_latency_levels/boards/cyw920829m2evk_02.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Changed default interrupts priority for GPIO to 4 */ +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt1 { + interrupts = <1 4>; +}; + +&gpio_prt3 { + interrupts = <3 4>; +}; + +&gpio_prt5 { + interrupts = <5 4>; +};