diff --git a/boards/st/stm32h7s78_dk/board.cmake b/boards/st/stm32h7s78_dk/board.cmake index 79bb6fcc70bef..222d0e8a96e1e 100644 --- a/boards/st/stm32h7s78_dk/board.cmake +++ b/boards/st/stm32h7s78_dk/board.cmake @@ -1,7 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 # keep first +if(CONFIG_STM32_MEMMAP) board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX66UW1G45G_STM32H7S78-DK.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +endif() + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index e4192d41641a1..a5f5b3d6d9237 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -19,6 +19,8 @@ zephyr,shell-uart = &uart4; zephyr,flash = &flash0; zephyr,sram = &sram0; + zephyr,flash-controller = &mx66uw1g45; + zephyr,code-partition = &slot0_partition; }; leds { @@ -97,6 +99,18 @@ ppre5 = <2>; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + }; +}; + &uart4 { pinctrl-0 = <&uart4_tx_pd1 &uart4_rx_pd0>; pinctrl-names = "default"; @@ -173,6 +187,52 @@ pinctrl-names = "default"; }; +&xspi1 { + /* same pins as xspi2 */ + pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 + &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 + &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 + &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 + &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 + &xspim_p2_dqs0_pn0>; + pinctrl-names = "default"; + + status = "okay"; + + mx66uw1g45: xspi-nor-flash@72000000 { + compatible = "st,stm32-xspi-nor"; + reg = <0x72000000 DT_SIZE_M(96)>; /* bank1 - 3*/ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* bank1 */ + slot0_partition: partition@0000000 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(2048)>; + }; + + /* bank2 */ + slot1_partition: partition@2000000 { + label = "image-1"; + reg = <0x2000000 DT_SIZE_K(2048)>; + }; + + /* bank3 */ + storage_partition: partition@4000000 { + label = "storage"; + reg = <0x4000000 DT_SIZE_K(128)>; + }; + }; + }; +}; + &die_temp { status = "okay"; }; diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml index e48895cbce1bb..89e24f1fd4e6c 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml @@ -13,4 +13,6 @@ supported: - watchdog - entropy - adc + - spi + - octospi vendor: st diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 81d6f21eb6487..fc847ee24d854 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -52,6 +52,11 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #include #endif /* STM32_XSPI_USE_DMA */ +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) +#include +#include +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ + #include "flash_stm32_xspi.h" static inline void xspi_lock_thread(const struct device *dev) @@ -190,7 +195,9 @@ static XSPI_RegularCmdTypeDef xspi_prepare_cmd(const uint8_t transfer_mode, .DQSMode = (transfer_rate == XSPI_DTR_TRANSFER) ? HAL_XSPI_DQS_ENABLE : HAL_XSPI_DQS_DISABLE, +#ifdef XSPI_CCR_SIOO .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD, +#endif /* XSPI_CCR_SIOO */ }; switch (transfer_mode) { @@ -773,7 +780,9 @@ static int stm32_xspi_mem_reset(const struct device *dev) .DataLength = HAL_XSPI_DATA_NONE, .DummyCycles = 0U, .DQSMode = HAL_XSPI_DQS_DISABLE, +#ifdef XSPI_CCR_SIOO .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD, +#endif /* XSPI_CCR_SIOO */ }; /* Reset enable in SPI mode and STR transfer mode */ @@ -1021,7 +1030,9 @@ static int flash_stm32_xspi_erase(const struct device *dev, off_t addr, .DataMode = HAL_XSPI_DATA_NONE, .DummyCycles = 0U, .DQSMode = HAL_XSPI_DQS_DISABLE, +#ifdef XSPI_CCR_SIOO .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD, +#endif /* XSPI_CCR_SIOO */ }; if (stm32_xspi_mem_ready(dev, @@ -2042,6 +2053,12 @@ static int flash_stm32_xspi_init(const struct device *dev) return -ENOTSUP; } +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + LL_PWR_EnableXSPIM2(); + __HAL_RCC_SBS_CLK_ENABLE(); + LL_SBS_EnableXSPI2SpeedOptim(); +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ + /* Signals configuration */ ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); if (ret < 0) { @@ -2118,15 +2135,17 @@ static int flash_stm32_xspi_init(const struct device *dev) if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) { dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; - } else { - } #if STM32_XSPI_DLYB_BYPASSED dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS; -#else +#elif !defined(CONFIG_SOC_SERIES_STM32H7RSX) dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON; #endif /* STM32_XSPI_DLYB_BYPASSED */ +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + dev_data->hxspi.Init.MaxTran = 0; + dev_data->hxspi.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1; +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) { LOG_ERR("XSPI Init failed"); @@ -2135,7 +2154,8 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_DBG("XSPI Init'd"); -#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) +#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) \ + || defined(XSPIM) || defined(XSPIM1) || defined(XSPIM2) /* XSPI I/O manager init Function */ XSPIM_CfgTypeDef xspi_mgr_cfg; @@ -2155,7 +2175,9 @@ static int flash_stm32_xspi_init(const struct device *dev) #endif /* XSPIM */ -#if defined(DLYB_XSPI1) || defined(DLYB_XSPI2) || defined(DLYB_OCTOSPI1) || defined(DLYB_OCTOSPI2) +#if !defined (CONFIG_SOC_SERIES_STM32H7RSX) && \ + (defined(DLYB_XSPI1) || defined(DLYB_XSPI2) || defined(DLYB_OCTOSPI1) \ + || defined(DLYB_OCTOSPI2)) /* XSPI delay block init Function */ HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0}; @@ -2169,7 +2191,7 @@ static int flash_stm32_xspi_init(const struct device *dev) } LOG_DBG("Delay Block Init"); -#endif /* DLYB_ */ +#endif /* !CONFIG_SOC_SERIES_STM32H7RSX && DLYB_ */ #if STM32_XSPI_USE_DMA /* Configure and enable the DMA channels after XSPI config */ diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index 25ba574d5b1f6..ef9354b534b22 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include /* @@ -81,7 +82,8 @@ compatible = "zephyr,memory-region"; reg = <0x70000000 DT_SIZE_M(256)>; zephyr,memory-region = "EXTMEM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + /* The ATTR_MPU_EXTMEM attribut causes an MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; clocks { @@ -776,6 +778,28 @@ interrupts = <37 0>; status = "disabled"; }; + + xspi1: xspi@52005000 { + compatible = "st,stm32-xspi"; + reg = <0x52005000 0x400>; + interrupts = <105 0>; + clock-names = "ospix"; + clocks = <&rcc STM32_CLOCK_BUS_AHB5 0x00000020>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi2: xspi@5200a000 { + compatible = "st,stm32-xspi"; + reg = <0x5200a000 0x400>; + interrupts = <106 0>; + clock-names = "ospix"; + clocks = <&rcc STM32_CLOCK_BUS_AHB5 0x000001000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; die_temp: dietemp { diff --git a/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.conf b/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.conf new file mode 100644 index 0000000000000..eac2504a7850e --- /dev/null +++ b/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.conf @@ -0,0 +1,2 @@ +CONFIG_FLASH=y +CONFIG_STM32_MEMMAP=y diff --git a/samples/sysbuild/with_mcuboot/sample.yaml b/samples/sysbuild/with_mcuboot/sample.yaml index 2478fa9df345a..11ade2657ac59 100644 --- a/samples/sysbuild/with_mcuboot/sample.yaml +++ b/samples/sysbuild/with_mcuboot/sample.yaml @@ -14,6 +14,7 @@ tests: - esp32s3_devkitm/esp32s3/procpu - esp32c3_devkitm - esp32c6_devkitc + - stm32h7s78_dk integration_platforms: - nrf52840dk/nrf52840 - esp32_devkitc_wrover/esp32/procpu