diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst index 958b3ec3a0b7b..95ac49e9fc7de 100644 --- a/boards/renesas/ek_ra2a1/doc/index.rst +++ b/boards/renesas/ek_ra2a1/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra2a1: - -RA2A1 Evaluation Kit -#################### +.. zephyr:board:: ek_ra2a1 Overview ******** @@ -31,12 +28,6 @@ Renesas RA2A1 Microcontroller Group has following features - Watchdog Timer - 49 Input/Output pins -.. figure:: ek_ra2a1.webp - :align: center - :alt: RA2A1 Evaluation Kit - - EK-RA2A1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig index 85bd6dcd4553d..15e3f1e271cf6 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig +++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 TOKITA Hiroshi # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra2l1/doc/index.rst b/boards/renesas/ek_ra2l1/doc/index.rst index d4f057899b189..2d9686625c86f 100644 --- a/boards/renesas/ek_ra2l1/doc/index.rst +++ b/boards/renesas/ek_ra2l1/doc/index.rst @@ -1,8 +1,5 @@ .. zephyr:board:: ek_ra2l1 -RA2L1 Evaluation Kit -#################### - Overview ******** diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst index 979c2a0c0791a..effa168b5ad79 100644 --- a/boards/renesas/ek_ra4e2/doc/index.rst +++ b/boards/renesas/ek_ra4e2/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra4e2: - -RA4E2 Evaluation Kit -#################### +.. zephyr:board:: ek_ra4e2 Overview ******** @@ -16,6 +13,7 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run 100 MHz with the following features: **MCU Native Pin Access** + - R7FA4E2B93CFM MCU (referred to as RA MCU) - 100 MHz, Arm® Cortex®-M33 core - 128 kB Code Flash, 40 kB SRAM @@ -23,10 +21,11 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run - Native pin access through 2 x 14-pin and 1 x 40-pin male headers - MCU current measurement points for precision current consumption measurement - Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision -20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the -RA MCU + 20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the + RA MCU **System Control and Ecosystem Access** + - USB Full Speed Device (micro-AB connector) - Three 5 V input sources @@ -61,15 +60,9 @@ RA MCU - CAN FD (3-pin header) -.. figure:: ek_ra4e2.webp - :align: center - :alt: RA4E2 Evaluation Kit - - EK-RA4E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_ +Detailed hardware features for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_ .. figure:: ra4e2_block_diagram.webp :width: 442px @@ -78,12 +71,12 @@ Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group Use RA4E2 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_ +Detailed hardware features for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA4E2 board: +The below features are currently supported on Zephyr for EK-RA4E2 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -129,11 +122,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig index 93569c968fce1..770a30fc47db0 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig +++ b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4l1/doc/index.rst b/boards/renesas/ek_ra4l1/doc/index.rst index ffbeaedebfbe3..067d2bdb8adee 100644 --- a/boards/renesas/ek_ra4l1/doc/index.rst +++ b/boards/renesas/ek_ra4l1/doc/index.rst @@ -1,8 +1,5 @@ .. zephyr:board:: ek_ra4l1 -RA4L1 Evaluation Kit -#################### - Overview ******** diff --git a/boards/renesas/ek_ra4m1/doc/index.rst b/boards/renesas/ek_ra4m1/doc/index.rst index abd0ecd936b81..be316702996a1 100644 --- a/boards/renesas/ek_ra4m1/doc/index.rst +++ b/boards/renesas/ek_ra4m1/doc/index.rst @@ -1,8 +1,5 @@ .. zephyr:board:: ek_ra4m1 -RA4M1 Evaluation Kit -#################### - Overview ******** diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst index 1719bf3187e8e..bdea3c5e2f85d 100644 --- a/boards/renesas/ek_ra4m2/doc/index.rst +++ b/boards/renesas/ek_ra4m2/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra4m2: - -RA4M2 Evaluation Kit -#################### +.. zephyr:board:: ek_ra4m2 Overview ******** @@ -17,17 +14,19 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run 100 MHz with the following features: **Renesas RA4M2 Microcontroller Group** + - R7FA4M2AD3CFP - 100-pin LQFP package - 100 MHz Arm® Cortex®-M33 core - 512 kB Code Flash, 128 KB SRAM - Native pin access through 4 x 28-pin male headers - MCU current measurement points for precision current consumption measurement -- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing -precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are -available internal to the RA MCU +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing + precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are + available internal to the RA MCU **System Control and Ecosystem Access** + - USB Full Speed Host and Device (micro AB connector) - Three 5 V input sources @@ -59,17 +58,12 @@ available internal to the RA MCU - MCU boot configuration jumper **Special Feature Access** -- 32 MB (256 Mb) External Quad-SPI Flash -.. figure:: ek_ra4m2.webp - :align: center - :alt: RA4M2 Evaluation Kit - - EK-RA4M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) +- 32 MB (256 Mb) External Quad-SPI Flash Hardware ******** -Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_ +Detailed hardware features for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_ .. figure:: ra4m2_block_diagram.webp :width: 442px @@ -78,12 +72,12 @@ Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group Use RA4M2 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_ +Detailed hardware features for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA4M2 board: +The below features are currently supported on Zephyr for EK-RA4M2 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -135,11 +129,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig index 93569c968fce1..770a30fc47db0 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig +++ b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst index 8ed2359c08d4f..aa843d9311f5f 100644 --- a/boards/renesas/ek_ra4m3/doc/index.rst +++ b/boards/renesas/ek_ra4m3/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra4m3: - -RA4M3 Evaluation Kit -#################### +.. zephyr:board:: ek_ra4m3 Overview ******** @@ -18,6 +15,7 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run 100 MHz with the following features: **MCU Native Pin Access** + - R7FA4M3AF3CFB - 100-pin LQFP package - 100 MHz Arm® Cortex®-M33 core @@ -26,24 +24,23 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run - Native pin access through 4 x 40-pin male headers - MCU and USB current measurement points for precision current consumption measurement - Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision -24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the -RA MCU + 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the + RA MCU **System Control and Ecosystem Access** + - USB Full Speed Host and Device (micro AB connector) -- Three 5 V input sources +- Three 5 V input sources - USB (Debug, Full Speed) - External power supply (using surface mount clamp test points and power input vias) - Three Debug modes - +- Three Debug modes - Debug on-board (SWD) - Debug in (ETM, SWD, and JTAG) - Debug out (SWD) - User LEDs and buttons - +- User LEDs and buttons - Three User LEDs (red, blue, green) - Power LED (white) indicating availability of regulated power - Debug LED (yellow) indicating the debug connection @@ -51,7 +48,6 @@ RA MCU - One Reset button - Five most popular ecosystems expansions - - 2 Seeed Grove® system (I2C/Analog) connectors - SparkFun® Qwiic® connector - 2 Digilent PmodTM (SPI and UART) connectors @@ -63,15 +59,9 @@ RA MCU **Special Feature Access** - 32 MB (256 Mb) External Quad-SPI Flash -.. figure:: ek_ra4m3.webp - :align: center - :alt: RA4M3 Evaluation Kit - - EK-RA4M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_ +Detailed hardware features for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_ .. figure:: ra4m3_block_diagram.webp :width: 442px @@ -80,12 +70,12 @@ Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group Use RA4M3 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_ +Detailed hardware features for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA4M3 board: +The below features are currently supported on Zephyr for EK-RA4M3 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig index 93569c968fce1..770a30fc47db0 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig +++ b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst index c9501e3dc1d6e..b763331a7f92c 100644 --- a/boards/renesas/ek_ra4w1/doc/index.rst +++ b/boards/renesas/ek_ra4w1/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra4w1: - -RA4W1 Evaluation Kit -#################### +.. zephyr:board:: ek_ra4w1 Overview ******** @@ -14,54 +11,56 @@ excellent reception performance. RA4W1 is geared towards IoT application requiri embedded RAM and low power consumption. **MCU Native Pin Access** + - R7FA4W1AD2CNG - QFN-56 package - On-chip memory: 512-KB ROM, 96-KB RAM, 8-KB data flash memory **Power-supply voltage** + - USB connector: 5-V input - Power-supply IC: 5-V input, 3.3-V output - External power-supply header*1: 3.3-V input, 2 pins x 1 **Main clock** + - Crystal oscillator (surface-mount technology (SMT)) for the main system clock - Crystal oscillator or ceramic resonator (lead type) for the main system clock **Sub-clock** + - Crystal oscillator (SMT) for the sub-clock **Bluetooth Low Energy** + - Bluetooth Low Energy (BLE) circuit x1 - Range of frequency: 2402 to 2480 MHz - Maximum transmission output power: 4 dBm (in 4-dBm output mode) - Output variation: +2 dB **Push switches** + - Reset switch x 1 - User switch x 1 **LED** + - Power indicator: green x 1 - User: green x 2 - ACT LED: green x 1 -**Conetivity** +**Connectivity** + - Connector for an on-board emulator: USB Micro-B - Connector for a USB serial-conversion interface: USB Micro-B - Pmod™ connector: Angle type, 12 pins - Arduino™ UNO connectors -- Emulator reset switch - -.. figure:: ek_ra4w1.webp - :align: center - :alt: RA4W1 Evaluation Kit - - EK-RA4W1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) +- Emulator reset switch: DIP switch x 1 Hardware ******** -Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_ +Detailed Hardware features for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_ .. figure:: ra4w1_block_diagram.webp :width: 442px @@ -70,12 +69,12 @@ Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group Use RA4W1 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_ +Detailed Hardware features for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA4W1 board: +The below features are currently supported on Zephyr for EK-RA4W1 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -121,11 +120,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig index fb7c4482b2448..770a30fc47db0 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig +++ b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst index 1e39eca3a14c1..15a9d7c43050b 100644 --- a/boards/renesas/ek_ra6e2/doc/index.rst +++ b/boards/renesas/ek_ra6e2/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6e2: - -RA6E2 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6e2 Overview ******** @@ -61,15 +58,9 @@ The key features of the EK-RA6E2 board are categorized in three groups as follow - 16 Mb (128 Mb) External Quad-SPI Flash - CAN (3-pin header) -.. figure:: ek_ra6e2.webp - :align: center - :alt: RA6E2 Evaluation Kit - - EK-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ +Detailed hardware features for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ .. figure:: ra6e2_block_diagram.webp :width: 442px @@ -78,12 +69,12 @@ Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group U RA6E2 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_ +Detailed hardware features for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6E2 board: +The below features are currently supported on Zephyr for EK-RA6E2 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -129,11 +120,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig index 882cf699d986f..770a30fc47db0 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig +++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst index 0394397ce07e2..941d55d089e88 100644 --- a/boards/renesas/ek_ra6m1/doc/index.rst +++ b/boards/renesas/ek_ra6m1/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6m1: - -RA6M1 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6m1 Overview ******** @@ -17,6 +14,7 @@ low power consumption. The key features of the EK-RA6M1 board are categorized in three groups as follow: **MCU Native Pin Access** + - R7FA6M1AD3CFP - 100-pin LQFP package - 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU) @@ -25,47 +23,42 @@ The key features of the EK-RA6M1 board are categorized in three groups as follow - 8 KB data flash memory **Connectivity** + - A Device USB connector for the Main MCU - S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the -RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external -debuggers and programmers. + RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external + debuggers and programmers. - Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for -rapid prototyping + rapid prototyping. - Pin headers for access to power and signals for the Main MCU **Multiple clock sources** + - Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference -clocks + clocks - Additional low-precision clocks are available internal to the Main MCU **General purpose I/O ports** + - One jumper to allow measuring of Main MCU current - Copper jumpers on PCB bottom side for configuration and access to selected MCU signals + **Operating voltage** + - External 5 V input through the Debug USB connector supplies the on-board power regulator to power -logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate -locations on the board. + logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate + locations on the board. - A two-color board status LED indicating availability of regulated power and connection status of the J-Link -interface. + interface. - A red User LED, controlled by the Main MCU firmware - A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer, -all of which are controlled by the Main MCU firmware + all of which are controlled by the Main MCU firmware - MCU reset push-button switch - MCU boot configuration jumper -**Special Feature Access** - -- USB Full Speed Debug and Device (micro-AB connector) - -.. figure:: ek_ra6m1.webp - :align: center - :alt: RA6M1 Evaluation Kit - - EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_ +Detailed hardware features for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_ .. figure:: ra6m1_block_diagram.webp :width: 442px @@ -74,12 +67,12 @@ Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group U RA6M1 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_ +Detailed hardware features for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6M1 board: +The below features are currently supported on Zephyr for EK-RA6M1 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -129,11 +122,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig index fb0bf97d8885b..35ed0307b9aa5 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig +++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig @@ -1,14 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 - # Enable GPIO CONFIG_GPIO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y - # Enable Console CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst index b0cd6689c65a6..c7c6a16579f75 100644 --- a/boards/renesas/ek_ra6m2/doc/index.rst +++ b/boards/renesas/ek_ra6m2/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6m2: - -RA6M2 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6m2 Overview ******** @@ -51,15 +48,9 @@ The key features of the EK-RA6M2 board are categorized in three groups as follow - USB Full Speed Host and Device (micro-AB connector) -.. figure:: ek_ra6m2.webp - :align: center - :alt: RA6M2 Evaluation Kit - - EK-RA6M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_ +Detailed hardware features for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_ .. figure:: ra6m2_block_diagram.webp :width: 871px @@ -68,12 +59,12 @@ Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group U RA6M2 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_ +Detailed hardware features for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6M2 board: +The below features are currently supported on Zephyr for EK-RA6M2 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig index fb0bf97d8885b..35ed0307b9aa5 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig +++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig @@ -1,14 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 - # Enable GPIO CONFIG_GPIO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y - # Enable Console CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst index a26a24c6e2369..1a898dc3a2756 100644 --- a/boards/renesas/ek_ra6m3/doc/index.rst +++ b/boards/renesas/ek_ra6m3/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6m3: - -RA6M3 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6m3 Overview ******** @@ -59,15 +56,9 @@ The key features of the EK-RA6M3 board are categorized in three groups as follow - USB High Speed Host and Device (micro-AB connector) - 32 Mb (256 Mb) External Quad-SPI Flash -.. figure:: ek_ra6m3.webp - :align: center - :alt: RA6M3 Evaluation Kit - - EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_ +Detailed hardware features for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_ .. figure:: ra6m3_block_diagram.webp :width: 442px @@ -76,12 +67,12 @@ Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group U RA6M3 Block diagram (Credit: Renesas Electronics Corporation) -Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_ +Detailed hardware features for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6M3 board: +The below features are currently supported on Zephyr for EK-RA6M3 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -133,11 +124,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig index 914980bc08c8c..791f9faca4092 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig +++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst index 7a550ccf80cee..6e65ebeeed79a 100644 --- a/boards/renesas/ek_ra6m4/doc/index.rst +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6m4: - -RA6M4 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6m4 Overview ******** @@ -64,15 +61,9 @@ The key features of the EK-RA6M4 board are categorized in three groups as follow - 32 Mb (256 Mb) External Quad-SPI Flash - 64 Mb (512 Mb) External Octo-SPI Flash -.. figure:: ek_ra6m4.webp - :align: center - :alt: RA6M4 Evaluation Kit - - EK-RA6M4 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_ +Detailed hardware features for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_ .. figure:: ra6m4_block_diagram.webp :width: 442px @@ -81,12 +72,12 @@ Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group U RA6M4 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_ +Detailed hardware features for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6M4 board: +The below features are currently supported on Zephyr for EK-RA6M4 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -138,11 +129,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig index 7d9405d620489..791f9faca4092 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig +++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst index f3d074f373bd9..5e3dd4b2683a4 100644 --- a/boards/renesas/ek_ra6m5/doc/index.rst +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra6m5: - -RA6M5 Evaluation Kit -#################### +.. zephyr:board:: ek_ra6m5 Overview ******** @@ -62,15 +59,9 @@ The key features of the EK-RA6M5 board are categorized in three groups as follow - 64 Mb (512 Mb) External Octo-SPI Flash - CAN (3-pin header) -.. figure:: ek_ra6m5.webp - :align: center - :alt: RA6M5 Evaluation Kit - - EK-RA6M5 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_ +Detailed hardware features for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_ .. figure:: ra6m5_block_diagram.webp :width: 442px @@ -79,12 +70,12 @@ Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group U RA6M5 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_ +Detailed hardware features for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA6M5 board: +The below features are currently supported on Zephyr for EK-RA6M5 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -138,11 +129,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig index 6a9a032666e9a..35ed0307b9aa5 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig +++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig @@ -1,14 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 - # Enable GPIO CONFIG_GPIO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y - # Enable Console CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst index a66c98a974247..c1275bd196df9 100644 --- a/boards/renesas/ek_ra8d1/doc/index.rst +++ b/boards/renesas/ek_ra8d1/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra8d1: - -RA8D1 Evaluation Kit -#################### +.. zephyr:board:: ek_ra8d1 Overview ******** @@ -61,15 +58,9 @@ The key features of the EK-RA8D1 board are categorized in three groups as follow - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8D1 board) - CAN FD (3-pin header) -.. figure:: ek_ra8d1.jpg - :align: center - :alt: RA8D1 Evaluation Kit - - EK-RA8D1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ +Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ .. figure:: ra8d1_block_diagram.png :width: 442px @@ -78,12 +69,12 @@ Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group Use RA8D1 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_ +Detailed Hardware features for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA8D1 board: +The below features are currently supported on Zephyr for EK-RA8D1 board: +--------------+------------+-----------------------------------+ | Interface | Controller | Driver/Component | @@ -169,11 +160,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig index 1f67b94e7c110..35ed0307b9aa5 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig +++ b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y -CONFIG_CLOCK_CONTROL=y - -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst index 31dd6fa78208c..3dd8bf440c4c5 100644 --- a/boards/renesas/ek_ra8m1/doc/index.rst +++ b/boards/renesas/ek_ra8m1/doc/index.rst @@ -1,7 +1,4 @@ -.. _ek_ra8m1: - -RA8M1 Evaluation Kit -#################### +.. zephyr:board:: ek_ra8m1 Overview ******** @@ -61,15 +58,9 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M1 board) - CAN FD (3-pin header) -.. figure:: ek_ra8m1.jpg - :align: center - :alt: RA8M1 Evaluation Kit - - EK-RA8M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_ +Detailed Hardware features for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_ .. figure:: ra8m1_block_diagram.jpg :width: 442px @@ -78,12 +69,12 @@ Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group Use RA8M1 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the EK-RA8M1 MCU can be found at `EK-RA8M1 - User's Manual`_ +Detailed Hardware features for the EK-RA8M1 MCU can be found at `EK-RA8M1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for EK-RA8M1 board: +The below features are currently supported on Zephyr for EK-RA8M1 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -151,11 +142,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8M1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8M1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig index d20f50324687f..35ed0307b9aa5 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig +++ b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/fpb_ra4e1/doc/index.rst b/boards/renesas/fpb_ra4e1/doc/index.rst index 37b2b7550737a..5f5898f595655 100644 --- a/boards/renesas/fpb_ra4e1/doc/index.rst +++ b/boards/renesas/fpb_ra4e1/doc/index.rst @@ -1,8 +1,5 @@ .. zephyr:board:: fpb_ra4e1 -RA4E1 Fast Prototyping Board -############################ - Overview ******** diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst index ac1f0aed2e044..416d412f910b4 100644 --- a/boards/renesas/fpb_ra6e1/doc/index.rst +++ b/boards/renesas/fpb_ra6e1/doc/index.rst @@ -1,7 +1,4 @@ -.. _fpb_ra6e1: - -RA6E1 Fast Prototyping Board -############################ +.. zephyr:board:: fpb_ra6e1 Overview ******** @@ -46,15 +43,9 @@ The key features of the FPB-RA6E1 board are categorized in three groups as follo - MCU boot configuration jumper -.. figure:: fpb_ra6e1.webp - :align: center - :alt: RA6E1 Fast Prototyping Board - - FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_ +Detailed hardware features for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_ .. figure:: ra6e1_block_diagram.webp :width: 442px @@ -63,12 +54,12 @@ Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group U RA6E1 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_ +Detailed hardware features for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for FPB-RA6E1 board: +The below features are currently supported on Zephyr for FPB-RA6E1 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -116,11 +107,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig index 4fd3e749468fa..770a30fc47db0 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig @@ -1,17 +1,11 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 - # Enable GPIO CONFIG_GPIO=y -CONFIG_BUILD_OUTPUT_HEX=y - # Enable Console CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst index 3785387de8c25..94d311a829c16 100644 --- a/boards/renesas/fpb_ra6e2/doc/index.rst +++ b/boards/renesas/fpb_ra6e2/doc/index.rst @@ -1,7 +1,4 @@ -.. _fpb_ra6e2: - -RA6E2 Fast Prototyping Board -############################ +.. zephyr:board:: fpb_ra6e2 Overview ******** @@ -50,15 +47,9 @@ The key features of the FPB-RA6E2 board are categorized in three groups as follo - MCU boot configuration jumper -.. figure:: fpb_ra6e2.webp - :align: center - :alt: RA6E2 Fast Prototyping Board - - FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) - Hardware ******** -Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ +Detailed hardware features for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ .. figure:: ra6e2_block_diagram.webp :width: 442px @@ -67,12 +58,12 @@ Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group U RA6E2 Block diagram (Credit: Renesas Electronics Corporation) -Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_ +Detailed hardware features for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for FPB-RA6E2 board: +The below features are currently supported on Zephyr for FPB-RA6E2 board: +-----------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -116,11 +107,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig index 882cf699d986f..770a30fc47db0 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,6 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/mck_ra8t1/board.yml b/boards/renesas/mck_ra8t1/board.yml index b7897016bbe15..dcd1bd718409e 100644 --- a/boards/renesas/mck_ra8t1/board.yml +++ b/boards/renesas/mck_ra8t1/board.yml @@ -1,6 +1,6 @@ board: name: mck_ra8t1 - full_name: RA8T1 Evaluation Kit + full_name: RA8T1 Motor Control Kit vendor: renesas socs: - name: r7fa8t1ahecbd diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst index 339a917fff579..c9b4f6d09a64b 100644 --- a/boards/renesas/mck_ra8t1/doc/index.rst +++ b/boards/renesas/mck_ra8t1/doc/index.rst @@ -1,7 +1,4 @@ -.. _mcb_ra8t1: - -RA8T1 Evaluation Kit -#################### +.. zephyr:board:: mck_ra8t1 Overview ******** @@ -20,7 +17,7 @@ MCK-RA8T1 kit includes the items below: .. figure:: mck_ra8t1_product_contents.jpg :align: center - :alt: RA8T1 Evaluation Kit + :alt: RA8T1 Motor Control Kit MCK-RA8T1 product contents (Credit: Renesas Electronics Corporation) @@ -54,12 +51,6 @@ The specifications of the CPU board are shown below: - Ethrnet connector - microSD card connector -.. figure:: mck_ra8t1.jpg - :align: center - :alt: RA8T1 Evaluation Kit - - CPU Board Layout (Credit: Renesas Electronics Corporation) - **Onboard debugger** This product has the onboard debugger circuit, J-Link On-Board (hereinafter called “J-Link-OB”). You can @@ -67,7 +58,7 @@ write a program (firmware) of RA8T1 with it. Hardware ******** -Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_ +Detailed Hardware features for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_ .. figure:: ra8t1_block_diagram.png :width: 442px @@ -76,12 +67,12 @@ Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group Use RA8T1 Block diagram (Credit: Renesas Electronics Corporation) -Detail Hardware feature for the MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_ +Detailed Hardware features for the MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_ Supported Features ================== -The below features are currently supported on Zephyr OS for MCB-RA8T1 board: +The below features are currently supported on Zephyr for MCB-RA8T1 board: +--------------+------------+----------------------+ | Interface | Controller | Driver/Component | @@ -144,11 +135,11 @@ SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ To flash the program to board - 1. Connect to J-Link OB via USB port to host PC +1. Connect to J-Link OB via USB port to host PC - 2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_ +2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_ - 3. Execute west command +3. Execute west command .. code-block:: console diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig index 07c0ee5f1ca5a..35ed0307b9aa5 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig +++ b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 - # Enable GPIO CONFIG_GPIO=y @@ -11,7 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y - -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/renesas/voice_ra4e1/doc/index.rst b/boards/renesas/voice_ra4e1/doc/index.rst index cdf1e4ef78fd3..2d737a3378941 100644 --- a/boards/renesas/voice_ra4e1/doc/index.rst +++ b/boards/renesas/voice_ra4e1/doc/index.rst @@ -1,8 +1,5 @@ .. zephyr:board:: voice_ra4e1 -RA4E1 Voice User Reference Kit -############################## - Overview ******** diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 30749ad038076..b32219c2ff789 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -413,7 +413,7 @@ Boards & SoC Support * Added support for :zephyr:board:`Seeed Studio XIAO RP2040 board `: ``xiao_rp2040``. * Added support for :zephyr:board:`Mikroe RA4M1 Clicker board `: ``mikroe_clicker_ra4m1``. * Added support for :ref:`Arduino UNO R4 WiFi board `: ``arduino_uno_r4_wifi``. - * Added support for :ref:`Renesas EK-RA8M1 board `: ``ek_ra8m1``. + * Added support for :zephyr:board:`Renesas EK-RA8M1 board `: ``ek_ra8m1``. * Added support for :zephyr:board:`ST Nucleo H533RE `: ``nucleo_h533re``. * Added support for :zephyr:board:`ST STM32C0116-DK Discovery Kit `: ``stm32c0116_dk``. * Added support for :zephyr:board:`ST STM32H745I Discovery `: ``stm32h745i_disco``. diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 8b9ede8f11eba..4dcf628ea722e 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -303,21 +303,21 @@ Boards & SoC Support * :zephyr:board:`NXP i.MX95 EVK ` (``imx95_evk``) * :zephyr:board:`NXP MIMXRT1180-EVK ` (``mimxrt1180_evk``) * :ref:`PHYTEC phyBOARD-Nash i.MX93 ` (``phyboard_nash``) - * :ref:`Renesas RA2A1 Evaluation Kit ` (``ek_ra2a1``) - * :ref:`Renesas RA4E2 Evaluation Kit ` (``ek_ra4e2``) - * :ref:`Renesas RA4M2 Evaluation Kit ` (``ek_ra4m2``) - * :ref:`Renesas RA4M3 Evaluation Kit ` (``ek_ra4m3``) - * :ref:`Renesas RA4W1 Evaluation Kit ` (``ek_ra4w1``) - * :ref:`Renesas RA6E2 Evaluation Kit ` (``ek_ra6e2``) - * :ref:`Renesas RA6M1 Evaluation Kit ` (``ek_ra6m1``) - * :ref:`Renesas RA6M2 Evaluation Kit ` (``ek_ra6m2``) - * :ref:`Renesas RA6M3 Evaluation Kit ` (``ek_ra6m3``) - * :ref:`Renesas RA6M4 Evaluation Kit ` (``ek_ra6m4``) - * :ref:`Renesas RA6M5 Evaluation Kit ` (``ek_ra6m5``) - * :ref:`Renesas RA8D1 Evaluation Kit ` (``ek_ra8d1``) - * :ref:`Renesas RA6E1 Fast Prototyping Board ` (``fpb_ra6e1``) - * :ref:`Renesas RA6E2 Fast Prototyping Board ` (``fpb_ra6e2``) - * :ref:`Renesas RA8T1 Evaluation Kit ` (``mck_ra8t1``) + * :zephyr:board:`Renesas RA2A1 Evaluation Kit ` (``ek_ra2a1``) + * :zephyr:board:`Renesas RA4E2 Evaluation Kit ` (``ek_ra4e2``) + * :zephyr:board:`Renesas RA4M2 Evaluation Kit ` (``ek_ra4m2``) + * :zephyr:board:`Renesas RA4M3 Evaluation Kit ` (``ek_ra4m3``) + * :zephyr:board:`Renesas RA4W1 Evaluation Kit ` (``ek_ra4w1``) + * :zephyr:board:`Renesas RA6E2 Evaluation Kit ` (``ek_ra6e2``) + * :zephyr:board:`Renesas RA6M1 Evaluation Kit ` (``ek_ra6m1``) + * :zephyr:board:`Renesas RA6M2 Evaluation Kit ` (``ek_ra6m2``) + * :zephyr:board:`Renesas RA6M3 Evaluation Kit ` (``ek_ra6m3``) + * :zephyr:board:`Renesas RA6M4 Evaluation Kit ` (``ek_ra6m4``) + * :zephyr:board:`Renesas RA6M5 Evaluation Kit ` (``ek_ra6m5``) + * :zephyr:board:`Renesas RA8D1 Evaluation Kit ` (``ek_ra8d1``) + * :zephyr:board:`Renesas RA6E1 Fast Prototyping Board ` (``fpb_ra6e1``) + * :zephyr:board:`Renesas RA6E2 Fast Prototyping Board ` (``fpb_ra6e2``) + * :zephyr:board:`Renesas RA8T1 Motor Control Kit ` (``mck_ra8t1``) * :zephyr:board:`Renode Cortex-R8 Virtual ` (``cortex_r8_virtual``) * :zephyr:board:`Seeed XIAO ESP32-S3 Sense Variant `: ``xiao_esp32s3``. * :ref:`sensry.io Ganymed Break-Out-Board (BOB) ` (``ganymed_bob``) diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 6d123486697f2..511355a8d93f7 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -141,6 +141,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <48000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 7252e48c53b5e..848309f5e2425 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -155,6 +155,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <100000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 5866ffda30525..a6dc48199e19a 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -215,6 +215,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <100000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 90f5c6ed8da1f..6ed9030387f47 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -226,6 +226,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <100000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 5afa2da38cbee..dbecb5edb786f 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -117,6 +117,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <48000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 3d368903774bb..3332ce1d6d7d9 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -194,6 +194,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <200000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index ce0070c22c28b..4998e1034b1f8 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -153,6 +153,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <200000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index 174148b8b47bd..c04daf4a985a0 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -108,6 +108,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <120000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index a407fd1c4590a..ad78df1ddf250 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -140,6 +140,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <120000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index d705afc56947e..f9dd42e405c89 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -199,6 +199,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <120000000>; div = <2>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index d864486b1cc68..1b568b5c5a8a3 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -302,6 +302,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <200000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index df6b6e6681297..d889317fd74ca 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -354,6 +354,7 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <200000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 5ee87dd34fed1..629908e00e48d 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -155,6 +155,7 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <480000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 57fa3dd97bfd6..88661e3abfe85 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -125,6 +125,7 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <480000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index e2f1b7f8af90b..9c45b7709516b 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -122,6 +122,7 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <480000000>; div = <1>; #clock-cells = <2>; status = "okay"; diff --git a/soc/renesas/ra/ra2a1/Kconfig.defconfig b/soc/renesas/ra/ra2a1/Kconfig.defconfig index 7176e95746acb..e0ae0c6bd23dc 100644 --- a/soc/renesas/ra/ra2a1/Kconfig.defconfig +++ b/soc/renesas/ra/ra2a1/Kconfig.defconfig @@ -6,4 +6,15 @@ if SOC_SERIES_RA2A1 config NUM_IRQS default 32 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + endif # SOC_SERIES_RA2A1 diff --git a/soc/renesas/ra/ra4e2/Kconfig.defconfig b/soc/renesas/ra/ra4e2/Kconfig.defconfig index f484852e0de22..ff781e3becb39 100644 --- a/soc/renesas/ra/ra4e2/Kconfig.defconfig +++ b/soc/renesas/ra/ra4e2/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA4E2 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra4m2/Kconfig.defconfig b/soc/renesas/ra/ra4m2/Kconfig.defconfig index 3c6f986e5ffa6..87ce2fc6817cd 100644 --- a/soc/renesas/ra/ra4m2/Kconfig.defconfig +++ b/soc/renesas/ra/ra4m2/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA4M2 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra4m3/Kconfig.defconfig b/soc/renesas/ra/ra4m3/Kconfig.defconfig index 717b6bce4322c..af4c164af81fd 100644 --- a/soc/renesas/ra/ra4m3/Kconfig.defconfig +++ b/soc/renesas/ra/ra4m3/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA4M3 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra4w1/Kconfig.defconfig b/soc/renesas/ra/ra4w1/Kconfig.defconfig index 56c1866d0e96b..3e3cbb9747c44 100644 --- a/soc/renesas/ra/ra4w1/Kconfig.defconfig +++ b/soc/renesas/ra/ra4w1/Kconfig.defconfig @@ -6,4 +6,15 @@ if SOC_SERIES_RA4W1 config NUM_IRQS default 32 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + endif # SOC_SERIES_RA4W1 diff --git a/soc/renesas/ra/ra6e1/Kconfig.defconfig b/soc/renesas/ra/ra6e1/Kconfig.defconfig index 5920c21c75962..d8478071e7a60 100644 --- a/soc/renesas/ra/ra6e1/Kconfig.defconfig +++ b/soc/renesas/ra/ra6e1/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6E1 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6e2/Kconfig.defconfig b/soc/renesas/ra/ra6e2/Kconfig.defconfig index d19b73b87a00c..9d56855abe191 100644 --- a/soc/renesas/ra/ra6e2/Kconfig.defconfig +++ b/soc/renesas/ra/ra6e2/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6E2 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6m1/Kconfig.defconfig b/soc/renesas/ra/ra6m1/Kconfig.defconfig index 520d9aac59ebc..f863f67d6f22d 100644 --- a/soc/renesas/ra/ra6m1/Kconfig.defconfig +++ b/soc/renesas/ra/ra6m1/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6m2/Kconfig.defconfig b/soc/renesas/ra/ra6m2/Kconfig.defconfig index ca2dc7346d415..7e5cd7a2eec12 100644 --- a/soc/renesas/ra/ra6m2/Kconfig.defconfig +++ b/soc/renesas/ra/ra6m2/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6m3/Kconfig.defconfig b/soc/renesas/ra/ra6m3/Kconfig.defconfig index 43f112acb609c..ae8951e40c5ca 100644 --- a/soc/renesas/ra/ra6m3/Kconfig.defconfig +++ b/soc/renesas/ra/ra6m3/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6m4/Kconfig.defconfig b/soc/renesas/ra/ra6m4/Kconfig.defconfig index 5352885ee93ba..7e6de81829e88 100644 --- a/soc/renesas/ra/ra6m4/Kconfig.defconfig +++ b/soc/renesas/ra/ra6m4/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra6m5/Kconfig.defconfig b/soc/renesas/ra/ra6m5/Kconfig.defconfig index 3e473cd89320b..51c5a3c0de2f5 100644 --- a/soc/renesas/ra/ra6m5/Kconfig.defconfig +++ b/soc/renesas/ra/ra6m5/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra8d1/Kconfig.defconfig b/soc/renesas/ra/ra8d1/Kconfig.defconfig index e009261b4b6c2..219dbd2336db9 100644 --- a/soc/renesas/ra/ra8d1/Kconfig.defconfig +++ b/soc/renesas/ra/ra8d1/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA8D1 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra8m1/Kconfig.defconfig b/soc/renesas/ra/ra8m1/Kconfig.defconfig index d963468bb07e3..18f1da7e08d2e 100644 --- a/soc/renesas/ra/ra8m1/Kconfig.defconfig +++ b/soc/renesas/ra/ra8m1/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA8M1 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128 diff --git a/soc/renesas/ra/ra8t1/Kconfig.defconfig b/soc/renesas/ra/ra8t1/Kconfig.defconfig index 3e721bd8fc3ac..44acb5cf41301 100644 --- a/soc/renesas/ra/ra8t1/Kconfig.defconfig +++ b/soc/renesas/ra/ra8t1/Kconfig.defconfig @@ -6,6 +6,17 @@ if SOC_SERIES_RA8T1 config NUM_IRQS default 96 +DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + # Set to the minimal size of data which can be written. config FLASH_FILL_BUFFER_SIZE default 128