From 0cfdd54edc296c21438fef2770df1d5738f7cfba Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 5 May 2025 14:21:45 +0200 Subject: [PATCH 1/8] soc: st: stm32 Kconfig to retrieve the external Flash Base address This commit is retrieving the config FLASH_BASE_ADDRESS from the XSPI node of the stm32 device dtsi property of the "st,stm32-xspi" node. For example the CONFIG_FLASH_BASE_ADDRESS is 0x90000000 and application is linked for that address. Size is given by the size property of the "st,stm32-xspi-nor" node. Signed-off-by: Francois Ramu --- soc/st/stm32/Kconfig.defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig index 1cf916d1611e1..18f343b9324c0 100644 --- a/soc/st/stm32/Kconfig.defconfig +++ b/soc/st/stm32/Kconfig.defconfig @@ -26,6 +26,13 @@ DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-fre DT_ST_PRESCALER := st,prescaler DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_XSPI := st,stm32-xspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) +DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI)) + config SYS_CLOCK_HW_CYCLES_PER_SEC default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" @@ -73,4 +80,9 @@ config USE_DT_CODE_PARTITION config BUILD_WITH_TFM default y if TRUSTED_EXECUTION_NONSECURE +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_XSPI) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + endif # SOC_FAMILY_STM32 From c41a0c7a101f1bf0d2bb63be267975073beb6c35 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 27 May 2024 11:18:52 +0200 Subject: [PATCH 2/8] drivers: flash: stm32 xspi driver supports clock domain config Add the clock domain configuration for the xspi nodes Where the DTS defines main clock and peripheral clock sel plus a XSPIM clock Signed-off-by: Francois Ramu --- drivers/flash/flash_stm32_xspi.c | 81 +++++++++++++++++--------------- drivers/flash/flash_stm32_xspi.h | 5 +- 2 files changed, 45 insertions(+), 41 deletions(-) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 4b5bf371cfdd4..03312e38cf5ce 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -2050,7 +2050,7 @@ static int flash_stm32_xspi_init(const struct device *dev) * If clock is off, then MemoryMapped is off too and we do init */ if (clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0]) + (clock_control_subsys_t) &dev_cfg->pclken) == CLOCK_CONTROL_STATUS_ON) { if (stm32_xspi_is_memorymap(dev)) { LOG_ERR("NOR init'd in MemMapped mode"); @@ -2076,53 +2076,44 @@ static int flash_stm32_xspi_init(const struct device *dev) return ret; } - if (dev_cfg->pclk_len > 3) { - /* Max 3 domain clock are expected */ - LOG_ERR("Could not select %d XSPI domain clock", dev_cfg->pclk_len); - return -EIO; - } - /* Clock configuration */ if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0]) != 0) { + (clock_control_subsys_t) &dev_cfg->pclken) != 0) { LOG_ERR("Could not enable XSPI clock"); return -EIO; } if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0], + (clock_control_subsys_t) &dev_cfg->pclken, &ahb_clock_freq) < 0) { LOG_ERR("Failed call clock_control_get_rate(pclken)"); return -EIO; } - /* Alternate clock config for peripheral if any */ - if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 1)) { - if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[1], - NULL) != 0) { - LOG_ERR("Could not select XSPI domain clock"); - return -EIO; - } - /* - * Get the clock rate from this one (update ahb_clock_freq) - * TODO: retrieve index in the clocks property where clocks has "xspi-ker" - * Assuming index is 1 - */ - if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[1], - &ahb_clock_freq) < 0) { - LOG_ERR("Failed call clock_control_get_rate(pclken)"); - return -EIO; - } + +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) + /* Kernel clock config for peripheral if any */ + if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_ker, + NULL) != 0) { + LOG_ERR("Could not select XSPI domain clock"); + return -EIO; } + + if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_ker, + &ahb_clock_freq) < 0) { + LOG_ERR("Failed call clock_control_get_rate(pclken_ker)"); + return -EIO; + } +#endif /* xspi_ker */ + +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) /* Clock domain corresponding to the IO-Mgr (XSPIM) */ - if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 2)) { - if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[2]) != 0) { - LOG_ERR("Could not enable XSPI Manager clock"); - return -EIO; - } - /* Do NOT Get the clock rate from this one */ + if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) { + LOG_ERR("Could not enable XSPI Manager clock"); + return -EIO; } +#endif /* xspi_mgr */ for (; prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX; prescaler++) { uint32_t clk = STM32_XSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler); @@ -2429,13 +2420,25 @@ static int flash_stm32_xspi_init(const struct device *dev) static void flash_stm32_xspi_irq_config_func(const struct device *dev); -static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(STM32_XSPI_NODE); - PINCTRL_DT_DEFINE(STM32_XSPI_NODE); static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = { - .pclken = pclken, - .pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE), + .pclken = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bits) + }, +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) + .pclken_ker = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bits) + }, +#endif /* xspi_ker */ +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) + .pclken_mgr = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits) + }, +#endif /* xspi_mgr */ .irq_config = flash_stm32_xspi_irq_config_func, .flash_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ .max_frequency = DT_INST_PROP(0, ospi_max_frequency), diff --git a/drivers/flash/flash_stm32_xspi.h b/drivers/flash/flash_stm32_xspi.h index 316efdbcd8788..3c1c149e0b2d8 100644 --- a/drivers/flash/flash_stm32_xspi.h +++ b/drivers/flash/flash_stm32_xspi.h @@ -67,8 +67,9 @@ struct stream { typedef void (*irq_config_func_t)(const struct device *dev); struct flash_stm32_xspi_config { - const struct stm32_pclken *pclken; - size_t pclk_len; + const struct stm32_pclken pclken; + const struct stm32_pclken pclken_ker; + const struct stm32_pclken pclken_mgr; irq_config_func_t irq_config; size_t flash_size; uint32_t max_frequency; From c7b54c24419efd51cede109519209a98e558aa41 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 31 May 2024 16:47:56 +0200 Subject: [PATCH 3/8] drivers: flash: stm32 xspi drivers supporting the stm32h7r/s mcu Add the support of the stm32h7rs serie to the drivers/flash/flash_stm32_xspi driver. The stm32h7rs has no delayblock Signed-off-by: Francois Ramu --- drivers/flash/flash_stm32_xspi.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 03312e38cf5ce..ed084ffcd4198 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -52,6 +52,11 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #include #endif /* STM32_XSPI_USE_DMA */ +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) +#include +#include +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ + #include "flash_stm32_xspi.h" static inline void xspi_lock_thread(const struct device *dev) @@ -2068,6 +2073,11 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_ERR("XSPI mode SPI|DUAL|QUAD/DTR is not valid"); return -ENOTSUP; } +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + LL_PWR_EnableXSPIM2(); + __HAL_RCC_SBS_CLK_ENABLE(); + LL_SBS_EnableXSPI2SpeedOptim(); +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ /* Signals configuration */ ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); @@ -2158,7 +2168,8 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_DBG("XSPI Init'd"); -#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) +#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) || \ + defined(XSPIM) || defined(XSPIM1) || defined(XSPIM2) /* XSPI I/O manager init Function */ XSPIM_CfgTypeDef xspi_mgr_cfg; @@ -2471,9 +2482,12 @@ static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = { : HAL_XSPI_CSSEL_NCS2), #endif .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE, -#if defined(OCTOSPI_DCR4_REFRESH) +#if defined(XSPI_DCR3_MAXTRAN) + .MaxTran = 0, +#endif /* XSPI_DCR3_MAXTRAN */ +#if defined(XSPI_DCR4_REFRESH) .Refresh = 0, -#endif /* OCTOSPI_DCR4_REFRESH */ +#endif /* XSPI_DCR4_REFRESH */ }, }, .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6), From 15bcfb6239ed0f84ce55b761e51aaa228ca53e5d Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 6 May 2025 08:36:37 +0200 Subject: [PATCH 4/8] drivers: flash: stm32 xspi flash driver set the DelayBlock if exists The stm32H7RS serie has no DelayBlock Bypass control in its DCR1 register. For other stm32 devices with DelayBlock bypass control, set the value directly in the structure. Signed-off-by: Francois Ramu --- drivers/flash/flash_stm32_xspi.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index ed084ffcd4198..7355c0c6a7653 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -42,8 +42,6 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #define STM32_XSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios) -#define STM32_XSPI_DLYB_BYPASSED DT_PROP(STM32_XSPI_NODE, dlyb_bypass) - #define STM32_XSPI_USE_DMA DT_NODE_HAS_PROP(STM32_XSPI_NODE, dmas) #if STM32_XSPI_USE_DMA @@ -2149,17 +2147,7 @@ static int flash_stm32_xspi_init(const struct device *dev) if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) { dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; - } else { - } -#if defined(XSPI_DCR1_DLYBYP) -#if STM32_XSPI_DLYB_BYPASSED - dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS; -#else - dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON; -#endif /* STM32_XSPI_DLYB_BYPASSED */ -#endif /* XSPI_DCR1_DLYBYP */ - if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) { LOG_ERR("XSPI Init failed"); @@ -2482,6 +2470,11 @@ static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = { : HAL_XSPI_CSSEL_NCS2), #endif .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE, +#if defined(XSPI_DCR1_DLYBYP) + .DelayBlockBypass = (DT_PROP(STM32_XSPI_NODE, dlyb_bypass) + ? HAL_XSPI_DELAY_BLOCK_BYPASS + : HAL_XSPI_DELAY_BLOCK_ON), +#endif /* XSPI_DCR1_DLYBYP */ #if defined(XSPI_DCR3_MAXTRAN) .MaxTran = 0, #endif /* XSPI_DCR3_MAXTRAN */ From 09493b92f712c21524e00824871364c432d63773 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 3 Apr 2025 15:12:18 +0200 Subject: [PATCH 5/8] drivers: clock control: stm32H7RS has a PLL2 & 3 or HCLK5 output Add the definitions of the PLL2 and PLL3 outputs for the stm32H7RS mcus and the HCLK 5 which is clock source for the XSPI instance. and other HCLKn for other peripherals. Signed-off-by: Francois Ramu --- drivers/clock_control/clock_stm32_ll_h7.c | 20 ++++++++++++++++++- .../dt-bindings/clock/stm32h7rs_clock.h | 5 +++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 5d6bcb72fa998..5556dac0c7522 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -337,6 +337,16 @@ int enabled_clock(uint32_t src_clk) ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) || ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + (src_clk == STM32_SRC_HCLK1) || + (src_clk == STM32_SRC_HCLK2) || + (src_clk == STM32_SRC_HCLK3) || + (src_clk == STM32_SRC_HCLK4) || + (src_clk == STM32_SRC_HCLK5) || + ((src_clk == STM32_SRC_PLL2_S) && IS_ENABLED(STM32_PLL2_S_ENABLED)) || + ((src_clk == STM32_SRC_PLL2_T) && IS_ENABLED(STM32_PLL2_T_ENABLED)) || + ((src_clk == STM32_SRC_PLL3_S) && IS_ENABLED(STM32_PLL3_S_ENABLED)) || +#endif ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { return 0; } @@ -460,6 +470,14 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB3: case STM32_CLOCK_BUS_AHB4: +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + /* HCLKn is a possible source clock for some peripherals */ + case STM32_SRC_HCLK1: + case STM32_SRC_HCLK2: + case STM32_SRC_HCLK3: + case STM32_SRC_HCLK4: + case STM32_SRC_HCLK5: +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ *rate = ahb_clock; break; case STM32_CLOCK_BUS_APB1: @@ -544,7 +562,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_N_MULTIPLIER, STM32_PLL_S_DIVISOR); break; - /* PLL 1 has no T-divider */ + /* PLL 1 has no T-divider */ #endif /* CONFIG_SOC_SERIES_STM32H7RSX */ #endif /* STM32_PLL_ENABLED */ #if defined(STM32_PLL2_ENABLED) diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h index d7943dbe73bca..36f15378be49f 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h @@ -38,6 +38,11 @@ /** Clock muxes */ #define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1) +#define STM32_SRC_HCLK1 (STM32_SRC_CKPER + 1) +#define STM32_SRC_HCLK2 (STM32_SRC_HCLK1 + 1) +#define STM32_SRC_HCLK3 (STM32_SRC_HCLK2 + 1) +#define STM32_SRC_HCLK4 (STM32_SRC_HCLK3 + 1) +#define STM32_SRC_HCLK5 (STM32_SRC_HCLK4 + 1) /** Others: Not yet supported */ /** Bus clocks */ From c2ddf9f3acbc00c9f010dea4f0f8f77b80b6a37b Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 30 May 2024 15:27:20 +0200 Subject: [PATCH 6/8] dts: arm: stm32h7rs mcu with external memory area Defines the corresponding memory area of the MPU for the external NOR xspi node. Signed-off-by: Francois Ramu --- dts/arm/st/h7rs/stm32h7rs.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index d4030d65e7bc7..c1dd2a3540303 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include /* @@ -81,7 +82,8 @@ compatible = "zephyr,memory-region"; reg = <0x70000000 DT_SIZE_M(256)>; zephyr,memory-region = "EXTMEM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; clocks { From e7a1f502d69bc161a8f9f26ee7bd03b43bf43b70 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 18 Nov 2024 16:56:48 +0100 Subject: [PATCH 7/8] boards: st: stm32h7s3l8 nucleo board supporting xspi instance Add the XSPI 2 which is an octoSPI connection to a octo NOR flash MX25UW25645GXDI00 (256 Mbits, 1.8 V, 200 MHz, DTR, rww) on the nucleo_h7s3l8 board. Signed-off-by: Francois Ramu --- boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts | 72 ++++++++++++++++++++++ boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml | 1 + 2 files changed, 73 insertions(+) diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts index e5d817bea578d..6d2b9ef80bf5f 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts @@ -85,6 +85,19 @@ status = "okay"; }; +/* PLL2 for clocking the xspi peripheral */ +&pll2 { + div-m = <12>; + mul-n = <200>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <2>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -139,3 +152,62 @@ status = "okay"; clock-frequency = ; }; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set the partitions with first MB to make use of the whole Bank1 */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + }; +}; + +&xspi2 { + pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 + &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 + &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 + &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 + &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 + &xspim_p2_dqs0_pn0>; + pinctrl-names = "default"; + + status = "okay"; + + mx25uw25645: xspi-nor-flash@0 { + compatible = "st,stm32-xspi-nor"; + reg = <0>; + size = ; /* 256Mbits */ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x0080000 DT_SIZE_K(512)>; + }; + scratch_partition: partition@100000 { + label = "image-scratch"; + reg = <0x00100000 DT_SIZE_K(64)>; + }; + storage_partition: partition@110000 { + label = "storage"; + reg = <0x00110000 DT_SIZE_K(64)>; + }; + }; + }; +}; diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml index f7b72a70d9237..4601260e27a52 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml @@ -12,4 +12,5 @@ supported: - watchdog - entropy - adc + - octospi vendor: st From 20adb4b8ac079dd35dea4b2d0f9b69b2cf813eba Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 27 May 2024 11:18:52 +0200 Subject: [PATCH 8/8] boards: arm: stm32h7s78 disco kit supporting xspi instance Add the XSPI 2 which is an octoSPI connection to a octo NOR flash mx66uw1g45 on the stm32h7s78_dk disco kit Signed-off-by: Francois Ramu --- boards/st/stm32h7s78_dk/stm32h7s78_dk.dts | 59 ++++++++++++++++++++++ boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml | 2 +- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index db864811c586b..4c66cb4c99791 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -207,6 +207,65 @@ }; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set the partitions with first MB to make use of the whole Bank1 */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + }; +}; + +&xspi2 { + pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 + &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 + &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 + &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 + &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 + &xspim_p2_dqs0_pn0>; + pinctrl-names = "default"; + + status = "okay"; + + mx66uw1g45: xspi-nor-flash@0 { + compatible = "st,stm32-xspi-nor"; + reg = <0>; + size = ; /* 1 Gbits */ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x0080000 DT_SIZE_K(512)>; + }; + scratch_partition: partition@100000 { + label = "image-scratch"; + reg = <0x00100000 DT_SIZE_K(64)>; + }; + storage_partition: partition@110000 { + label = "storage"; + reg = <0x00110000 DT_SIZE_K(64)>; + }; + }; + }; +}; + &die_temp { status = "okay"; }; diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml index 4aa585d4e9b7c..6e9cc6c401afd 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml @@ -13,7 +13,7 @@ supported: - watchdog - entropy - adc - - usb_device + - octospi - usbd - memc vendor: st