diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index b4edf9c02a691..3e5988fc698cf 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -32,7 +32,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index 29ec478524686..a285113aad209 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -29,7 +29,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index 4e9ed86b082fe..1cb30f2cfa9ed 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -24,7 +24,7 @@ jobs: run_id: ${{ github.event.workflow_run.id }} - name: Publish BabbleSim Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 with: check_name: BabbleSim Test Results comment_mode: off diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 60d4187cfe3e4..951adc4d267b1 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -98,7 +98,7 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Check common triggering files - uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 + uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 id: check-common-files with: files: | @@ -117,7 +117,7 @@ jobs: modules/hal_nordic/** - name: Check if Bluethooth files changed - uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 + uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 id: check-bluetooth-files with: files: | @@ -127,7 +127,7 @@ jobs: tests/bsim/bluetooth/ - name: Check if Networking files changed - uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 + uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 id: check-networking-files with: files: | @@ -140,7 +140,7 @@ jobs: include/zephyr/net/ieee802154* - name: Check if UART files changed - uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 + uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 id: check-uart-files with: files: | @@ -193,7 +193,7 @@ jobs: junit.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 with: check_name: Bsim Test Results files: "junit.xml" diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index befa8cdb8bf15..e4cc5b7fddabd 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -27,7 +27,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 752ced4389578..2e085c2bb3602 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -142,12 +142,12 @@ jobs: persist-credentials: false - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 with: path: artifacts - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -172,7 +172,7 @@ jobs: junit-clang.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 if: always() with: check_name: Unit Test Results diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 2cd4ab16d9a5d..74ca259c91fa2 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -69,7 +69,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.4.0 with: python-version: 3.12 cache: pip @@ -145,7 +145,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -156,7 +156,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 with: path: coverage/reports @@ -232,7 +232,7 @@ jobs: - name: Upload coverage to Codecov if: always() - uses: codecov/codecov-action@ad3126e916f78f00edff4ed0317cf185271ccc2d # v5.4.2 + uses: codecov/codecov-action@0565863a31f2c772f9f0395002a31e3f06189574 # v5.4.0 with: env_vars: OS,PYTHON fail_ci_if_error: false diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index 869467e030a80..f9295f68cd719 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -39,7 +39,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Initialize CodeQL - uses: github/codeql-action/init@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/init@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 with: languages: ${{ matrix.language }} build-mode: ${{ matrix.build-mode }} @@ -53,6 +53,6 @@ jobs: exit 0 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/analyze@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 with: category: "/language:${{matrix.language}}" diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index b574199cff166..cf3d7182f18f5 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -17,7 +17,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 9d1621cc4d3a9..12f2601c01642 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -44,7 +44,7 @@ jobs: git log --pretty=oneline | head -n 10 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 4b89661a8afe4..02eef3c776f6f 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -32,7 +32,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index bf61725c26009..00a498bbc4594 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -36,7 +36,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index bc147ee381798..144f872e5f588 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -32,7 +32,7 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Check if Documentation related files changed - uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 + uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 id: check-doc-files with: files: | @@ -101,7 +101,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -203,7 +203,7 @@ jobs: path: zephyr - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 9552d72b3d9f2..54ac20d6ad46a 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -43,7 +43,7 @@ jobs: - name: Check PR number if: steps.download-artifacts.outputs.found_artifact == 'true' id: check-pr - uses: carpentries/actions/check-valid-pr@2e20fd5ee53b691e27455ce7ca3b16ea885140e8 # v0.15.0 + uses: carpentries/actions/check-valid-pr@e27aa6c531dadd357d2aa4c9a21e90849e23e963 # v0.14.0 with: pr: ${{ env.PR_NUM }} sha: ${{ github.event.workflow_run.head_sha }} diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index cb4d1e6650c01..c974b0ded252b 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -69,7 +69,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 560e747c0d294..8fb8b11597b04 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -54,7 +54,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.11 diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index bacd0ba768bd8..889fe073e06b3 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -21,7 +21,7 @@ jobs: persist-credentials: false - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -53,3 +53,10 @@ jobs: verbosity-level: '1' labels: 'manifest' dnm-labels: 'DNM (manifest)' + + - name: Check for label + if: ${{ contains(github.event.*.labels.*.name, 'DNM (manifest)') }} + run: | + echo "Pull request is labeled as 'DNM (manifest)'." + echo "This workflow fails so that the pull request cannot be merged." + exit 1 diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml index c89eb7464f76d..12ca596322190 100644 --- a/.github/workflows/pinned-gh-actions.yml +++ b/.github/workflows/pinned-gh-actions.yml @@ -16,4 +16,4 @@ jobs: - name: Checkout code uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Ensure SHA pinned actions - uses: zgosalvez/github-actions-ensure-sha-pinned-actions@2d6823da4039243036c86d76f503c84e2ded2517 # v3.0.24 + uses: zgosalvez/github-actions-ensure-sha-pinned-actions@4830be28ce81da52ec70d65c552a7403821d98d4 # v3.0.23 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml index 91c997279df8c..199c76dde1bc3 100644 --- a/.github/workflows/pr_metadata_check.yml +++ b/.github/workflows/pr_metadata_check.yml @@ -18,23 +18,15 @@ jobs: name: Prevent Merging runs-on: ubuntu-24.04 steps: - - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - - - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 - with: - python-version: 3.12 - cache: pip - cache-dependency-path: scripts/requirements-actions.txt - - - name: Install Python dependencies + - name: Check for label + if: ${{ contains(github.event.*.labels.*.name, 'DNM') || + contains(github.event.*.labels.*.name, 'TSC') || + contains(github.event.*.labels.*.name, 'Architecture Review') || + contains(github.event.*.labels.*.name, 'dev-review') }} run: | - pip install -r scripts/requirements-actions.txt --require-hashes - - - name: Run the check script - run: | - ./scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" + echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'." + echo "This workflow fails so that the pull request cannot be merged." + exit 1 empty_pr_description: if: ${{ github.event.pull_request.body == '' }} diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index edf38bad2b9c7..29cfd1a52730f 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -35,7 +35,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index 3d4471e70a58e..d54e76cdcb8c5 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/upload-sarif@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 with: sarif_file: results.sarif diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 4140dacbd63dd..0664dbcebc569 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -52,7 +52,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index 5ca8eb9aa9d54..bb79f77280177 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -19,7 +19,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index 8c700a81f38c0..ceac5a7736bfa 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -28,7 +28,7 @@ jobs: fetch-depth: 0 persist-credentials: false - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index a40bbbef66097..946cfff778e4f 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -51,7 +51,7 @@ jobs: - name: Set up Python if: github.event_name == 'pull_request' - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -325,7 +325,7 @@ jobs: persist-credentials: false - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: 3.12 cache: pip @@ -336,7 +336,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 with: path: artifacts @@ -356,7 +356,7 @@ jobs: junit.xml - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 with: check_name: Unit Test Results files: "**/twister.xml" diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index bb95812b7be67..394936a29aa3e 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -42,7 +42,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 6cc922adb613b..1e9303e24dd3c 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -18,18 +18,13 @@ on: permissions: contents: read -env: - PYTHONIOENCODING: utf-8 - jobs: twister-tests: name: Twister Black Box Tests + runs-on: ubuntu-24.04 strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-24.04, macos-14, windows-2022] - fail-fast: false - runs-on: ${{ matrix.os }} steps: - name: Checkout uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 @@ -38,12 +33,19 @@ jobs: fetch-depth: 0 - name: Set Up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip cache-dependency-path: scripts/requirements-actions.txt + - name: install-packages + working-directory: zephyr + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + sudo apt-get update -y + sudo apt-get install -y lcov + - name: Setup Zephyr project uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 with: @@ -51,7 +53,6 @@ jobs: toolchains: all - name: Run Pytest For Twister Black Box Tests - if: ${{ startsWith(runner.os, 'ubuntu') }} working-directory: zephyr shell: bash env: @@ -62,125 +63,3 @@ jobs: echo "Run twister tests" source zephyr-env.sh PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/ - - - name: Build firmware No. 1 - basic - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS - - - name: Build firmware No. 2 - save and load with emulation only - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --save-tests tests.file $BASIC_FLAGS - ./scripts/twister --load-tests tests.file --emulation-only $BASIC_FLAGS - rm tests.file - - - name: Build firmware No. 3 - print out test plan - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --test-tree -T tests/kernel/spinlock $BASIC_FLAGS - - - name: Build firmware No. 4 - integration, exclude tag, filter, shuffle, dry run - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --dry-run --integration --subset 1/3 --shuffle-tests --shuffle-tests-seed 1 --filter runnable --exclude-tag audio --exclude-tag driver $BASIC_FLAGS - - - name: Build firmware No. 5 - test, arch, vendor, exclude-platform, platform-reports - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --test kernel.multiprocessing.spinlock --arch x86 --exclude-platform qemu_x86_64 --vendor qemu --platform-reports $BASIC_FLAGS - - - name: Build firmware No. 6 - subtest, platform, rom-ram report, ROM footprint report from buildlog, size report - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS - - - name: Build firmware No. 7 - list tags - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS - - - name: Build firmware No. 8 - list tests - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister -T tests/posix/common --list-tests $BASIC_FLAGS - - - name: Build firmware No. 9 - report flags - dir, name, suffix, summary, all-options, filtered - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS - - - name: Build firmware No. 10 - force platform and toolchain, log level, timestamps, logfile - working-directory: zephyr - shell: bash - run: | - if [ "${{ runner.os }}" = "macOS" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --build-only" - elif [ "${{ runner.os }}" = "Windows" ]; then - EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" - fi - BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS - rm log.file diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index c391148b5812d..1756664303d8d 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -39,7 +39,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 3a8e4a384f652..276bdcdd546ce 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -1685,6 +1685,7 @@ exclude = [ "./scripts/west_commands/runners/mdb.py", "./scripts/west_commands/runners/misc.py", "./scripts/west_commands/runners/native.py", + "./scripts/west_commands/runners/nios2.py", "./scripts/west_commands/runners/nrf_common.py", "./scripts/west_commands/runners/nrfjprog.py", "./scripts/west_commands/runners/nrfutil.py", diff --git a/CMakeLists.txt b/CMakeLists.txt index 74052ded69217..196a87294ea92 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -96,6 +96,7 @@ set(OFFSETS_H_TARGET offsets_h) set(SYSCALL_LIST_H_TARGET syscall_list_h_target) set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target) set(KOBJ_TYPES_H_TARGET kobj_types_h_target) +set(PARSE_SYSCALLS_TARGET parse_syscalls_target) set(DEVICE_API_LD_TARGET device_api_ld_target) define_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT BRIEF_DOCS " " FULL_DOCS " ") @@ -343,18 +344,6 @@ if (CONFIG_PICOLIBC AND NOT CONFIG_PICOLIBC_IO_FLOAT) zephyr_compile_options($<$:$>) endif() -if(CONFIG_UBSAN) - zephyr_compile_options($<$:$>) - zephyr_link_libraries($) - if(CONFIG_UBSAN_LIBRARY) - zephyr_compile_options($<$:$>) - zephyr_link_libraries($) - elseif(CONFIG_UBSAN_TRAP) - zephyr_compile_options($<$:$>) - zephyr_link_libraries($) - endif() -endif() - # @Intent: Set compiler specific flag for tentative definitions, no-common zephyr_compile_options($) @@ -833,7 +822,7 @@ add_custom_command( --file-list ${syscalls_file_list_output} $<$:--emit-all-syscalls> DEPENDS ${syscalls_subdirs_trigger} ${PARSE_SYSCALLS_HEADER_DEPENDS} - ${syscalls_file_list_output} syscalls_interface + ${syscalls_file_list_output} ${syscalls_interface} ) # Make sure Picolibc is built before the rest of the system; there's no explicit @@ -851,6 +840,12 @@ set_property(TARGET ${SYSCALL_LIST_H_TARGET} ${CMAKE_CURRENT_BINARY_DIR}/include/generated/zephyr/syscalls ) +add_custom_target(${PARSE_SYSCALLS_TARGET} + DEPENDS + ${syscalls_json} + ${struct_tags_json} + ) + # 64-bit systems do not require special handling of 64-bit system call # parameters or return values, indicate this to the system call boilerplate # generation script. @@ -893,24 +888,30 @@ add_custom_command( COMMAND ${LEGACY_SYSCALL_LIST_H_ARGS} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS ${syscalls_json} + DEPENDS ${PARSE_SYSCALLS_TARGET} ) -include(${ZEPHYR_BASE}/cmake/kobj.cmake) +# This is passed into all calls to the gen_kobject_list.py script. +set(gen_kobject_list_include_args --include-subsystem-list ${struct_tags_json}) set(DRV_VALIDATION ${PROJECT_BINARY_DIR}/include/generated/zephyr/driver-validation.h) -gen_kobject_list( - TARGET ${DRIVER_VALIDATION_H_TARGET} - OUTPUTS ${DRV_VALIDATION} - SCRIPT_ARGS --validation-output ${DRV_VALIDATION} - INCLUDES ${struct_tags_json} - DEPENDS ${struct_tags_json} +add_custom_command( + OUTPUT ${DRV_VALIDATION} + COMMAND + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py + --validation-output ${DRV_VALIDATION} + ${gen_kobject_list_include_args} + $<$:--verbose> + DEPENDS + ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py + ${PARSE_SYSCALLS_TARGET} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) +add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION}) -gen_kobject_list_headers( - INCLUDES ${struct_tags_json} - DEPENDS ${struct_tags_json} - ) +include(${ZEPHYR_BASE}/cmake/kobj.cmake) +gen_kobj(KOBJ_INCLUDE_PATH) # Generate sections for kernel device subsystems set( @@ -1109,6 +1110,7 @@ if(CONFIG_USERSPACE) NO_COVERAGE_FLAGS "${compiler_flags_priv}" ) + set(GEN_KOBJ_LIST ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py) set(PROCESS_GPERF ${ZEPHYR_BASE}/scripts/build/process_gperf.py) endif() @@ -1262,13 +1264,23 @@ if(CONFIG_USERSPACE) set(KOBJECT_PREBUILT_HASH_OUTPUT_SRC_PRE kobject_prebuilt_hash_preprocessed.c) set(KOBJECT_PREBUILT_HASH_OUTPUT_SRC kobject_prebuilt_hash.c) - gen_kobject_list_gperf( - TARGET kobj_prebuilt_hash_list + add_custom_command( OUTPUT ${KOBJECT_PREBUILT_HASH_LIST} - KERNEL_TARGET ${ZEPHYR_LINK_STAGE_EXECUTABLE} - INCLUDES ${struct_tags_json} - DEPENDS ${struct_tags_json} + COMMAND + ${PYTHON_EXECUTABLE} + ${GEN_KOBJ_LIST} + --kernel $ + --gperf-output ${KOBJECT_PREBUILT_HASH_LIST} + ${gen_kobject_list_include_args} + $<$:--verbose> + DEPENDS + ${ZEPHYR_LINK_STAGE_EXECUTABLE} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) + add_custom_target( + kobj_prebuilt_hash_list + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_PREBUILT_HASH_LIST} + ) add_custom_command( OUTPUT ${KOBJECT_PREBUILT_HASH_OUTPUT_SRC_PRE} @@ -1459,13 +1471,23 @@ if(CONFIG_USERSPACE) # Use the script GEN_KOBJ_LIST to scan the kernel binary's # (${ZEPHYR_LINK_STAGE_EXECUTABLE}) DWARF information to produce a table of kernel # objects (KOBJECT_HASH_LIST) which we will then pass to gperf - gen_kobject_list_gperf( - TARGET kobj_hash_list + add_custom_command( OUTPUT ${KOBJECT_HASH_LIST} - KERNEL_TARGET ${ZEPHYR_LINK_STAGE_EXECUTABLE} - INCLUDES ${struct_tags_json} - DEPENDS ${struct_tags_json} + COMMAND + ${PYTHON_EXECUTABLE} + ${GEN_KOBJ_LIST} + --kernel $ + --gperf-output ${KOBJECT_HASH_LIST} + ${gen_kobject_list_include_args} + $<$:--verbose> + DEPENDS + ${ZEPHYR_LINK_STAGE_EXECUTABLE} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) + add_custom_target( + kobj_hash_list + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_HASH_LIST} + ) # Use gperf to generate C code (KOBJECT_HASH_OUTPUT_SRC_PRE) which implements a # perfect hashtable based on KOBJECT_HASH_LIST @@ -1728,8 +1750,13 @@ if(CONFIG_BUILD_OUTPUT_ADJUST_LMA) ) endif() +if(NOT CONFIG_CPP_EXCEPTIONS) + set(eh_frame_section ".eh_frame") +else() + set(eh_frame_section "") +endif() set(remove_sections_argument_list "") -foreach(section .comment COMMON) +foreach(section .comment COMMON ${eh_frame_section}) list(APPEND remove_sections_argument_list $${section}) endforeach() @@ -1810,28 +1837,6 @@ if(CONFIG_BUILD_OUTPUT_BIN AND CONFIG_BUILD_OUTPUT_UF2) set(BYPRODUCT_KERNEL_UF2_NAME "${PROJECT_BINARY_DIR}/${KERNEL_UF2_NAME}" CACHE FILEPATH "Kernel uf2 file" FORCE) endif() -if(CONFIG_BUILD_OUTPUT_MOT) - get_property(elfconvert_formats TARGET bintools PROPERTY elfconvert_formats) - if(srec IN_LIST elfconvert_formats) - list(APPEND - post_build_commands - COMMAND $ - $ - ${GAP_FILL} - $srec - $${OUTPUT_FORMAT} - $${KERNEL_ELF_NAME} - $${KERNEL_MOT_NAME} - $ - ) - list(APPEND - post_build_byproducts - ${KERNEL_MOT_NAME} - ) - set(BYPRODUCT_KERNEL_MOT_NAME "${PROJECT_BINARY_DIR}/${KERNEL_MOT_NAME}" CACHE FILEPATH "Kernel mot file" FORCE) - endif() -endif() - set(KERNEL_META_PATH ${PROJECT_BINARY_DIR}/${KERNEL_META_NAME} CACHE INTERNAL "") if(CONFIG_BUILD_OUTPUT_META) list(APPEND @@ -2297,7 +2302,7 @@ if(CONFIG_LLEXT_EDK) ${SYSCALL_SPLIT_TIMEOUT_ARG} COMMAND ${CMAKE_COMMAND} -P ${ZEPHYR_BASE}/cmake/llext-edk.cmake - DEPENDS ${logical_target_for_zephyr_elf} ${syscalls_json} build_info_yaml_saved + DEPENDS ${logical_target_for_zephyr_elf} build_info_yaml_saved COMMAND_EXPAND_LISTS ) add_custom_target(llext-edk DEPENDS ${llext_edk_file}) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 99295612b68ff..23f7507b432f3 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -785,12 +785,6 @@ config BUILD_OUTPUT_UF2 Build a UF2 binary zephyr/zephyr.uf2 in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. -config BUILD_OUTPUT_MOT - bool "Build a binary in MOT format" - help - Build a MOT binary zephyr/zephyr.mot in the build directory. - The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. - if BUILD_OUTPUT_UF2 config BUILD_OUTPUT_UF2_FAMILY_ID diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 635869785c90f..2597ec3284e9c 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -126,19 +126,6 @@ ACPI: tests: - acpi -Aesc Platform: - status: maintained - maintainers: - - dnltz - files: - - soc/aesc/ - - dts/riscv/aesc/ - - boards/aesc/ - files-regex: - - ^drivers/.*aesc(\.c)?$ - labels: - - "area: Aesc Silicon Platform" - Antmicro platforms: status: maintained maintainers: @@ -183,7 +170,6 @@ Arduino Platforms: - facchinm files: - boards/arduino/ - - drivers/*/*modulino* ARM arch: status: maintained @@ -536,7 +522,6 @@ Bluetooth Audio: - tests/bsim/bluetooth/audio_samples/ - tests/bluetooth/shell/audio.conf - tests/bluetooth/tester/overlay-le-audio.conf - - tests/bluetooth/tester/overlay-bt_ll_sw_split.conf - tests/bluetooth/tester/src/audio/ - doc/connectivity/bluetooth/api/audio/ - doc/connectivity/bluetooth/shell/audio/ @@ -1006,7 +991,6 @@ Display drivers: - jfischer-no - danieldegrasse - VynDragon - - jarmouniA files: - drivers/display/ - dts/bindings/display/ @@ -1853,8 +1837,6 @@ Release Notes: status: odd fixes collaborators: - aasinclair - - nordic-auko - - seov-nordic files: - drivers/mfd/ - include/zephyr/drivers/mfd/ @@ -1882,8 +1864,7 @@ Release Notes: "Drivers: Regulators": status: maintained maintainers: - - nordic-auko - - seov-nordic + - gmarull collaborators: - danieldegrasse - aasinclair @@ -1995,7 +1976,9 @@ Release Notes: - sample.drivers.espi.ps2 "Drivers: PTP Clock": - status: odd fixes + status: maintained + maintainers: + - tbursztyka files: - drivers/ptp_clock/ - include/zephyr/drivers/ptp_clock.h @@ -2179,7 +2162,6 @@ Release Notes: - loicpoulain - josuah - ngphibang - - avolmat-st files: - drivers/video/ - include/zephyr/drivers/video.h @@ -2309,7 +2291,9 @@ Release Notes: - "area: Display Controller" "Drivers: Virtualization": - status: odd fixes + status: maintained + maintainers: + - tbursztyka files: - drivers/virtualization/ - tests/drivers/virtualization/ @@ -2872,6 +2856,7 @@ Networking: - jukkar collaborators: - pdgendt + - tbursztyka - ssharks files: - scripts/net/ @@ -2940,6 +2925,7 @@ Networking: - jhedberg collaborators: - rlubos + - tbursztyka - jukkar files: - doc/services/net_buf/ @@ -3151,6 +3137,25 @@ Networking: tests: - net.http +NIOS-2 arch: + status: maintained + maintainers: + - nashif + files: + - arch/nios2/ + - dts/nios2/intel/ + - boards/common/nios2.board.cmake + - soc/altr/*nios2*/ + - include/zephyr/arch/nios2/ + - tests/boards/altera_max10/ + - boards/qemu/nios2/ + - boards/altr/max10/ + - scripts/support/quartus-flash.py + labels: + - "area: NIOS2" + tests: + - boards.altera_max10 + nRF BSIM: status: maintained maintainers: @@ -3503,7 +3508,6 @@ Bouffalolab Platforms: status: maintained maintainers: - nandojve - - VynDragon files: - boards/bflb/ - drivers/*/*bflb* @@ -3829,12 +3833,10 @@ NXP Wireless: collaborators: - MaochenWang1 - axelnxp - - George-Stefan files: - drivers/wifi/nxp/ - drivers/bluetooth/hci/*nxp* - drivers/ieee802154/ieee802154_kw41z.c - - drivers/*/*mcxw*.c labels: - "platform: NXP Drivers" @@ -3891,7 +3893,6 @@ NXP Platforms (S32): - manuargue collaborators: - Dat-NguyenDuy - - congnguyenhuu files: - boards/nxp/*s32*/ - boards/common/*nxp_s32* @@ -3904,8 +3905,6 @@ NXP Platforms (S32): - include/zephyr/dt-bindings/*/nxp-s32* - include/zephyr/dt-bindings/*/nxp_s32* - include/zephyr/drivers/*/*nxp_s32* - files-exclude: - - boards/nxp/ucans32k1sic/ labels: - "platform: NXP S32" description: NXP S32 platforms and S32-specific drivers @@ -3948,13 +3947,10 @@ NXP Platforms (Robotics Products): maintainers: - bperseghetti - PetervdPerk-NXP - collaborators: - - manuargue files: - boards/nxp/vmu*/ - boards/nxp/rddrone_fmuk66/ - boards/nxp/mr_canhubk3/ - - boards/nxp/ucans32k1sic/ labels: - "platform: NXP Robotics" description: NXP Robotics Module Platform Products @@ -4023,19 +4019,13 @@ nRF Platforms: files: - boards/nordic/ - drivers/*/*nrf*.c - - drivers/*/*nrf*/ - drivers/*/*nordic*/ - soc/nordic/ - samples/boards/nordic/ - dts/*/nordic/ - dts/bindings/*/nordic,* - - include/zephyr/drivers/*/*nrf*.h - - include/zephyr/drivers/*/*nrf*/ - - include/zephyr/dt-bindings/*/nordic*.h - - include/zephyr/dt-bindings/*/nrf*.h - tests/drivers/*/*nrf*/ - snippets/nordic*/ - - tests/boards/nrf/ labels: - "platform: nRF" @@ -4181,7 +4171,6 @@ STM32 Platforms: - marwaiehm-st - mathieuchopstm - djiatsaf-st - - etienne-lms files: - boards/st/ - drivers/*/*stm32*.c @@ -4279,20 +4268,6 @@ ITE Platforms: labels: - "platform: ITE" -TI MSPM0 Platforms: - status: maintained - maintainers: - - ssekar15 - files: - - soc/ti/mspm0/ - - boards/ti/lp_mspm0g3507/ - - dts/arm/ti/mspm0/ - - dts/bindings/*/*mspm0* - - drivers/*/*_mspm0* - - modules/Kconfig.mspm0 - labels: - - "platform: Texas Instruments MSPM0" - TI SimpleLink Platforms: status: maintained maintainers: @@ -4595,9 +4570,6 @@ TDK Sensors: status: maintained maintainers: - RobinKastberg - collaborators: - - bjorniuppsala - - LoveKarlsson files: - cmake/*/iar/ - include/zephyr/toolchain/iar.h @@ -4944,6 +4916,15 @@ West: labels: - "platform: ADI" +"West project: hal_altera": + status: odd fixes + collaborators: + - nashif + files: + - modules/Kconfig.altera + labels: + - "platform: Altera" + "West project: hal_ambiq": status: odd fixes collaborators: @@ -4970,7 +4951,6 @@ West: status: maintained maintainers: - nandojve - - VynDragon files: - modules/hal_bouffalolab/ labels: @@ -5810,19 +5790,3 @@ zbus: - "area: llext" tests: - llext - -RX arch: - status: maintained - maintainers: - - duynguyenxa - files: - - arch/rx/ - - include/zephyr/arch/rx/ - - dts/rx/ - - boards/qemu/rx/ - - soc/renesas/rx/ - - tests/arch/rx/ - labels: - - "area: RX" - tests: - - arch.rx diff --git a/README.rst b/README.rst index a82f73b6fb0a1..9472db6d5ee7e 100644 --- a/README.rst +++ b/README.rst @@ -24,7 +24,7 @@ resource-constrained systems: from simple embedded environmental sensors and LED wearables to sophisticated smart watches and IoT wireless gateways. The Zephyr kernel supports multiple architectures, including ARM (Cortex-A, -Cortex-R, Cortex-M), Intel x86, ARC, Tensilica Xtensa, and RISC-V, +Cortex-R, Cortex-M), Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, SPARC, MIPS, and a large number of `supported boards`_. .. below included in doc/introduction/introduction.rst diff --git a/arch/Kconfig b/arch/Kconfig index 669263cbb38ca..916351ae605e6 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -33,7 +33,6 @@ config ARM select ARCH_IS_SET select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M select ARCH_SUPPORTS_COREDUMP_THREADS if CPU_CORTEX_M - select ARCH_SUPPORTS_COREDUMP_STACK_PTR if CPU_CORTEX_M # FIXME: current state of the code for all ARM requires this, but # is really only necessary for Cortex-M with ARM MPU! select GEN_PRIV_STACKS @@ -104,6 +103,15 @@ config X86 help x86 architecture +config NIOS2 + bool + select ARCH_IS_SET + select ATOMIC_OPERATIONS_C + imply XIP + select ARCH_HAS_TIMING_FUNCTIONS + help + Nios II Gen 2 architecture + config RISCV bool select ARCH_IS_SET @@ -158,15 +166,6 @@ config ARCH_POSIX help POSIX (native) architecture -config RX - bool - select ARCH_IS_SET - select ATOMIC_OPERATIONS_C - select USE_SWITCH - select USE_SWITCH_SUPPORTED - help - Renesas RX architecture - config ARCH_IS_SET bool help @@ -228,7 +227,7 @@ config SRAM_BASE_ADDRESS /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. -if ARC || ARM || ARM64 || X86 || RISCV || RX +if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_FLASH := zephyr,flash @@ -251,7 +250,7 @@ config FLASH_BASE_ADDRESS normally set by the board's defconfig file and the user should generally avoid modifying it via the menu configuration. -endif # ARM || ARM64 || ARC || X86 || RISCV || RX +endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV if ARCH_HAS_TRUSTED_EXECUTION @@ -328,7 +327,6 @@ config PRIVILEGED_STACK_SIZE config KOBJECT_TEXT_AREA int "Size of kobject text area" - default 1024 if UBSAN default 512 if COVERAGE_GCOV default 512 if NO_OPTIMIZATIONS default 512 if STACK_CANARIES && RISCV @@ -697,9 +695,6 @@ config ARCH_SUPPORTS_COREDUMP_THREADS config ARCH_SUPPORTS_COREDUMP_PRIV_STACKS bool -config ARCH_SUPPORTS_COREDUMP_STACK_PTR - bool - config ARCH_SUPPORTS_ARCH_HW_INIT bool diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index be3dc0c40aa27..bf3ab454a2c42 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -92,8 +92,8 @@ static void arc_cluster_scm_enable(void) /* Invalidate SCM before enabling. */ arc_cln_write_reg_nolock(ARC_CLN_CACHE_CMD, ARC_CLN_CACHE_CMD_OP_REG_INV | ARC_CLN_CACHE_CMD_INCR); - while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) { - } + while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) + ; arc_cln_write_reg_nolock(ARC_CLN_CACHE_STATUS, ARC_CLN_CACHE_STATUS_EN); } diff --git a/arch/archs.yml b/arch/archs.yml index 352a296dde2a5..e07d10ffe80b3 100644 --- a/arch/archs.yml +++ b/arch/archs.yml @@ -7,6 +7,8 @@ archs: path: arm64 - name: mips path: mips + - name: nios2 + path: nios2 - name: posix path: posix - name: riscv @@ -17,5 +19,3 @@ archs: path: xtensa - name: x86 path: x86 - - name: rx - path: rx diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index cab76d32f495f..07c5b32bf327e 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -63,13 +63,13 @@ void arch_dcache_disable(void) { uint32_t val; - L1C_CleanInvalidateDCacheAll(); - val = __get_SCTLR(); val &= ~SCTLR_C_Msk; barrier_dsync_fence_full(); __set_SCTLR(val); barrier_isync_fence_full(); + + arch_dcache_flush_and_invd_all(); } int arch_dcache_flush_all(void) diff --git a/arch/arm/core/cortex_m/coredump.c b/arch/arm/core/cortex_m/coredump.c index 787cfcdf4a751..ddb539c4e34ef 100644 --- a/arch/arm/core/cortex_m/coredump.c +++ b/arch/arm/core/cortex_m/coredump.c @@ -6,7 +6,6 @@ #include #include -#include #define ARCH_HDR_VER 2 @@ -97,8 +96,3 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_ARM_CORTEX_M; } - -uintptr_t arch_coredump_stack_ptr_get(const struct k_thread *thread) -{ - return (thread == _current) ? z_arm_coredump_fault_sp : thread->callee_saved.psp; -} diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index 530fc65835e3c..3e797c749c328 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -219,17 +219,13 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_resume) push {r0, lr} bl pm_s2ram_mark_check_and_clear cmp r0, #0x1 + pop {r0, lr} beq .L_resume - pop {r0, pc} + bx lr .L_resume: /* - * Switch to the stack used to execute "arch_pm_s2ram_suspend" - * and restore CPU context backed up by that function, then - * return to the call site of "arch_pm_s2ram_suspend". - * - * Note: the "push {r0, lr}" performed earlier doesn't - * need to be balanced out since we are switching stacks. + * Restore the CPU context */ ldr r0, =_cpu_context diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig index 698b2bb270a84..ff48692ec65fe 100644 --- a/arch/arm/core/mpu/Kconfig +++ b/arch/arm/core/mpu/Kconfig @@ -71,7 +71,6 @@ config CUSTOM_SECTION_MIN_ALIGN_SIZE config ARM_MPU_PXN bool - default y depends on ARMV8_1_M_MAINLINE help Enable support for Armv8.1-m MPU's Privileged Execute Never (PXN) attr. diff --git a/arch/arm/core/mpu/arm_mpu_v7_internal.h b/arch/arm/core/mpu/arm_mpu_v7_internal.h index 40d03865d07c9..9641ab250003c 100644 --- a/arch/arm/core/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v7_internal.h @@ -145,7 +145,7 @@ static inline int get_dyn_region_min_index(void) /* Only a single bit is set for all user accessible permissions. * In ARMv7-M MPU this is bit AP[1]. */ -#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO) +#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO & RO) /** * This internal function checks if the region is user accessible or not. diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index cbac2724587a6..0800a16436f16 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -47,7 +47,7 @@ extern volatile irq_offload_routine_t offload_routine; /* Prefix. Indicates that this is an EXC_RETURN value. * This field reads as 0b11111111. */ -#define EXC_RETURN_INDICATOR_PREFIX (0xFFU << 24) +#define EXC_RETURN_INDICATOR_PREFIX (0xFF << 24) /* bit[0]: Exception Secure. The security domain the exception was taken to. */ #define EXC_RETURN_EXCEPTION_SECURE_Pos 0 #define EXC_RETURN_EXCEPTION_SECURE_Msk BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 21327f62c1ba1..35a480a24fde6 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -126,7 +126,6 @@ config PRIVILEGED_STACK_SIZE default 4096 config KOBJECT_TEXT_AREA - default 1024 if UBSAN default 512 if TEST config WAIT_AT_RESET_VECTOR diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index cb5f485c0d520..e7480c9de15aa 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -207,28 +207,24 @@ static bool is_address_mapped(uint64_t *addr) { uintptr_t *phys = NULL; - if (*addr == 0U) { + if (*addr == 0U) return false; - } /* Check alignment. */ - if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) return false; - } return !arch_page_phys_get((void *) addr, phys); } static bool is_valid_jump_address(uint64_t *addr) { - if (*addr == 0U) { + if (*addr == 0U) return false; - } /* Check alignment. */ - if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) return false; - } return ((*addr >= (uint64_t)__text_region_start) && (*addr <= (uint64_t)(__text_region_end))); @@ -270,9 +266,8 @@ static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct a if (!is_address_mapped(fp)) break; lr = fp[1]; - if (!is_valid_jump_address(&lr)) { + if (!is_valid_jump_address(&lr)) break; - } if (!cb(cookie, lr, fp)) { break; } diff --git a/arch/nios2/CMakeLists.txt b/arch/nios2/CMakeLists.txt new file mode 100644 index 0000000000000..f0424b169b6fc --- /dev/null +++ b/arch/nios2/CMakeLists.txt @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_GP_NONE) +set(gpopt none) +elseif(CONFIG_GP_LOCAL) +set(gpopt local) +elseif(CONFIG_GP_GLOBAL) +set(gpopt global) +elseif(CONFIG_GP_ALL_DATA) +set(gpopt data) +endif() + +# Set Global Pointer option based on Kconfig. +zephyr_cc_option(-mgpopt=${gpopt}) + +# TODO Find a way to pull this out of system.h somehow +# instead of having Kconfig for it + +if(CONFIG_HAS_MUL_INSTRUCTION) +zephyr_cc_option(-mhw-mul) +else() +zephyr_cc_option(-mno-hw-mul) +endif() + +if(CONFIG_HAS_MULX_INSTRUCTION) +zephyr_cc_option(-mhw-mulx) +else() +zephyr_cc_option(-mno-hw-mulx) +endif() + +if(CONFIG_HAS_DIV_INSTRUCTION) +zephyr_cc_option(-mhw-div) +else() +zephyr_cc_option(-mno-hw-div) +endif() + +add_subdirectory(core) diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig new file mode 100644 index 0000000000000..6e147119421a4 --- /dev/null +++ b/arch/nios2/Kconfig @@ -0,0 +1,96 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +menu "Nios II Options" + depends on NIOS2 + +config ARCH + string + default "nios2" + +menu "Nios II Gen 2 Processor Options" + +config CPU_NIOS2_GEN2 + bool + default y + select BUILD_OUTPUT_HEX + select ARCH_HAS_EXTRA_EXCEPTION_INFO + help + This option signifies the use of a Nios II Gen 2 CPU + +endmenu + +menu "Nios II Family Options" + +config GEN_ISR_TABLES + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config NUM_IRQS + int + default 32 + +config HAS_MUL_INSTRUCTION + bool + +config HAS_DIV_INSTRUCTION + bool + +config HAS_MULX_INSTRUCTION + bool + +config INCLUDE_RESET_VECTOR + bool "Include Reset vector" + default y + help + Include the reset vector stub, which enables instruction/data caches + and then jumps to __start. This code is typically located at the very + beginning of flash memory. You may need to omit this if using the + nios2-download tool since it refuses to load data anywhere other than + RAM. + +config EXTRA_EXCEPTION_INFO + bool "Extra exception debug information" + help + Have exceptions print additional useful debugging information in + human-readable form, at the expense of code size. For example, + the cause code for an exception will be supplemented by a string + describing what that cause code means. + +choice + prompt "Global Pointer options" + default GP_GLOBAL + +config GP_NONE + bool "No global pointer" + help + Do not use global pointer relative offsets at all + +config GP_LOCAL + bool "Local data global pointer references" + help + Use global pointer relative offsets for small globals declared in the + same C file as the code that uses it. + +config GP_GLOBAL + bool "Global data global pointer references" + help + Use global pointer relative offsets for small globals declared + anywhere in the executable. Note that if any small globals that are put + in alternate sections they must be declared + in headers with proper __attribute__((section)) or the linker will + error out. + +config GP_ALL_DATA + bool "All data global pointer references" + help + Use GP relative access for all data in the program, not just + small data. Use this if your board has 64K or less of RAM. + +endchoice + +endmenu + +endmenu diff --git a/arch/nios2/core/CMakeLists.txt b/arch/nios2/core/CMakeLists.txt new file mode 100644 index 0000000000000..84fa0b49b3f3e --- /dev/null +++ b/arch/nios2/core/CMakeLists.txt @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources( + thread.c + cpu_idle.c + fatal.c + irq_manage.c + swap.S + prep_c.c + reset.S + cache.c + exception.S + crt0.S + ) + +zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) +zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) diff --git a/arch/nios2/core/cache.c b/arch/nios2/core/cache.c new file mode 100644 index 0000000000000..c13c43c7188d9 --- /dev/null +++ b/arch/nios2/core/cache.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + + +/** + * Flush the entire instruction cache and pipeline. + * + * You will need to call this function if the application writes new program + * text to memory, such as a boot copier or runtime synthesis of code. If the + * new text was written with instructions that do not bypass cache memories, + * this should immediately be followed by an invocation of + * z_nios2_dcache_flush_all() so that cached instruction data is committed to + * RAM. + * + * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more + * information on cache considerations. + */ +#if ALT_CPU_ICACHE_SIZE > 0 +void z_nios2_icache_flush_all(void) +{ + uint32_t i; + + for (i = 0U; i < ALT_CPU_ICACHE_SIZE; i += ALT_CPU_ICACHE_LINE_SIZE) { + z_nios2_icache_flush(i); + } + + /* Get rid of any stale instructions in the pipeline */ + z_nios2_pipeline_flush(); +} +#endif + +/** + * Flush the entire data cache. + * + * This will be typically needed after writing new program text to memory + * after flushing the instruction cache. + * + * The Nios II does not support hardware cache coherency for multi-master + * or multi-processor systems and software coherency must be implemented + * when communicating with shared memory. If support for this is introduced + * in Zephyr additional APIs for flushing ranges of the data cache will need + * to be implemented. + * + * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more + * information on cache considerations. + */ +#if ALT_CPU_DCACHE_SIZE > 0 +void z_nios2_dcache_flush_all(void) +{ + uint32_t i; + + for (i = 0U; i < ALT_CPU_DCACHE_SIZE; i += ALT_CPU_DCACHE_LINE_SIZE) { + z_nios2_dcache_flush(i); + } +} +#endif + +/* + * z_nios2_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the z_nios2_dcache_flush() routine instead. + */ +#if ALT_CPU_DCACHE_SIZE > 0 +void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len) +{ + uint8_t *i; + uint8_t *end = ((char *) start) + len; + + for (i = start; i < end; i += ALT_CPU_DCACHE_LINE_SIZE) { + __asm__ volatile ("initda (%0)" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on ALT_CPU_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((uint32_t) start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) { + __asm__ volatile ("initda (%0)" :: "r" (i)); + } +} +#endif diff --git a/arch/nios2/core/cpu_idle.c b/arch/nios2/core/cpu_idle.c new file mode 100644 index 0000000000000..b201ecfa84ea0 --- /dev/null +++ b/arch/nios2/core/cpu_idle.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE +void arch_cpu_idle(void) +{ + /* Do nothing but unconditionally unlock interrupts and return to the + * caller. This CPU does not have any kind of power saving instruction. + */ + irq_unlock(NIOS2_STATUS_PIE_MSK); +} +#endif + +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE +void arch_cpu_atomic_idle(unsigned int key) +{ + /* Do nothing but restore IRQ state. This CPU does not have any + * kind of power saving instruction. + */ + irq_unlock(key); +} +#endif diff --git a/arch/nios2/core/crt0.S b/arch/nios2/core/crt0.S new file mode 100644 index 0000000000000..2f708bf26f4af --- /dev/null +++ b/arch/nios2/core/crt0.S @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* exports */ +GTEXT(__start) +GTEXT(__reset) + +/* imports */ +GTEXT(z_prep_c) +GTEXT(z_interrupt_stacks) + + /* Allow use of r1/at (the assembler temporary register) in this + * code, normally reserved for internal assembler use + */ + .set noat + + +#if CONFIG_INCLUDE_RESET_VECTOR +/* + * Reset vector entry point into the system. Placed into special 'reset' + * section so that the linker puts this at ALT_CPU_RESET_ADDR defined in + * system.h + * + * This code can be at most 0x20 bytes, since the exception vector for Nios II + * is usually configured to be 0x20 past the reset vector. + */ +SECTION_FUNC(reset, __reset) + +#if ALT_CPU_ICACHE_SIZE > 0 + /* Aside from the instruction cache line associated with the reset + * vector, the contents of the cache memories are indeterminate after + * reset. To ensure cache coherency after reset, the reset handler + * located at the reset vector must immediately initialize the + * instruction cache. Next, either the reset handler or a subsequent + * routine should proceed to initialize the data cache. + * + * The cache memory sizes are *always* a power of 2. + */ +#if ALT_CPU_ICACHE_SIZE > 0x8000 + movhi r2, %hi(ALT_CPU_ICACHE_SIZE) +#else + movui r2, ALT_CPU_ICACHE_SIZE +#endif +0: + /* If ECC present, need to execute initd for each word address + * to ensure ECC parity bits in data RAM get initialized + */ +#ifdef ALT_CPU_ECC_PRESENT + subi r2, r2, 4 +#else + subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE +#endif + initi r2 + bgt r2, zero, 0b +#endif /* ALT_CPU_ICACHE_SIZE > 0 */ + + /* Done all we need to do here, jump to __text_start */ + movhi r1, %hi(__start) + ori r1, r1, %lo(__start) + jmp r1 +#endif /* CONFIG_INCLUDE_RESET_VECTOR */ + +/* Remainder of asm-land initialization code before we can jump into + * the C domain + */ +SECTION_FUNC(TEXT, __start) + + /* TODO if shadow register sets enabled, ensure we are in set 0 + * GH-1821 + */ + + /* Initialize the data cache if booting from bare metal. If + * we're not booting from our reset vector, either by a bootloader + * or JTAG, assume caches already initialized. + */ +#if ALT_CPU_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR) + /* Per documentation data cache size is always a power of two. */ +#if ALT_CPU_DCACHE_SIZE > 0x8000 + movhi r2, %hi(ALT_CPU_DCACHE_SIZE) +#else + movui r2, ALT_CPU_DCACHE_SIZE +#endif +0: + /* If ECC present, need to execute initd for each word address + * to ensure ECC parity bits in data RAM get initialized + */ +#ifdef ALT_CPU_ECC_PRESENT + subi r2, r2, 4 +#else + subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE +#endif + initd 0(r2) + bgt r2, zero, 0b +#endif /* ALT_CPU_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */ + +#ifdef CONFIG_INIT_STACKS + /* Pre-populate all bytes in z_interrupt_stacks with 0xAA + * init.c enforces that the z_interrupt_stacks pointer + * and CONFIG_ISR_STACK_SIZE are a multiple of ARCH_STACK_PTR_ALIGN (4) + */ + movhi r1, %hi(z_interrupt_stacks) + ori r1, r1, %lo(z_interrupt_stacks) + movhi r2, %hi(CONFIG_ISR_STACK_SIZE) + ori r2, r2, %lo(CONFIG_ISR_STACK_SIZE) + /* Put constant 0xaaaaaaaa in r3 */ + movhi r3, 0xaaaa + ori r3, r3, 0xaaaa +1: + /* Loop through the z_interrupt_stacks treating it as an array of + * uint32_t, setting each element to r3 */ + stw r3, (r1) + subi r2, r2, 4 + addi r1, r1, 4 + blt r0, r2, 1b +#endif + + /* Set up the initial stack pointer to the interrupt stack, safe + * to use this as the CPU boots up with interrupts disabled and we + * don't turn them on until much later, when the kernel is on + * the main stack */ + movhi sp, %hi(z_interrupt_stacks) + ori sp, sp, %lo(z_interrupt_stacks) + addi sp, sp, CONFIG_ISR_STACK_SIZE + +#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL) || \ + defined(CONFIG_GP_ALL_DATA) + /* Initialize global pointer with the linker variable we set */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) +#endif + + /* TODO if shadow register sets enabled, interate through them to set + * up. Need to clear r0, write gp, set the exception stack pointer + * GH-1821 + */ + + /* Jump into C domain. z_prep_c zeroes BSS, copies rw data into RAM, + * and then enters z_cstart */ + call z_prep_c + diff --git a/arch/nios2/core/exception.S b/arch/nios2/core/exception.S new file mode 100644 index 0000000000000..8dd7e0b9b9b8f --- /dev/null +++ b/arch/nios2/core/exception.S @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/* exports */ +GTEXT(_exception) + +/* import */ +GTEXT(z_nios2_fault) +GTEXT(arch_swap) +#ifdef CONFIG_IRQ_OFFLOAD +GTEXT(z_irq_do_offload) +GTEXT(_offload_routine) +#endif + +/* Allows use of r1/at register, otherwise reserved for assembler use */ +.set noat + +/* Placed into special 'exception' section so that the linker can put this code + * at ALT_CPU_EXCEPTION_ADDR defined in system.h + * + * This is the common entry point for processor exceptions and interrupts from + * the Internal Interrupt Controller (IIC). + * + * If the External (EIC) controller is in use, then we will never get here on + * behalf of an interrupt, instead the EIC driver will have set up a vector + * table and the processor will jump directly into the appropriate table + * entry. + */ +SECTION_FUNC(exception.entry, _exception) + /* Reserve thread stack space for saving context */ + subi sp, sp, __struct_arch_esf_SIZEOF + + /* Preserve all caller-saved registers onto the thread's stack */ + stw ra, __struct_arch_esf_ra_OFFSET(sp) + stw r1, __struct_arch_esf_r1_OFFSET(sp) + stw r2, __struct_arch_esf_r2_OFFSET(sp) + stw r3, __struct_arch_esf_r3_OFFSET(sp) + stw r4, __struct_arch_esf_r4_OFFSET(sp) + stw r5, __struct_arch_esf_r5_OFFSET(sp) + stw r6, __struct_arch_esf_r6_OFFSET(sp) + stw r7, __struct_arch_esf_r7_OFFSET(sp) + stw r8, __struct_arch_esf_r8_OFFSET(sp) + stw r9, __struct_arch_esf_r9_OFFSET(sp) + stw r10, __struct_arch_esf_r10_OFFSET(sp) + stw r11, __struct_arch_esf_r11_OFFSET(sp) + stw r12, __struct_arch_esf_r12_OFFSET(sp) + stw r13, __struct_arch_esf_r13_OFFSET(sp) + stw r14, __struct_arch_esf_r14_OFFSET(sp) + stw r15, __struct_arch_esf_r15_OFFSET(sp) + + /* Store value of estatus control register */ + rdctl et, estatus + stw et, __struct_arch_esf_estatus_OFFSET(sp) + + /* ea-4 is the address of the instruction when the exception happened, + * put this in the stack frame as well + */ + addi r15, ea, -4 + stw r15, __struct_arch_esf_instr_OFFSET(sp) + + /* Figure out whether we are here because of an interrupt or an + * exception. If an interrupt, switch stacks and enter IRQ handling + * code. If an exception, remain on current stack and enter exception + * handing code. From the CPU manual, ipending must be nonzero and + * estatis.PIE must be enabled for this to be considered an interrupt. + * + * Stick ipending in r4 since it will be an arg for _enter_irq + */ + rdctl r4, ipending + beq r4, zero, not_interrupt + /* We stashed estatus in et earlier */ + andi r15, et, 1 + beq r15, zero, not_interrupt + +is_interrupt: + /* If we get here, this is an interrupt */ + + /* Grab a reference to _kernel in r10 so we can determine the + * current irq stack pointer + */ + movhi r10, %hi(_kernel) + ori r10, r10, %lo(_kernel) + + /* Stash a copy of thread's sp in r12 so that we can put it on the IRQ + * stack + */ + mov r12, sp + + /* Switch to interrupt stack */ + ldw sp, _kernel_offset_to_irq_stack(r10) + + /* Store thread stack pointer onto IRQ stack */ + addi sp, sp, -4 + stw r12, 0(sp) + +on_irq_stack: + + /* Enter C interrupt handling code. Value of ipending will be the + * function parameter since we put it in r4 + */ + call _enter_irq + + /* Interrupt handler finished and the interrupt should be serviced + * now, the appropriate bits in ipending should be cleared */ + + /* Get a reference to _kernel again in r10 */ + movhi r10, %hi(_kernel) + ori r10, r10, %lo(_kernel) + +#ifdef CONFIG_PREEMPT_ENABLED + ldw r11, _kernel_offset_to_current(r10) + /* Determine whether the exception of the ISR requires context + * switch + */ + + /* Call into the kernel to see if a scheduling decision is necessary */ + ldw r2, _kernel_offset_to_ready_q_cache(r10) + beq r2, r11, no_reschedule + + /* + * A context reschedule is required: keep the volatile registers of + * the interrupted thread on the context's stack. Utilize + * the existing arch_swap() primitive to save the remaining + * thread's registers (including floating point) and perform + * a switch to the new thread. + */ + + /* We put the thread stack pointer on top of the IRQ stack before + * we switched stacks. Restore it to go back to thread stack + */ + ldw sp, 0(sp) + + /* Argument to Swap() is estatus since that's the state of the + * status register before the exception happened. When coming + * out of the context switch we need this info to restore + * IRQ lock state. We put this value in et earlier. + */ + mov r4, et + + call arch_swap + jmpi _exception_exit +#else + jmpi no_reschedule +#endif /* CONFIG_PREEMPT_ENABLED */ + +not_interrupt: + + /* Since this wasn't an interrupt we're not going to restart the + * faulting instruction. + * + * We earlier put ea - 4 in the stack frame, replace it with just ea + */ + stw ea, __struct_arch_esf_instr_OFFSET(sp) + +#ifdef CONFIG_IRQ_OFFLOAD + /* Check the contents of _offload_routine. If non-NULL, jump into + * the interrupt code anyway. + */ + movhi r10, %hi(_offload_routine) + ori r10, r10, %lo(_offload_routine) + ldw r11, (r10) + bne r11, zero, is_interrupt +#endif + +_exception_enter_fault: + /* If we get here, the exception wasn't in interrupt or an + * invocation of irq_offload(). Let z_nios2_fault() handle it in + * C domain + */ + + mov r4, sp + call z_nios2_fault + jmpi _exception_exit + +no_reschedule: + + /* We put the thread stack pointer on top of the IRQ stack before + * we switched stacks. Restore it to go back to thread stack + */ + ldw sp, 0(sp) + + /* Fall through */ + +_exception_exit: + /* We are on the thread stack. Restore all saved registers + * and return to the interrupted context */ + + /* Return address from the exception */ + ldw ea, __struct_arch_esf_instr_OFFSET(sp) + + /* Restore estatus + * XXX is this right??? */ + ldw r5, __struct_arch_esf_estatus_OFFSET(sp) + wrctl estatus, r5 + + /* Restore caller-saved registers */ + ldw ra, __struct_arch_esf_ra_OFFSET(sp) + ldw r1, __struct_arch_esf_r1_OFFSET(sp) + ldw r2, __struct_arch_esf_r2_OFFSET(sp) + ldw r3, __struct_arch_esf_r3_OFFSET(sp) + ldw r4, __struct_arch_esf_r4_OFFSET(sp) + ldw r5, __struct_arch_esf_r5_OFFSET(sp) + ldw r6, __struct_arch_esf_r6_OFFSET(sp) + ldw r7, __struct_arch_esf_r7_OFFSET(sp) + ldw r8, __struct_arch_esf_r8_OFFSET(sp) + ldw r9, __struct_arch_esf_r9_OFFSET(sp) + ldw r10, __struct_arch_esf_r10_OFFSET(sp) + ldw r11, __struct_arch_esf_r11_OFFSET(sp) + ldw r12, __struct_arch_esf_r12_OFFSET(sp) + ldw r13, __struct_arch_esf_r13_OFFSET(sp) + ldw r14, __struct_arch_esf_r14_OFFSET(sp) + ldw r15, __struct_arch_esf_r15_OFFSET(sp) + + /* Put the stack pointer back where it was when we entered + * exception state + */ + addi sp, sp, __struct_arch_esf_SIZEOF + + /* All done, copy estatus into status and transfer to ea */ + eret diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c new file mode 100644 index 0000000000000..3f34c1e8fc7ec --- /dev/null +++ b/arch/nios2/core/fatal.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, + const struct arch_esf *esf) +{ +#if CONFIG_EXCEPTION_DEBUG + if (esf != NULL) { + /* Subtract 4 from EA since we added 4 earlier so that the + * faulting instruction isn't retried. + * + * TODO: Only caller-saved registers get saved upon exception + * entry. We may want to introduce a config option to save and + * dump all registers, at the expense of some stack space. + */ + LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4); + LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x", + esf->r1, esf->r2, esf->r3, esf->r4); + LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x", + esf->r5, esf->r6, esf->r7, esf->r8); + LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x", + esf->r9, esf->r10, esf->r11, esf->r12); + LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x", + esf->r13, esf->r14, esf->r15, esf->ra); + LOG_ERR("estatus: %08x", esf->estatus); + } +#endif /* CONFIG_EXCEPTION_DEBUG */ + + z_fatal_error(reason, esf); + CODE_UNREACHABLE; +} + +#if defined(CONFIG_EXTRA_EXCEPTION_INFO) && \ + (defined(CONFIG_PRINTK) || defined(CONFIG_LOG)) \ + && defined(ALT_CPU_HAS_EXTRA_EXCEPTION_INFO) +static char *cause_str(uint32_t cause_code) +{ + switch (cause_code) { + case 0: + return "reset"; + case 1: + return "processor-only reset request"; + case 2: + return "interrupt"; + case 3: + return "trap"; + case 4: + return "unimplemented instruction"; + case 5: + return "illegal instruction"; + case 6: + return "misaligned data address"; + case 7: + return "misaligned destination address"; + case 8: + return "division error"; + case 9: + return "supervisor-only instruction address"; + case 10: + return "supervisor-only instruction"; + case 11: + return "supervisor-only data address"; + case 12: + return "TLB miss"; + case 13: + return "TLB permission violation (execute)"; + case 14: + return "TLB permission violation (read)"; + case 15: + return "TLB permission violation (write)"; + case 16: + return "MPU region violation (instruction)"; + case 17: + return "MPU region violation (data)"; + case 18: + return "ECC TLB error"; + case 19: + return "ECC fetch error (instruction)"; + case 20: + return "ECC register file error"; + case 21: + return "ECC data error"; + case 22: + return "ECC data cache writeback error"; + case 23: + return "bus instruction fetch error"; + case 24: + return "bus data region violation"; + default: + return "unknown"; + } +} +#endif + +FUNC_NORETURN void z_nios2_fault(const struct arch_esf *esf) +{ +#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) + /* Unfortunately, completely unavailable on Nios II/e cores */ +#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO + uint32_t exc_reg, badaddr_reg, eccftl; + enum nios2_exception_cause cause; + + exc_reg = z_nios2_creg_read(NIOS2_CR_EXCEPTION); + + /* Bit 31 indicates potentially fatal ECC error */ + eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0U; + + /* Bits 2-6 contain the cause code */ + cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK) + >> NIOS2_EXCEPTION_REG_CAUSE_OFST; + + LOG_ERR("Exception cause: %d ECCFTL: 0x%x", cause, eccftl); +#if CONFIG_EXTRA_EXCEPTION_INFO + LOG_ERR("reason: %s", cause_str(cause)); +#endif + if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) { + badaddr_reg = z_nios2_creg_read(NIOS2_CR_BADADDR); + LOG_ERR("Badaddr: 0x%x", badaddr_reg); + } +#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */ +#endif /* CONFIG_PRINTK || CONFIG_LOG */ + + z_nios2_fatal_error(K_ERR_CPU_EXCEPTION, esf); +} + +#ifdef ALT_CPU_HAS_DEBUG_STUB +FUNC_NORETURN void arch_system_halt(unsigned int reason) +{ + ARG_UNUSED(reason); + + z_nios2_break(); + CODE_UNREACHABLE; +} +#endif diff --git a/arch/nios2/core/irq_manage.c b/arch/nios2/core/irq_manage.c new file mode 100644 index 0000000000000..6f4b2bdf10cf8 --- /dev/null +++ b/arch/nios2/core/irq_manage.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Nios II C-domain interrupt management code for use with Internal + * Interrupt Controller (IIC) + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +FUNC_NORETURN void z_irq_spurious(const void *unused) +{ + ARG_UNUSED(unused); + LOG_ERR("Spurious interrupt detected! ipending: %x", + z_nios2_creg_read(NIOS2_CR_IPENDING)); + z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); +} + + +void arch_irq_enable(unsigned int irq) +{ + uint32_t ienable; + unsigned int key; + + key = irq_lock(); + + ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); + ienable |= BIT(irq); + z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); + + irq_unlock(key); +}; + + + +void arch_irq_disable(unsigned int irq) +{ + uint32_t ienable; + unsigned int key; + + key = irq_lock(); + + ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); + ienable &= ~BIT(irq); + z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); + + irq_unlock(key); +}; + +int arch_irq_is_enabled(unsigned int irq) +{ + uint32_t ienable; + + ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); + return ienable & BIT(irq); +} + +/** + * @brief Interrupt demux function + * + * Given a bitfield of pending interrupts, execute the appropriate handler + * + * @param ipending Bitfield of interrupts + */ +void _enter_irq(uint32_t ipending) +{ + int index; + + _kernel.cpus[0].nested++; + +#ifdef CONFIG_IRQ_OFFLOAD + z_irq_do_offload(); +#endif + + while (ipending) { + struct _isr_table_entry *ite; + +#ifdef CONFIG_TRACING_ISR + sys_trace_isr_enter(); +#endif + + index = find_lsb_set(ipending) - 1; + ipending &= ~BIT(index); + + ite = &_sw_isr_table[index]; + + ite->isr(ite->arg); +#ifdef CONFIG_TRACING_ISR + sys_trace_isr_exit(); +#endif + } + + _kernel.cpus[0].nested--; +#ifdef CONFIG_STACK_SENTINEL + z_check_stack_sentinel(); +#endif +} + +#ifdef CONFIG_DYNAMIC_INTERRUPTS +int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, + void (*routine)(const void *parameter), + const void *parameter, uint32_t flags) +{ + ARG_UNUSED(flags); + ARG_UNUSED(priority); + + z_isr_install(irq, routine, parameter); + return irq; +} +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/nios2/core/irq_offload.c b/arch/nios2/core/irq_offload.c new file mode 100644 index 0000000000000..0c918896be958 --- /dev/null +++ b/arch/nios2/core/irq_offload.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +volatile irq_offload_routine_t _offload_routine; +static volatile const void *offload_param; + +/* Called by _enter_irq if it was passed 0 for ipending. + * Just in case the offload routine itself generates an unhandled + * exception, clear the offload_routine global before executing. + */ +void z_irq_do_offload(void) +{ + irq_offload_routine_t tmp; + + if (!_offload_routine) { + return; + } + + tmp = _offload_routine; + _offload_routine = NULL; + + tmp((const void *)offload_param); +} + +void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) +{ + unsigned int key; + + key = irq_lock(); + _offload_routine = routine; + offload_param = parameter; + + __asm__ volatile ("trap"); + + irq_unlock(key); +} + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/nios2/core/offsets/offsets.c b/arch/nios2/core/offsets/offsets.c new file mode 100644 index 0000000000000..9d381d87446c1 --- /dev/null +++ b/arch/nios2/core/offsets/offsets.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Nios II kernel structure member offset definition file + * + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various Nios II kernel + * structures. + * + * All of the absolute symbols defined by this module will be present in the + * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms + * symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. + */ + + +#include +#include +#include +#include + +/* struct coop member offsets */ +GEN_OFFSET_SYM(_callee_saved_t, r16); +GEN_OFFSET_SYM(_callee_saved_t, r17); +GEN_OFFSET_SYM(_callee_saved_t, r18); +GEN_OFFSET_SYM(_callee_saved_t, r19); +GEN_OFFSET_SYM(_callee_saved_t, r20); +GEN_OFFSET_SYM(_callee_saved_t, r21); +GEN_OFFSET_SYM(_callee_saved_t, r22); +GEN_OFFSET_SYM(_callee_saved_t, r23); +GEN_OFFSET_SYM(_callee_saved_t, r28); +GEN_OFFSET_SYM(_callee_saved_t, ra); +GEN_OFFSET_SYM(_callee_saved_t, sp); +GEN_OFFSET_SYM(_callee_saved_t, key); +GEN_OFFSET_SYM(_callee_saved_t, retval); + +GEN_OFFSET_STRUCT(arch_esf, ra); +GEN_OFFSET_STRUCT(arch_esf, r1); +GEN_OFFSET_STRUCT(arch_esf, r2); +GEN_OFFSET_STRUCT(arch_esf, r3); +GEN_OFFSET_STRUCT(arch_esf, r4); +GEN_OFFSET_STRUCT(arch_esf, r5); +GEN_OFFSET_STRUCT(arch_esf, r6); +GEN_OFFSET_STRUCT(arch_esf, r7); +GEN_OFFSET_STRUCT(arch_esf, r8); +GEN_OFFSET_STRUCT(arch_esf, r9); +GEN_OFFSET_STRUCT(arch_esf, r10); +GEN_OFFSET_STRUCT(arch_esf, r11); +GEN_OFFSET_STRUCT(arch_esf, r12); +GEN_OFFSET_STRUCT(arch_esf, r13); +GEN_OFFSET_STRUCT(arch_esf, r14); +GEN_OFFSET_STRUCT(arch_esf, r15); +GEN_OFFSET_STRUCT(arch_esf, estatus); +GEN_OFFSET_STRUCT(arch_esf, instr); +GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); + +GEN_ABS_SYM_END diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c new file mode 100644 index 0000000000000..c599620595682 --- /dev/null +++ b/arch/nios2/core/prep_c.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Full C support initialization + * + * + * Initialization of full C support: zero the .bss, copy the .data if XIP, + * call z_cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * @brief Prepare to and run C code + * + * This routine prepares for the execution of and runs C code. + */ + +void z_prep_c(void) +{ +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + + z_bss_zero(); + z_data_copy(); + /* In most XIP scenarios we copy the exception code into RAM, so need + * to flush instruction cache. + */ +#ifdef CONFIG_XIP + z_nios2_icache_flush_all(); +#if ALT_CPU_ICACHE_SIZE > 0 + /* Only need to flush the data cache here if there actually is an + * instruction cache, so that the cached instruction data written is + * actually committed. + */ + z_nios2_dcache_flush_all(); +#endif +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif + z_cstart(); + CODE_UNREACHABLE; +} diff --git a/arch/nios2/core/reset.S b/arch/nios2/core/reset.S new file mode 100644 index 0000000000000..6ec3ff3044dd2 --- /dev/null +++ b/arch/nios2/core/reset.S @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +GTEXT(__start) + diff --git a/arch/nios2/core/swap.S b/arch/nios2/core/swap.S new file mode 100644 index 0000000000000..fa1cd597bc463 --- /dev/null +++ b/arch/nios2/core/swap.S @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/* exports */ +GTEXT(arch_swap) +GTEXT(z_thread_entry_wrapper) + +/* imports */ +GTEXT(_k_neg_eagain) + +/* unsigned int arch_swap(unsigned int key) + * + * Always called with interrupts locked + */ +SECTION_FUNC(exception.other, arch_swap) + +#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) + /* Need to preserve r4 as it has the function argument. */ + addi sp, sp, -12 + stw ra, 8(sp) + stw fp, 4(sp) + stw r4, 0(sp) + + call z_thread_mark_switched_out + + ldw r4, 0(sp) + ldw fp, 4(sp) + ldw ra, 8(sp) + addi sp, sp, 12 +#endif + + /* Get a reference to _kernel in r10 */ + movhi r10, %hi(_kernel) + ori r10, r10, %lo(_kernel) + + /* Get the pointer to kernel->current */ + ldw r11, _kernel_offset_to_current(r10) + + /* Store all the callee saved registers. We either got here via + * an exception or from a cooperative invocation of arch_swap() from C + * domain, so all the caller-saved registers have already been + * saved by the exception asm or the calling C code already. + */ + stw r16, _thread_offset_to_r16(r11) + stw r17, _thread_offset_to_r17(r11) + stw r18, _thread_offset_to_r18(r11) + stw r19, _thread_offset_to_r19(r11) + stw r20, _thread_offset_to_r20(r11) + stw r21, _thread_offset_to_r21(r11) + stw r22, _thread_offset_to_r22(r11) + stw r23, _thread_offset_to_r23(r11) + stw r28, _thread_offset_to_r28(r11) + stw ra, _thread_offset_to_ra(r11) + stw sp, _thread_offset_to_sp(r11) + + /* r4 has the 'key' argument which is the result of irq_lock() + * before this was called + */ + stw r4, _thread_offset_to_key(r11) + + /* Populate default return value */ + movhi r5, %hi(_k_neg_eagain) + ori r5, r5, %lo(_k_neg_eagain) + ldw r4, (r5) + stw r4, _thread_offset_to_retval(r11) + + /* get cached thread to run */ + ldw r2, _kernel_offset_to_ready_q_cache(r10) + + /* At this point r2 points to the next thread to be swapped in */ + + /* the thread to be swapped in is now the current thread */ + stw r2, _kernel_offset_to_current(r10) + + /* Restore callee-saved registers and switch to the incoming + * thread's stack + */ + ldw r16, _thread_offset_to_r16(r2) + ldw r17, _thread_offset_to_r17(r2) + ldw r18, _thread_offset_to_r18(r2) + ldw r19, _thread_offset_to_r19(r2) + ldw r20, _thread_offset_to_r20(r2) + ldw r21, _thread_offset_to_r21(r2) + ldw r22, _thread_offset_to_r22(r2) + ldw r23, _thread_offset_to_r23(r2) + ldw r28, _thread_offset_to_r28(r2) + ldw ra, _thread_offset_to_ra(r2) + ldw sp, _thread_offset_to_sp(r2) + + /* We need to irq_unlock(current->coopReg.key); + * key was supplied as argument to arch_swap(). Fetch it. + */ + ldw r3, _thread_offset_to_key(r2) + + /* + * Load return value into r2 (return value register). -EAGAIN unless + * someone previously called arch_thread_return_value_set(). Do this + * before we potentially unlock interrupts. + */ + ldw r2, _thread_offset_to_retval(r2) + + /* Now do irq_unlock(current->coopReg.key) */ +#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \ + (defined ALT_CPU_EIC_PRESENT) || \ + (defined ALT_CPU_MMU_PRESENT) || \ + (defined ALT_CPU_MPU_PRESENT) + andi r3, r3, NIOS2_STATUS_PIE_MSK + beq r3, zero, no_unlock + rdctl r3, status + ori r3, r3, NIOS2_STATUS_PIE_MSK + wrctl status, r3 + +no_unlock: +#else + wrctl status, r3 +#endif + +#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) + /* Also need to preserve r2, r3 as return values */ + addi sp, sp, -20 + stw ra, 16(sp) + stw fp, 12(sp) + stw r4, 8(sp) + stw r3, 4(sp) + stw r2, 0(sp) + + call z_thread_mark_switched_in + + ldw r2, 0(sp) + ldw r3, 4(sp) + ldw r4, 8(sp) + ldw fp, 12(sp) + ldw ra, 16(sp) + addi sp, sp, 20 +#endif + ret + + +/* void z_thread_entry_wrapper(void) + */ +SECTION_FUNC(TEXT, z_thread_entry_wrapper) + /* This all corresponds to struct init_stack_frame defined in + * thread.c. We need to take this stuff off the stack and put + * it in the appropriate registers + */ + + /* Can't return from here, just put NULL in ra */ + movi ra, 0 + + /* Calling convention has first 4 arguments in registers r4-r7. */ + ldw r4, 0(sp) + ldw r5, 4(sp) + ldw r6, 8(sp) + ldw r7, 12(sp) + + /* pop all the stuff that we just loaded into registers */ + addi sp, sp, 16 + + call z_thread_entry + diff --git a/arch/nios2/core/thread.c b/arch/nios2/core/thread.c new file mode 100644 index 0000000000000..c2f674a3fb056 --- /dev/null +++ b/arch/nios2/core/thread.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* forward declaration to asm function to adjust setup the arguments + * to z_thread_entry() since this arch puts the first four arguments + * in r4-r7 and not on the stack + */ +void z_thread_entry_wrapper(k_thread_entry_t, void *, void *, void *); + +struct init_stack_frame { + /* top of the stack / most recently pushed */ + + /* Used by z_thread_entry_wrapper. pulls these off the stack and + * into argument registers before calling z_thread_entry() + */ + k_thread_entry_t entry_point; + void *arg1; + void *arg2; + void *arg3; + + /* least recently pushed */ +}; + + +void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, + char *stack_ptr, k_thread_entry_t entry, + void *arg1, void *arg2, void *arg3) +{ + struct init_stack_frame *iframe; + + /* Initial stack frame data, stored at the base of the stack */ + iframe = Z_STACK_PTR_TO_FRAME(struct init_stack_frame, stack_ptr); + + /* Setup the initial stack frame */ + iframe->entry_point = entry; + iframe->arg1 = arg1; + iframe->arg2 = arg2; + iframe->arg3 = arg3; + + thread->callee_saved.sp = (uint32_t)iframe; + thread->callee_saved.ra = (uint32_t)z_thread_entry_wrapper; + thread->callee_saved.key = NIOS2_STATUS_PIE_MSK; + /* Leave the rest of thread->callee_saved junk */ +} diff --git a/arch/nios2/core/timing.c b/arch/nios2/core/timing.c new file mode 100644 index 0000000000000..80ee73c6f069e --- /dev/null +++ b/arch/nios2/core/timing.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2020 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "altera_avalon_timer_regs.h" + +#define NIOS2_SUBTRACT_CLOCK_CYCLES(val) \ + ((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) << 16 | \ + (IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) - \ + ((uint32_t)val)) + +#define TIMING_INFO_OS_GET_TIME() \ + (NIOS2_SUBTRACT_CLOCK_CYCLES( \ + ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) \ + << 16) | \ + ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))) + +void arch_timing_init(void) +{ +} + +void arch_timing_start(void) +{ +} + +void arch_timing_stop(void) +{ +} + +timing_t arch_timing_counter_get(void) +{ + IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10); + return TIMING_INFO_OS_GET_TIME(); +} + +uint64_t arch_timing_cycles_get(volatile timing_t *const start, + volatile timing_t *const end) +{ + timing_t start_ = *start; + timing_t end_ = *end; + + if (end_ >= start_) { + return (end_ - start_); + } + return (end_ + NIOS2_SUBTRACT_CLOCK_CYCLES(start_)); +} + +uint64_t arch_timing_freq_get(void) +{ + return sys_clock_hw_cycles_per_sec(); +} + +uint64_t arch_timing_cycles_to_ns(uint64_t cycles) +{ + return k_cyc_to_ns_floor64(cycles); +} + +uint64_t arch_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count) +{ + return arch_timing_cycles_to_ns(cycles) / count; +} + +uint32_t arch_timing_freq_get_mhz(void) +{ + return (uint32_t)(arch_timing_freq_get() / 1000000U); +} diff --git a/arch/nios2/include/kernel_arch_data.h b/arch/nios2/include/kernel_arch_data.h new file mode 100644 index 0000000000000..2f1dbdd1f91e1 --- /dev/null +++ b/arch/nios2/include/kernel_arch_data.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016 Intel Corporation + * Copyright (c) 2016 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Private kernel definitions + * + * This file contains private kernel structures definitions and various + * other definitions for the Nios II processor architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute + * symbols" in the offsets.o module. + */ + +#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ +#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ + +#include +#include +#include + +#ifndef _ASMLANGUAGE + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/nios2/include/kernel_arch_func.h b/arch/nios2/include/kernel_arch_func.h new file mode 100644 index 0000000000000..c325ea49b49b9 --- /dev/null +++ b/arch/nios2/include/kernel_arch_func.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Private kernel definitions + * + * This file contains private kernel function/macro definitions and various + * other definitions for the Nios II processor architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute + * symbols" in the offsets.o module. + */ + +#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _ASMLANGUAGE + +static ALWAYS_INLINE void arch_kernel_init(void) +{ +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ +} + +static ALWAYS_INLINE void +arch_thread_return_value_set(struct k_thread *thread, unsigned int value) +{ + thread->callee_saved.retval = value; +} + +FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, + const struct arch_esf *esf); + +static inline bool arch_is_in_isr(void) +{ + return _kernel.cpus[0].nested != 0U; +} + +int arch_swap(unsigned int key); + +#ifdef CONFIG_IRQ_OFFLOAD +void z_irq_do_offload(void); +#endif + +#if ALT_CPU_ICACHE_SIZE > 0 +void z_nios2_icache_flush_all(void); +#else +#define z_nios2_icache_flush_all() do { } while (false) +#endif + +#if ALT_CPU_DCACHE_SIZE > 0 +void z_nios2_dcache_flush_all(void); +void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len); +#else +#define z_nios2_dcache_flush_all() do { } while (false) +#define z_nios2_dcache_flush_no_writeback(x, y) do { } while (false) +#endif + +#endif /* _ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/nios2/include/offsets_short_arch.h b/arch/nios2/include/offsets_short_arch.h new file mode 100644 index 0000000000000..3b961e1fcb92c --- /dev/null +++ b/arch/nios2/include/offsets_short_arch.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ +#define ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ + +#include + +/* kernel */ + +/* nothing for now */ + +/* end - kernel */ + +/* threads */ + +#define _thread_offset_to_r16 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r16_OFFSET) + +#define _thread_offset_to_r17 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r17_OFFSET) + +#define _thread_offset_to_r18 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r18_OFFSET) + +#define _thread_offset_to_r19 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r19_OFFSET) + +#define _thread_offset_to_r20 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r20_OFFSET) + +#define _thread_offset_to_r21 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r21_OFFSET) + +#define _thread_offset_to_r22 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r22_OFFSET) + +#define _thread_offset_to_r23 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r23_OFFSET) + +#define _thread_offset_to_r28 \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r28_OFFSET) + +#define _thread_offset_to_ra \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_ra_OFFSET) + +#define _thread_offset_to_sp \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET) + +#define _thread_offset_to_key \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_key_OFFSET) + +#define _thread_offset_to_retval \ + (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) + +/* end - threads */ + +#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/posix/core/irq.c b/arch/posix/core/irq.c index eba9cda41d258..a1d3568c154e0 100644 --- a/arch/posix/core/irq.c +++ b/arch/posix/core/irq.c @@ -17,7 +17,6 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) void arch_irq_offload_init(void) { - /* Nothing to be done for this architecture */ } #endif diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 29fc8cf9225da..7ac915865d15a 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -162,11 +162,3 @@ config RISCV_ISA_EXT_ZBS The Zbs instructions can be used for single-bit instructions that provide a mechanism to set, clear, invert, or extract a single bit in a register. - -config RISCV_ISA_EXT_ZMMUL - bool - help - (Zmmul) - Zmmul Extension for Integer Multiplication - - The Zmmul extension implements the multiplication subset of the M - extension. diff --git a/arch/rx/CMakeLists.txt b/arch/rx/CMakeLists.txt deleted file mode 100644 index f7c57ff76b9b6..0000000000000 --- a/arch/rx/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(core) -set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-rx-le) # needed for e.g. objcopy diff --git a/arch/rx/Kconfig b/arch/rx/Kconfig deleted file mode 100644 index 9e34a16ea099f..0000000000000 --- a/arch/rx/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -# Renesas RX architecture configuration options - -# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -menu "Renesas RX Options" - depends on RX - -config ARCH - string - default "rx" - -config CPU_RXV1 - bool - help - Set if the processor supports the Renesas RXv1 instruction set. - -config CPU_RXV2 - bool - help - Set if the processor supports the Renesas RXv2 instruction set. - -config CPU_RXV3 - bool - help - Set if the processor supports the Renesas RXv3 instruction set. - -config HAS_EXCEPT_VECTOR_TABLE - bool - help - Set if the processor has the exception vector table. - -config XIP - default y - -config NUM_IRQ_PRIO_LEVELS - int "Number of supported interrupt priority levels" - range 1 16 - default 16 - help - Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The - minimum value is 1. The BSP must provide a valid default for proper - operation. - -config NUM_IRQS - int - default 256 - -config GEN_ISR_TABLES - default y - -config GEN_SW_ISR_TABLE - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config GEN_IRQ_START_VECTOR - default 16 - -config DYNAMIC_INTERRUPTS - default y - -config MAIN_STACK_SIZE - default 1024 - -config INITIALIZATION_STACK_SIZE - int "Initialization stack size (in bytes)" - default 512 - help - Stack size for initialization process of kernel (in bytes) - -endmenu diff --git a/arch/rx/core/CMakeLists.txt b/arch/rx/core/CMakeLists.txt deleted file mode 100644 index 5b3e888db6a56..0000000000000 --- a/arch/rx/core/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - switch.S - cpu_idle.c - prep_c.c - irq_manage.c - reset.S - thread.c - vects.c - isr_exit.S -) - -zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) diff --git a/arch/rx/core/cpu_idle.c b/arch/rx/core/cpu_idle.c deleted file mode 100644 index a109057f88dfd..0000000000000 --- a/arch/rx/core/cpu_idle.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -void arch_cpu_idle(void) -{ - sys_trace_idle(); - - /* The assembler instruction "wait" switches the processor to sleep mode, - * which stops program execution until an interrupt is triggered. - * All clocks that are not in a stop state continue operating, including - * the system timer. - * - * Also, "wait" sets the PSW I bit, activating - * interrupts (otherwise, the processor would never return from sleep - * mode). This is consistent with the Zephyr API description, according - * to which "In some architectures, before returning, the function - * unmasks interrupts unconditionally." - this is such an architecture. - */ - __asm__ volatile("wait"); -} - -void arch_cpu_atomic_idle(unsigned int key) -{ - sys_trace_idle(); - - /* The assembler instruction "wait" switches the processor to sleep mode, - * which stops program execution until an interrupt is triggered. - * All clocks that are not in a stop state continue operating, including - * the system timer. - */ - __asm__ volatile("wait"); - - /* "wait" unconditionally unlocks interrupts. To restore the interrupt - * lockout state before calling arch_cpu_atomic_idle, interrupts have - * to be locked after returning from "wait" if irq_lock would NOT have - * unlocked interrupts (i.e. if the key indicates nested interrupt - * locks) - */ - if (key == 0) { - irq_lock(); - } -} diff --git a/arch/rx/core/irq_manage.c b/arch/rx/core/irq_manage.c deleted file mode 100644 index 7bbba8907384b..0000000000000 --- a/arch/rx/core/irq_manage.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include - -#define IR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IR) -#define IER_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IER) -#define IPR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IPR) - -#define NUM_IRQS_PER_REG 8 -#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) -#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) -#define REG(addr) *((uint8_t *)(addr)) - -/** - * @brief Enable an IRQ by setting the corresponding IEN bit. - * - * Note that this will have no effect for IRQs 0-15 as the - * Renesas rx chip ignores write operations on the corresponding - * Registers - * - * @param irq interrupt to enable (16-255) - */ -void arch_irq_enable(unsigned int irq) -{ - __ASSERT(irq < CONFIG_NUM_IRQS, "trying to enable invalid interrupt (%u)", irq); - __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to enable reserved interrupt (%u)", - irq); - - uint32_t key = irq_lock(); - - /* reset interrupt before activating */ - WRITE_BIT(REG(IR_BASE_ADDRESS + irq), 0, false); - WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), true); - irq_unlock(key); -} - -/** - * @brief Disable an IRQ by clearing the corresponding IEN bit. - * - * Note that this will have no effect for IRQs 0-15 as the - * Renesas rx chip ignores write operations on the corresponding - * Registers. - * - * @param irq interrupt to disable (16-255) - */ -void arch_irq_disable(unsigned int irq) -{ - __ASSERT(irq < CONFIG_NUM_IRQS, "trying to disable invalid interrupt (%u)", irq); - __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to disable reserved interrupt (%u)", - irq); - - uint32_t key = irq_lock(); - - WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), false); - irq_unlock(key); -} - -/** - * @brief Determine if an IRQ is enabled by reading the corresponding IEN bit. - * - * @param irq interrupt number - * - * @return true if the interrupt is enabled - */ -int arch_irq_is_enabled(unsigned int irq) -{ - __ASSERT(irq < CONFIG_NUM_IRQS, "is_enabled on invalid interrupt (%u)", irq); - __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "is_enabled on reserved interrupt (%u)", irq); - - return (REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)) & BIT(BIT_FROM_IRQ(irq))) != 0; -} - -/* - * @brief Spurious interrupt handler - * - * Installed in all dynamic interrupt slots at boot time. Throws an error if - * called. - * - * @return N/A - */ - -void z_irq_spurious(const void *unused) -{ - ARG_UNUSED(unused); - z_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); -} - -/* - * @internal - * - * @brief Set an interrupt's priority - * - * Higher values take priority over lower values. - * - * @return N/A - */ - -void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) -{ - __ASSERT(irq < CONFIG_NUM_IRQS, "irq_priority_set on invalid interrupt (%u)", irq); - __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "irq_priority_set on reserved interrupt (%u)", - irq); - __ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS, "invalid priority (%u) for interrupt %u", prio, - irq); - - uint32_t key = irq_lock(); - - if (irq >= 34) { - /* for interrupts >= 34, the IPR is regular */ - REG(IPR_BASE_ADDRESS + irq) = prio; - } else { - switch (irq) { - /* 0-15: no IPR */ - case 16: - /* 17: no IPR */ - case 18: - REG(IPR_BASE_ADDRESS) = prio; - break; - /* 19,20: no IPR */ - case 21: - REG(IPR_BASE_ADDRESS + 1) = prio; - break; - /* 22: no IPR */ - case 23: - REG(IPR_BASE_ADDRESS + 2) = prio; - break; - /* 24,25: no IPR */ - case 26: - case 27: - REG(IPR_BASE_ADDRESS + 3) = prio; - break; - case 28: - REG(IPR_BASE_ADDRESS + 4) = prio; - break; - case 29: - REG(IPR_BASE_ADDRESS + 5) = prio; - break; - case 30: - REG(IPR_BASE_ADDRESS + 6) = prio; - break; - case 31: - REG(IPR_BASE_ADDRESS + 7) = prio; - break; - /* 32,33: no IPR */ - } - } - irq_unlock(key); -} - -#ifdef CONFIG_DYNAMIC_INTERRUPTS -/** - * @brief connect a callback function to an interrupt at runtime - * - * @param irq interrupt number - * @param priority priority of the interrupt - * @param routine routine to call when the interrupt is triggered - * @param parameter parameter to supply to the routine on call - * @param flags flags for the interrupt - * - * @return the interrupt number - */ -int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), const void *parameter, - uint32_t flags) -{ - z_isr_install(irq, routine, parameter); - z_irq_priority_set(irq, priority, flags); - return irq; -} -#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/rx/core/irq_offload.c b/arch/rx/core/irq_offload.c deleted file mode 100644 index 9845bb4da8717..0000000000000 --- a/arch/rx/core/irq_offload.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Software interrupts utility code - Renesas rx architecture implementation. - * - * The code is using the first software interrupt (SWINT) of the RX processor - * should this interrupt ever be used for something else, this has to be - * changed - maybe to the second software interrupt (SWINT2). - */ - -#include -#include -#include - -#define SWINT1_IRQ_LINE 27 -#define SWINT1_PRIO 14 -/* Address of the software interrupt trigger register for SWINT1 */ -#define SWINT_REGISTER_ADDRESS 0x872E0 -#define SWINTR_SWINT *(uint8_t *)(SWINT_REGISTER_ADDRESS) - -static irq_offload_routine_t _offload_routine; -static const void *offload_param; - -void z_irq_do_offload(void) -{ - irq_offload_routine_t tmp; - - if (!_offload_routine) { - return; - } - - tmp = _offload_routine; - _offload_routine = NULL; - - tmp((const void *)offload_param); -} - -static void swi0_handler(void) -{ - z_irq_do_offload(); -} - -void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) -{ - _offload_routine = routine; - offload_param = parameter; - - SWINTR_SWINT = 1; -} - -void arch_irq_offload_init(void) -{ - IRQ_CONNECT(SWINT1_IRQ_LINE, SWINT1_PRIO, swi0_handler, NULL, 0); - irq_enable(SWINT1_IRQ_LINE); -} diff --git a/arch/rx/core/isr_exit.S b/arch/rx/core/isr_exit.S deleted file mode 100644 index 69fcd0482d9ab..0000000000000 --- a/arch/rx/core/isr_exit.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -.list -.section .text -GTEXT(_z_rx_irq_exit) - -_z_rx_irq_exit: - mov #__kernel, r1 ; Load the base address of _kernel into r1 - mov r1, r3 ; Load the base address of _kernel into r1 - - add #___cpu_t_current_OFFSET, r1 ; Add the offset for the 'current' field to r1 - mov [r1], r2 ; Load the value of _kernel.cpus[0].current into r2 - - push r2 ; Save old_thread to the stack - - ; Get the next thread to schedule - mov #0,r1 ; Use r1 to pass NULL since we haven't saved the context yet - bsr _z_get_next_switch_handle ; Call the function - - ; The return value of z_get_next_switch_handle will now be in r1 - ; Restore old_thread from the stack - pop r2 ; Restore old_thread from the stack - - ; Check if a switch is necessary - cmp #0, r1 - bz no_switch ; If new_thread (in r1) is NULL, jump to no_switch - - add #___thread_t_switch_handle_OFFSET, r2 - - ; Call arch_switch to perform the context switch - bsr _z_rx_arch_switch ; r1: new_thread->switch_handle, r2: old_thread->switch_handle - -no_switch: - rts diff --git a/arch/rx/core/offsets/offsets.c b/arch/rx/core/offsets/offsets.c deleted file mode 100644 index b0ac1b4dd5c19..0000000000000 --- a/arch/rx/core/offsets/offsets.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief RX Kernel structure member offset definition file - * - * This module is responsible for the generation of the absolute symbols whose - * value represents the member offsets for various structures. - * - * All of the absolute symbols defined by this module will be present in the - * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms - * symbol). - * - * INTERNAL - * It is NOT necessary to define the offset for every member of a structure. - * Typically, only those members that are accessed by assembly language routines - * are defined; however, it doesn't hurt to define all fields for the sake of - * completeness. - */ -#ifndef _RX_OFFSETS_INC_ -#define _RX_OFFSETS_INC_ - -#include -#include -#include -#include - -GEN_ABSOLUTE_SYM(__callee_saved_t_SIZEOF, sizeof(_callee_saved_t)); -GEN_ABSOLUTE_SYM(__thread_arch_t_SIZEOF, sizeof(_thread_arch_t)); - -GEN_ABS_SYM_END - -#endif /* _RX_OFFSETS_INC_ */ diff --git a/arch/rx/core/prep_c.c b/arch/rx/core/prep_c.c deleted file mode 100644 index 09d86d10d3634..0000000000000 --- a/arch/rx/core/prep_c.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Full C support initialization - * - * - * Initialization of full C support: zero the .bss and call z_cstart(). - * - * Stack is available in this module, but not the global data/bss until their - * initialization is performed. - */ - -#include -#include -#include -#include -#include - -K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MAX_NUM_CPUS, - CONFIG_INITIALIZATION_STACK_SIZE); -/** - * @brief Prepare to and run C code - * - * This routine prepares for the execution of and runs C code. - * - * @return N/A - */ -void z_prep_c(void) -{ - z_bss_zero(); - - z_data_copy(); - - z_cstart(); - CODE_UNREACHABLE; -} diff --git a/arch/rx/core/reset.S b/arch/rx/core/reset.S deleted file mode 100644 index 80246fe397e3f..0000000000000 --- a/arch/rx/core/reset.S +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -.list -.section .text -GTEXT(__start) -__start : - -/* during initialization (before the main thread is started), z_initialization_process_stacks - * is used to do the kernel initialization. - */ - mvtc #(_z_initialization_process_stacks + CONFIG_INITIALIZATION_STACK_SIZE),USP - -/* initialise interrupt stack pointer */ - mvtc #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE),ISP - -/* set exception vector address (_ExceptVectors is defined in vects.c) */ -#if CONFIG_HAS_EXCEPT_VECTOR_TABLE - mvtc #_ExceptVectors, extb -#endif - -/* set interrupt vector address (_rvectors_start is defined in vects.c) */ - mvtc #_rvectors_start, intb - -/* load data section from ROM to RAM */ - - mov #_mdata,r2 /* src ROM address of data section in R2 */ - mov #_data,r1 /* dest start RAM address of data section in R1 */ - mov #_edata,r3 /* end RAM address of data section in R3 */ - sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ -#ifdef __RX_ALLOW_STRING_INSNS__ - smovf /* block copy R3 bytes from R2 to R1 */ -#else - cmp #0, r3 - beq 2f - -1: mov.b [r2+], r5 - mov.b r5, [r1+] - sub #1, r3 - bne 1b -2: -#endif - -/* bss initialisation: zero out bss */ - mov #0,r2 /* load R2 reg with zero */ - mov #_ebss, r3 /* store the end address of bss in R3 */ - mov #_bss, r1 /* store the start address of bss in R1 */ - sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ - sstr.b - -#ifdef CONFIG_INIT_STACKS - /* initialize the irq stack (it is located in the bss section) */ - mov #0xaa,r2 /* initialization value 0xaa */ - mov #_z_interrupt_stacks, r1 /* start address */ - mov #CONFIG_ISR_STACK_SIZE, r3 /* stack size */ - sstr.b -#endif - -/* setup PSW - use user stack register and lock interrupts during initialization */ - mvtc #0x20000, psw - -#ifdef CPPAPP - bsr __rx_init -#endif - -/* start user program */ - bsr _z_cstart - bsr _exit - -#ifdef CPPAPP - .global _rx_run_preinit_array - .type _rx_run_preinit_array,@function -_rx_run_preinit_array: - mov #__preinit_array_start,r1 - mov #__preinit_array_end,r2 - mov #_rx_run_inilist,r7 - jsr r7 - - .global _rx_run_init_array - .type _rx_run_init_array,@function -_rx_run_init_array: - mov #__init_array_start,r1 - mov #__init_array_end,r2 - mov #4, r3 - mov #_rx_run_inilist,r7 - jsr r7 - - .global _rx_run_fini_array - .type _rx_run_fini_array,@function -_rx_run_fini_array: - mov #__fini_array_start,r2 - mov #__fini_array_end,r1 - mov #-4, r3 - /* fall through */ - -_rx_run_inilist: -next_inilist: - cmp r1,r2 - beq.b done_inilist - mov.l [r1],r4 - cmp #-1, r4 - beq.b skip_inilist - cmp #0, r4 - beq.b skip_inilist - pushm r1-r3 - jsr r4 - popm r1-r3 -skip_inilist: - add r3,r1 - mov #next_inilist,r7 - jsr r7 -done_inilist: - rts - - .section .init,"ax" - .balign 4 - - .global __rx_init -__rx_init: - - .section .fini,"ax" - .balign 4 - - .global __rx_fini -__rx_fini: - mov #_rx_run_fini_array,r7 - jsr r7 - - .section .sdata - .balign 4 - .global __gp - .weak __gp -__gp: - - .section .data - .global ___dso_handle - .weak ___dso_handle -___dso_handle: - .long 0 - - .section .init,"ax" - mov #_rx_run_preinit_array,r7 - jsr r7 - mov #_rx_run_init_array,r7 - jsr r7 - rts - - .global __rx_init_end -__rx_init_end: - - .section .fini,"ax" - - rts - .global __rx_fini_end -__rx_fini_end: - -#endif - -/* call to exit*/ -_exit: - bra _loop_here -_loop_here: - bra _loop_here - - .text - .end diff --git a/arch/rx/core/switch.S b/arch/rx/core/switch.S deleted file mode 100644 index 5894530b3af9a..0000000000000 --- a/arch/rx/core/switch.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -GTEXT(_z_rx_arch_switch) -GTEXT(_switch_isr_wrapper) - -/* void z_rx_arch_switch(void *switch_to, void **switched_from) - * - * @brief switch between threads - * - * @param switch_to (r1) pointer to switch handle of the new thread - * @param switched_from (r2) pointer to pointer to switch handle of the old - * thread - * - * Thread-switching is treated differently depending on whether it is a - * cooperative switch triggered by old thread itself or a preemptive switch - * triggered by an interrupt (in this case the function has been called from an - * ISR). - */ -.section .text._z_rx_arch_switch -.align 4 -_z_rx_arch_switch: - - mvfc psw,r3 - tst #0x130000, r3 /* test if PM, U or I bit are set*/ - bz _z_rx_context_switch_isr /* if none of them are set, this is an isr */ - - mov #_coop_switch_to,r3 - mov r1,[r3] - mov #_coop_switched_from,r3 - mov r2,[r3] - - /* trigger unconditional interrupt dedicated to thread switching. The content of r1 and r2 - * will not change by invoking the interrupt so the parameters switch_to and switched_from - * will be available in _z_rx_context_switch_isr, which has been entered into the vector - * table as ISR for interrupt 1 - */ - int #1 - - /* at this point, r0 points to the entry point, so RTS will enter it */ - rts - -/* void switch_isr_wrapper(void) - * - * @brief isr for interrupt 1 as wrapper for _z_rx_context_switch_isr - * - * _z_rx_context_switch_isr ends in rts, so it does not return from the interrupt context - */ -.section .text._switch_isr_wrapper -.align 4 -_switch_isr_wrapper: - pushm r1-r15 - - /* Save the accumulator. */ - mvfachi r15 /* Accumulator high 32 bits. */ - push r15 - mvfacmi r15 /* Accumulator middle 32 bits. */ - shll #16, r15 /* Shifted left as it is restored to the low order word.*/ - push r15 - - mov #_coop_switch_to,r3 - mov [r3],r1 - mov #_coop_switched_from,r3 - mov [r3],r2 - - bsr _z_rx_context_switch_isr - - /* Restore the registers from the stack of the task pointed to by - pxCurrentTCB. */ - pop r15 - mvtaclo r15 /* Accumulator low 32 bits. */ - pop r15 - mvtachi r15 /* Accumulator high 32 bits. */ - - popm r1-r15 - rte - -/* void z_rx_context_switch_isr(void *switch_to, void **switched_from) - * - * @brief switch between threads in the interrupt context - * - * @param switch_to (r1) pointer to switch handle of the new thread - * @param switched_from (r2) pointer to pointer to switch handle of the old thread - * - * since this is part of an ISR, PSW, PC and general registers of the old thread are already - * stored in the interrupt stack, so copy the corresponding part of the interrupt stack to the - * stack of the interrupted thread - */ -_z_rx_context_switch_isr: - - /* store arguments switch_to and switched_from to registers r4 and r5 as - * registers r2 and r3 are needed for the smovf operation */ - mov r1,r4 - mov r2,r5 - - /* set r2 (smovb source address) to the beginning of the interrupt stack */ - mov #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)-1,r2 - - mvfc usp,r1 /* set r1 (smovb dest) to USP */ - - sub #1,r1 /* correct by one byte to use smovb compared to push/pop */ - - /* set r3 to number of bytes to move - * Accumulator 64bit (4byte * 2) - * 15*4 byte for 15 general registers - * + PSW (4 byte) - * + PC (4 byte) - */ - mov #76,r3 - smovb /* block copy from interrupt stack to old thread stack */ - - add #1,r1 /* smovb leaves r1 pointing 1 byte before the stack */ - add #1,r2 /* same with r2 */ - - mov r1,[r5] /* store stack pointer of old thread in *switched_from */ - - mov r2,r1 /* set r1 (smovf dest) to the beginning of the interrupt stack */ - - mov r4,r2 /* set r2 (smovf source) to the sp of the new thread*/ - mov #76,r3 /* set r3 to number of bytes to move */ - - smovf /* block copy from new thread stack to interrupt stack */ - - mvtc r2,usp /* set USP to the new thread stack */ - -#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING - bsr _z_thread_mark_switched_in -#endif - - rts diff --git a/arch/rx/core/thread.c b/arch/rx/core/thread.c deleted file mode 100644 index 88670bf75dace..0000000000000 --- a/arch/rx/core/thread.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); - -/* variables to store the arguments of z_rx_context_switch_isr() (zephyr\arch\rx\core\switch.S) - * when performing a cooperative thread switch. In that case, z_rx_context_switch_isr() triggerss - * unmaskable interrupt 1 to actually perform the switch. The ISR to interrupt 1 - * (switch_isr_wrapper()) reads the arguments from these variables. - */ -void *coop_switch_to; -void **coop_switched_from; - -void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, - k_thread_entry_t entry, void *arg1, void *arg2, void *arg3) -{ - struct arch_esf *iframe; - - iframe = Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr); - - /* initial value for the PSW (bits U and I are set) */ - iframe->psw = 0x30000; - /* the initial entry point is the function z_thread_entry */ - iframe->entry_point = (uint32_t)z_thread_entry; - /* arguments for the call of z_thread_entry (to be written to r1-r4) */ - iframe->r1 = (uint32_t)entry; - iframe->r2 = (uint32_t)arg1; - iframe->r3 = (uint32_t)arg2; - iframe->r4 = (uint32_t)arg3; - /* for debugging: */ - iframe->r5 = 5; - iframe->r6 = 6; - iframe->r7 = 7; - iframe->r8 = 8; - iframe->r9 = 9; - iframe->r10 = 10; - iframe->r11 = 11; - iframe->r12 = 12; - iframe->r13 = 13; - iframe->r14 = 14; - iframe->r15 = 15; - iframe->acc_l = 16; - iframe->acc_h = 17; - - thread->switch_handle = (void *)iframe; -} diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c deleted file mode 100644 index 836e9d3adb2ff..0000000000000 --- a/arch/rx/core/vects.c +++ /dev/null @@ -1,499 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -typedef void (*fp)(void); -extern void _start(void); -extern void z_rx_irq_exit(void); - -/* this is mainly to give Visual Studio Code peace of mind */ -#ifndef CONFIG_GEN_IRQ_START_VECTOR -#define CONFIG_GEN_IRQ_START_VECTOR 0 -#endif - -#define EXVECT_SECT __attribute__((section(".exvectors"))) -#define RVECT_SECT __attribute__((section(".rvectors"))) -#define FVECT_SECT __attribute__((section(".fvectors"))) - -#define __ISR__ __attribute__((interrupt, naked)) - -static ALWAYS_INLINE void REGISTER_SAVE(void) -{ - __asm volatile( - /* Save the Registers to ISP at the top of ISR. */ - /* This code is relate on arch_new_thread() at thread.c */ - /* You should store the registers at the same registers arch_new_thread() */ - /* except PC and PSW. */ - "PUSHM R1-R15\n" - - "MVFACHI R15\n" - "PUSH.L R15\n" - "MVFACMI R15\n" - "SHLL #16, R15\n" - "PUSH.L R15\n"); -} - -static ALWAYS_INLINE void REGISTER_RESTORE_EXIT(void) -{ - __asm volatile( - /* Restore the registers and do the RTE at the End of ISR. */ - "POP R15\n" - "MVTACLO R15\n" - "POP R15\n" - "MVTACHI R15\n" - - "POPM R1-R15\n" - "RTE\n"); -} - -/* Privileged instruction execption */ -static void __ISR__ INT_Excep_SuperVisorInst(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* Access exception */ -static void __ISR__ INT_Excep_AccessInst(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* Undefined instruction exception */ -static void __ISR__ INT_Excep_UndefinedInst(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* floating point exception */ -static void __ISR__ INT_Excep_FloatingPoint(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* Non-maskable interrupt */ -static void __ISR__ INT_NonMaskableInterrupt(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* dummy function */ -static void __ISR__ Dummy(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/** - * @brief select Zephyr ISR and argument from software ISR table and call - * function - * - * @param irq interrupt to handle - */ -static ALWAYS_INLINE void handle_interrupt(uint8_t irq) -{ - ISR_DIRECT_HEADER(); - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - ISR_DIRECT_FOOTER(1); -} - -/** - * @brief isr for reserved interrupts (0-15) that are not handled through - * the zephyr sw isr table - */ -static void __ISR__ reserved_isr(void) -{ - REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); - REGISTER_RESTORE_EXIT(); -} - -/* wrapper for z_rx_context_switch_isr, defined in switch.S */ -extern void __ISR__ switch_isr_wrapper(void); - -/* this macro is used to define "demuxing" ISRs for all interrupts that are - * handled through Zephyr's software isr table. - */ - -#define INT_DEMUX(irq) \ - static __attribute__((interrupt, naked)) void int_demux_##irq(void) \ - { \ - REGISTER_SAVE(); \ - handle_interrupt(irq - CONFIG_GEN_IRQ_START_VECTOR); \ - REGISTER_RESTORE_EXIT(); \ - } - -INT_DEMUX(16); -INT_DEMUX(17); -INT_DEMUX(18); -INT_DEMUX(19); -INT_DEMUX(20); -INT_DEMUX(21); -INT_DEMUX(22); -INT_DEMUX(23); -INT_DEMUX(24); -INT_DEMUX(25); -INT_DEMUX(27); -INT_DEMUX(26); -INT_DEMUX(28); -INT_DEMUX(29); -INT_DEMUX(30); -INT_DEMUX(31); -INT_DEMUX(32); -INT_DEMUX(33); -INT_DEMUX(34); -INT_DEMUX(35); -INT_DEMUX(36); -INT_DEMUX(37); -INT_DEMUX(38); -INT_DEMUX(39); -INT_DEMUX(40); -INT_DEMUX(41); -INT_DEMUX(42); -INT_DEMUX(43); -INT_DEMUX(44); -INT_DEMUX(45); -INT_DEMUX(46); -INT_DEMUX(47); -INT_DEMUX(48); -INT_DEMUX(49); -INT_DEMUX(50); -INT_DEMUX(51); -INT_DEMUX(52); -INT_DEMUX(53); -INT_DEMUX(54); -INT_DEMUX(55); -INT_DEMUX(56); -INT_DEMUX(57); -INT_DEMUX(58); -INT_DEMUX(59); -INT_DEMUX(60); -INT_DEMUX(61); -INT_DEMUX(62); -INT_DEMUX(63); -INT_DEMUX(64); -INT_DEMUX(65); -INT_DEMUX(66); -INT_DEMUX(67); -INT_DEMUX(68); -INT_DEMUX(69); -INT_DEMUX(70); -INT_DEMUX(71); -INT_DEMUX(72); -INT_DEMUX(73); -INT_DEMUX(74); -INT_DEMUX(75); -INT_DEMUX(76); -INT_DEMUX(77); -INT_DEMUX(78); -INT_DEMUX(79); -INT_DEMUX(80); -INT_DEMUX(81); -INT_DEMUX(82); -INT_DEMUX(83); -INT_DEMUX(84); -INT_DEMUX(85); -INT_DEMUX(86); -INT_DEMUX(87); -INT_DEMUX(88); -INT_DEMUX(89); -INT_DEMUX(90); -INT_DEMUX(91); -INT_DEMUX(92); -INT_DEMUX(93); -INT_DEMUX(94); -INT_DEMUX(95); -INT_DEMUX(96); -INT_DEMUX(97); -INT_DEMUX(98); -INT_DEMUX(99); -INT_DEMUX(100) -INT_DEMUX(101); -INT_DEMUX(102); -INT_DEMUX(103); -INT_DEMUX(104); -INT_DEMUX(105); -INT_DEMUX(106); -INT_DEMUX(107); -INT_DEMUX(108); -INT_DEMUX(109); -INT_DEMUX(110); -INT_DEMUX(111); -INT_DEMUX(112); -INT_DEMUX(113); -INT_DEMUX(114); -INT_DEMUX(115); -INT_DEMUX(116); -INT_DEMUX(117); -INT_DEMUX(118); -INT_DEMUX(119); -INT_DEMUX(120); -INT_DEMUX(121); -INT_DEMUX(122); -INT_DEMUX(123); -INT_DEMUX(124); -INT_DEMUX(125); -INT_DEMUX(126); -INT_DEMUX(127); -INT_DEMUX(128); -INT_DEMUX(129); -INT_DEMUX(130); -INT_DEMUX(131); -INT_DEMUX(132); -INT_DEMUX(133); -INT_DEMUX(134); -INT_DEMUX(135); -INT_DEMUX(136); -INT_DEMUX(137); -INT_DEMUX(138); -INT_DEMUX(139); -INT_DEMUX(140); -INT_DEMUX(141); -INT_DEMUX(142); -INT_DEMUX(143); -INT_DEMUX(144); -INT_DEMUX(145); -INT_DEMUX(146); -INT_DEMUX(147); -INT_DEMUX(148); -INT_DEMUX(149); -INT_DEMUX(150); -INT_DEMUX(151); -INT_DEMUX(152); -INT_DEMUX(153); -INT_DEMUX(154); -INT_DEMUX(155); -INT_DEMUX(156); -INT_DEMUX(157); -INT_DEMUX(158); -INT_DEMUX(159); -INT_DEMUX(160); -INT_DEMUX(161); -INT_DEMUX(162); -INT_DEMUX(163); -INT_DEMUX(164); -INT_DEMUX(165); -INT_DEMUX(166); -INT_DEMUX(167); -INT_DEMUX(168); -INT_DEMUX(169); -INT_DEMUX(170); -INT_DEMUX(171); -INT_DEMUX(172); -INT_DEMUX(173); -INT_DEMUX(174); -INT_DEMUX(175); -INT_DEMUX(176); -INT_DEMUX(177); -INT_DEMUX(178); -INT_DEMUX(179); -INT_DEMUX(180); -INT_DEMUX(181); -INT_DEMUX(182); -INT_DEMUX(183); -INT_DEMUX(184); -INT_DEMUX(185); -INT_DEMUX(186); -INT_DEMUX(187); -INT_DEMUX(188); -INT_DEMUX(189); -INT_DEMUX(190); -INT_DEMUX(191); -INT_DEMUX(192); -INT_DEMUX(193); -INT_DEMUX(194); -INT_DEMUX(195); -INT_DEMUX(196); -INT_DEMUX(197); -INT_DEMUX(198); -INT_DEMUX(199); -INT_DEMUX(200); -INT_DEMUX(201); -INT_DEMUX(202); -INT_DEMUX(203); -INT_DEMUX(204); -INT_DEMUX(205); -INT_DEMUX(206); -INT_DEMUX(207); -INT_DEMUX(208); -INT_DEMUX(209); -INT_DEMUX(210); -INT_DEMUX(211); -INT_DEMUX(212); -INT_DEMUX(213); -INT_DEMUX(214); -INT_DEMUX(215); -INT_DEMUX(216); -INT_DEMUX(217); -INT_DEMUX(218); -INT_DEMUX(219); -INT_DEMUX(220); -INT_DEMUX(221); -INT_DEMUX(222); -INT_DEMUX(223); -INT_DEMUX(224); -INT_DEMUX(225); -INT_DEMUX(226); -INT_DEMUX(227); -INT_DEMUX(228); -INT_DEMUX(229); -INT_DEMUX(230); -INT_DEMUX(231); -INT_DEMUX(232); -INT_DEMUX(233); -INT_DEMUX(234); -INT_DEMUX(235); -INT_DEMUX(236); -INT_DEMUX(237); -INT_DEMUX(238); -INT_DEMUX(239); -INT_DEMUX(240); -INT_DEMUX(241); -INT_DEMUX(242); -INT_DEMUX(243); -INT_DEMUX(244); -INT_DEMUX(245); -INT_DEMUX(246); -INT_DEMUX(247); -INT_DEMUX(248); -INT_DEMUX(249); -INT_DEMUX(250); -INT_DEMUX(251); -INT_DEMUX(252); -INT_DEMUX(253); -INT_DEMUX(254); -INT_DEMUX(255); - -const void *FixedVectors[] FVECT_SECT = { - /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ - /* Reserved for OFSM */ - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - /* Reserved area */ - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - /* Reserved for ID Code */ - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - /* Reserved area */ - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - /* Reserved area */ - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - /* 0x50: Privileged instruction exception */ - INT_Excep_SuperVisorInst, - /* 0x54: Access exception */ - INT_Excep_AccessInst, - /* 0x58: Reserved */ - Dummy, - /* 0x5c: Undefined Instruction Exception */ - INT_Excep_UndefinedInst, - /* 0x60: Reserved */ - Dummy, - /* 0x64: Floating Point Exception */ - INT_Excep_FloatingPoint, - /* 0x68-0x74: Reserved */ - Dummy, - Dummy, - Dummy, - Dummy, - /* 0x78: Non-maskable interrupt */ - INT_NonMaskableInterrupt, - _start, -}; - -const fp RelocatableVectors[] RVECT_SECT = { - reserved_isr, switch_isr_wrapper, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, int_demux_16, int_demux_17, int_demux_18, int_demux_19, - int_demux_20, int_demux_21, int_demux_22, int_demux_23, int_demux_24, - int_demux_25, int_demux_26, int_demux_27, int_demux_28, int_demux_29, - int_demux_30, int_demux_31, int_demux_32, int_demux_33, int_demux_34, - int_demux_35, int_demux_36, int_demux_37, int_demux_38, int_demux_39, - int_demux_40, int_demux_41, int_demux_42, int_demux_43, int_demux_44, - int_demux_45, int_demux_46, int_demux_47, int_demux_48, int_demux_49, - int_demux_50, int_demux_51, int_demux_52, int_demux_53, int_demux_54, - int_demux_55, int_demux_56, int_demux_57, int_demux_58, int_demux_59, - int_demux_60, int_demux_61, int_demux_62, int_demux_63, int_demux_64, - int_demux_65, int_demux_66, int_demux_67, int_demux_68, int_demux_69, - int_demux_70, int_demux_71, int_demux_72, int_demux_73, int_demux_74, - int_demux_75, int_demux_76, int_demux_77, int_demux_78, int_demux_79, - int_demux_80, int_demux_81, int_demux_82, int_demux_83, int_demux_84, - int_demux_85, int_demux_86, int_demux_87, int_demux_88, int_demux_89, - int_demux_90, int_demux_91, int_demux_92, int_demux_93, int_demux_94, - int_demux_95, int_demux_96, int_demux_97, int_demux_98, int_demux_99, - int_demux_100, int_demux_101, int_demux_102, int_demux_103, int_demux_104, - int_demux_105, int_demux_106, int_demux_107, int_demux_108, int_demux_109, - int_demux_110, int_demux_111, int_demux_112, int_demux_113, int_demux_114, - int_demux_115, int_demux_116, int_demux_117, int_demux_118, int_demux_119, - int_demux_120, int_demux_121, int_demux_122, int_demux_123, int_demux_124, - int_demux_125, int_demux_126, int_demux_127, int_demux_128, int_demux_129, - int_demux_130, int_demux_131, int_demux_132, int_demux_133, int_demux_134, - int_demux_135, int_demux_136, int_demux_137, int_demux_138, int_demux_139, - int_demux_140, int_demux_141, int_demux_142, int_demux_143, int_demux_144, - int_demux_145, int_demux_146, int_demux_147, int_demux_148, int_demux_149, - int_demux_150, int_demux_151, int_demux_152, int_demux_153, int_demux_154, - int_demux_155, int_demux_156, int_demux_157, int_demux_158, int_demux_159, - int_demux_160, int_demux_161, int_demux_162, int_demux_163, int_demux_164, - int_demux_165, int_demux_166, int_demux_167, int_demux_168, int_demux_169, - int_demux_170, int_demux_171, int_demux_172, int_demux_173, int_demux_174, - int_demux_175, int_demux_176, int_demux_177, int_demux_178, int_demux_179, - int_demux_180, int_demux_181, int_demux_182, int_demux_183, int_demux_184, - int_demux_185, int_demux_186, int_demux_187, int_demux_188, int_demux_189, - int_demux_190, int_demux_191, int_demux_192, int_demux_193, int_demux_194, - int_demux_195, int_demux_196, int_demux_197, int_demux_198, int_demux_199, - int_demux_200, int_demux_201, int_demux_202, int_demux_203, int_demux_204, - int_demux_205, int_demux_206, int_demux_207, int_demux_208, int_demux_209, - int_demux_210, int_demux_211, int_demux_212, int_demux_213, int_demux_214, - int_demux_215, int_demux_216, int_demux_217, int_demux_218, int_demux_219, - int_demux_220, int_demux_221, int_demux_222, int_demux_223, int_demux_224, - int_demux_225, int_demux_226, int_demux_227, int_demux_228, int_demux_229, - int_demux_230, int_demux_231, int_demux_232, int_demux_233, int_demux_234, - int_demux_235, int_demux_236, int_demux_237, int_demux_238, int_demux_239, - int_demux_240, int_demux_241, int_demux_242, int_demux_243, int_demux_244, - int_demux_245, int_demux_246, int_demux_247, int_demux_248, int_demux_249, - int_demux_250, int_demux_251, int_demux_252, int_demux_253, int_demux_254, - int_demux_255, -}; diff --git a/arch/rx/include/kernel_arch_data.h b/arch/rx/include/kernel_arch_data.h deleted file mode 100644 index 43762032f63a4..0000000000000 --- a/arch/rx/include/kernel_arch_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Private kernel definitions (rx) - * - * This file contains private kernel structures definitions and various - * other definitions for the Renesas rx architecture. - * - * This file is also included by assembly language files which must #define - * _ASMLANGUAGE before including this header file. Note that kernel - * assembly source files obtains structure offset values via "absolute symbols" - * in the offsets.o module. - */ - -#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ -#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ - -#include -#include -#include - -#ifndef _ASMLANGUAGE -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* place C-code here */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ASMLANGUAGE */ - -#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/rx/include/kernel_arch_func.h b/arch/rx/include/kernel_arch_func.h deleted file mode 100644 index 70058fb5c96ab..0000000000000 --- a/arch/rx/include/kernel_arch_func.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ -#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ - -#ifndef _ASMLANGUAGE -#include - -#ifdef __cplusplus -extern "C" { -#endif - -static ALWAYS_INLINE void arch_kernel_init(void) -{ - /* check if: further device initialization functions must be called here */ -} - -static inline bool arch_is_in_isr(void) -{ - return arch_curr_cpu()->nested != 0U; -} - -extern void z_rx_arch_switch(void *switch_to, void **switched_from); - -static inline void arch_switch(void *switch_to, void **switched_from) -{ - z_rx_arch_switch(switch_to, switched_from); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _ASMLANGUAGE */ - -#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/rx/include/offsets_short_arch.h b/arch/rx/include/offsets_short_arch.h deleted file mode 100644 index 796d4512b26dc..0000000000000 --- a/arch/rx/include/offsets_short_arch.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#define ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ - -#include - -/* kernel */ -#define KERNEL_OFFSET(field) _kernel_offset_to_##field - -#define _kernel_offset_to_flags (___kernel_t_arch_OFFSET + ___kernel_arch_t_flags_OFFSET) - -/* end - kernel */ - -/* threads */ -#define THREAD_OFFSET(field) _thread_offset_to_##field - -#define _thread_offset_to_sp (___thread_t_callee_saved_OFFSET + ___callee_saved_t_topOfStack_OFFSET) - -#define _thread_offset_to_retval (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) - -#define _thread_offset_to_coopCoprocReg \ - (___thread_t_arch_OFFSET + ___thread_arch_t_coopCoprocReg_OFFSET) - -#define _thread_offset_to_preempCoprocReg \ - (___thread_t_arch_OFFSET + ___thread_arch_t_preempCoprocReg_OFFSET) - -#define _thread_offset_to_cpStack \ - (_thread_offset_to_preempCoprocReg + __tPreempCoprocReg_cpStack_OFFSET) - -#define _thread_offset_to_cpEnable (_thread_offset_to_cpStack + XT_CPENABLE) - -/* end - threads */ - -#endif /* ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt index c34c6909b0172..abbc052a62472 100644 --- a/arch/x86/core/CMakeLists.txt +++ b/arch/x86/core/CMakeLists.txt @@ -27,8 +27,6 @@ zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) -zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) - if(CONFIG_X86_64) include(intel64.cmake) else() diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index e1f5869c7722d..7b5359a7ecd63 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -35,6 +35,7 @@ config ARCH_HAS_STACKWALK select DEBUG_INFO select THREAD_STACK_INFO depends on !OMIT_FRAME_POINTER + depends on NO_OPTIMIZATIONS help Internal config to indicate that the arch_stack_walk() API is implemented and it can be enabled. diff --git a/arch/x86/core/elf.c b/arch/x86/core/elf.c deleted file mode 100644 index a1660387d0ece..0000000000000 --- a/arch/x86/core/elf.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2025 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); - -#ifdef CONFIG_64BIT -#define R_X86_64_64 1 -#define R_X86_64_PC32 2 -#define R_X86_64_PLT32 4 -#define R_X86_64_32 10 -#define R_X86_64_32S 11 - -/** - * @brief Architecture specific function for relocating shared elf - * - * Elf files contain a series of relocations described in multiple sections. - * These relocation instructions are architecture specific and each architecture - * supporting modules must implement this. - * - * The relocation codes are well documented: - * - * https://refspecs.linuxfoundation.org/elf/x86_64-abi-0.95.pdf (intel64) - */ -int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, - const elf_shdr_t *shdr) -{ - int ret = 0; - const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); - elf_sym_t sym; - uintptr_t sym_base_addr; - const char *sym_name; - - ret = llext_read_symbol(ldr, ext, rel, &sym); - - if (ret != 0) { - LOG_ERR("Could not read symbol from binary!"); - return ret; - } - - sym_name = llext_symbol_name(ldr, ext, &sym); - - ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); - - if (ret != 0) { - LOG_ERR("Could not find symbol %s!", sym_name); - return ret; - } - - sym_base_addr += rel->r_addend; - - int reloc_type = ELF32_R_TYPE(rel->r_info); - - switch (reloc_type) { - case R_X86_64_PC32: - case R_X86_64_PLT32: - *(uint32_t *)loc = sym_base_addr - loc; - break; - case R_X86_64_64: - case R_X86_64_32: - case R_X86_64_32S: - *(uint32_t *)loc = sym_base_addr; - break; - default: - LOG_ERR("unknown relocation: %u\n", reloc_type); - ret = -ENOEXEC; - break; - } - - return ret; -} -#else -#define R_386_32 1 -#define R_286_PC32 2 - -/** - * @brief Architecture specific function for relocating shared elf - * - * Elf files contain a series of relocations described in multiple sections. - * These relocation instructions are architecture specific and each architecture - * supporting modules must implement this. - * - * The relocation codes are well documented: - * - * https://docs.oracle.com/cd/E19683-01/817-3677/chapter6-26/index.html (ia32) - */ -int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, - const elf_shdr_t *shdr) -{ - int ret = 0; - const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); - elf_sym_t sym; - uintptr_t sym_base_addr; - const char *sym_name; - - /* x86 uses elf_rel_t records with no addends */ - uintptr_t addend = *(uintptr_t *)loc; - - ret = llext_read_symbol(ldr, ext, rel, &sym); - - if (ret != 0) { - LOG_ERR("Could not read symbol from binary!"); - return ret; - } - - sym_name = llext_symbol_name(ldr, ext, &sym); - - ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); - - if (ret != 0) { - LOG_ERR("Could not find symbol %s!", sym_name); - return ret; - } - - sym_base_addr += addend; - - int reloc_type = ELF32_R_TYPE(rel->r_info); - - switch (reloc_type) { - case R_386_32: - *(uint32_t *)loc = sym_base_addr; - break; - case R_286_PC32: - *(uint32_t *)loc = sym_base_addr - loc; - break; - default: - LOG_ERR("unknown relocation: %u\n", reloc_type); - ret = -ENOEXEC; - break; - } - - return ret; -} -#endif diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 31dbf060d6c9c..8d68afa2a1913 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -97,7 +97,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, */ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot) { -#if defined(CONFIG_ACPI) && !defined(CONFIG_ACRN_COMMON) +#if defined(CONFIG_ACPI) __ASSERT(z_x86_cpuid_get_current_physical_apic_id() == x86_cpu_loapics[cpuboot->cpu_id], "APIC ID miss match!"); #endif diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index e3d6025a91f22..f3a4419f32c67 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -39,17 +39,6 @@ if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc") zephyr_library_sources(xcc_stubs.c) endif() -# ...where to find core-isa.h for custom compilation commands below. -if(CONFIG_SOC_FAMILY_ESPRESSIF_ESP32) - set(XTENSA_CONFIG_HAL_INCLUDE_DIR - -I${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/components/xtensa/${CONFIG_SOC}/include - ) -else() - set(XTENSA_CONFIG_HAL_INCLUDE_DIR - -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} - ) -endif() - add_subdirectory(startup) # This produces a preprocessed and regenerated (in the sense of gcc @@ -65,7 +54,7 @@ set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c) file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG} - ${XTENSA_CONFIG_HAL_INCLUDE_DIR} + -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) @@ -109,7 +98,7 @@ set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers) add_custom_command( OUTPUT ${HANDLERS}_tmp.c COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__ - ${XTENSA_CONFIG_HAL_INCLUDE_DIR} + -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} -o ${HANDLERS}_tmp.c - < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl) diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index d16f51e61a239..6b83a9c0c612c 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -52,9 +52,8 @@ static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, for (sh_ndx = 0; sh_ndx < ext->sect_cnt; sh_ndx++) { if (ext->sect_hdrs[sh_ndx].sh_addr <= *got_entry && *got_entry < - ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) { + ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) break; - } } if (sh_ndx == ext->sect_cnt) { diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c index 91a1d58f8014a..0ebc9cc68ccd5 100644 --- a/arch/xtensa/core/gdbstub.c +++ b/arch/xtensa/core/gdbstub.c @@ -427,14 +427,14 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - uint32_t *bsa = *(const int **)stack; + uint32_t *bsa = *(int **)stack; - if (bsa - (const uint32_t *)stack > 12) { - num_laddr_regs = 16; - } else if (bsa - (const uint32_t *)stack > 8) { - num_laddr_regs = 12; - } else if (bsa - (const uint32_t *)stack > 4) { + if ((int *)bsa - stack > 4) { num_laddr_regs = 8; + } else if ((int *)bsa - stack > 8) { + num_laddr_regs = 12; + } else if ((int *)bsa - stack > 12) { + num_laddr_regs = 16; } else { num_laddr_regs = 4; } @@ -445,7 +445,8 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) if (reg->regno == SOC_GDB_REGNO_A1) { /* A1 is calculated */ - reg->val = POINTER_TO_UINT(((char *)bsa) + sizeof(_xtensa_irq_bsa_t)); + reg->val = POINTER_TO_UINT( + ((char *)bsa) + BASE_SAVE_AREA_SIZE); reg->seqno = ctx->seqno; } else { reg->val = bsa[reg->stack_offset / 4]; @@ -517,14 +518,14 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - _xtensa_irq_bsa_t *bsa = (void *)*(const int **)stack; + _xtensa_irq_bsa_t *bsa = (void *)*(int **)stack; - if ((uint32_t *)bsa - (const uint32_t *)stack > 12) { - num_laddr_regs = 16; - } else if ((uint32_t *)bsa - (const uint32_t *)stack > 8) { - num_laddr_regs = 12; - } else if ((uint32_t *)bsa - (const uint32_t *)stack > 4) { + if ((int *)bsa - stack > 4) { num_laddr_regs = 8; + } else if ((int *)bsa - stack > 8) { + num_laddr_regs = 12; + } else if ((int *)bsa - stack > 12) { + num_laddr_regs = 16; } else { num_laddr_regs = 4; } @@ -546,7 +547,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) /* Shouldn't be changing stack pointer */ continue; } else { - ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; + bsa[reg->stack_offset / 4] = reg->val; } } @@ -558,7 +559,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) continue; } else if (reg->stack_offset != 0) { /* For those registers stashed in stack */ - ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; + bsa[reg->stack_offset / 4] = reg->val; } else if (gdb_xtensa_is_special_reg(reg)) { /* * Currently not writing back any special diff --git a/boards/acrn/acrn/Kconfig.defconfig b/boards/acrn/acrn/Kconfig.defconfig index dbc4a23333cc5..678c8a5e378f4 100644 --- a/boards/acrn/acrn/Kconfig.defconfig +++ b/boards/acrn/acrn/Kconfig.defconfig @@ -5,11 +5,6 @@ config MP_MAX_NUM_CPUS default 2 -configdefault HEAP_MEM_POOL_ADD_SIZE_ACPI +config HEAP_MEM_POOL_ADD_SIZE_ACPI default 32768 - -configdefault MAIN_STACK_SIZE - default 32000 if ACPI - -configdefault SHELL_STACK_SIZE - default 32000 if SHELL && ACPI + depends on ACPI diff --git a/boards/acrn/acrn/acrn_adl_crb.dts b/boards/acrn/acrn/acrn_adl_crb.dts index 064b9d46231fb..c13054d38912f 100644 --- a/boards/acrn/acrn/acrn_adl_crb.dts +++ b/boards/acrn/acrn/acrn_adl_crb.dts @@ -4,49 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -/dts-v1/; - -#include - -#define DT_DRAM_SIZE DT_SIZE_K(8192) -#define DT_DRAM_BASE 0 - -#include - -/ { - model = "ACRN"; - compatible = "acrn"; - - aliases { - uart-0 = &uart0; - uart-1 = &uart1; - }; - - chosen { - zephyr,sram = &dram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; - - pcie0: pcie0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "pcie-controller"; - acpi-hid = "PNP0A03"; - ranges; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; - -&cpu { - compatible = "intel,x86_64"; -}; +#include "acrn.dts" diff --git a/boards/acrn/acrn/acrn_adl_crb_defconfig b/boards/acrn/acrn/acrn_adl_crb_defconfig index 765fc7e30712f..de5dfe547e78a 100644 --- a/boards/acrn/acrn/acrn_adl_crb_defconfig +++ b/boards/acrn/acrn/acrn_adl_crb_defconfig @@ -13,6 +13,3 @@ CONFIG_BUILD_OUTPUT_BIN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n CONFIG_KERNEL_VM_SIZE=0x5000000 CONFIG_APIC_TSC_DEADLINE_TIMER=y -CONFIG_MP_MAX_NUM_CPUS=1 -CONFIG_ACPI=y -CONFIG_PCIE=y diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 index 5baed3c43d479..63f45c11300ec 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2 diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft index bdf0d84d47c54..e54cad03d4221 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse index 1025c63cf4df4..1d470f8749063 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE diff --git a/boards/adafruit/feather_esp32s2/Kconfig.defconfig b/boards/adafruit/feather_esp32s2/Kconfig.defconfig index a2559a48619f2..734863a6654b1 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.defconfig +++ b/boards/adafruit/feather_esp32s2/Kconfig.defconfig @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi index bd19e0ddc4494..a6c67847bbb3f 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner . + * Copyright (c) 2025 Philipp Steiner . * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts index 4cf4d79c29a9f..e7e3f8efb7b50 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay index 0fdd649728bd5..096357d93eb77 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay index c8f08e5b34454..94550a53acda4 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi index ae0eaf92ade61..257ea650a298b 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts index 114a2d9cb91d1..c57ebdc8b8b97 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts index be28841df3a4d..1775f4c1a6344 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,6 +19,7 @@ aliases { backlight = &led1; + fuel-gauge0 = &max17048; }; leds { diff --git a/boards/adafruit/feather_esp32s2/board.c b/boards/adafruit/feather_esp32s2/board.c index aa4053f60fa1e..e7f65a4ba537a 100644 --- a/boards/adafruit/feather_esp32s2/board.c +++ b/boards/adafruit/feather_esp32s2/board.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst index a5fb76324d985..2c6adf70de2f0 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- LC709203F or MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Built-in NeoPixel indicator RGB LED - STEMMA QT connector for I2C devices, with switchable power for low-power mode @@ -28,12 +28,10 @@ Hardware overlay. All boards, except the `Adafruit ESP32-S2 Feather with BME280 Sensor`_ have a space for it, but will not be shipped with. - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the - now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + now-discontinued LC709203F to the MAX17048. Check the back silkscreen of your Feather to see which chip you have. - - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via - a devicetree overlay. - - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC - is not available. + - For the MAX17048 and LC709203F a driver in zephyr exists and is supported, but needs to be + added via a devicetree overlay. - For the `Adafruit ESP32-S2 Feather`_ there are two different Revisions ``rev B`` and ``rev C``. The ``rev C`` board has revised the power circuitry for the NeoPixel and I2C QT port. Instead of a transistor the ``rev C`` has a LDO regulator. To enable the @@ -304,19 +302,64 @@ functioning correctly with Zephyr: :board: adafruit_feather_esp32s2@C :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** -There is a sample available to verify that the MAX17048 fuel gauge on the board are -functioning correctly with Zephyr: +There is a sample available to verify that the MAX17048 or LC709203F fuel gauge on the board are +functioning correctly with Zephyr .. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203F to the MAX17048. +**Rev B** + +For the Rev B a devicetree overlay for the LC709203F fuel gauge already exists in the +``samples/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge + :board: adafruit_feather_esp32s2@B + :goals: build flash + +**Rev C** + +For the Rev C a devicetree overlay for the MAX17048 fuel gauge already exists in the +``samples/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge + :board: adafruit_feather_esp32s2@C + :goals: build flash + +For the LC709203F a devicetree overlay needs to be added to the build. +The overlay can be added via the ``--extra-dtc-overlay`` argument and should most likely includes +the following: + +.. code-block:: devicetree + + / { + aliases { + fuel-gauge0 = &lc709203f; + }; + }; + + &i2c0 { + lc709203f: lc709203f@0b { + compatible = "onnn,lc709203f"; + status = "okay"; + reg = <0x0b>; + power-domains = <&i2c_reg>; + apa = "500mAh"; + battery-profile = <0x01>; + }; + }; + + .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/fuel_gauge :board: adafruit_feather_esp32s2@C + :west-args: --extra-dtc-overlay="boards/name_of_your.overlay" :goals: build flash Testing Wi-Fi diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst index 6f44363ca4b59..a6bb8bdb925f2 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- LC709203F or MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Charging indicator LED, user LED, reset and boot buttons. - Built-in NeoPixel indicator RGB LED - STEMMA QT connector for I2C devices, with switchable power for low-power mode @@ -26,12 +26,10 @@ Hardware - The board has a space for a BME280, but will not be shipped with. - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the - now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + now-discontinued LC709203F to the MAX17048. Check the back silkscreen of your Feather to see which chip you have. - - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via - a devicetree overlay. - - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC - is not available. + - For the MAX17048 and LC709203F a driver in zephyr exists and is supported, but needs to be + added via a devicetree overlay. Supported Features ================== @@ -252,19 +250,52 @@ Testing the TFT :board: adafruit_feather_esp32s2_tft :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** -There is a sample available to verify that the MAX17048 fuel gauge on the board are -functioning correctly with Zephyr: +There is a sample available to verify that the MAX17048 or LC709203F fuel gauge on the board are +functioning correctly with Zephyr. .. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203F to the MAX17048. +**LC709203F Fuel Gauge** + +For the LC709203F a devicetree overlay already exists in the ``samples/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +**MAX17048 Fuel Gauge** + +For the MAX17048 a devicetree overlay needs to be added to the build. +The overlay can be added via the ``--extra-dtc-overlay`` argument and should most likely includes +the following: + +.. code-block:: devicetree + + / { + aliases { + fuel-gauge0 = &max17048; + }; + }; + + &i2c0 { + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "okay"; + reg = <0x36 >; + power-domains = <&i2c_reg>; + }; + }; + .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/fuel_gauge :board: adafruit_feather_esp32s2_tft + :west-args: --extra-dtc-overlay="boards/name_of_your.overlay" :goals: build flash Testing Wi-Fi diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst index fcbb635220591..3ca1ac9be25c1 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Charging indicator LED, user LED, reset and boot buttons and has 2 additional buttons. - Built-in NeoPixel indicator RGB LED - 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset. @@ -249,18 +249,14 @@ functioning correctly with Zephyr: :board: adafruit_feather_esp32s2_tft_reverse :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** There is a sample available to verify that the MAX17048 fuel gauge on the board are functioning correctly with Zephyr: -.. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 - to the MAX17048. - .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/fuel_gauge :board: adafruit_feather_esp32s2_tft_reverse :goals: build flash diff --git a/boards/adafruit/feather_esp32s2/feather_connector.dtsi b/boards/adafruit/feather_esp32s2/feather_connector.dtsi index f4bfbc1c3b57b..8414fbbfb106c 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector.dtsi @@ -1,7 +1,7 @@ /* * Copyright (c) 2020 Richard Osterloh * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi index a593471c7879d..3a2eb8c3e0da8 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi @@ -1,7 +1,7 @@ /* * Copyright (c) 2020 Richard Osterloh * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts index b745820ddaa09..a782536176bc6 100644 --- a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts @@ -38,6 +38,7 @@ sw0 = &button0; led0 = &led0; led-strip = &led_strip; + fuel-gauge0 = &max17048; }; buttons { diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts index b09b6262aa1e9..ab7659eef4676 100644 --- a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts @@ -22,6 +22,7 @@ aliases { i2c-0 = &i2c0; watchdog0 = &wdt0; + fuel-gauge0 = &max17048; }; chosen { diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index f291e50a80689..4de11b92848b1 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -9,7 +9,6 @@ #include #include #include -#include #include / { @@ -83,37 +82,6 @@ <20 0 &gpio2 17 0>, /* D14 */ <21 0 &gpio2 18 0>; /* D15 */ }; - - pmod_header: pmod-header { - compatible = "digilent,pmod"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 0 0>, /* IO1/CS */ - <1 0 &gpio1 1 0>, /* IO2/MOSI */ - <2 0 &gpio1 2 0>, /* IO3/MISO */ - <3 0 &gpio1 3 0>, /* IO4/SCK */ - <4 0 &gpio2 21 0>, /* IO5/INT */ - <5 0 &gpio1 6 0>, /* IO6/RESET */ - <6 0 &gpio1 4 0>, /* IO7/CS2 */ - <7 0 &gpio1 5 0>; /* IO8/CS3 */ - }; - - sdram1: sdram1@60000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - status = "disabled"; - device_type = "memory"; - reg = <0x60000000 DT_SIZE_M(64)>; - zephyr,memory-region = "SDRAM1"; - }; - - sdram2: sdram2@70000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - status = "disabled"; - device_type = "memory"; - reg = <0x70000000 DT_SIZE_M(64)>; - zephyr,memory-region = "SDRAM2"; - }; }; &clk_ipo { @@ -259,52 +227,3 @@ pmod_spi: &spi4 { pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>; pinctrl-names = "default"; }; - -&hpb { - pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_cs1n_p1_17 &hyp_rwds_p1_14 - &hyp_d0_p1_12 &hyp_d1_p1_15 - &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 - &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; - pinctrl-names = "default"; - enable-emcc; - - mem@0 { - reg = <0>; - base-address = <0x60000000>; - device-type = ; - - latency-cycles = ; - read-cs-high = ; - write-cs-high = ; - read-cs-setup = ; - write-cs-setup = ; - read-cs-hold = ; - write-cs-hold = ; - - /* CR0 settings. Key setting is enabling 6-clock latency, since - * HPB doesn't support 7-clock latency which is default - */ - config-regs = <0x1000>; - config-reg-vals = <0x801F>; - }; - - mem@1 { - reg = <1>; - base-address = <0x70000000>; - device-type = ; - - latency-cycles = ; - read-cs-high = ; - write-cs-high = ; - read-cs-setup = ; - write-cs-setup = ; - read-cs-hold = ; - write-cs-hold = ; - - /* CR0 settings. Key setting is enabling 6-clock latency, since - * HPB doesn't support 7-clock latency which is default - */ - config-regs = <0x1000>; - config-reg-vals = <0x801F>; - }; -}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml index ba9f690d05494..bf6486d175b38 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.yaml +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -11,13 +11,11 @@ supported: - arduino_serial - arduino_spi - pmod_spi - - pmod_gpio - gpio - serial - spi - trng - counter - w1 - - memc ram: 1024 flash: 3072 diff --git a/boards/adi/max32650evkit/max32650evkit.dts b/boards/adi/max32650evkit/max32650evkit.dts index 48d8e177a890b..2292bfd8b8ac4 100644 --- a/boards/adi/max32650evkit/max32650evkit.dts +++ b/boards/adi/max32650evkit/max32650evkit.dts @@ -18,7 +18,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram4; + zephyr,sram = &sram0; zephyr,flash = &flash0; }; @@ -56,7 +56,6 @@ aliases { led0 = &led1; led1 = &led2; - watchdog0 = &wdt0; }; }; @@ -88,27 +87,3 @@ &gpio3 { status = "okay"; }; - -&dma0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_scl_p2_8 &i2c0_sda_p2_7>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spi2 { - status = "okay"; - pinctrl-0 = <&spi2_mosi_p2_4 &spi2_miso_p2_3 &spi2_sck_p2_2 &spi2_ss0_p2_5>; - pinctrl-names = "default"; -}; - -&wdt0 { - status = "okay"; -}; - -&rtc_counter { - status = "okay"; -}; diff --git a/boards/adi/max32650evkit/max32650evkit.yaml b/boards/adi/max32650evkit/max32650evkit.yaml index 21b8ce3bfa005..8e3ced3c43711 100644 --- a/boards/adi/max32650evkit/max32650evkit.yaml +++ b/boards/adi/max32650evkit/max32650evkit.yaml @@ -9,11 +9,5 @@ toolchain: supported: - gpio - serial - - spi - - i2c - - dma - - watchdog - - counter - - rtc_counter ram: 1024 flash: 3072 diff --git a/boards/adi/max32650fthr/max32650fthr.dts b/boards/adi/max32650fthr/max32650fthr.dts index aa6fcf4e4417a..b471e2523ce0f 100644 --- a/boards/adi/max32650fthr/max32650fthr.dts +++ b/boards/adi/max32650fthr/max32650fthr.dts @@ -18,7 +18,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram4; + zephyr,sram = &sram0; zephyr,flash = &flash0; }; @@ -56,7 +56,6 @@ aliases { led0 = &led1; led1 = &led2; - watchdog0 = &wdt0; }; }; @@ -88,21 +87,3 @@ &gpio3 { status = "okay"; }; - -&dma0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_mosi_p1_29 &spi1_miso_p1_28 &spi1_sck_p1_26 &spi1_ss0_p1_23>; - pinctrl-names = "default"; -}; - -&wdt0 { - status = "okay"; -}; - -&rtc_counter { - status = "okay"; -}; diff --git a/boards/adi/max32650fthr/max32650fthr.yaml b/boards/adi/max32650fthr/max32650fthr.yaml index 880af88f9c4f5..f967621e7020c 100644 --- a/boards/adi/max32650fthr/max32650fthr.yaml +++ b/boards/adi/max32650fthr/max32650fthr.yaml @@ -9,11 +9,5 @@ toolchain: supported: - gpio - serial - - spi - - i2c - - dma - - watchdog - - counter - - rtc_counter ram: 1024 flash: 3072 diff --git a/boards/adi/max32657evkit/Kconfig.defconfig b/boards/adi/max32657evkit/Kconfig.defconfig index dc6e2838d637e..0309586a787ee 100644 --- a/boards/adi/max32657evkit/Kconfig.defconfig +++ b/boards/adi/max32657evkit/Kconfig.defconfig @@ -22,24 +22,4 @@ DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition config FLASH_LOAD_SIZE default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) -if BOARD_MAX32657EVKIT_MAX32657_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -# MAX32657 has one UART interface, -# It can be used either on TFM or Zephyr -# Enabling debug (TFM_SPM_LOG_LEVEL || TFM_PARTITION_LOG_LEVEL) will transfer it to the TFM side -# Disabling TFM debug will transfer it to the Zephyr side. - -choice TFM_SPM_LOG_LEVEL - default TFM_SPM_LOG_LEVEL_SILENCE -endchoice - -choice TFM_PARTITION_LOG_LEVEL - default TFM_PARTITION_LOG_LEVEL_SILENCE -endchoice - -endif # BOARD_MAX32657EVKIT_MAX32657_NS - endif # BOARD_MAX32657EVKIT diff --git a/boards/adi/max32657evkit/Kconfig.max32657evkit b/boards/adi/max32657evkit/Kconfig.max32657evkit index c43a70cd6f710..7f1cae8fc8376 100644 --- a/boards/adi/max32657evkit/Kconfig.max32657evkit +++ b/boards/adi/max32657evkit/Kconfig.max32657evkit @@ -2,5 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MAX32657EVKIT - select SOC_MAX32657 if BOARD_MAX32657EVKIT_MAX32657 || \ - BOARD_MAX32657EVKIT_MAX32657_NS + select SOC_MAX32657 if BOARD_MAX32657EVKIT_MAX32657 diff --git a/boards/adi/max32657evkit/board.cmake b/boards/adi/max32657evkit/board.cmake index ecf66679a2335..09717336e5fda 100644 --- a/boards/adi/max32657evkit/board.cmake +++ b/boards/adi/max32657evkit/board.cmake @@ -1,10 +1,6 @@ # Copyright (c) 2024-2025 Analog Devices, Inc. # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_BOARD_MAX32657EVKIT_MAX32657_NS) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - board_runner_args(jlink "--device=MAX32657" "--reset-after-load") include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) diff --git a/boards/adi/max32657evkit/board.yml b/boards/adi/max32657evkit/board.yml index 6fa072a593ce1..48af69011b6b6 100644 --- a/boards/adi/max32657evkit/board.yml +++ b/boards/adi/max32657evkit/board.yml @@ -6,5 +6,3 @@ board: vendor: adi socs: - name: max32657 - variants: - - name: "ns" diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst index e96410f6a1e18..67694e070eb19 100644 --- a/boards/adi/max32657evkit/doc/index.rst +++ b/boards/adi/max32657evkit/doc/index.rst @@ -288,7 +288,6 @@ Zephyr board options The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) featuring an ARM Cortex-M33 architecture that provides Trustzone technology which allow define secure and non-secure application. -Zephyr provides support for building for both Secure (S) and Non-Secure (NS) firmware. The BOARD options are summarized below: @@ -297,18 +296,16 @@ The BOARD options are summarized below: +===============================+===========================================+ | max32657evkit/max32657 | For building Trust Zone Disabled firmware | +-------------------------------+-------------------------------------------+ -| max32657evkit/max32657/ns | Building with TF-M (includes NS+S images) | -+-------------------------------+-------------------------------------------+ BOARD: max32657evkit/max32657 ============================= -Build the zephyr app for ``max32657evkit/max32657`` board target will generate secure firmware +Build the zephyr app for ``max32657evkit/max32657`` board will generate secure firmware for zephyr. In this configuration 960KB of flash is used to store the code and 64KB is used for storage section. In this mode tf-m is off and secure mode flag is on -(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_SECURE` to ``y`` and -:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``n``) +``:kconfig:option:CONFIG_TRUSTED_EXECUTION_SECURE=y`` and +``:kconfig:option:CONFIG_BUILD_WITH_TFM=n`` +----------+------------------+---------------------------------+ | Name | Address[Size] | Comment | @@ -327,172 +324,6 @@ using :zephyr:code-sample:`blinky` sample: :goals: build -BOARD: max32657evkit/max32657/ns -================================ - -The ``max32657evkit/max32657/ns`` board target is used to build the secure firmware -image using TF-M (:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``y``) and -the non-secure firmware image using Zephyr -(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_NONSECURE` to ``y``). - -Here are the instructions to build zephyr with a non-secure configuration, -using :zephyr:code-sample:`blinky` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky/ - :board: max32657evkit/max32657/ns - :goals: build - -The above command will: - * Build a bootloader image (MCUboot) - * Build a TF-M (secure) firmware image - * Build Zephyr application as non-secure firmware image - * Merge them as ``tfm_merged.hex`` which contain all images. - - -Note: - -Zephyr build TF-M with :kconfig:option:`CONFIG_TFM_PROFILE_TYPE_NOT_SET` mode -that meet most use case configuration especially for BLE related applications. -if TF-M small profile meet your application requirement you can set TF-M profile as small -:kconfig:option:`CONFIG_TFM_PROFILE_TYPE_SMALL` to ``y`` to decrease TF-M RAM and flash use. - - -Memory mappings ---------------- - -MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, -TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. -Default layout of MAX32657 is listed in below table. - -+----------+------------------+---------------------------------+ -| Name | Address[Size] | Comment | -+==========+==================+=================================+ -| boot | 0x1000000[64K] | MCU Bootloader | -+----------+------------------+---------------------------------+ -| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | -+----------+------------------+---------------------------------+ -| slot0_ns | 0x1060000[576k] | Non-secure image slot0 (Zephyr) | -+----------+------------------+---------------------------------+ -| slot1 | 0x10F0000[0k] | Updates slot0 image | -+----------+------------------+---------------------------------+ -| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | -+----------+------------------+---------------------------------+ -| storage | 0x10f0000[64k] | Persistent storage | -+----------+------------------+---------------------------------+ - - -+----------------+------------------+-------------------+ -| RAM | Address[Size] | Comment | -+================+==================+===================+ -| secure_ram | 0x20000000[64k] | Secure memory | -+----------------+------------------+-------------------+ -| non_secure_ram | 0x20010000[192k] | Non-Secure memory | -+----------------+------------------+-------------------+ - - -Flash memory layout are defines both on zephyr board file and `Trusted Firmware M`_ (TF-M) project -these definition shall be match. Zephyr defines it in -:zephyr_file:`boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi` -file under flash section. TF-M project define them in -../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/partition/flash_layout.h file.` -If you would like to update flash region for your application you shall update related section in -these files. - -Additionally if firmware update feature requires slot1 and slot1_ns section need to be -defined. On default the section size set as 0 due to firmware update not requires on default. - - -Peripherals and Memory Ownership --------------------------------- - -The ARM Security Extensions model allows system developers to partition device hardware and -software resources, so that they exist in either the Secure world for the security subsystem, -or the Normal world for everything else. Correct system design can ensure that no Secure world -assets can be accessed from the Normal world. A Secure design places all sensitive resources -in the Secure world, and ideally has robust software running that can protect assets against -a wide range of possible software attacks (`1`_). - -MPC (Memory Protection Controller) and PPC (Peripheral Protection Controller) are allow to -protect memory and peripheral. Incase of need peripheral and flash ownership can be updated in -../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/s_ns_access.cmake` -file by updating cmake flags to ON/OFF. - -As an example for below configuration TRNG, SRAM_0 and SRAM_1 is not going to be accessible -by non-secure. All others is going to be accessible by NS world. - -.. code-block:: - - set(ADI_NS_PRPH_GCR ON CACHE BOOL "") - set(ADI_NS_PRPH_SIR ON CACHE BOOL "") - set(ADI_NS_PRPH_FCR ON CACHE BOOL "") - set(ADI_NS_PRPH_WDT ON CACHE BOOL "") - set(ADI_NS_PRPH_AES OFF CACHE BOOL "") - set(ADI_NS_PRPH_AESKEY OFF CACHE BOOL "") - set(ADI_NS_PRPH_CRC ON CACHE BOOL "") - set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") - set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") - set(ADI_NS_PRPH_I3C ON CACHE BOOL "") - set(ADI_NS_PRPH_UART ON CACHE BOOL "") - set(ADI_NS_PRPH_SPI ON CACHE BOOL "") - set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") - set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") - set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") - set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") - set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") - set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") - set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") - set(ADI_NS_PRPH_RTC ON CACHE BOOL "") - set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") - set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") - set(ADI_NS_PRPH_PWR ON CACHE BOOL "") - set(ADI_NS_PRPH_MCR ON CACHE BOOL "") - - # SRAMs - set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") - set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") - set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") - set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") - set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") - - # Ramfuncs section size - set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") - - # Flash: BL2, TFM and Zephyr are contiguous sections. - set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") - set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") - set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") - set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") - set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") - - # - # Allow user set S-NS resources ownership by overlay file - # - if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") - include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) - endif() - - -As an alternative method (which recommended) user can configurate ownership peripheral by -an cmake overlay file too without touching TF-M source files. For this path -create ``s_ns_access_overlay.cmake`` file under your project root folder and put peripheral/memory -you would like to be accessible by secure world. - -As an example if below configuration files been put in the ``s_ns_access_overlay.cmake`` file -TRNG, SRAM_0 and SRAM_1 will be accessible by secure world only. - -.. code-block:: - - set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") - set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") - set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") - - Programming and Debugging ************************* @@ -517,34 +348,6 @@ see the following message in the terminal: ***** Booting Zephyr OS build v4.1.0 ***** Hello World! max32657evkit/max32657 -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- -The TF-M integration samples can be run using the -``max32657evkit/max32657/ns`` board target. To run we need to manually flash -the resulting image (``tfm_merged.hex``) with a J-Link as follows -(reset and erase are for recovering a locked core): - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: max32657evkit/max32657/ns - :goals: build - -.. code-block:: console - - west flash --hex-file build/zephyr/tfm_merged.hex - -.. code-block:: console - - [INF] Starting bootloader - [WRN] This device was provisioned with dummy keys. This device is NOT SECURE - [INF] PSA Crypto init done, sig_type: RSA-3072 - [WRN] Cannot upgrade: slots have non-compatible sectors - [WRN] Cannot upgrade: slots have non-compatible sectors - [INF] Bootloader chainload address offset: 0x10000 - [INF] Jumping to the first image slot - ***** Booting Zephyr OS build v4.1.0 ***** - Hello World! max32657evkit/max32657/ns - Debugging ========= @@ -564,12 +367,3 @@ should see the following message in the terminal: ***** Booting Zephyr OS build v4.1.0 ***** Hello World! max32657evkit/max32657 - -References -********** - -.. _1: - https://developer.arm.com/documentation/100935/0100/The-TrustZone-hardware-architecture- - -.. _Trusted Firmware M: - https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts b/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts deleted file mode 100644 index a8e9369eeedbc..0000000000000 --- a/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2024-2025 Analog Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "max32657evkit_max32657_common.dtsi" - -/ { - chosen { - zephyr,sram = &non_secure_ram; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_ns_partition; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* RAM split used by TFM */ - secure_ram: partition@20000000 { - label = "secure-memory"; - reg = <0x20000000 DT_SIZE_K(64)>; - }; - - non_secure_ram: partition@20010000 { - label = "non-secure-memory"; - reg = <0x20010000 DT_SIZE_K(192)>; - }; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(64)>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x10000 DT_SIZE_K(320)>; - }; - - slot0_ns_partition: partition@60000 { - label = "image-0-nonsecure"; - reg = <0x60000 DT_SIZE_K(576)>; - }; - - /* - * slot1_partition: partition@f0000 { - * label = "image-1"; - * reg = <0xf0000 DT_SIZE_K(0)>; - * }; - * slot1_ns_partition: partition@f0000 { - * label = "image-1-nonsecure"; - * reg = <0xf0000 DT_SIZE_K(0)>; - * }; - */ - - storage_partition: partition@f0000 { - label = "storage"; - reg = <0xf0000 DT_SIZE_K(64)>; - }; - }; -}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml deleted file mode 100644 index 82703d9e3544a..0000000000000 --- a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: max32657evkit/max32657/ns -name: max32657evkit-max32657-Non-Secure -vendor: adi -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - serial - - gpio -ram: 192 -flash: 576 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig deleted file mode 100644 index d808f79c54594..0000000000000 --- a/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024-2025 Analog Devices, Inc. -# SPDX-License-Identifier: Apache-2.0 - -# Enable GPIO -CONFIG_GPIO=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable UART -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# It is non-secure fw, enable flags -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Set TFM and Zephyr sign key -CONFIG_TFM_MCUBOOT_SIGNATURE_TYPE="RSA-3072" diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index 8e2aabb71f89a..132f29f304174 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -9,7 +9,6 @@ #include #include #include -#include #include #include @@ -96,30 +95,6 @@ mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; }; - - sdram1: sdram1@60000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - status = "disabled"; - device_type = "memory"; - reg = <0x60000000 DT_SIZE_M(8)>; - zephyr,memory-region = "SDRAM1"; - }; -}; - -&hpb { - pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_rwds_p1_14 &hyp_d0_p1_12 &hyp_d1_p1_15 - &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 - &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; - pinctrl-names = "default"; - enable-emcc; - - mem@0 { - reg = <0>; - base-address = <0x60000000>; - device-type = ; - config-regs = <1>; - config-reg-vals = <2>; - }; }; &clk_ipo { diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml index 83c03c9715d8b..8278d3fe168b0 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -21,6 +21,5 @@ supported: - w1 - flash - usbd - - memc ram: 1024 flash: 3072 diff --git a/boards/adi/max32690fthr/doc/max32690fthr.webp b/boards/adi/max32690fthr/doc/max32690fthr.webp deleted file mode 100644 index cf4062dcbe9a2..0000000000000 Binary files a/boards/adi/max32690fthr/doc/max32690fthr.webp and /dev/null differ diff --git a/boards/aesc/elemrv/Kconfig.elemrv b/boards/aesc/elemrv/Kconfig.elemrv deleted file mode 100644 index 9c22c252583c0..0000000000000 --- a/boards/aesc/elemrv/Kconfig.elemrv +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Aesc Silicon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ELEMRV - select SOC_ELEMRV_N diff --git a/boards/aesc/elemrv/board.yml b/boards/aesc/elemrv/board.yml deleted file mode 100644 index 8a4890dd13a80..0000000000000 --- a/boards/aesc/elemrv/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: elemrv - full_name: ElemRV-N - vendor: aesc - socs: - - name: elemrv_n diff --git a/boards/aesc/elemrv/doc/index.rst b/boards/aesc/elemrv/doc/index.rst deleted file mode 100644 index cae642e0a2745..0000000000000 --- a/boards/aesc/elemrv/doc/index.rst +++ /dev/null @@ -1,72 +0,0 @@ -.. zephyr:board:: elemrv - -Overview -******** - -ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL. - -Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_. - -For more details, refer to the official `GitHub Project`_. - -.. note:: - The currently supported silicon version is ElemRV-N 0.2. - -Supported Features -****************** - -.. zephyr:board-supported-hw:: - -System Clock -============ - -The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property. - -CPU -=== - -ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions: - -* M (Integer Multiply/Divide) -* C (Compressed Instructions) - -It also includes the following general-purpose ``Z`` extensions: - -* Zicntr – Base Counter and Timer extensions -* Zicsr – Control and Status Register operations -* Zifencei – Instruction-fetch fence - -The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei`` - -Hart-Level Interrupt Controller (HLIC) -====================================== - -Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs). - -Machine Timer -============= - -A RISC-V compliant machine timer is enabled by default. - -Serial -====== - -The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data. - -By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree. - -To evaluate the UART interface, build and run the following sample: - -.. zephyr-app-commands:: - :board: elemrv/elemrv_n - :zephyr-app: samples/hello_world - :goals: build - -.. _GitHub Project: - https://github.com/aesc-silicon/elemrv - -.. _IHP's Open PDK: - https://github.com/IHP-GmbH/IHP-Open-PDK - -.. _FMD-QNC: - https://www.elektronikforschung.de/projekte/fmd-qnc diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.dts b/boards/aesc/elemrv/elemrv_elemrv_n.dts deleted file mode 100644 index 4b9ea13bf8493..0000000000000 --- a/boards/aesc/elemrv/elemrv_elemrv_n.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2025 Aesc Silicon - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - model = "ElemRV-N"; - compatible = "aesc,elemrv-n"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &hyperbus; - zephyr,flash = &flash; - }; - - soc { - ocram: memory@80000000 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0x80000000 DT_SIZE_K(1)>; - }; - - hyperbus: memory@90000000 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0x90000000 DT_SIZE_K(32)>; - }; - - flash: flash@a0010000 { - compatible = "soc-nv-flash"; - reg = <0xa0010000 DT_SIZE_K(32)>; - }; - }; -}; - -&uart0 { - clock-frequency = ; - current-speed = <115200>; - status = "okay"; -}; - -&cpu0 { - clock-frequency = ; -}; diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.yaml b/boards/aesc/elemrv/elemrv_elemrv_n.yaml deleted file mode 100644 index 4c9c3a9917493..0000000000000 --- a/boards/aesc/elemrv/elemrv_elemrv_n.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: elemrv/elemrv_n -name: ElemRV-N -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -ram: 32 -flash: 32 diff --git a/boards/aesc/elemrv/elemrv_elemrv_n_defconfig b/boards/aesc/elemrv/elemrv_elemrv_n_defconfig deleted file mode 100644 index ac046a3cbbc5a..0000000000000 --- a/boards/aesc/elemrv/elemrv_elemrv_n_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2025 Aesc Silicon -# SPDX-License-Identifier: Apache-2.0 - -# Serial Driver -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/aesc/index.rst b/boards/aesc/index.rst deleted file mode 100644 index 2471cc5acc010..0000000000000 --- a/boards/aesc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-aesc: - -Aesc Silicon -############ - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f b/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f deleted file mode 100644 index 9c4fa2f57d729..0000000000000 --- a/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_AI_WB2_12F - select SOC_BL602C00Q2I diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi b/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi deleted file mode 100644 index 2ca4920928772..0000000000000 --- a/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - uart0_default: uart0_default { - group1 { - pinmux = , - ; - bias-pull-up; - input-schmitt-enable; - }; - }; - - uart0_sleep: uart0_sleep { - group1 { - pinmux = , - ; - bias-high-impedance; - }; - }; -}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts deleted file mode 100644 index d3e99d7a45fa0..0000000000000 --- a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "ai_wb2_12f-pinctrl.dtsi" - -/ { - model = "Ai-Thinker WB2-12F development board"; - compatible = "bflb,bl602"; - - chosen { - zephyr,flash = &flash0; - zephyr,itcm = &itcm; - zephyr,dtcm = &dtcm; - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&spi1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4000b000 0x1000 0x23000000 0x400000>; - - flash0: flash@0 { - compatible = "zb,25vq32", "jedec,spi-nor"; - status = "disabled"; - size = ; - jedec-id = [5e 40 16]; - reg = <0>; - spi-max-frequency = ; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml deleted file mode 100644 index e7c5a4dc59e57..0000000000000 --- a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) -# -# SPDX-License-Identifier: Apache-2.0 - -identifier: ai_wb2_12f -name: Ai-Thinker WB2-12F development board -type: mcu -arch: riscv -ram: 64 -toolchain: - - zephyr -testing: - ignore_tags: - - net - - bluetooth -supported: - - pinctrl - - uart -vendor: bflb diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig b/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig deleted file mode 100644 index 7836442f7c45d..0000000000000 --- a/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_UART_CONSOLE=y diff --git a/boards/aithinker/ai_wb2_12f/board.cmake b/boards/aithinker/ai_wb2_12f/board.cmake deleted file mode 100644 index 1a2a98c777e15..0000000000000 --- a/boards/aithinker/ai_wb2_12f/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) -# -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") - -board_runner_args(openocd --use-elf --no-load --no-init) -board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") -board_runner_args(openocd --gdb-init "set architecture riscv:rv32") -board_runner_args(openocd --gdb-init "set remotetimeout 250") -board_runner_args(openocd --gdb-init "set print asm-demangle on") -board_runner_args(openocd --gdb-init "set backtrace limit 32") -board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") -board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") -board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") -board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") -board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") -board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") -board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/aithinker/ai_wb2_12f/board.yml b/boards/aithinker/ai_wb2_12f/board.yml deleted file mode 100644 index 071ebf95f871f..0000000000000 --- a/boards/aithinker/ai_wb2_12f/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: ai_wb2_12f - full_name: Ai-Thinker WB2-12F development board - vendor: bflb - socs: - - name: bl602c00q2i diff --git a/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp b/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp deleted file mode 100644 index ae6ef3f02dc16..0000000000000 Binary files a/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp and /dev/null differ diff --git a/boards/aithinker/ai_wb2_12f/doc/index.rst b/boards/aithinker/ai_wb2_12f/doc/index.rst deleted file mode 100644 index b68fc820bbc9b..0000000000000 --- a/boards/aithinker/ai_wb2_12f/doc/index.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. zephyr:board:: ai_wb2_12f - -Overview -******** - -BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used -for low power consumption and high performance application development. The -wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 -baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU -with low power consumption, cache and memory. The power management unit -controls the low power consumption mode. In addition, it also supports -various security features. The external interfaces include SDIO, SPI, UART, -I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. - -This WB2 (BL602) 12F format Module Development Board features a SiFive E24 32 bit -RISC-V CPU with FPU, it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, -2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 -with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed -image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key -Accelerator). - -Hardware -******** - -For more information about the Bouffalo Lab BL-60x MCU: - -- `Bouffalo Lab BL60x MCU Website`_ -- `Bouffalo Lab BL60x MCU Datasheet`_ -- `Bouffalo Lab Development Zone`_ -- `ai_wb2_12f Schematics`_ -- `The RISC-V BL602 Book`_ - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -System Clock -============ - -The WB2 (BL602) Development Board is configured to run at max speed (192MHz). - -Serial Port -=========== - -The ``ai_wb2_12f`` board uses UART0 as default serial port. It is connected -to USB Serial converter and port is used for both program and console. - - -Programming and Debugging -************************* - -Samples -======= - -#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample -application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ai_wb2_12f - :goals: build flash - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ screen /dev/ttyUSB0 115200 - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - - Then, press and release RST button - - .. code-block:: console - - *** Booting Zephyr OS build v4.1.0 *** - Hello World! ai_wb2_12f/bl602c00q2i - -Congratulations, you have ``ai_wb2_12f`` configured and running Zephyr. - - -.. _Bouffalo Lab BL60x MCU Website: - https://en.bouffalolab.com/product/?type=detail&id=6 - -.. _Bouffalo Lab BL60x MCU Datasheet: - https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en - -.. _Bouffalo Lab Development Zone: - https://dev.bouffalolab.com/home?id=guest - -.. _ai_wb2_12f Schematics: - https://docs.ai-thinker.com/en/wb2 - -.. _The RISC-V BL602 Book: - https://lupyuen.github.io/articles/book - -.. _Flashing Firmware to BL602: - https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/aithinker/ai_wb2_12f/support/bl60x.cfg b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg deleted file mode 100644 index fcabb2c4e7c04..0000000000000 --- a/boards/aithinker/ai_wb2_12f/support/bl60x.cfg +++ /dev/null @@ -1,79 +0,0 @@ -# Copyright (c) 2022-2025 ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME riscv -} - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -if { [info exists WORKAREAADDR] } { - set _WORKAREAADDR $WORKAREAADDR -} else { - set _WORKAREAADDR 0x22020000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x20000c05 -} - -transport select jtag -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME - -$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 - -echo "Ready for Remote Connections" - -$_TARGETNAME.0 configure -event reset-assert-pre { - echo "reset-assert-pre" - adapter speed 100 -} - -$_TARGETNAME.0 configure -event reset-deassert-post { - echo "reset-deassert-post" - - adapter speed 100 - - reg mstatus 0x7800 - reg mie 0x0 -# reg pc 0x23000000 -} - -$_TARGETNAME.0 configure -event reset-init { - echo "reset-init" - - adapter speed 3000 -} - -$_TARGETNAME.0 configure -event gdb-attach { - echo "Debugger attaching: halting execution" - reset halt - gdb_breakpoint_override hard -} - -$_TARGETNAME.0 configure -event gdb-detach { - echo "Debugger detaching: resuming execution" - resume -} - -gdb_memory_map enable -gdb_flash_program enable - -# 'progbuf', 'sysbus' or 'abstract' -riscv set_mem_access sysbus -riscv set_command_timeout_sec 1 - -init -reset init diff --git a/boards/aithinker/ai_wb2_12f/support/openocd.cfg b/boards/aithinker/ai_wb2_12f/support/openocd.cfg deleted file mode 100644 index 9a3b1644e96d2..0000000000000 --- a/boards/aithinker/ai_wb2_12f/support/openocd.cfg +++ /dev/null @@ -1,5 +0,0 @@ -# For WCH linkE in DAP mode - -interface cmsis-dap - -adapter speed 1000 diff --git a/boards/aithinker/index.rst b/boards/aithinker/index.rst deleted file mode 100644 index cdefd628132bc..0000000000000 --- a/boards/aithinker/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-aithinker: - -Ai-Thinker Co. -############## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/altr/index.rst b/boards/altr/index.rst new file mode 100644 index 0000000000000..83220f8c905bc --- /dev/null +++ b/boards/altr/index.rst @@ -0,0 +1,10 @@ +.. _boards-altera: + +Altera Corporation +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 new file mode 100644 index 0000000000000..b0b39da844877 --- /dev/null +++ b/boards/altr/max10/Kconfig.altera_max10 @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +config BOARD_ALTERA_MAX10 + select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig new file mode 100644 index 0000000000000..d0617d44c33cd --- /dev/null +++ b/boards/altr/max10/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +if BOARD_ALTERA_MAX10 + +if FLASH + +config SOC_FLASH_NIOS2_QSPI + default y + +endif # FLASH + +endif # BOARD_ALTERA_MAX10 diff --git a/boards/altr/max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts new file mode 100644 index 0000000000000..30c7e44250571 --- /dev/null +++ b/boards/altr/max10/altera_max10.dts @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2018 Intel */ + +/dts-v1/; + +#include +#include + +/ { + model = "altera_max10"; + compatible = "altr,nios2-max10"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; +}; + +&qspi { + status = "okay"; + n25q512ax3: n25q512ax3@0 { + compatible = "altr,nios2-qspi-nor"; + size = ; /* in bits */ + reg = <0>; + }; +}; diff --git a/boards/altr/max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml new file mode 100644 index 0000000000000..eb068f21f47cc --- /dev/null +++ b/boards/altr/max10/altera_max10.yaml @@ -0,0 +1,7 @@ +identifier: altera_max10 +name: Altera MAX10 +type: mcu +arch: nios2 +toolchain: + - zephyr +vendor: altr diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig new file mode 100644 index 0000000000000..ac9a2e96e4d3c --- /dev/null +++ b/boards/altr/max10/altera_max10_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +CONFIG_HAS_ALTERA_HAL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/altr/max10/board.cmake b/boards/altr/max10/board.cmake new file mode 100644 index 0000000000000..9e7a8dd873d55 --- /dev/null +++ b/boards/altr/max10/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(nios2 "--cpu-sof=${ZEPHYR_BASE}/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof") +include(${ZEPHYR_BASE}/boards/common/nios2.board.cmake) diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml new file mode 100644 index 0000000000000..9106b7e15ec0b --- /dev/null +++ b/boards/altr/max10/board.yml @@ -0,0 +1,6 @@ +board: + name: altera_max10 + full_name: MAX10 + vendor: altr + socs: + - name: zephyr_nios2f diff --git a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg new file mode 100644 index 0000000000000..5c71d7bf80d8c Binary files /dev/null and b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg differ diff --git a/boards/altr/max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg new file mode 100644 index 0000000000000..51d5424c2f8f5 Binary files /dev/null and b/boards/altr/max10/doc/img/altera_max10.jpg differ diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst new file mode 100644 index 0000000000000..1e5064b0f0d7f --- /dev/null +++ b/boards/altr/max10/doc/index.rst @@ -0,0 +1,324 @@ +.. zephyr:board:: altera_max10 + +Overview +******** + +The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using +the Nios II Gen 2 soft CPU. + +Hardware +******** + +DIP Switch settings +=================== + +There are two sets of switches on the back of the board. Of particular +importance is SW2: + +* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first + boot image is CFM0 +* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing + scripts won't work +* Switch 4 (HSMC_BYPASSN) should be OFF (up) + +.. image:: img/Altera_MAX10_switches.jpg + :align: center + :alt: Altera's MAX* 10 Switches + +Other switches are user switches, their position is application-specific. + +Necessary Software +================== + +You will need the Altera Quartus SDK in order to work with this device. The +`Altera Lite Distribution`_ of Quartus may be obtained without +charge. + +For your convenience using the SDK tools (such as ``nios2-configure-sof``), +you should put the binaries provided by the SDK +in your path. Below is an example, adjust ALTERA_BASE to where you installed the +SDK: + +.. code-block:: console + + export ALTERA_BASE=/opt/altera_lite/16.0 + export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin + +You may need to adjust your udev rules so that you can talk to the USB Blaster +II peripheral, which is the built-in JTAG interface for this device. + +The following works for Fedora 23: + +.. code-block:: console + + # For Altera USB-Blaster permissions. + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6010",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6810",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + +You can test connectivity with the SDK jtagconfig tool, you should see something +like: + +.. code-block:: console + + $ jtagconfig + 1) USB-BlasterII [1-1.2] + 031050DD 10M50DA(.|ES)/10M50DC + 020D10DD VTAP10 + + +Reference CPU +============= + +A reference CPU design of a Nios II/f core is included in the Zephyr tree +in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory. + +Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA +configuration file +:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`: + +.. code-block:: console + + $ nios2-configure-sof ghrd_10m50da.sof + +This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. +For any Nios II SOC definition, you can find out more details about the CPU +configuration by inspecting system.h in the SOC's include directory. + +Console Output +============== + +16550 UART +---------- + +By default, the kernel is configured to send console output to the 16550 UART. +You can monitor this on your workstation by connecting to the top right mini USB +port on the board (it will show up in /dev as a ttyUSB node), and then running +minicom with flow control disabled, 115200-8N1 settings. + +JTAG UART +--------- + +You can also have it send its console output to the JTAG UART. +Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: + +.. code-block:: devicetree + + &jtag_uart { + status = "okay"; + current-speed = <115200>; + }; + +To view these messages on your local workstation, run the terminal application +in the SDK: + +.. code-block:: console + + $ nios2-terminal + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Flashing Kernel into UFM +------------------------ + +The usual ``flash`` target will work with the ``altera_max10`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +This provisions the Zephyr kernel and the CPU configuration onto the board, +using the scripts/support/quartus-flash.py script. After it completes the kernel +will immediately boot. + + +Flashing Kernel directly into RAM over JTAG +------------------------------------------- + +The SDK included the nios2-download tool which will let you flash a kernel +directly into RAM and then boot it from the __start symbol. + +In order for this to work, your entire kernel must be located in RAM. Make sure +the following config options are disabled: + +.. code-block:: cfg + + CONFIG_XIP=n + CONFIG_INCLUDE_RESET_VECTOR=n + +Then, after building your kernel, push it into device's RAM by running +this from the build directory: + +.. code-block:: console + + $ nios2-download --go zephyr/zephyr.elf + +If you have a console session running (either minicom or nios2-terminal) you +should see the application's output. There are additional arguments you can pass +to nios2-download so that it spawns a GDB server that you can connect to, +although it's typically simpler to just use nios2-gdb-server as described below. + +Debugging +========= + +The Altera SDK includes a GDB server which can be used to debug a MAX10 board. +You can either debug a running image that was flashed onto the device in User +Flash Memory (UFM), or load an image over the JTAG using GDB. + +Debugging With UFM Flashed Image +-------------------------------- + +You can debug an application in the usual way. Here is an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: debug + +You will see output similar to the following: + +.. code-block:: console + + Nios II GDB server running on port 3335 + Ignoring --stop option because --tcpport also specified + GNU gdb (GDB) 7.11.0.20160511-git + Copyright (C) 2016 Free Software Foundation, Inc. + License GPLv3+: GNU GPL version 3 or later + This is free software: you are free to change and redistribute it. + There is NO WARRANTY, to the extent permitted by law. Type "show copying" + and "show warranty" for details. + This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". + Type "show configuration" for configuration details. + For bug reporting instructions, please see: + . + Find the GDB manual and other documentation resources online at: + . + For help, type "help". + Type "apropos word" to search for commands related to "word"... + Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. + Remote debugging using :3335 + Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 + Resetting and pausing target processor: OK + Listening on port 3335 for connection from GDB: accepted + isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 + 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); + (gdb) b z_prep_c + Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. + (gdb) b z_cstart + Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. + (gdb) c + Continuing. + + Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 + 348 { + (gdb) + +To start debugging manually: + + +.. code-block:: console + + nios2-gdb-server --tcpport 1234 --stop --reset-target + +And then connect with GDB from the build directory: + + +.. code-block:: console + + nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" + +Debugging With JTAG Flashed Image +--------------------------------- + +In order for this to work, execute-in-place must be disabled, since the GDB +'load' command can only put text and data in RAM. Ensure this is in your +configuration: + +.. code-block:: cfg + + CONFIG_XIP=n + +It is OK for this procedure to leave the reset vector enabled, unlike +nios2-download (which errors out if it finds sections outside of SRAM) it will +be ignored. + +In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if +any) is on the device, but you should have at least flashed a CPU using +nios2-configure-sof. You can leave this process running. + +.. code-block:: console + + $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target + +Build your Zephyr kernel, and load it into a GDB built for Nios II (included in +the Zephyr SDK) from the build directory: + +.. code-block:: console + + $ nios2-poky-elf-gdb zephyr/zephyr.elf + +Then connect to the GDB server: + +.. code-block:: console + + (gdb) target remote :1234 + +And then load the kernel image over the wire. The CPU will not start from the +reset vector, instead it will boot from the __start symbol: + + +.. code-block:: console + + (gdb) load + Loading section reset, size 0xc lma 0x0 + Loading section exceptions, size 0x1b0 lma 0x400020 + Loading section text, size 0x8df0 lma 0x4001d0 + Loading section devconfig, size 0x30 lma 0x408fc0 + Loading section rodata, size 0x3f4 lma 0x408ff0 + Loading section datas, size 0x888 lma 0x4093e4 + Loading section initlevel, size 0x30 lma 0x409c6c + Loading section _k_task_list, size 0x58 lma 0x409c9c + Loading section _k_task_ptr, size 0x8 lma 0x409cf4 + Loading section _k_event_list, size 0x10 lma 0x409cfc + Start address 0x408f54, load size 40184 + Transfer rate: 417 KB/sec, 368 bytes/write. + After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. + + + +References +********** + +* `CPU Documentation `_ +* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ +* `Embedded Peripherals IP User Guide `_ +* `MAX 10 FPGA Configuration User Guide `_ +* `MAX 10 FPGA Development Kit User Guide `_ +* `Nios II Command-Line Tools `_ +* `Quartus II Scripting Reference Manual `_ + + +.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index ed7a0494a70af..b6cf18bc1c6ad 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -30,6 +30,7 @@ sw1 = &button1; bootloader-led0 = &led0; mcuboot-led0 = &led0; + rtc = &rtc0; }; leds { @@ -144,7 +145,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "disabled"; + status = "okay"; }; }; @@ -155,16 +156,44 @@ clock-frequency = ; scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "disabled"; + status = "okay"; }; }; &counter0 { - status = "disabled"; + status = "okay"; +}; + +&counter1 { + status = "okay"; +}; + +&counter2 { + status = "okay"; +}; + +&counter3 { + status = "okay"; +}; + +&counter4 { + status = "okay"; +}; + +&counter5 { + status = "okay"; +}; + +&counter6 { + status = "okay"; +}; + +&counter7 { + status = "okay"; }; &rtc0 { - status = "disabled"; + status = "okay"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index 8b3371389741d..a40767bd37118 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -26,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; }; leds { @@ -122,7 +123,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "disabled"; + status = "okay"; }; }; @@ -133,16 +134,44 @@ clock-frequency = ; scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "disabled"; + status = "okay"; }; }; &counter0 { - status = "disabled"; + status = "okay"; +}; + +&counter1 { + status = "okay"; +}; + +&counter2 { + status = "okay"; +}; + +&counter3 { + status = "okay"; +}; + +&counter4 { + status = "okay"; +}; + +&counter5 { + status = "okay"; +}; + +&counter6 { + status = "okay"; +}; + +&counter7 { + status = "okay"; }; &rtc0 { - status = "disabled"; + status = "okay"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index f33e454272e20..a4e8fdd6b439c 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -26,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; }; leds { @@ -76,11 +77,11 @@ }; &counter0 { - status = "disabled"; + status = "okay"; }; &rtc0 { - status = "disabled"; + status = "okay"; clock = "XTAL"; }; @@ -95,7 +96,7 @@ clock-frequency = ; scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "disabled"; + status = "okay"; }; }; @@ -105,7 +106,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "disabled"; + status = "okay"; }; }; @@ -120,7 +121,7 @@ &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &flash0 { diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index 567ec2143fe91..cdac604591c0e 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -25,6 +25,8 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; + sdhc0 = &sdio0; }; leds { @@ -77,15 +79,15 @@ &adc0 { pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &counter0 { - status = "disabled"; + status = "okay"; }; &rtc0 { - status = "disabled"; + status = "okay"; clock = "XTAL"; }; @@ -100,7 +102,7 @@ clock-frequency = ; scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "disabled"; + status = "okay"; }; }; @@ -110,26 +112,26 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = <1000000>; - status = "disabled"; + status = "okay"; }; }; &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &mspi1 { pinctrl-0 = <&mspi1_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &mspi2 { pinctrl-0 = <&mspi2_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &flash0 { @@ -158,11 +160,11 @@ pinctrl-names = "default"; txdelay = <0>; rxdelay = <0>; - status = "disabled"; + status = "okay"; mmc { compatible = "zephyr,mmc-disk"; disk-name = "SD2"; - status = "disabled"; + status = "okay"; }; }; diff --git a/boards/ambiq/apollo510_evb/Kconfig.defconfig b/boards/ambiq/apollo510_evb/Kconfig.defconfig index 8fd84d081a08f..9f9c9b2a196e4 100644 --- a/boards/ambiq/apollo510_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo510_evb/Kconfig.defconfig @@ -12,11 +12,4 @@ config LOG_BACKEND_SWO_FREQ_HZ default 1000000 depends on LOG_BACKEND_SWO -if MSPI - -config MSPI_INIT_PRIORITY - default 40 - -endif # MSPI - endif # BOARD_APOLLO510_EVB diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi index 2f1472fc061ed..3f173b61a03bc 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi @@ -11,256 +11,14 @@ group1 { pinmux = ; }; - group2 { pinmux = ; input-enable; }; }; - swo_default: swo_default { group0 { pinmux = ; }; }; - - adc0_default: adc0_default{ - group1 { - pinmux = , ; - drive-strength = "0.1"; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c2_default: i2c2_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c3_default: i2c3_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c5_default: i2c5_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c6_default: i2c6_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - i2c7_default: i2c7_default { - group1 { - pinmux = , ; - drive-open-drain; - drive-strength = "0.5"; - bias-pull-up; - }; - }; - - spid0_default: spid0_default { - group1 { - pinmux = , , , ; - }; - }; - - spi0_default: spi0_default { - group1 { - pinmux = , , ; - }; - }; - - spi1_default: spi1_default { - group1 { - pinmux = , , ; - }; - }; - - spi2_default: spi2_default { - group1 { - pinmux = , , ; - }; - }; - - spi3_default: spi3_default { - group1 { - pinmux = , , ; - }; - }; - - spi4_default: spi4_default { - group1 { - pinmux = , , ; - }; - }; - - spi5_default: spi5_default { - group1 { - pinmux = , , ; - }; - }; - - spi6_default: spi6_default { - group1 { - pinmux = , , ; - }; - }; - - spi7_default: spi7_default { - group1 { - pinmux = , , ; - }; - }; - - mspi0_default: mspi0_default { - group0 { - pinmux = , - , - ; - drive-strength = "0.5"; - }; - - group1 { - pinmux = ; - drive-strength = "0.75"; - }; - }; - - mspi1_default: mspi1_default { - group0 { - pinmux = , - , - , - ; - drive-strength = "0.5"; - }; - }; - - mspi0_sleep: mspi0_sleep { - group1 { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - mspi1_sleep: mspi1_sleep { - group1 { - pinmux = , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - mspi0_psram: mspi0_psram { - group0 { - pinmux = , /* D0 */ - , /* D1 */ - , /* D2 */ - , /* D3 */ - , /* D4 */ - , /* D5 */ - , /* D6 */ - , /* D7 */ - , /* DQS0 */ - , /* D8 */ - , /* D9 */ - , /* D10 */ - , /* D11 */ - , /* D12 */ - , /* D13 */ - , /* D14 */ - , /* D15 */ - , /* DQS1 */ - ; /* CE0 */ - drive-strength = "0.5"; - }; - - group1 { - pinmux = ; /* SCK */ - drive-strength = "0.75"; - }; - }; - - mspi1_flash: mspi1_flash { - group0 { - pinmux = , - , - , - , - , - , - , - , - , - ; - drive-strength = "1.0"; - }; - - group1 { - pinmux = ; - drive-strength = "0.5"; - }; - }; }; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts index 4d4b898629c7a..2303e43e1259b 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.dts +++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts @@ -43,17 +43,14 @@ leds { compatible = "gpio-leds"; - led0: led_0 { gpios = <&gpio160_191 5 GPIO_ACTIVE_LOW>; label = "LED 0"; }; - led1: led_1 { gpios = <&gpio64_95 25 GPIO_ACTIVE_LOW>; label = "LED 1"; }; - led2: led_2 { gpios = <&gpio64_95 28 GPIO_ACTIVE_LOW>; label = "LED 2"; @@ -63,14 +60,12 @@ buttons { compatible = "gpio-keys"; polling-mode; - button0: button_0 { gpios = <&gpio64_95 29 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN0"; zephyr,code = ; status = "okay"; }; - button1: button_1 { gpios = <&gpio64_95 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN1"; @@ -89,21 +84,6 @@ pinctrl-names = "default"; }; -&adc0 { - pinctrl-0 = <&adc0_default>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&counter0 { - status = "disabled"; -}; - -&rtc0 { - status = "disabled"; - clock = "XTAL"; -}; - &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.yaml b/boards/ambiq/apollo510_evb/apollo510_evb.yaml index ca2353540b486..704c2c00208a4 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.yaml +++ b/boards/ambiq/apollo510_evb/apollo510_evb.yaml @@ -9,16 +9,9 @@ toolchain: - gnuarmemb supported: - uart - - adc - watchdog - - counter - gpio - - spi - - i2c - - rtc - - hwinfo - clock_control - - mspi testing: ignore_tags: - net diff --git a/boards/amd/versal2_rpu/CMakeLists.txt b/boards/amd/versal2_rpu/CMakeLists.txt deleted file mode 100644 index bd0a687ea487e..0000000000000 --- a/boards/amd/versal2_rpu/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2025 Advanced Micro Devices, Inc. -# - -find_package(Dtc 1.4.6 REQUIRED) - -# Check if the board-specific qemu.dts file exists -if(EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts") - # Ensure DTC executable is available - if(DTC_FOUND) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${DTC} -I dts -O dtb -q "${BOARD_DIR}/${BOARD}-qemu.dts" -o "${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb" - ) - else() - message(FATAL_ERROR "DTC not found, but required for compiling ${BOARD}-qemu.dts") - endif() -endif() diff --git a/boards/amd/versal2_rpu/Kconfig.versal2_rpu b/boards/amd/versal2_rpu/Kconfig.versal2_rpu deleted file mode 100644 index 8317003f3ff38..0000000000000 --- a/boards/amd/versal2_rpu/Kconfig.versal2_rpu +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2025 Advanced Micro Devices, Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_VERSAL2_RPU - select SOC_AMD_VERSAL2_RPU diff --git a/boards/amd/versal2_rpu/board.cmake b/boards/amd/versal2_rpu/board.cmake deleted file mode 100644 index c03f2a1a98e63..0000000000000 --- a/boards/amd/versal2_rpu/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2025 Advanced Micro Devices, Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH xilinx-aarch64) -set(QEMU_CPU_TYPE_${ARCH} cortex-a78ae) - -set(QEMU_FLAGS_${ARCH} - -machine arm-generic-fdt - -hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb - -device loader,addr=0xEB5E0310,data=0x2,data-len=4 - -nographic - -m 2g -) - -set(QEMU_KERNEL_OPTION - -device loader,cpu-num=8,file=\$ -) diff --git a/boards/amd/versal2_rpu/board.yml b/boards/amd/versal2_rpu/board.yml deleted file mode 100644 index 744fc6acdd586..0000000000000 --- a/boards/amd/versal2_rpu/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: versal2_rpu - full_name: Versal 2 RPU development board - vendor: amd - socs: - - name: amd_versal2_rpu diff --git a/boards/amd/versal2_rpu/doc/index.rst b/boards/amd/versal2_rpu/doc/index.rst deleted file mode 100644 index 44e4b707e051d..0000000000000 --- a/boards/amd/versal2_rpu/doc/index.rst +++ /dev/null @@ -1,73 +0,0 @@ -.. zephyr:board:: versal2_rpu - -Overview -******** -This configuration provides support for the RPU(R52), real-time processing unit on Xilinx -Versal2 SOC, it can operate as following: - -* Two independent R52 cores with their own TCMs (tightly coupled memories) -* Or as a single dual lock step unit with the TCM. - -This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices: - -* ARM GIC v3 Interrupt Controller -* Global Timer Counter -* SBSA UART - -Hardware -******** -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Devices -======== -System Timer ------------- - -This board configuration uses a system timer tick frequency of 100 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -on-chip UART0. - -Memories --------- - -Although Flash, DDR and OCM memory regions are defined in the DTS file, -all the code plus data of the application will be loaded in the sram0 region, -which points to the DDR memory. The ocm0 memory area is currently available -for usage, although nothing is placed there by default. - -Known Problems or Limitations -============================== - -The following platform features are unsupported: - -* Only the first core of the R52 subsystem is supported. - -Programming and Debugging -************************* - -Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: versal2_rpu - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! versal2_rpu/amd_versal2_rpu - - -References -********** - -1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520) -2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en) diff --git a/boards/amd/versal2_rpu/support/xsdb.cfg b/boards/amd/versal2_rpu/support/xsdb.cfg deleted file mode 100644 index 88313923170d5..0000000000000 --- a/boards/amd/versal2_rpu/support/xsdb.cfg +++ /dev/null @@ -1,78 +0,0 @@ -# Copyright (c) 2025 Advanced Micro Devices, Inc. -# -# SPDX-License-Identifier: Apache-2.0 - -proc rpu0_core0_rst { {mem "default"} } { - targets -set -filter {name =~ "DAP*"} - #CRL write protect - mwr -force 0xeb5e001c 0x0 - mwr -force 0xEB580000 1 - mwr -force 0xbbf20000 0xeafffffe - # write BASE_HI and BASE_LO - if {$mem eq "ddr"} { - set addr 0x100000 - } elseif {$mem eq "tcm"} { - set addr 0x0 - } elseif {$mem eq "default"} { - set addr 0xbbf20000 - } - mwr -force 0xEB588008 $addr - # write TCMBOOT as one - mask_write 0xEB588000 0x10 0x10 - # reset CORE0A_RESET out of reset A_TOPRESET and CORE0A_POR - mask_write 0xEB5E0310 0x10101 0x1 - # out of reset CORE0A_RESET - mask_write 0xEB5E0310 0x1 0x0 - targets -set -filter {name =~ "Cortex-R52*0" && parent =~ "*0x00100000"} - after 300 - stop - after 1000 - ta -} - - -proc load_image args { - set elf_file [lindex $args 0] - - if { [info exists ::env(HW_SERVER_URL)] } { - connect -url $::env(HW_SERVER_URL) - } else { - connect - } - - if { [info exists ::env(PDI_FILE_PATH)] } { - device program $::env(PDI_FILE_PATH) - } else { - puts "Error: env variable PDI_FILE_PATH is not set" - exit - } - - if { [info exists ::env(HW_SERVER_URL)] } { - set hw_server_url [split $::env(HW_SERVER_URL) ":"] - set host [lindex $hw_server_url 0] - set port [lindex $hw_server_url 1] - disconnect - after 2000 - connect -host $host -port $port - after 3000 - ta - } - after 1000 - targets -set -nocase -filter {name =~ "DAP*"} - after 100 - # Configure timestamp generator to run global timer gracefully - # Ideally these registers should be set from bootloader (cdo) - - mwr -force 0xea470020 100000000 - mwr -force 0xea470000 0x1 - after 100 - - rpu0_core0_rst - - after 100 - dow -force $elf_file - con - exit -} - -load_image {*}$argv diff --git a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts deleted file mode 100644 index f888f1a17c5c0..0000000000000 --- a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts +++ /dev/null @@ -1,7832 +0,0 @@ -/dts-v1/; - -/ { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - - pmc_ppu0_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x248>; - phandle = <0x108>; - }; - - pmc_ppu1_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x249>; - phandle = <0x109>; - }; - - psm_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x238>; - phandle = <0x10a>; - }; - - ddrmc_ub0_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x00>; - phandle = <0x10b>; - }; - - ddrmc_ub1_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x00>; - phandle = <0x10c>; - }; - - pmc_dma0_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x24a>; - phandle = <0x8b>; - }; - - pmc_dma1_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x24b>; - phandle = <0x8c>; - }; - - pmc_qspi_dma_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x244>; - phandle = <0x7d>; - }; - - pmc_qspi_dma_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x244>; - phandle = <0x7b>; - }; - - apu0_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x260>; - phandle = <0xd3>; - }; - - apu0_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x260>; - phandle = <0xd4>; - }; - - apu1_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x261>; - phandle = <0xd5>; - }; - - apu1_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x261>; - phandle = <0xd6>; - }; - - rpu0_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x200>; - phandle = <0xe4>; - }; - - rpu1_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x204>; - phandle = <0xe7>; - }; - - gem0_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x234>; - phandle = <0x18>; - }; - - gem0_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x234>; - phandle = <0x19>; - }; - - gem1_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x235>; - phandle = <0x1d>; - }; - - gem1_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x235>; - phandle = <0x1e>; - }; - - ospi_dma_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x245>; - phandle = <0x81>; - }; - - ospi_dma_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x245>; - phandle = <0x7c>; - }; - - sd0_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x242>; - phandle = <0x77>; - }; - - sd0_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x242>; - phandle = <0x78>; - }; - - sd1_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x243>; - phandle = <0x79>; - }; - - sd1_w_ma_smid { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x243>; - phandle = <0x7a>; - }; - - usb0_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x230>; - phandle = <0x20>; - }; - - amba_root@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - #interrupt-cells = <0x01>; - interrupt-map-mask = <0x00 0x00 0xffff>; - interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x01 -0x04 0x00 0x00 0x02 0x01 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x03 0x04 0x00 0x00 0x04 0x01 -0x00 0x04 0x04 0x00 0x00 0x05 0x01 0x00 0x05 0x04 0x00 0x00 0x06 0x01 0x00 0x06 0x04 0x00 -0x00 0x07 0x01 0x00 0x07 0x04 0x00 0x00 0x08 0x01 0x00 0x08 0x04 0x00 0x00 0x09 0x01 0x00 -0x09 0x04 0x00 0x00 0x0a 0x01 0x00 0x0a 0x04 0x00 0x00 0x0b 0x01 0x00 0x0b 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0x04 0x00 0x00 -0xfc 0x07 0x00 0xfc 0x04 0x00 0x00 0xfd 0x07 0x00 0xfd 0x04 0x00 0x00 0xfe 0x07 0x00 0xfe -0x04 0x00 0x00 0xff 0x07 0x00 0xff 0x04 0x00 0x00 0xa0 0x07 0x00 0xa0 0x04 0x00 0x00 0xbca -0x08 0x12 0x00 0x00 0xbd4 0x08 0x1c 0x00 0x00 0xbd5 0x08 0x1d 0x00 0x00 0xfbc 0x09 0x1c>; - phandle = <0x10d>; - - amba@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x0d>; - - downstream_amba_lpd { - compatible = "qemu:memory-region"; - alias = <0x0a>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_fpd { - compatible = "qemu:memory-region"; - alias = <0x0b>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_internal { - compatible = "qemu:memory-region"; - alias = <0x0c>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - xmpu_ocm@0 { - compatible = "xlnx,versal-xmpu"; - interrupts = <0x10>; - reg-extended = <0x0d 0x00 0xeb400000 0x00 0x10000 0x00 0x0d 0x00 -0xbbf00000 0x00 0x80000 0x02>; - protected-mr = <0x0e>; - mr-0 = <0x0d>; - protected-base = <0xbbf00000>; - phandle = <0x10e>; - }; - - xmpu_ocm2@0 { - compatible = "xlnx,versal-xmpu"; - interrupts = <0x10>; - reg-extended = <0x0d 0x00 0xeb9e0000 0x00 0x10000 0x00 0x0d 0x00 -0xbbe00000 0x00 0x80000 0x00>; - protected-mr = <0x0e>; - mr-0 = <0x0d>; - protected-base = <0xbbe00000>; - phandle = <0x10f>; - }; - - loader_write_cpu0_0x1@0xF1110880 { - compatible = "loader"; - addr = <0xf1110880>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x110>; - }; - - loader_write_cpu0_0x5@0xFD1A0050 { - compatible = "loader"; - addr = <0xfd1a0050>; - data = <0x05>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x111>; - }; - - loader_write_cpu0_0xFF@0xF111010C { - compatible = "loader"; - addr = <0xf111010c>; - data = <0xff>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x112>; - }; - - s_axi_tcm_a@0 { - compatible = "qemu:memory-region"; - alias = <0x0f>; - reg = <0x00 0xeba00000 0x00 0x800000 0x00>; - phandle = <0x34>; - }; - - s_axi_tcm_b@0 { - compatible = "qemu:memory-region"; - alias = <0x10>; - reg = <0x00 0xeba80000 0x00 0x800000 0x00>; - phandle = <0x38>; - }; - - s_axi_tcm_c@0 { - compatible = "qemu:memory-region"; - alias = <0x11>; - reg = <0x00 0xebb00000 0x00 0x800000 0x00>; - phandle = <0x3c>; - }; - - s_axi_tcm_d@0 { - compatible = "qemu:memory-region"; - alias = <0x12>; - reg = <0x00 0xebb80000 0x00 0x800000 0x00>; - phandle = <0x40>; - }; - - s_axi_tcm_e@0 { - compatible = "qemu:memory-region"; - alias = <0x13>; - reg = <0x00 0xebc00000 0x00 0x800000 0x00>; - phandle = <0x44>; - }; - - loader_write_cpu0_0x80C@0xF12B0100 { - compatible = "loader"; - addr = <0xf12b0100>; - data = <0x80c>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x113>; - }; - - loader_write_cpu0_0x77@0xF1260320 { - compatible = "loader"; - addr = <0xf1260320>; - data = <0x77>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x114>; - }; - - xmpu_ocm1@0 { - compatible = "xlnx,versal-xmpu"; - interrupts = <0x10>; - reg-extended = <0x0d 0x00 0xeb980000 0x00 0x10000 0x00 0x0d 0x00 -0xbbf80000 0x00 0x80000 0x00>; - protected-mr = <0x0e>; - mr-0 = <0x0d>; - protected-base = <0xbbf80000>; - phandle = <0x115>; - }; - - xmpu_ocm3@0 { - compatible = "xlnx,versal-xmpu"; - interrupts = <0x10>; - reg-extended = <0x0d 0x00 0xeaa10000 0x00 0x10000 0x00 0x0d 0x00 -0xbbe80000 0x00 0x80000 0x00>; - protected-mr = <0x0e>; - mr-0 = <0x0d>; - protected-base = <0xbbe80000>; - phandle = <0x116>; - }; - }; - - amba_lpd@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x0a>; - - downstream_amba_psm { - compatible = "qemu:memory-region"; - alias = <0x14>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_xram { - compatible = "qemu:memory-region"; - alias = <0x15>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - xppu_lpd@0xeb990000 { - compatible = "xlnx,versal-xppu"; - reg-extended = <0x0a 0x00 0xeb990000 0x00 0x10000 0x00 0x16 0x00 -0xeb000000 0x00 0x1000000 0x02 0x16 0x00 0xea000000 0x00 0x1000000 0x02>; - mr = <0x0a>; - interrupts = <0x13>; - phandle = <0x117>; - }; - - ethernet@0xf1a60000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - #priority-cells = <0x00>; - compatible = "cdns,gem"; - interrupts = <0x27 0x27>; - dma = <0x17>; - memattr = <0x18>; - memattr-write = <0x19>; - reg = <0x00 0xf1a60000 0x00 0x10000 0x00>; - num-priority-queues = <0x02>; - reset-gpios = <0x1a 0x01>; - power-gpios = <0x1b 0x2c>; - mdio = <0x1c>; - phandle = <0x118>; - }; - - ethernet@0xf1a70000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - #priority-cells = <0x00>; - compatible = "cdns,gem"; - interrupts = <0x29 0x29>; - dma = <0x17>; - memattr = <0x1d>; - memattr-write = <0x1e>; - reg = <0x00 0xf1a70000 0x00 0x10000 0x00>; - num-priority-queues = <0x02>; - reset-gpios = <0x1a 0x02>; - power-gpios = <0x1b 0x2d>; - mdio = <0x1c>; - phandle = <0x119>; - }; - - serial@0xf1920000 { - compatible = "pl011"; - interrupts = <0x19>; - reg = <0x00 0xf1920000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x05>; - chardev = "serial2"; - phandle = <0x11a>; - }; - - serial@0xf1930000 { - compatible = "pl011"; - interrupts = <0x1a>; - reg = <0x00 0xf1930000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x06>; - chardev = "con"; - phandle = <0x11b>; - }; - - canfdbus@0 { - compatible = "can-bus"; - phandle = <0x1f>; - }; - - can@0xf19e0000 { - compatible = "xlnx,versal-canfd"; - rx-fifo0 = <0x40>; - rx-fifo1 = <0x40>; - enable-rx-fifo1 = <0x01>; - canfdbus = <0x1f>; - interrupts = <0x1b>; - reg = <0x00 0xf19e0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x09>; - phandle = <0x11c>; - }; - - can@0xf19f0000 { - compatible = "xlnx,versal-canfd"; - rx-fifo0 = <0x40>; - rx-fifo1 = <0x40>; - enable-rx-fifo1 = <0x01>; - canfdbus = <0x1f>; - interrupts = <0x1c>; - reg = <0x00 0xf19f0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x0a>; - phandle = <0x11d>; - }; - - crl@0xeb5e0000 { - compatible = "xlnx,psxc_crl"; - reg = <0x00 0xeb5e0000 0x00 0x300000 0x00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1a>; - }; - - slcr@0xf1a20000 { - compatible = "xlnx,versal-lpd-iou-slcr"; - reg = <0x00 0xf1a20000 0x00 0x20000 0x00>; - phandle = <0x11e>; - }; - - ipi@0xeb300000 { - compatible = "xlnx,versal-ipi"; - reg = <0x00 0xeb300000 0x00 0x100000 0x00>; - interrupts = <0xfbc 0xbd4 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0xbd5 -0x46 0x40 0x41 0x42 0x43 0x44 0x45>; - reset-gpios = <0x1a 0x19>; - num-master-ids = <0x20>; - phandle = <0x11f>; - }; - - spi@0xf19c0000 { - compatible = "cdns,spi-r1p6"; - interrupts = <0x17>; - num-ss-bits = <0x04>; - reg = <0x00 0xf19c0000 0x00 0x10000 0x00>; - #address-cells = <0x01>; - #size-cells = <0x00>; - #bus-cells = <0x01>; - reset-gpios = <0x1a 0x07>; - phandle = <0x120>; - - spi0_flash0@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25p80\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x00 0x00>; - blockdev-node-name = "spi0_flash0"; - phandle = <0x121>; - - spi0_flash0@0x00000000 { - label = "spi0_flash0"; - reg = <0x00 0x100000>; - }; - }; - }; - - spi@0xf19d0000 { - compatible = "cdns,spi-r1p6"; - interrupts = <0x18>; - num-ss-bits = <0x04>; - reg = <0x00 0xf19d0000 0x00 0x10000 0x00>; - #address-cells = <0x01>; - #size-cells = <0x00>; - #bus-cells = <0x01>; - reset-gpios = <0x1a 0x08>; - phandle = <0x122>; - - spi1_flash0@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25p80\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x00 0x00>; - blockdev-node-name = "spi1_flash0"; - phandle = <0x123>; - - spi1_flash0@0x00000000 { - label = "spi1_flash0"; - reg = <0x00 0x100000>; - }; - }; - }; - - usb2@USB2_0_XHCI { - compatible = "usb_dwc3"; - reg = <0x00 0xf1b0c100 0x00 0x600 0x00 0x00 0xf1b00000 0x00 -0x100000 0x00>; - interrupts = <0x1d 0x1e 0x1f 0x20>; - dma = <0x17>; - memattr = <0x20>; - reset-gpios = <0x1a 0x03>; - intrs = <0x04>; - slots = <0x02>; - phandle = <0x124>; - }; - - timer@0xf1e60000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x2b 0x2b 0x2b>; - reg = <0x00 0xf1e60000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x12>; - phandle = <0x125>; - }; - - timer@0xf1e70000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x2c 0x2c 0x2c>; - reg = <0x00 0xf1e70000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x13>; - phandle = <0x126>; - }; - - timer@0xf1e80000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x2d 0x2d 0x2d>; - reg = <0x00 0xf1e80000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x14>; - phandle = <0x127>; - }; - - timer@0xf1e90000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x2e 0x2e 0x2e>; - reg = <0x00 0xf1e90000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x15>; - phandle = <0x128>; - }; - - adma0mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x210>; - phandle = <0x21>; - }; - - dma-controller@0xebd00000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd00000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x48>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x21>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x00>; - phandle = <0x129>; - }; - - adma1mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x212>; - phandle = <0x23>; - }; - - dma-controller@0xebd10000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd10000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x49>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x23>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x01>; - phandle = <0x12a>; - }; - - adma2mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x214>; - phandle = <0x24>; - }; - - dma-controller@0xebd20000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd20000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4a>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x24>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x02>; - phandle = <0x12b>; - }; - - adma3mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x216>; - phandle = <0x25>; - }; - - dma-controller@0xebd30000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd30000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4b>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x25>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x03>; - phandle = <0x12c>; - }; - - adma4mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x218>; - phandle = <0x26>; - }; - - dma-controller@0xebd40000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd40000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4c>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x26>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x04>; - phandle = <0x12d>; - }; - - adma5mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x21a>; - phandle = <0x27>; - }; - - dma-controller@0xebd50000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd50000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4d>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x27>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x05>; - phandle = <0x12e>; - }; - - adma6mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x21c>; - phandle = <0x28>; - }; - - dma-controller@0xebd60000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd60000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4e>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x28>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x06>; - phandle = <0x12f>; - }; - - adma7mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x21e>; - phandle = <0x29>; - }; - - dma-controller@0xebd70000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd70000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x4f>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x29>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x07>; - phandle = <0x130>; - }; - - afi_fm@0xeb9b0000 { - compatible = "xlnx,versal-afi-fm"; - reg = <0x00 0xeb9b0000 0x00 0x10000 0x00>; - }; - - lpd_i2c_wrapper { - - ps_i2c@0xf1940000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x15>; - reg-extended = <0x0a 0x00 0xf1940000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x0b>; - phandle = <0x131>; - }; - - ps_i2c@0xf1950000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x16>; - reg-extended = <0x0a 0x00 0xf1950000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x0c>; - phandle = <0x132>; - }; - - ps_i2c@0xf1960000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x0b>; - reg-extended = <0x0a 0x00 0xf1960000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x30>; - phandle = <0x133>; - }; - - ps_i2c@0xf1970000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x0c>; - reg-extended = <0x0a 0x00 0xf1970000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x31>; - phandle = <0x134>; - }; - - ps_i2c@0xf1980000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x0d>; - reg-extended = <0x0a 0x00 0xf1980000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x32>; - phandle = <0x135>; - }; - - ps_i2c@0xf1990000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x64>; - reg-extended = <0x0a 0x00 0xf1990000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x33>; - phandle = <0x136>; - }; - - ps_i2c@0xf19a0000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x65>; - reg-extended = <0x0a 0x00 0xf19a0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x34>; - phandle = <0x137>; - }; - - ps_i2c@0xf19b0000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0x66>; - reg-extended = <0x0a 0x00 0xf19b0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x35>; - phandle = <0x138>; - }; - }; - - ocm_ctrl@OCM { - compatible = "xlnx,zynqmp-ocmc"; - interrupts = <0x10>; - memsize = <0x80000>; - reg = <0x00 0xeb5d0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x18>; - phandle = <0x139>; - }; - - lpd_slcr@0xeb410000 { - compatible = "xlnx.psxc-lpx-slcr"; - reg = <0x00 0xeb410000 0x00 0x100000 0x00>; - interrupt-parent = <0x08>; - interrupts = <0x1e>; - #gpio-cells = <0x01>; - gpio-controller; - num-rpu = <0x0a>; - core-0 = <0x2a>; - core-1 = <0x2b>; - core-2 = <0x2c>; - core-3 = <0x2d>; - core-4 = <0x2e>; - core-5 = <0x2f>; - core-6 = <0x30>; - core-7 = <0x31>; - core-8 = <0x32>; - core-9 = <0x33>; - phandle = <0x1b>; - }; - - lpd_slcr_secure@0xeb510000 { - compatible = "xlnx.versal2-psxc-lpx-slcr-secure"; - reg = <0x00 0xeb510000 0x00 0x40000 0x00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x22>; - }; - - lpd_iou_slcr_secure@0xf1a40000 { - compatible = "xlnx,versal-lpd-iou-slcr-secure"; - reg = <0x00 0xf1a40000 0x00 0x10000 0x00>; - memattr-gem0 = <0x18>; - memattr-write-gem0 = <0x19>; - memattr-gem1 = <0x1d>; - memattr-write-gem1 = <0x1e>; - phandle = <0x13a>; - }; - - wwdt@0xeb000000 { - compatible = "xlnx,versal-wwdt"; - reg = <0x00 0xeb000000 0x00 0x10000 0x00>; - interrupts = <0xec 0xed 0xee 0xef>; - pclk = <0x5f5e100>; - reset-gpios = <0x1a 0x17>; - phandle = <0x13b>; - }; - - lpd_gpio@0xf1a50000 { - #gpio-cells = <0x01>; - compatible = "xlnx,zynqmp-gpio"; - gpio-controller; - interrupts = <0x14>; - reg = <0x00 0xf1a50000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x11>; - phandle = <0x13c>; - }; - - virtio_mmio_0 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e00000 0x00 0x1000 0x00>; - interrupts = <0x10e>; - }; - - virtio_mmio_1 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e01000 0x00 0x1000 0x00>; - interrupts = <0x10f>; - }; - - virtio_mmio_2 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e02000 0x00 0x1000 0x00>; - interrupts = <0x110>; - }; - - virtio_mmio_3 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e03000 0x00 0x1000 0x00>; - interrupts = <0x111>; - }; - - virtio_mmio_4 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e04000 0x00 0x1000 0x00>; - interrupts = <0x112>; - }; - - virtio_mmio_5 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e05000 0x00 0x1000 0x00>; - interrupts = <0x113>; - }; - - virtio_mmio_6 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e06000 0x00 0x1000 0x00>; - interrupts = <0x114>; - }; - - virtio_mmio_7 { - compatible = "virtio-mmio"; - reg = <0x00 0xf5e07000 0x00 0x1000 0x00>; - interrupts = <0x115>; - }; - - rpu_ctrl@0 { - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x13d>; - }; - - rpu_cluster@0xeb580000 { - compatible = "xlnx,psx_rpu_cluster_2.0"; - reg = <0x00 0xeb580000 0x00 0x8000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - tcm-mr = <0x34>; - phandle = <0x36>; - }; - - rpu_ctrl_a0@0xeb588000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb588000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x23>; - core = <0x2a>; - tcm-mr = <0x35>; - phandle = <0xe5>; - }; - - rpu_ctrl_a1@0xeb58c000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb58c000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x24 0x36 0x00>; - core = <0x2b>; - tcm-mr = <0x37>; - phandle = <0xe8>; - }; - - rpu_cluster@0xeb590000 { - compatible = "xlnx,psx_rpu_cluster_2.0"; - reg = <0x00 0xeb590000 0x00 0x8000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - tcm-mr = <0x38>; - phandle = <0x3a>; - }; - - rpu_ctrl_b0@0xeb598000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb598000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x25>; - core = <0x2c>; - tcm-mr = <0x39>; - phandle = <0xeb>; - }; - - rpu_ctrl_b1@0xeb59c000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb59c000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x26 0x3a 0x00>; - core = <0x2d>; - tcm-mr = <0x3b>; - phandle = <0xee>; - }; - - rpu_cluster@0xeb5a0000 { - compatible = "xlnx,psx_rpu_cluster_2.0"; - reg = <0x00 0xeb5a0000 0x00 0x8000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - tcm-mr = <0x3c>; - phandle = <0x3e>; - }; - - rpu_ctrl_c0@0xeb5a8000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5a8000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x27>; - core = <0x2e>; - tcm-mr = <0x3d>; - phandle = <0xf1>; - }; - - rpu_ctrl_c1@0xeb5ac000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5ac000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x28 0x3e 0x00>; - core = <0x2f>; - tcm-mr = <0x3f>; - phandle = <0xf4>; - }; - - rpu_cluster@0xeb5b0000 { - compatible = "xlnx,psx_rpu_cluster_2.0"; - reg = <0x00 0xeb5b0000 0x00 0x8000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - tcm-mr = <0x40>; - phandle = <0x42>; - }; - - rpu_ctrl_d0@0xeb5b8000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5b8000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x29>; - core = <0x30>; - tcm-mr = <0x41>; - phandle = <0xf7>; - }; - - rpu_ctrl_d1@0xeb5bc000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5bc000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x2a 0x42 0x00>; - core = <0x31>; - tcm-mr = <0x43>; - phandle = <0xfa>; - }; - - rpu_cluster@0xeb5c0000 { - compatible = "xlnx,psx_rpu_cluster_2.0"; - reg = <0x00 0xeb5c0000 0x00 0x8000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - tcm-mr = <0x44>; - phandle = <0x46>; - }; - - rpu_ctrl_e0@0xeb5c8000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5c8000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x2b>; - core = <0x32>; - tcm-mr = <0x45>; - phandle = <0xfd>; - }; - - rpu_ctrl_e1@0xeb5cc000 { - compatible = "xlnx,psxc-rpu-cluster-core"; - version = <0x01>; - reg = <0x00 0xeb5cc000 0x00 0x4000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - gpios = <0x1a 0x2c 0x46 0x00>; - core = <0x33>; - tcm-mr = <0x47>; - phandle = <0x100>; - }; - - usb2@USB2_0_XHCI1 { - compatible = "usb_dwc3"; - reg = <0x00 0xf1c0c100 0x00 0x600 0x00 0x00 0xf1c00000 0x00 -0x100000 0x00>; - interrupts = <0x22 0x23 0x24 0x25>; - dma = <0x17>; - memattr = <0x48>; - reset-gpios = <0x1a 0x04>; - intrs = <0x04>; - slots = <0x02>; - phandle = <0x13e>; - }; - - i3c0@0xf1940000 { - compatible = "dwc.i3c"; - reg = <0x00 0xf1948000 0x00 0x10000 0x00>; - num-devices = <0x0b>; - interrupts = <0x15>; - phandle = <0x13f>; - }; - - i3c1@0xf1950000 { - compatible = "dwc.i3c"; - reg = <0x00 0xf1958000 0x00 0x10000 0x00>; - slave-static-addr-en = <0x01>; - device-id = <0x01>; - interrupts = <0x16>; - phandle = <0x140>; - }; - - ocm_ctrl@0xeb960000 { - compatible = "xlnx,zynqmp-ocmc"; - interrupts = <0x11>; - memsize = <0x80000>; - reg = <0x00 0xeb960000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0xf1>; - phandle = <0x141>; - }; - - ocm_ctrl@0xeb9d0000 { - compatible = "xlnx,zynqmp-ocmc"; - interrupts = <0x0e>; - memsize = <0x80000>; - reg = <0x00 0xeb9d0000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0xf2>; - phandle = <0x142>; - }; - - ocm_ctrl@0xeaa00000 { - compatible = "xlnx,zynqmp-ocmc"; - interrupts = <0x0f>; - memsize = <0x80000>; - reg = <0x00 0xeaa00000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0xf3>; - phandle = <0x143>; - }; - - can@0xf1a00000 { - compatible = "xlnx,versal-canfd"; - rx-fifo0 = <0x40>; - rx-fifo1 = <0x40>; - enable-rx-fifo1 = <0x01>; - canfdbus = <0x1f>; - interrupts = <0x5f>; - reg = <0x00 0xf1a00000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x2e>; - phandle = <0x144>; - }; - - can@0xf1a10000 { - compatible = "xlnx,versal-canfd"; - rx-fifo0 = <0x40>; - rx-fifo1 = <0x40>; - enable-rx-fifo1 = <0x01>; - canfdbus = <0x1f>; - interrupts = <0x60>; - reg = <0x00 0xf1a10000 0x00 0x10000 0x00>; - reset-gpios = <0x1a 0x2f>; - phandle = <0x145>; - }; - - timer@0xf1ea0000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x2f 0x2f 0x2f>; - reg = <0x00 0xf1ea0000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x36>; - phandle = <0x146>; - }; - - timer@0xf1eb0000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x30 0x30 0x30>; - reg = <0x00 0xf1eb0000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x37>; - phandle = <0x147>; - }; - - timer@0xf1ec0000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x31 0x31 0x31>; - reg = <0x00 0xf1ec0000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x38>; - phandle = <0x148>; - }; - - timer@0xf1ed0000 { - compatible = "xlnx,ps7-ttc-1.00.a"; - interrupts = <0x32 0x32 0x32>; - reg = <0x00 0xf1ed0000 0x00 0x10000 0x00>; - width = <0x20>; - reset-gpios = <0x1a 0x39>; - phandle = <0x149>; - }; - - sdma0mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x220>; - phandle = <0x49>; - }; - - dma-controller@0xebd80000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd80000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x70>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x49>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x08>; - phandle = <0x14a>; - }; - - sdma1mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x222>; - phandle = <0x4a>; - }; - - dma-controller@0xebd90000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebd90000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x71>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4a>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x09>; - phandle = <0x14b>; - }; - - sdma2mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x224>; - phandle = <0x4b>; - }; - - dma-controller@0xebda0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebda0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x72>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4b>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0a>; - phandle = <0x14c>; - }; - - sdma3mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x226>; - phandle = <0x4c>; - }; - - dma-controller@0xebdb0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebdb0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x73>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4c>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0b>; - phandle = <0x14d>; - }; - - sdma4mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x228>; - phandle = <0x4d>; - }; - - dma-controller@0xebdc0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebdc0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x74>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4d>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0c>; - phandle = <0x14e>; - }; - - sdma5mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x22a>; - phandle = <0x4e>; - }; - - dma-controller@0xebdd0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebdd0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x75>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4e>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0d>; - phandle = <0x14f>; - }; - - sdma6mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x22c>; - phandle = <0x4f>; - }; - - dma-controller@0xebde0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebde0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x76>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x4f>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0e>; - phandle = <0x150>; - }; - - sdma7mattr { - compatible = "qemu:memory-transaction-attr"; - requester-id = <0x22e>; - phandle = <0x50>; - }; - - dma-controller@0xebdf0000 { - compatible = "xlnx,zdma"; - reg = <0x00 0xebdf0000 0x00 0x10000 0x00>; - bus-width = <0x80>; - has-parity = <0x01>; - interrupts = <0x77>; - #stream-id-cells = <0x01>; - dma = <0x17>; - memattr = <0x50>; - reset-gpios = <0x1a 0x00>; - #gpio-cells = <0x01>; - gpio-names = "memattr-secure"; - gpios = <0x22 0x0f>; - phandle = <0x151>; - }; - - wwdt@0xeb010000 { - compatible = "xlnx,versal-wwdt"; - reg = <0x00 0xeb010000 0x00 0x10000 0x00>; - interrupts = <0xf0 0xf1 0xf2 0xf3>; - pclk = <0x5f5e100>; - reset-gpios = <0x1a 0x3a>; - phandle = <0x152>; - }; - - lpd_afi_fs@0xeb560000 { - compatible = "xlnx.psxc_afi_fs"; - reg = <0x00 0xeb560000 0x00 0x8000 0x00>; - phandle = <0x153>; - }; - - downstream_amba_asu { - compatible = "qemu:memory-region"; - alias = <0x51>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - }; - - amba_fpd@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x0b>; - - afi_fm@0xec880000 { - compatible = "xlnx,versal-afi-fm"; - reg = <0x00 0xec880000 0x00 0x10000 0x00>; - }; - - afi_fm@0xec8a0000 { - compatible = "xlnx,versal-afi-fm"; - reg = <0x00 0xec8a0000 0x00 0x10000 0x00>; - }; - - cpm_crcpm@0xfca00000 { - compatible = "xlnx,versal_cpm_crcpm"; - reg = <0x00 0xfca00000 0x00 0x10000 0x00>; - }; - - cpm_pcsr@0xfcff0000 { - compatible = "xlnx,versal_cpm_pcsr"; - reg = <0x00 0xfcff0000 0x00 0x10000 0x00>; - }; - - cpm_slcr_secure@0xfca20000 { - compatible = "xlnx.cpm_slcr_secure"; - reg = <0x00 0xfca20000 0x00 0x10000 0x00>; - }; - - fpd_slcr@0xec8c0000 { - compatible = "xlnx,versal-fpd-slcr"; - interrupts = <0x8c>; - reg = <0x00 0xec8c0000 0x00 0x10000 0x00>; - }; - - fpd_slcr_secure@0xec8c0000 { - compatible = "xlnx,versal-fpd-slcr-secure"; - interrupts = <0x8c>; - reg = <0x00 0xec8e0000 0x00 0x10000 0x00>; - }; - - watchdog@0xecc10000 { - compatible = "xlnx,versal-wwdt"; - reg = <0x00 0xecc10000 0x00 0x10000 0x00>; - interrupts = <0xec 0xed 0xee 0xef>; - pclk = <0x5f5e100>; - reset-gpios = <0x52 0x1b>; - phandle = <0x154>; - }; - - apu_cluster@0xecc00000 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,versal-apu-ctrl"; - reg = <0x00 0xecc00000 0x00 0x10000 0x00>; - cpu0 = <0x53>; - cpu1 = <0x54>; - cpu2 = <0x55>; - cpu3 = <0x55>; - cores-per-cluster = <0x02>; - phandle = <0x155>; - }; - - apu_cluster@0xecd00000 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,versal-apu-ctrl"; - reg = <0x00 0xecd00000 0x00 0x10000 0x00>; - cpu0 = <0x56>; - cpu1 = <0x57>; - cpu2 = <0x55>; - cpu3 = <0x55>; - cores-per-cluster = <0x02>; - phandle = <0x156>; - }; - - apu_cluster@0xece00000 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,versal-apu-ctrl"; - reg = <0x00 0xece00000 0x00 0x10000 0x00>; - cpu0 = <0x58>; - cpu1 = <0x59>; - cpu2 = <0x55>; - cpu3 = <0x55>; - cores-per-cluster = <0x02>; - phandle = <0x157>; - }; - - apu_cluster@0xecf00000 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,versal-apu-ctrl"; - reg = <0x00 0xecf00000 0x00 0x10000 0x00>; - cpu0 = <0x5a>; - cpu1 = <0x5b>; - cpu2 = <0x55>; - cpu3 = <0x55>; - cores-per-cluster = <0x02>; - phandle = <0x158>; - }; - - cmn600ae@0xa0000000 { - compatible = "arm,cmn600ae"; - reg = <0x00 0xa0000000 0x00 0x3000000 0x00>; - }; - - smmuv3@MM_FPD_SMMU { - compatible = "arm-smmuv3"; - reg-extended = <0x0b 0x00 0xec000000 0x00 0x200000 0x00 0x17 0x00 -0x00 0xffffffff 0xffffffff 0x00 0x5c 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5d 0x00 0x00 -0xffffffff 0xffffffff 0x00 0x5e 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5f 0x00 0x00 -0xffffffff 0xffffffff 0x00 0x60 0x00 0x00 0xffffffff 0xffffffff 0x00 0x61 0x00 0x00 -0xffffffff 0xffffffff 0x00 0x62 0x00 0x00 0xffffffff 0xffffffff 0x00 0x63 0x00 0x00 -0xffffffff 0xffffffff 0x00 0x64 0x00 0x00 0xffffffff 0xffffffff 0x00 0x65 0x00 0x00 -0xffffffff 0xffffffff 0x00 0x66 0x00 0x00 0xffffffff 0xffffffff 0x00 0x67 0x00 0x00 -0xffffffff 0xffffffff 0x00>; - mr-0 = <0x0d>; - mr-1 = <0x0d>; - mr-2 = <0x0d>; - mr-3 = <0x0d>; - mr-4 = <0x0d>; - mr-5 = <0x0d>; - mr-6 = <0x0d>; - mr-7 = <0x0d>; - mr-8 = <0x0d>; - mr-9 = <0x0d>; - mr-10 = <0x0d>; - mr-11 = <0x0d>; - mr-12 = <0x0d>; - dma_mr = <0x0d>; - primary-bus = <0x68>; - phandle = <0x159>; - }; - - dummy_pcie@0x6_0000_0000 { - compatible = "PCI"; - phandle = <0x68>; - }; - - apu_pcil@0xecb10000 { - compatible = "xlnx.apu_pcil"; - reg = <0x00 0xecb10000 0x00 0x10000 0x00>; - core-mask = <0x3333>; - cluster-mask = <0x0f>; - gpios = <0x1b 0x52 0x1b 0x53 0x1b 0x54 0x1b 0x55 0x1b 0x56 0x1b 0x57 -0x1b 0x58 0x1b 0x59 0x1b 0x5a 0x1b 0x5b 0x1b 0x5c 0x1b 0x5d 0x1b 0x5e 0x1b 0x5f 0x1b 0x60 0x1b 0x61 -0x1b 0x62 0x1b 0x63 0x1b 0x64 0x1b 0x65 0x1b 0x66 0x1b 0x67 0x1b 0x68 0x1b 0x69>; - core-0 = <0x53>; - core-1 = <0x54>; - core-4 = <0x56>; - core-5 = <0x57>; - core-8 = <0x58>; - core-9 = <0x59>; - core-12 = <0x5a>; - core-13 = <0x5b>; - phandle = <0x15a>; - }; - - lpd_afi_fs@0xec860000 { - compatible = "xlnx.psxc_afi_fs"; - reg = <0x00 0xec860000 0x00 0x8000 0x00>; - phandle = <0x15b>; - }; - - mmi_gem_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x25e>; - phandle = <0x69>; - }; - - mmi_usb_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x20e>; - phandle = <0x6b>; - }; - - amba_mmi@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x6d>; - - mdio_10gbe@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - #priority-cells = <0x00>; - compatible = "mdio"; - phandle = <0x6a>; - - phy@1 { - compatible = "phy-clause45-generic"; - device_type = "ethernet-phy"; - reg = <0x01>; - phandle = <0x15c>; - }; - }; - - ethernet@0xed920000 { - #address-cells = <0x01>; - #size-cells = <0x00>; - #priority-cells = <0x00>; - compatible = "cdns,gem"; - reg = <0x00 0xed920000 0x00 0x10000 0x00>; - interrupts = <0xa4 0xa4 0xa4 0xa4>; - dma = <0x5d>; - memattr = <0x69>; - num-priority-queues = <0x04>; - mdio = <0x6a>; - has-usxgmii = <0x01>; - phandle = <0x15d>; - }; - - usb_drd@0xedec0000 { - compatible = "usb_dwc3"; - reg = <0x00 0xedec0000 0x00 0x10000 0x00>; - interrupts = <0xbf 0xc0>; - dma = <0x5d>; - memattr = <0x6b>; - intrs = <0x02>; - slots = <0x02>; - phandle = <0x15e>; - }; - - mmi_crs@0xedc00000 { - compatible = "xlnx.mmi_crx"; - reg = <0x00 0xedc00000 0x00 0x10000 0x00>; - phandle = <0x15f>; - }; - - mmi_pcsr@0xeb2f0000 { - compatible = "xlnx,noc-npi-dev"; - reg = <0x00 0xeb2f0000 0x00 0x10000 0x01>; - map-size = <0x10000>; - custom = <0x01>; - pcsr-status = <0x7ffe>; - phandle = <0x160>; - }; - - mmi_gtyp@0xed900000 { - compatible = "xlnx,noc-npi-dev"; - reg = <0x00 0xed900000 0x00 0x20000 0x01>; - map-size = <0xed900000>; - custom = <0x01>; - pcsr-status = <0x3a00d0>; - phandle = <0x161>; - }; - - mmi_slcr_sec@0 { - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - reg = <0x00 0xedc30000 0x00 0x10000 0x00>; - read-only; - phandle = <0x162>; - }; - - trng@0xede80000 { - doc-status = "complete"; - compatible = "xlnx,versal-trng"; - reg = <0x00 0xede80000 0x00 0x10000 0x00>; - interrupts = <0xc7>; - #gpio-cells = <0x01>; - phandle = <0x6c>; - }; - - udh_slcr@0xedea0000 { - compatible = "xlnx.mmi_udh_slcr"; - reg = <0x00 0xedea0000 0x00 0x8000 0x00>; - gpios = <0x6c 0x00>; - phandle = <0x163>; - }; - - udh_pll@0xede90000 { - compatible = "xlnx.mmi_udh_pll"; - reg = <0x00 0xede90000 0x00 0x10000 0x00>; - phandle = <0x164>; - }; - - mmi_gpu_a@0 { - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - reg = <0x00 0xed0a0098 0x00 0x10 0x00>; - read-only; - phandle = <0x165>; - }; - - loader_write_cpu0_0x1@0xEDC30440 { - compatible = "loader"; - addr = <0xedc30440>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x166>; - }; - - loader_write_cpu0_0x7F@0xEDC30444 { - compatible = "loader"; - addr = <0xedc30444>; - data = <0x7f>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x167>; - }; - - loader_write_cpu0_0x1@0xEDC3044c { - compatible = "loader"; - addr = <0xedc3044c>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x168>; - }; - - loader_write_cpu0_0x1@0xEDC30450 { - compatible = "loader"; - addr = <0xedc30450>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x169>; - }; - - loader_write_cpu0_0x1@0xEDC30460 { - compatible = "loader"; - addr = <0xedc30460>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x16a>; - }; - - loader_write_cpu0_0x7f@0xEDC30464 { - compatible = "loader"; - addr = <0xedc30464>; - data = <0x7f>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x16b>; - }; - - loader_write_cpu0_0x1@0xEDC3046c { - compatible = "loader"; - addr = <0xedc3046c>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x16c>; - }; - - loader_write_cpu0_0x1@0xEDC30470 { - compatible = "loader"; - addr = <0xedc30470>; - data = <0x01>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x16d>; - }; - - loader_write_cpu0_0x3@0xED0A0098 { - compatible = "loader"; - addr = <0xed0a0098>; - data = <0x03>; - data-len = <0x04>; - cpu-num = <0x00>; - attrs-debug = <0x01>; - attrs-secure = <0x00>; - attrs-requester-id = <0x00>; - phandle = <0x16e>; - }; - }; - - downstream_amba_mmi { - compatible = "qemu:memory-region"; - alias = <0x6d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - }; - - amba_pmc_internal@0 { - doc-ignore = <0x01>; - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x0c>; - - downstream_amba_pmc_ppu { - compatible = "qemu:memory-region"; - alias = <0x6e>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_iou { - compatible = "qemu:memory-region"; - alias = <0x16>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_sec { - compatible = "qemu:memory-region"; - alias = <0x6f>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_sys { - compatible = "qemu:memory-region"; - alias = <0x70>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_pl { - compatible = "qemu:memory-region"; - alias = <0x71>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_bat { - compatible = "qemu:memory-region"; - alias = <0x72>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - xmpu_pmc@0 { - compatible = "xlnx,versal-xmpu"; - interrupts = <0x13>; - reg-extended = <0x0c 0x00 0xf12f0000 0x00 0x10000 0x00 0x0c 0x00 -0xf2000000 0x00 0x20000 0x02>; - protected-mr = <0x73>; - mr-0 = <0x0c>; - protected-base = <0xf2000000>; - phandle = <0x16f>; - }; - - xppu_pmc_npi@0xf1300000 { - compatible = "xlnx,versal-xppu"; - reg-extended = <0x0c 0x00 0xf1300000 0x00 0x10000 0x00 0x0c 0x00 -0xf6000000 0x00 0x1000000 0x02 0x0c 0x00 0xf7000000 0x00 0x1000000 0x02>; - mr = <0x71>; - interrupts = <0x13>; - phandle = <0x170>; - }; - - xppu_pmc@0xf1310000 { - compatible = "xlnx,versal-xppu"; - reg-extended = <0x0c 0x00 0xf1310000 0x00 0x10000 0x00 0x0d 0x00 -0xf1000000 0x00 0x1000000 0x02 0x0d 0x00 0xf0000000 0x00 0x1000000 0x02 0x0d 0x00 0xc0000000 0x00 -0x20000000 0x02>; - mr = <0x0c>; - interrupts = <0x13>; - phandle = <0x171>; - }; - }; - - amba_pmc@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x74>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - downstream_amba_pmc_internal { - compatible = "qemu:memory-region"; - alias = <0x0c>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - xmpu_pmc_cfu@0xf1340000 { - compatible = "xlnx,versal-xmpu"; - reg-extended = <0x74 0x00 0xf1340000 0x00 0x10000 0x00 0x71 0x00 -0xf12b0000 0x00 0x11000 0x02 0x71 0x00 0xf1f80000 0x00 0x40000 0x02>; - protected-mr = <0x75>; - mr-0 = <0x71>; - protected-base = <0xf12b0000>; - phandle = <0x172>; - }; - - pmx_err_mng@0xf1110000 { - compatible = "xlnx,pmxc-err-mng"; - reg = <0x00 0xf1130000 0x00 0x10000 0x01>; - gpios = <0x76 0x03 0x1b 0x2e 0x1b 0x2f 0x1b 0x30 0x1b 0x31>; - interrupts = <0xbca>; - phandle = <0x173>; - }; - - intpmxc_config@0xf1400000 { - compatible = "xlnx.pmxc_intpmx_config"; - reg = <0x00 0xf1400000 0x00 0x300000 0x00>; - phandle = <0x174>; - }; - }; - - amba_pmc_iou@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "PMC IOU"; - doc-status = "partial"; - phandle = <0x16>; - - pmc_iou_slcr@0xf1060000 { - doc-status = "partial"; - compatible = "xlnx,versal-pmx-iou-slcr"; - reg = <0x00 0xf1060000 0x00 0x1000 0x00>; - interrupts = <0xde>; - gpio-controller; - #gpio-cells = <0x02>; - phandle = <0x85>; - }; - - pmc_iou_slcr_secure@0xf1070000 { - compatible = "xlnx,versal-pmc-iou-slcr-secure"; - reg = <0x00 0xf1070000 0x00 0x10000 0x00>; - interrupts = <0xbca>; - memattr-sd0 = <0x77>; - memattr-write-sd0 = <0x78>; - memattr-sd1 = <0x79>; - memattr-write-sd1 = <0x7a>; - memattr-write-qspi = <0x7b>; - memattr-write-ospi = <0x7c>; - phandle = <0x175>; - }; - - pmc_qspi_dma@QSPI_DMA { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - interrupts = <0xd9>; - #stream-id-cells = <0x01>; - reg = <0x00 0xf1030800 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x7d>; - memattr-write = <0x7b>; - is-dst = <0x01>; - reset-gpios = <0x7e 0x00>; - phandle = <0x7f>; - }; - - pmc_qspi@0xf1030000 { - doc-status = "complete"; - #address-cells = <0x01>; - #size-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "xlnx,usmp-gqspi\0cdns,spi-r1p6"; - stream-connected-dma = <0x7f>; - dma = <0x74>; - interrupts = <0xd9>; - num-ss-bits = <0x02>; - reg-extended = <0x16 0x00 0xf1030000 0x00 0x1000 0x00 0x80 0x00 0x00 -0x00 0x20000000 0x00>; - speed-hz = <0x989680>; - xlnx,fb-clk = <0x01>; - xlnx,qspi-clk-freq-hz = <0xbebc200>; - xlnx,qspi-mode = <0x02>; - reset-gpios = <0x7e 0x00>; - phandle = <0x176>; - - qspi_flash_lcs_lb@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25qu02gcbb\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x00 0x00>; - drive-index = <0x00>; - phandle = <0x177>; - - qspi_flash_lcs_lb@0x00000000 { - label = "qspi_flash_lcs_lb"; - reg = <0x00 0x2000000>; - }; - }; - - qspi_flash_lcs_ub@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25qu02gcbb\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x02 0x01>; - drive-index = <0x01>; - phandle = <0x178>; - - qspi_flash_lcs_ub@0x00000000 { - label = "qspi_flash_lcs_ub"; - reg = <0x00 0x2000000>; - }; - }; - - qspi_flash_ucs_lb@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25qu02gcbb\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x01 0x00>; - drive-index = <0x02>; - phandle = <0x179>; - - qspi_flash_ucs_lb@0x00000000 { - label = "qspi_flash_ucs_lb"; - reg = <0x00 0x2000000>; - }; - }; - - qspi_flash_ucs_ub@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "m25qu02gcbb\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x03 0x01>; - drive-index = <0x03>; - phandle = <0x17a>; - - qspi_flash_ucs_ub@0x00000000 { - label = "qspi_flash_ucs_ub"; - reg = <0x00 0x2000000>; - }; - }; - }; - - ospi_dst_dma@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - interrupts = <0xd8>; - reg = <0x00 0xf1011800 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x81>; - memattr-write = <0x7c>; - is-dst = <0x01>; - reset-gpios = <0x7e 0x01>; - phandle = <0x83>; - }; - - ospi_src_dma@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - interrupts = <0xd8>; - reg = <0x00 0xf1011000 0x00 0x800 0x00>; - dma = <0x82>; - memattr = <0x81>; - memattr-write = <0x7c>; - stream-connected-dma = <0x83>; - reset-gpios = <0x7e 0x01>; - phandle = <0x84>; - }; - - spi@0xf1010000 { - doc-status = "complete"; - #address-cells = <0x01>; - #size-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "xlnx,versal-ospi"; - reg-extended = <0x16 0x00 0xf1010000 0x00 0x1000 0x00 0x82 0x00 0x00 -0x00 0x20000000 0x00>; - dma-src = <0x84>; - interrupts = <0xd8>; - reset-gpios = <0x7e 0x01>; - gpios = <0x85 0x03 0x00>; - phandle = <0x17b>; - - ospi_flash_lcs_lb@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "mt35xu02gbba"; - spi-max-frequency = <0x2faf080>; - reg = <0x00 0x00>; - drive-index = <0x04>; - phandle = <0x17c>; - - ospi_flash_lcs_lb@0x00000000 { - label = "ospi_flash_lcs_lb"; - reg = <0x00 0x2000000>; - }; - }; - - ospi_flash_lcs_ub@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "mt35xu02gbba"; - spi-max-frequency = <0x2faf080>; - reg = <0x01 0x00>; - drive-index = <0x05>; - phandle = <0x17d>; - - ospi_flash_lcs_ub@0x00000000 { - label = "ospi_flash_lcs_ub"; - reg = <0x00 0x2000000>; - }; - }; - - ospi_flash_ucs_lb@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "mt35xu01gbba\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x02 0x00>; - drive-index = <0x06>; - phandle = <0x17e>; - - ospi_flash_ucs_lb@0x00000000 { - label = "ospi_flash_ucs_lb"; - reg = <0x00 0x2000000>; - }; - }; - - ospi_flash_ucs_ub@0 { - #address-cells = <0x01>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - #bus-cells = <0x01>; - compatible = "mt35xu01gbba\0st,m25p80"; - spi-max-frequency = <0x2faf080>; - reg = <0x03 0x00>; - drive-index = <0x07>; - phandle = <0x17f>; - - ospi_flash_ucs_ub@0x00000000 { - label = "ospi_flash_ucs_ub"; - reg = <0x00 0x2000000>; - }; - }; - }; - - gpio_mr_mux@0xc0000000 { - doc-status = "complete"; - compatible = "gpio-mr-mux"; - reg = <0x00 0xc0000000 0x00 0x20000000 0x00>; - gpios = <0x85 0x02 0x00 0x85 0x03 0x00>; - mr-size = <0x20000000>; - mr0 = <0x80>; - mr1 = <0x82>; - mr2 = <0x80>; - mr3 = <0x82>; - phandle = <0x180>; - }; - - pmc_gpio@0xf1020000 { - #gpio-cells = <0x01>; - compatible = "xlnx,zynqmp-gpio"; - gpio-controller; - interrupts = <0xca>; - reg = <0x00 0xf1020000 0x00 0x10000 0x00>; - reset-gpios = <0x7e 0x05>; - phandle = <0x181>; - }; - - mmc@0xf1040000 { - doc-status = "complete"; - compatible = "xilinx,zynqmp-sdhci\0generic-sdhci"; - drive-index = <0x00>; - reg = <0x00 0xf1040000 0x00 0x10000 0x00>; - interrupts = <0xda>; - dma = <0x17>; - memattr = <0x77>; - memattr-write = <0x78>; - gpios = <0x85 0x00 0x00>; - gpio-names = "SLOTTYPE"; - reset-gpios = <0x7e 0x08>; - is-mmc = <0x00>; - xlnx,has-cd = <0x01>; - xlnx,has-power = <0x00>; - xlnx,has-wp = <0x01>; - xlnx,sdio-clk-freq-hz = <0x2faf080>; - phandle = <0x182>; - }; - - mmc@0xf1050000 { - doc-status = "complete"; - compatible = "xlnx,versalnet-emmc"; - drive-index = <0x01>; - reg = <0x00 0xf1050200 0x00 0x100 0x00 0x00 0xf1050000 0x00 -0x100 0x00>; - interrupts = <0xdc>; - dma = <0x17>; - memattr = <0x79>; - memattr-write = <0x7a>; - gpios = <0x85 0x01 0x00>; - gpio-names = "SLOTTYPE"; - reset-gpios = <0x7e 0x03>; - is-mmc = <0x00>; - xlnx,has-cd = <0x01>; - xlnx,has-power = <0x00>; - xlnx,has-wp = <0x01>; - xlnx,sdio-clk-freq-hz = <0x2faf080>; - phandle = <0x183>; - }; - - pmc_tap@0xf11a0000 { - doc-status = "complete"; - doc-comments = "Just a stub."; - compatible = "xlnx,pmc-tap"; - interrupts-extended = <0x86 0x1e>; - interrupt-names = "sec-dbg-int"; - reg = <0x00 0xf11a0000 0x00 0x80000 0x00>; - idcode = <0x14ca8093>; - platform-ver = <0x01>; - phandle = <0x184>; - }; - - pmc_i2c_wrapper { - - pmc_i2c@0xf1000000 { - compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; - interrupts = <0xcb>; - reg-extended = <0x16 0x00 0xf1000000 0x00 0x10000 0x00>; - #address-cells = <0x01>; - #size-cells = <0x00>; - reset-gpios = <0x7e 0x04>; - phandle = <0x185>; - }; - }; - - wwdt@0xf03f0000 { - compatible = "xlnx,versal-wwdt"; - reg = <0x00 0xf03f0000 0x00 0x10000 0x00>; - pclk = <0x5f5e100>; - phandle = <0x186>; - }; - - pmc_ufshc@0xf10b0000 { - compatible = "ufshc-sysbus"; - reg = <0x00 0xf10b0000 0x00 0x10000 0x00>; - interrupts = <0xea>; - ufs-target = <0x87>; - unipro-mphy = <0x88>; - dma = <0x74>; - phandle = <0x89>; - }; - - unipro@0 { - compatible = "unipro-mphy"; - ufshc = <0x89>; - #gpio-cells = <0x01>; - phandle = <0x88>; - }; - - ufs_dev@0 { - compatible = "ufs-dev"; - num-luns = <0x08>; - phandle = <0x87>; - }; - - ufs_reg@0xf1060000 { - compatible = "dwc.ufs_reg"; - reg = <0x00 0xf1061000 0x00 0x100 0x01>; - gpios = <0x88 0x00>; - phandle = <0x187>; - }; - }; - - amba_pmc_sec@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "PMC Secure"; - doc-status = "in-progress"; - qemu-fdt-abort-on-error = "Unable to create PMC security models. -Cannot continue.\nTry installing libgcrypt."; - phandle = <0x6f>; - - trng@0xf1230000 { - doc-status = "complete"; - compatible = "xlnx,versal-trng"; - reg = <0x00 0xf1230000 0x00 0x1000 0x00>; - interrupts = <0xe9>; - }; - - pmc_dma0_src@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - stream-connected-dma0 = <0x8a>; - reg = <0x00 0xf11c0000 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x8b>; - dma-width = <0x10>; - interrupts = <0xe0>; - reset-gpios = <0x7e 0x13>; - byte-align = <0x01>; - phandle = <0x188>; - }; - - pmc_dma0_dst@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xf11c0800 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x8b>; - is-dst = <0x01>; - dma-width = <0x10>; - interrupts = <0xe0>; - reset-gpios = <0x7e 0x13>; - byte-align = <0x01>; - phandle = <0x8d>; - }; - - pmc_dma1_src@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - stream-connected-dma1 = <0x8a>; - reg = <0x00 0xf11d0000 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x8c>; - dma-width = <0x10>; - interrupts = <0xe1>; - reset-gpios = <0x7e 0x14>; - byte-align = <0x01>; - phandle = <0x189>; - }; - - pmc_dma1_dst@0 { - doc-status = "complete"; - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xf11d0800 0x00 0x800 0x00>; - dma = <0x74>; - memattr = <0x8c>; - is-dst = <0x01>; - dma-width = <0x10>; - interrupts = <0xe1>; - reset-gpios = <0x7e 0x14>; - byte-align = <0x01>; - phandle = <0x8e>; - }; - - pmc_stream_switch@0 { - doc-status = "complete"; - compatible = "versal,pmc-sss"; - reg-extended = <0x70 0x00 0xf1110500 0x00 0x04 0x01>; - stream-connected-dma0 = <0x8d>; - stream-connected-dma1 = <0x8e>; - stream-connected-aes = <0x8f>; - stream-connected-sha = <0x90>; - stream-connected-sbi = <0x91>; - stream-connected-sha1 = <0x92>; - phandle = <0x8a>; - }; - - pmc_sha@0xf1210000 { - doc-status = "complete"; - compatible = "xlnx,asu_sha3"; - reg = <0x00 0xf1210000 0x00 0x100 0x00>; - interrupts = <0xe7>; - phandle = <0x90>; - }; - - pmc_aes@0xf11e0000 { - doc-status = "in-progress"; - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx-pmxc-aes"; - stream-connected-aes = <0x8a>; - reg = <0x00 0xf11e0000 0x00 0x100 0x00>; - interrupts = <0xe4>; - gpios = <0x93 0x00 0x93 0x01>; - gpio-names = "busy\0done"; - aes-core = <0x93>; - integrated-endianness-swap = <0x01>; - asu-aes = <0x94>; - phandle = <0x8f>; - - xlnx_aes@0 { - #gpio-cells = <0x01>; - compatible = "xlnx-aes"; - gpios = <0x8f 0x00>; - gpio-names = "reset"; - phandle = <0x93>; - }; - }; - - pmc_rsa@0xf1200000 { - doc-status = "complete"; - compatible = "xlnx,versal-ecdsa-rsa"; - reg = <0x00 0xf1200000 0x00 0x6c 0x00>; - interrupts = <0xe5>; - ram-nr-words = <0x100>; - phandle = <0x18a>; - }; - - xlnx_pmc_efuse_cache@0xf1250000 { - doc-status = "complete"; - compatible = "xlnx,pmx_efuse_cache"; - reg = <0x00 0xf1250000 0x00 0x10000 0x00>; - efuse = <0x95>; - phandle = <0x99>; - }; - - pmc_puf_ctrl@0 { - compatible = "xlnx,versal-puf-ctrl"; - zynqmp-aes-key-sink-puf = <0x8f>; - efuse = <0x95>; - reg = <0x00 0xf1150000 0x00 0x10000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x97>; - }; - - pmc_efuse@0xf1240000 { - doc-status = "complete"; - compatible = "xlnx,pmx_efuse_ctrl"; - #gpio-cells = <0x02>; - zynqmp-aes-key-sink-efuses = <0x8f>; - zynqmp-aes-key-sink-efuses-user0 = <0x8f>; - zynqmp-aes-key-sink-efuses-user1 = <0x8f>; - reg = <0x00 0xf1240000 0x00 0x10000 0x00>; - interrupts = <0xe6>; - efuse = <0x95>; - phandle = <0x18b>; - - xlnx_efuse@0 { - doc-ignore = <0x01>; - compatible = "xlnx,efuse"; - efuse-nr = <0x03>; - efuse-size = <0x2000>; - init-factory-extidcode = <0x01>; - phandle = <0x95>; - }; - }; - - pmc_bbram@0xf11f0000 { - doc-status = "partial"; - doc-limitations = "Missing AES key connections."; - compatible = "xlnx,bbram-ctrl"; - reg = <0x00 0xf11f0000 0x00 0x10000 0x00>; - interrupts = <0xbca>; - zynqmp-aes-key-sink-bbram = <0x8f>; - crc-zpads = <0x00>; - phandle = <0x98>; - }; - - pmc_sbi@0xf1220000 { - doc-status = "complete"; - compatible = "pmc,slave-boot"; - reg = <0x00 0xf1220000 0x00 0x10000 0x00 0x00 0xf2100000 -0x00 0x10000 0x00>; - interrupts = <0xe3>; - stream-connected-sbi = <0x8a>; - reset-gpios = <0x7e 0x12>; - phandle = <0x91>; - }; - - pmc_sha1@0xF1800000 { - doc-status = "complete"; - compatible = "xlnx,asu_sha2"; - reg = <0x00 0xf1800000 0x00 0x10000 0x00>; - phandle = <0x92>; - }; - }; - - amba_pmc_ppu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x6e>; - - pmc_gic_proxy@0 { - doc-status = "complete"; - #interrupt-cells = <0x03>; - interrupt-controller; - compatible = "xlnx,zynqmp-gicp"; - reg = <0x00 0xf1140000 0x00 0x100 0x00>; - interrupt-parent = <0x08>; - interrupts = <0x10>; - max-ints = <0x100>; - phandle = <0x07>; - }; - }; - - amba_pmc_sys@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "PMC System"; - doc-status = "partial"; - phandle = <0x70>; - - pmc_clk_rst@0xf1260000 { - doc-status = "partial"; - compatible = "xlnx,pmx_crp"; - reg = <0x00 0xf1260000 0x00 0x80000 0x00>; - interrupts = <0xbca>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x7e>; - }; - - pmc_int@0xf1400000 { - doc-status = "partial"; - compatible = "xlnx,versal-pmc-int"; - reg = <0x00 0xf1400000 0x00 0x300000 0x00>; - interrupts = <0xe2>; - phandle = <0x18c>; - }; - - pmc_reset_domain@0 { - compatible = "qemu,reset-device"; - gpios = <0x7e 0x02>; - }; - - pmc_global@0xf1110000 { - doc-status = "partial"; - #gpio-cells = <0x01>; - gpio-controller; - interrupts-extended = <0x08 0x10 0x08 0x1b 0x08 0x1b 0x08 0x1b 0x08 -0x1b 0x08 0x11 0x08 0x11 0x96 0x00 0x86 0x10 0x86 0x11 0x86 0x12 0x86 0x13 0x86 0x14 0x86 0x15 0x86 -0x16 0x86 0x17 0x86 0x18 0x86 0x19 0x86 0x1a 0x86 0x1b 0x96 0x00 0x86 0x1d>; - reg = <0x00 0xf1110000 0x00 0x50000 0x00>; - gpios = <0x97 0x00>; - bbram = <0x98>; - efuse = <0x99>; - compatible = "xlnx,pmxc_global"; - phandle = <0x76>; - }; - - pmc_stream_zero@ { - compatible = "xlnx,pmc-stream-zero"; - reg = <0x00 0xf1110518 0x00 0x04 0x01>; - stream-connected-pzm = <0x8a>; - phandle = <0x18d>; - }; - - pmc_analog@0xf1160000 { - compatible = "xlnx,pmxc_anlg"; - reg = <0x00 0xf1160000 0x00 0x40000 0x00>; - interrupts-extended = <0x07 0x00 0x13 0x00>; - tamper-sink = <0x76>; - phandle = <0x18e>; - }; - - pmc_sysmon@0xf1270000 { - compatible = "xlnx,pmc-sysmon"; - reg = <0x00 0xf1270000 0x00 0x30000 0x00>; - interrupts = <0x12 0x79>; - reset-gpios = <0x7e 0x15>; - efuse = <0x99>; - ams-sats = <0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0>; - tamper-sink = <0x76>; - phandle = <0x18f>; - }; - - pmc_ams_sat@0 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xf1280000 0x00 0x10000 0x01>; - phandle = <0x9a>; - }; - - pmc_ams_sat@1 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xf1290000 0x00 0x10000 0x01>; - phandle = <0x9b>; - }; - - versal_pmc_tamper@ { - compatible = "xlnx,pmc_tamper"; - reg-extended = <0x70 0x00 0xf1110530 0x00 0x38 0x01 0xa1 0x00 -0xf0041100 0x00 0x38 0x02>; - phandle = <0x190>; - }; - - lpd_ams_sat@0 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xeb550000 0x00 0x10000 0x01>; - phandle = <0x9c>; - }; - - fpd_ams_sat@0 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xecc30000 0x00 0x10000 0x01>; - phandle = <0x9d>; - }; - - fpd_ams_sat@1 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xecd30000 0x00 0x10000 0x01>; - phandle = <0x9e>; - }; - - fpd_ams_sat@2 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xece30000 0x00 0x10000 0x01>; - phandle = <0x9f>; - }; - - fpd_ams_sat@3 { - compatible = "xlnx,ams-sat"; - reg = <0x00 0xecf30000 0x00 0x10000 0x01>; - phandle = <0xa0>; - }; - }; - - amba_pmc_pl@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "PMC PL"; - doc-status = "partial"; - phandle = <0x71>; - - noc_npi_nir@0xf6000000 { - compatible = "xlnx.npi-nir"; - reg = <0x00 0xf6000000 0x00 0x10000 0x01>; - phandle = <0x191>; - }; - - npi_ddrmc_ub0@0xf62c0000 { - doc-limitations = "Only the uB rst is supported"; - compatible = "xlnx,ddrmc5_ub"; - reg = <0x00 0xf62c0000 0x00 0x40000 0x01>; - reset-gpios = <0x7e 0x0f>; - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x192>; - }; - - npi_ddrmc_main0@0xf6290000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-main"; - reg = <0x00 0xf6290000 0x00 0x10000 0x01>; - reset-gpios = <0x7e 0x0f>; - phandle = <0xcf>; - }; - - npi_ddrmc_noc0@0xf62a0000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-noc"; - reg = <0x00 0xf62a0000 0x00 0x20000 0xffffffff>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x193>; - }; - - npi_ddrmc_ub1@0xf63b0000 { - doc-limitations = "Only the uB rst is supported"; - compatible = "xlnx,ddrmc5_ub"; - reg = <0x00 0xf63b0000 0x00 0x40000 0x01>; - reset-gpios = <0x7e 0x0f>; - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x194>; - }; - - npi_ddrmc_main1@0xf6380000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-main"; - reg = <0x00 0xf6380000 0x00 0x10000 0x01>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x195>; - }; - - npi_ddrmc_noc1@0xf6390000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-noc"; - reg = <0x00 0xf6390000 0x00 0x20000 0xffffffff>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x196>; - }; - - npi_ddrmc_ub2@0xf6940000 { - doc-limitations = "Only the uB rst is supported"; - compatible = "xlnx,ddrmc5_ub"; - reg = <0x00 0xf6940000 0x00 0x40000 0x01>; - reset-gpios = <0x7e 0x0f>; - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x197>; - }; - - npi_ddrmc_main2@0xf6910000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-main"; - reg = <0x00 0xf6910000 0x00 0x10000 0x01>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x198>; - }; - - npi_ddrmc_noc2@0xf6920000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-noc"; - reg = <0x00 0xf6920000 0x00 0x20000 0xffffffff>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x199>; - }; - - npi_ddrmc_ub3@0xf6a20000 { - doc-limitations = "Only the uB rst is supported"; - compatible = "xlnx,ddrmc5_ub"; - reg = <0x00 0xf6a20000 0x00 0x40000 0x01>; - reset-gpios = <0x7e 0x0f>; - #gpio-cells = <0x01>; - gpio-controller; - phandle = <0x19a>; - }; - - npi_ddrmc_main3@0xf69f0000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-main"; - reg = <0x00 0xf69f0000 0x00 0x10000 0x01>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x19b>; - }; - - npi_ddrmc_noc3@0xf6a00000 { - doc-limitations = "Just a stub"; - compatible = "xlnx,versal-ddrmc-noc"; - reg = <0x00 0xf6a00000 0x00 0x20000 0xffffffff>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x19c>; - }; - - npi_ddrmc_xmpu0@0xf62a0000 { - compatible = "xlnx,versal-ddrmc-xmpu"; - reg-extended = <0x71 0x00 0xf62b2000 0x00 0x10000 0x01 0x0d 0x00 -0x00 0x00 0x80000000 0x00>; - protected-mr = <0xa2>; - mr-0 = <0x0d>; - protected-base = <0x00>; - phandle = <0x19d>; - }; - - npi_me@0xf6540000 { - compatible = "xlnx.aie2p_s_npi"; - reg = <0x00 0xf6540000 0x00 0x10000 0x01>; - reset-gpios = <0x7e 0x0f>; - phandle = <0x19e>; - }; - - noc_npi_devs@0 { - compatible = "xlnx,noc-npi-dev"; - reg = <0x00 0xf6000000 0x00 0x2000000 0x00>; - phandle = <0x19f>; - }; - - cfu_fdro@0xf12c2000 { - compatible = "xlnx,versal-cfu-fdro"; - reg = <0x00 0xf12c2000 0x00 0x1000 0x00>; - phandle = <0xa4>; - }; - - cfu_sfr@0xf12c1000 { - compatible = "xlnx,versal-cfu-sfr"; - reg = <0x00 0xf12c1000 0x00 0x1000 0x00>; - cfu = <0xa3>; - phandle = <0x1a0>; - }; - - cframe0_reg@0xf12d0000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12d0000 0x00 0x1000 0x00 0x00 0xf12d1000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - blktype0-frames = <0x853f>; - blktype1-frames = <0xdc8>; - blktype2-frames = <0x3200>; - blktype3-frames = <0x0b>; - blktype4-frames = <0x05>; - blktype5-frames = <0x01>; - blktype6-frames = <0x01>; - phandle = <0xa5>; - }; - - cframe1_reg@0xf12d2000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12d2000 0x00 0x1000 0x00 0x00 0xf12d3000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - blktype0-frames = <0x9662>; - blktype1-frames = <0xf01>; - blktype2-frames = <0x3c01>; - blktype3-frames = <0x0d>; - blktype4-frames = <0x07>; - blktype5-frames = <0x03>; - blktype6-frames = <0x01>; - phandle = <0xa6>; - }; - - cframe2_reg@0xf12d4000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12d4000 0x00 0x1000 0x00 0x00 0xf12d5000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - blktype0-frames = <0x9662>; - blktype1-frames = <0xf01>; - blktype2-frames = <0x3c01>; - blktype3-frames = <0x0d>; - blktype4-frames = <0x07>; - blktype5-frames = <0x03>; - blktype6-frames = <0x01>; - phandle = <0xa7>; - }; - - cframe3_reg@0xf12d6000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12d6000 0x00 0x1000 0x00 0x00 0xf12d7000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - blktype0-frames = <0x9662>; - blktype1-frames = <0xf01>; - blktype2-frames = <0x3c01>; - blktype3-frames = <0x0d>; - blktype4-frames = <0x07>; - blktype5-frames = <0x03>; - blktype6-frames = <0x01>; - phandle = <0xa8>; - }; - - cframe4_reg@0xf12d8000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12d8000 0x00 0x1000 0x00 0x00 0xf12d9000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xa9>; - }; - - cframe5_reg@0xf12da000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12da000 0x00 0x1000 0x00 0x00 0xf12db000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xaa>; - }; - - cframe6_reg@0xf12dc000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12dc000 0x00 0x1000 0x00 0x00 0xf12dd000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xab>; - }; - - cframe7_reg@0xf12de000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12de000 0x00 0x1000 0x00 0x00 0xf12df000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xac>; - }; - - cframe8_reg@0xf12e0000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12e0000 0x00 0x1000 0x00 0x00 0xf12e1000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xad>; - }; - - cframe9_reg@0xf12e2000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12e2000 0x00 0x1000 0x00 0x00 0xf12e3000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xae>; - }; - - cframe10_reg@0xf12e4000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12e4000 0x00 0x1000 0x00 0x00 0xf12e5000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xaf>; - }; - - cframe11_reg@0xf12e6000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12e6000 0x00 0x1000 0x00 0x00 0xf12e7000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xb0>; - }; - - cframe12_reg@0xf12e8000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12e8000 0x00 0x1000 0x00 0x00 0xf12e9000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xb1>; - }; - - cframe13_reg@0xf12ea000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12ea000 0x00 0x1000 0x00 0x00 0xf12eb000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xb2>; - }; - - cframe14_reg@0xf12ec000 { - compatible = "xlnx.cframe_reg"; - reg = <0x00 0xf12ec000 0x00 0x1000 0x00 0x00 0xf12ed000 -0x00 0x1000 0x00>; - interrupts = <0x13>; - cfu-fdro = <0xa4>; - phandle = <0xb3>; - }; - - cframe_bcast_reg@0xf12ee000 { - compatible = "xlnx.cframe-bcast-reg"; - reg = <0x00 0xf12ee000 0x00 0x1000 0x00 0x00 0xf12ef000 -0x00 0x1000 0x00>; - cframe0 = <0xa5>; - cframe1 = <0xa6>; - cframe2 = <0xa7>; - cframe3 = <0xa8>; - cframe4 = <0xa9>; - cframe5 = <0xaa>; - cframe6 = <0xab>; - cframe7 = <0xac>; - cframe8 = <0xad>; - cframe9 = <0xae>; - cframe10 = <0xaf>; - cframe11 = <0xb0>; - cframe12 = <0xb1>; - cframe13 = <0xb2>; - cframe14 = <0xb3>; - phandle = <0x1a1>; - }; - - gtyp_npi_slave_0@0xf65a0000 { - compatible = "xlnx,xlnx,gtyp_npi_slave"; - reg = <0x00 0xf65a0000 0x00 0x20000 0x00>; - }; - - gtyp_npi_slave_1@0xf66c0000 { - compatible = "xlnx,xlnx,gtyp_npi_slave"; - reg = <0x00 0xf66c0000 0x00 0x20000 0x00>; - }; - - gtyp_npi_slave_2@0xf6720000 { - compatible = "xlnx,xlnx,gtyp_npi_slave"; - reg = <0x00 0xf6720000 0x00 0x20000 0x00>; - }; - - dummy_cfu_mem@0xf12b0000 { - compatible = "qemu:memory-region"; - phandle = <0x75>; - - cfu@0x0 { - doc-status = "partial"; - doc-comments = "Stub"; - doc-limitations = "No way to extract CFRAME data."; - compatible = "xlnx,versal-cfu"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x10000 0x00 0x1000 -0x00 0x00 0xcd0000 0x00 0x40000 0x00>; - chardev = "pmc-cfu"; - dma = <0x74>; - phandle = <0xa3>; - }; - }; - }; - - amba_pmc_bat@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "PMC BAT"; - doc-status = "partial"; - phandle = <0x72>; - - rtc@0xf12a0000 { - doc-status = "complete"; - doc-comments = "Versal PMC RTC"; - compatible = "xlnx,zynqmp-rtc"; - interrupts = <0xbca 0xc8 0xc9>; - reg = <0x00 0xf12a0000 0x00 0x10000 0x00>; - xlnx,version = "2.0.0"; - phandle = <0x1a2>; - }; - }; - - amba_psm@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x14>; - }; - - amba_xram@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x15>; - - xram_ctrl_0 { - compatible = "xlnx,versal-xramc"; - reg = <0x00 0xeb8e0000 0x00 0x10000 0x00>; - interrupts = <0x4f>; - alloc-ram = <0x00>; - }; - - xram_ctrl_1 { - compatible = "xlnx,versal-xramc"; - reg = <0x00 0xeb8f0000 0x00 0x10000 0x00>; - interrupts = <0x4f>; - alloc-ram = <0x00>; - }; - - xram_ctrl_2 { - compatible = "xlnx,versal-xramc"; - reg = <0x00 0xeb900000 0x00 0x10000 0x00>; - interrupts = <0x4f>; - alloc-ram = <0x00>; - }; - - xram_ctrl_3 { - compatible = "xlnx,versal-xramc"; - reg = <0x00 0xeb910000 0x00 0x10000 0x00>; - interrupts = <0x4f>; - alloc-ram = <0x00>; - }; - }; - - crf@0xec200000 { - compatible = "xlnx,versal-psx-crf"; - reg-extended = <0x0b 0x00 0xec200000 0x00 0x100000 0x00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x52>; - }; - - amba_asu_cpu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - #interrupt-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xb4>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - }; - - amba_asu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x51>; - - asu_instr_ram@0xebe00000 { - compatible = "qemu:memory-region"; - device_type = "memory"; - qemu,ram = <0x01>; - reg = <0x00 0xebe00000 0x00 0x40000 0x00>; - phandle = <0x1a3>; - }; - - io-module@0xebe80000 { - #address-cells = <0x02>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; - container = <0xb4>; - priority = <0xffffffff>; - xlnx,freq = <0x47868c0>; - xlnx,instance = "iomodule_0"; - xlnx,io-mask = <0xfffe0000>; - xlnx,lmb-awidth = <0x20>; - xlnx,lmb-dwidth = <0x20>; - xlnx,mask = <0xffffff80>; - xlnx,use-io-bus = <0x01>; - phandle = <0x1a4>; - - asu_io_intc@0C { - #interrupt-cells = <0x01>; - compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; - interrupt-controller; - interrupts-extended = <0xb5 0x0b>; - reg = <0x00 0xebe8000c 0x04 0x00 0xebe80030 0x10 0x00 -0xebe80080 0x7c>; - xlnx,intc-addr-width = <0x20>; - xlnx,intc-base-vectors = <0x00>; - xlnx,intc-has-fast = <0x00>; - xlnx,intc-intr-size = <0x10>; - xlnx,intc-level-edge = <0x00>; - xlnx,intc-positive = <0xffff>; - xlnx,intc-use-ext-intr = <0x01>; - phandle = <0x09>; - }; - - asu_gpi@20 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x09>; - interrupts = <0x0b>; - reg = <0x00 0xebe80020 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1a5>; - }; - - asu_gpo@10 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xebe80010 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x03>; - xlnx,use-gpo = <0x01>; - phandle = <0xb6>; - }; - - asu_gpo@14 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xebe80014 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1a6>; - }; - - asu_pit@40 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x09>; - interrupts = <0x03>; - reg = <0x00 0xebe80040 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xb6 0x01 0xb7 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1a7>; - }; - - asu_pit@50 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x09>; - interrupts = <0x04>; - reg = <0x00 0xebe80050 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xb7>; - }; - - asu_pit@60 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x09>; - interrupts = <0x05>; - reg = <0x00 0xebe80060 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xb6 0x02 0xb8 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1a8>; - }; - - asu_pit@70 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x09>; - interrupts = <0x06>; - reg = <0x00 0xebe80070 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xb8>; - }; - }; - - asu_mdm_uart@0xebef0000 { - compatible = "xlnx,xps-uartlite"; - reg = <0x00 0xebef0000 0x00 0x10 0x01>; - chardev = "serial4"; - phandle = <0x1a9>; - }; - - asu_global@0xebf80000 { - compatible = "xlnx,asu_global"; - reg = <0x00 0xebf80000 0x00 0x20000 0x00>; - gpios = <0xb9 0x00>; - phandle = <0x1aa>; - }; - - asu_global_pmc@0xebf80000 { - compatible = "xlnx,asu_global_pmc"; - reg = <0x00 0xebf90000 0x00 0x20000 0x00>; - phandle = <0x1ab>; - }; - - asu_local@0xebe8e000 { - compatible = "xlnx,asu_local_reg"; - reg = <0x00 0xebe8e000 0x00 0x2000 0x00>; - phandle = <0x1ac>; - }; - - asu_sss@0xebe8e000 { - compatible = "asu-sss"; - reg = <0x00 0xebe8e000 0x00 0x08 0x01>; - stream-connected-dma0 = <0xba>; - stream-connected-sha2 = <0xbb>; - stream-connected-sha3 = <0xbc>; - stream-connected-dma1 = <0xbd>; - stream-connected-aes = <0xb9>; - phandle = <0xbe>; - }; - - asu_dma_src@0xebe8c000 { - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xebe8c000 0x00 0x800 0x00>; - interrupts = <0x13>; - stream-connected-dma0 = <0xbe>; - dma = <0xb4>; - memattr = <0x8b>; - dma-width = <0x10>; - byte-align = <0x01>; - phandle = <0x1ad>; - }; - - asu_dma_dst@0xebe8c000 { - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xebe8c800 0x00 0x800 0x00>; - interrupts = <0x13>; - dma = <0xb4>; - memattr = <0x8b>; - dma-width = <0x10>; - is-dst = <0x01>; - byte-align = <0x01>; - phandle = <0xba>; - }; - - asu_dma1_src@0xebe8d000 { - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xebe8d000 0x00 0x800 0x00>; - interrupts = <0x13>; - stream-connected-dma1 = <0xbe>; - dma = <0xb4>; - memattr = <0x8c>; - dma-width = <0x10>; - byte-align = <0x01>; - phandle = <0x1ae>; - }; - - asu_dma1_dst@0xebe8d000 { - compatible = "zynqmp,csu-dma"; - reg = <0x00 0xebe8d800 0x00 0x800 0x00>; - interrupts = <0x14>; - dma = <0xb4>; - memattr = <0x8c>; - dma-width = <0x10>; - is-dst = <0x01>; - byte-align = <0x01>; - phandle = <0xbd>; - }; - - asu_xmpu@0xebf60000 { - compatible = "xlnx,versal-xmpu"; - reg-extended = <0x51 0x00 0xebf60000 0x00 0x10000 0x00 0x51 0x00 -0xebe40000 0x00 0x20000 0x02>; - protected-mr = <0xbf>; - mr-0 = <0x0d>; - protected-base = <0xebe40000>; - phandle = <0x1af>; - }; - - asu_aes@0xebe88000 { - doc-status = "complete"; - compatible = "xlnx,asu-aes"; - reg = <0x00 0xebe88000 0x00 0x2000 0x00>; - #gpio-cells = <0x01>; - gpio-controller; - interrupts = <0x12 0x1a>; - keyvault = <0x94>; - stream-connected-aes = <0xbe>; - phandle = <0xb9>; - }; - - asu_kv@0xebe8a000 { - compatible = "xlnx,asu-kv"; - reg = <0x00 0xebe8a000 0x00 0x2000 0x00>; - pmxc-aes = <0x8f>; - aes-engine = <0xb9>; - phandle = <0x94>; - }; - - asu_sha3@0xebf40000 { - doc-status = "complete"; - compatible = "xlnx,asu_sha3"; - reg = <0x00 0xebf40000 0x00 0x10000 0x00>; - interrupts = <0x15>; - phandle = <0xbc>; - }; - - asu_sha2@0xebf30000 { - doc-status = "complete"; - compatible = "xlnx,asu_sha2"; - reg = <0x00 0xebf30000 0x00 0x10000 0x00>; - phandle = <0xbb>; - }; - - pmc_rsa@0xebf50000 { - doc-status = "complete"; - compatible = "xlnx,asu-ecdsa-rsa"; - reg = <0x00 0xebf50000 0x00 0x10000 0x00>; - interrupts = <0x17>; - phandle = <0x1b0>; - }; - - trng@0xebf20000 { - doc-status = "complete"; - compatible = "xlnx-asu-trng"; - reg = <0x00 0xebf10000 0x00 0x20000 0x00>; - interrupts = <0x18>; - phandle = <0x1b1>; - }; - - asu_ecc@0xebf00000 { - doc-status = "complete"; - compatible = "xlnx,asu_ecc"; - reg = <0x00 0xebf00000 0x00 0x10000 0x00>; - interrupts = <0x16>; - phandle = <0x1b2>; - }; - }; - }; - - lmb_pmc_ppu0@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "LMB PPU0"; - doc-status = "complete"; - phandle = <0xa1>; - - main_bus_for_pmc { - compatible = "qemu:memory-region"; - alias = <0x74>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - - pmc_rom@0xf0000000 { - reg = <0x00 0xf0000000 0x00 0x40000 0x01>; - compatible = "qemu:memory-region"; - container = <0xa1>; - qemu,ram = <0x01>; - read-only; - phandle = <0x1b3>; - }; - - ppu0_ram@0xf0060000 { - reg = <0x00 0xf0060000 0x00 0x8000 0x01>; - compatible = "qemu:memory-region"; - container = <0xa1>; - qemu,ram = <0x01>; - phandle = <0x1b4>; - }; - - io-module@00 { - doc-status = "complete"; - #address-cells = <0x02>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; - container = <0xa1>; - priority = <0xffffffff>; - xlnx,freq = <0x47868c0>; - xlnx,instance = "iomodule_1"; - xlnx,io-mask = <0xfffe0000>; - xlnx,lmb-awidth = <0x20>; - xlnx,lmb-dwidth = <0x20>; - xlnx,mask = <0xffffff80>; - xlnx,use-io-bus = <0x01>; - phandle = <0x1b5>; - - pmc_ppu0_intc@0C { - #interrupt-cells = <0x01>; - compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; - interrupt-controller; - interrupts-extended = <0xc0 0x00>; - reg = <0x00 0xf008000c 0x04 0x00 0xf0080030 0x10 0x00 -0xf0080080 0x7c>; - xlnx,intc-addr-width = <0x20>; - xlnx,intc-base-vectors = <0x00>; - xlnx,intc-has-fast = <0x00>; - xlnx,intc-intr-size = <0x10>; - xlnx,intc-level-edge = <0x00>; - xlnx,intc-positive = <0xffff>; - xlnx,intc-use-ext-intr = <0x01>; - phandle = <0x86>; - }; - - pmc_ppu0_gpi@20 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x86>; - interrupts = <0x0b>; - reg = <0x00 0xf0080020 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1b6>; - }; - - pmc_ppu0_gpi@24 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x86>; - interrupts = <0x0c>; - reg = <0x00 0xf0080024 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1b7>; - }; - - pmc_ppu0_gpi@28 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x86>; - interrupts = <0x0d>; - reg = <0x00 0xf0080028 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1b8>; - }; - - pmc_ppu0_gpi@2c { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x86>; - interrupts = <0x0e>; - reg = <0x00 0xf008002c 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1b9>; - }; - - pmc_ppu0_gpo@10 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0080010 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x09>; - xlnx,use-gpo = <0x01>; - phandle = <0xc1>; - }; - - pmc_ppu0_gpo@14 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0080014 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1ba>; - }; - - pmc_ppu0_gpo@18 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0080018 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1bb>; - }; - - pmc_ppu0_gpo@1c { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf008001c 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1bc>; - }; - - pmc_ppu0_pit@40 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x86>; - interrupts = <0x03>; - reg = <0x00 0xf0080040 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xc1 0x01 0xc2 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1bd>; - }; - - pmc_ppu0_pit@50 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x86>; - interrupts = <0x04>; - reg = <0x00 0xf0080050 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xc2>; - }; - - pmc_ppu0_pit@60 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x86>; - interrupts = <0x05>; - reg = <0x00 0xf0080060 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xc1 0x06 0xc3 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1be>; - }; - - pmc_ppu0_pit@70 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x86>; - interrupts = <0x06>; - reg = <0x00 0xf0080070 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xc3>; - }; - }; - }; - - lmb_pmc_ppu1@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "LMB PPU1"; - doc-status = "complete"; - phandle = <0xc4>; - - main_bus_for_pmc { - compatible = "qemu:memory-region"; - alias = <0x74>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - - io-module@00 { - doc-status = "complete"; - #address-cells = <0x02>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; - container = <0xc4>; - priority = <0xffffffff>; - xlnx,freq = <0x47868c0>; - xlnx,instance = "iomodule_1"; - xlnx,io-mask = <0xfffe0000>; - xlnx,lmb-awidth = <0x20>; - xlnx,lmb-dwidth = <0x20>; - xlnx,mask = <0xffffff80>; - xlnx,use-io-bus = <0x01>; - phandle = <0x1bf>; - - pmc_ppu1_intc@0C { - #interrupt-cells = <0x01>; - compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; - interrupt-controller; - interrupts-extended = <0xc5 0x00>; - reg = <0x00 0xf030000c 0x04 0x00 0xf0300030 0x10 0x00 -0xf0300080 0x7c>; - xlnx,intc-addr-width = <0x20>; - xlnx,intc-base-vectors = <0x00>; - xlnx,intc-has-fast = <0x00>; - xlnx,intc-intr-size = <0x10>; - xlnx,intc-level-edge = <0x00>; - xlnx,intc-positive = <0xffff>; - xlnx,intc-use-ext-intr = <0x01>; - phandle = <0x08>; - }; - - pmc_ppu1_gpi@20 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x08>; - interrupts = <0x0b>; - reg = <0x00 0xf0300020 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1c0>; - }; - - pmc_ppu1_gpi@24 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x08>; - interrupts = <0x0c>; - reg = <0x00 0xf0300024 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1c1>; - }; - - pmc_ppu1_gpi@28 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x08>; - interrupts = <0x0d>; - reg = <0x00 0xf0300028 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1c2>; - }; - - pmc_ppu1_gpi@2c { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; - interrupt-parent = <0x08>; - interrupts = <0x0e>; - reg = <0x00 0xf030002c 0x04>; - xlnx,gpi-interrupt = <0x01>; - xlnx,gpi-size = <0x20>; - xlnx,use-gpi = <0x01>; - phandle = <0x1c3>; - }; - - pmc_ppu1_gpo@10 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0300010 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x09>; - xlnx,use-gpo = <0x01>; - phandle = <0xc6>; - }; - - pmc_ppu1_gpo@14 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0300014 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1c4>; - }; - - pmc_ppu1_gpo@18 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf0300018 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1c5>; - }; - - pmc_ppu1_gpo@1c { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0xf030001c 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x20>; - xlnx,use-gpo = <0x01>; - phandle = <0x1c6>; - }; - - pmc_ppu1_pit@40 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x08>; - interrupts = <0x03>; - reg = <0x00 0xf0300040 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x5f5e100>; - gpios = <0xc6 0x01 0xc7 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1c7>; - }; - - pmc_ppu1_pit@50 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x08>; - interrupts = <0x04>; - reg = <0x00 0xf0300050 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x5f5e100>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xc7>; - }; - - pmc_ppu1_pit@60 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x08>; - interrupts = <0x05>; - reg = <0x00 0xf0300060 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x5f5e100>; - gpios = <0xc6 0x06 0xc8 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - windows-frequency = <0x13d620>; - phandle = <0x1c8>; - }; - - pmc_ppu1_pit@70 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0x08>; - interrupts = <0x06>; - reg = <0x00 0xf0300070 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x5f5e100>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xc8>; - }; - }; - }; - - lmb_psm@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x1c9>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - main_bus_for_pmc { - compatible = "qemu:memory-region"; - alias = <0x14>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - lmb_ddrmc@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - doc-name = "LMB DDRMC0"; - doc-status = "partial"; - phandle = <0xc9>; - - ddrmc0_ram_data@0x1c000 { - reg = <0x00 0x1c000 0x00 0x4000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1ca>; - }; - - ddrmc0_ram_instr@0x20000 { - reg = <0x00 0x20000 0x00 0x20000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1cb>; - }; - - ddrmc0_ram_exchange@0x08000 { - reg = <0x00 0x8000 0x00 0x8000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1cc>; - }; - - io-module@00 { - doc-status = "complete"; - #address-cells = <0x02>; - #size-cells = <0x01>; - #priority-cells = <0x00>; - compatible = "simple-bus"; - container = <0xc9>; - priority = <0xffffffff>; - phandle = <0x1cd>; - - ddrmc0_intc@0C { - #interrupt-cells = <0x01>; - compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; - interrupt-controller; - interrupts-extended = <0xca 0x00>; - reg = <0x00 0x1b00c 0x04 0x00 0x1b030 0x10 0x00 0x1b080 0x7c>; - xlnx,intc-addr-width = <0x20>; - xlnx,intc-base-vectors = <0x00>; - xlnx,intc-has-fast = <0x00>; - xlnx,intc-intr-size = <0x10>; - xlnx,intc-level-edge = <0x00>; - xlnx,intc-positive = <0xffff>; - xlnx,intc-use-ext-intr = <0x01>; - phandle = <0xcb>; - }; - - ddrmc0_gpo@10 { - #gpio-cells = <0x01>; - gpio-controller; - compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; - reg = <0x00 0x1b010 0x04>; - xlnx,gpo-init = <0x00>; - xlnx,gpo-size = <0x03>; - xlnx,use-gpo = <0x01>; - phandle = <0xcc>; - }; - - ddrmc0_pit@40 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0xcb>; - interrupts = <0x03>; - reg = <0x00 0x1b040 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xcc 0x01 0xcd 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1ce>; - }; - - ddrmc0_pit@50 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0xcb>; - interrupts = <0x04>; - reg = <0x00 0x1b050 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xcd>; - }; - - ddrmc0_pit@60 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0xcb>; - interrupts = <0x05>; - reg = <0x00 0x1b060 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpios = <0xcc 0x06 0xce 0x00>; - gpio-names = "ps_config\0ps_hit_in"; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x1cf>; - }; - - ddrmc0_pit@70 { - compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; - interrupt-parent = <0xcb>; - interrupts = <0x06>; - reg = <0x00 0x1b070 0x0c>; - xlnx,pit-interrupt = <0x01>; - xlnx,pit-prescaler = <0x09>; - xlnx,pit-readable = <0x01>; - xlnx,pit-size = <0x20>; - xlnx,use-pit = <0x01>; - frequency = <0x1b6b0b00>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0xce>; - }; - }; - - ddrmc_uart0@0 { - compatible = "xlnx,io_uart"; - reg = <0x00 0x1b000 0x0c 0x1b04c 0x04>; - xlnx,use-uart-rx = <0x01>; - xlnx,use-uart-tx = <0x01>; - chardev = "ddrmc-uart0\0serial1"; - phandle = <0x1d0>; - }; - - alias_npi_ddrmc_main { - compatible = "qemu:memory-region"; - alias = <0xcf>; - reg = <0x00 0x00 0x00 0x8000 0x00>; - }; - }; - - lmb_ddrmc@1 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x1d1>; - - ddrmc1_ram_data@0x1c000 { - reg = <0x00 0x1c000 0x00 0x4000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1d2>; - }; - - ddrmc1_ram_instr@0x20000 { - reg = <0x00 0x20000 0x00 0x20000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1d3>; - }; - - ddrmc1_ram_exchange@0x08000 { - reg = <0x00 0x8000 0x00 0x8000 0x01>; - compatible = "qemu:memory-region"; - qemu,ram = <0x01>; - phandle = <0x1d4>; - }; - }; - - amba_rpu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xd0>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - - timer_a { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x02>; - interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; - clock-frequency = <0x5f5e100>; - }; - - timer_b { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x03>; - interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; - clock-frequency = <0x5f5e100>; - }; - - timer_c { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x04>; - interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; - clock-frequency = <0x5f5e100>; - }; - - timer_d { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x05>; - interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; - clock-frequency = <0x5f5e100>; - }; - - timer_e { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x06>; - interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; - clock-frequency = <0x5f5e100>; - }; - }; - - amba_r5@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xe3>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x35>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic0 { - compatible = "qemu:memory-region"; - alias = <0xd1>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - }; - - amba_r5@1 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xe6>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x37>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic0 { - compatible = "qemu:memory-region"; - alias = <0xd1>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - }; - - dummy1@0 { - doc-ignore = <0x01>; - interrupt-controller; - #interrupt-cells = <0x01>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x96>; - }; - - tbu0_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x17>; - }; - - tbu1_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x5c>; - }; - - tbu2_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x5d>; - }; - - tbu3_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x5e>; - }; - - tbu4_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x5f>; - }; - - tbu5_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x60>; - }; - - tbu6_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x61>; - }; - - memory@00000000 { - compatible = "qemu:memory-region"; - device_type = "memory"; - container = <0x0d>; - phandle = <0x102>; - }; - - memory@8_0000_0000 { - compatible = "qemu:memory-region"; - device_type = "memory"; - container = <0x0d>; - phandle = <0x103>; - }; - - memory@0x50000000000ULL { - compatible = "qemu:memory-region"; - device_type = "memory"; - container = <0x0d>; - phandle = <0x1d5>; - }; - - ocm_mem_bank_0@ { - compatible = "qemu:memory-region"; - container = <0x0e>; - qemu,ram = <0x01>; - reg = <0x00 0x100000 0x00 0x80000 0x00>; - phandle = <0x1d6>; - }; - - ocm_mem_bank_1@ { - compatible = "qemu:memory-region"; - container = <0x0e>; - qemu,ram = <0x01>; - reg = <0x00 0x180000 0x00 0x80000 0x00>; - phandle = <0x1d7>; - }; - - ocm_mem_bank_2@ { - compatible = "qemu:memory-region"; - container = <0x0e>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x80000 0x00>; - phandle = <0x1d8>; - }; - - ocm_mem_bank_3@ { - compatible = "qemu:memory-region"; - container = <0x0e>; - qemu,ram = <0x01>; - reg = <0x00 0x80000 0x00 0x80000 0x00>; - phandle = <0x1d9>; - }; - - xram_mem@0xbbe00000 { - compatible = "qemu:memory-region"; - phandle = <0x1da>; - }; - - ipi_msgbuf@0 { - compatible = "qemu:memory-region"; - device_type = "memory"; - container = <0x0a>; - qemu,ram = <0x01>; - reg = <0x00 0xeb3f0000 0x00 0x1000 0x00>; - phandle = <0x1db>; - }; - - pmc_ram@0xf2000000 { - compatible = "qemu:memory-region"; - phandle = <0x73>; - }; - - pmc_ram_bank_0@0x0 { - compatible = "qemu:memory-region"; - container = <0x73>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x20000 0x00>; - phandle = <0x1dc>; - }; - - pmc_ppu1_ram@0xf0200000 { - compatible = "qemu:memory-region"; - container = <0x0d>; - qemu,ram = <0x01>; - reg = <0x00 0xf0200000 0x00 0x80000 0x00>; - phandle = <0x1dd>; - }; - - pmc_ppu1_ram@0xf0280000 { - compatible = "qemu:memory-region"; - container = <0x0d>; - qemu,ram = <0x01>; - reg = <0x00 0xf0280000 0x00 0x20000 0x00>; - phandle = <0x1de>; - }; - - ppu0_mdm_uart@0xf0110000 { - doc-status = "complete"; - compatible = "xlnx,xps-uartlite"; - reg-extended = <0xa1 0x00 0xf0110000 0x00 0x10 0x01>; - chardev = "serial0"; - }; - - ppu1_mdm_uart@0xf0310000 { - doc-status = "complete"; - compatible = "xlnx,xps-uartlite"; - reg-extended = <0xc4 0x00 0xf0310000 0x00 0x10 0x01>; - chardev = "serial1"; - }; - - lqspi_mr@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x80>; - }; - - lospi_mr@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x82>; - }; - - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; - - apu_cpu@0 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x00>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 0"; - #interrupt-cells = <0x01>; - memattr_s = <0xd3>; - memattr_ns = <0xd4>; - reset-gpios = <0x52 0x00>; - gpios = <0x1b 0x40>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x00>; - mp-affinity = <0x1000000>; - generic-timer-frequency = <0x298100>; - phandle = <0x53>; - }; - - apu_cpu@1 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x01>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 1"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xd5>; - memattr_ns = <0xd6>; - reset-gpios = <0x52 0x01>; - gpios = <0x1b 0x41>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x01>; - mp-affinity = <0x1000100>; - generic-timer-frequency = <0x298100>; - phandle = <0x54>; - }; - - apu_cpu@2 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x02>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 2"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xd7>; - memattr_ns = <0xd8>; - reset-gpios = <0x52 0x04>; - gpios = <0x1b 0x42>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x02>; - mp-affinity = <0x1010000>; - generic-timer-frequency = <0x298100>; - phandle = <0x56>; - }; - - apu_cpu@3 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x03>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 3"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xd9>; - memattr_ns = <0xda>; - reset-gpios = <0x52 0x05>; - gpios = <0x1b 0x43>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x03>; - mp-affinity = <0x1010100>; - generic-timer-frequency = <0x298100>; - phandle = <0x57>; - }; - - apu_cpu@4 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x04>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 4"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xdb>; - memattr_ns = <0xdc>; - reset-gpios = <0x52 0x08>; - gpios = <0x1b 0x44>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x04>; - mp-affinity = <0x1020000>; - generic-timer-frequency = <0x298100>; - phandle = <0x58>; - }; - - apu_cpu@5 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x05>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 5"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xdd>; - memattr_ns = <0xde>; - reset-gpios = <0x52 0x09>; - gpios = <0x1b 0x45>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x05>; - mp-affinity = <0x1020100>; - generic-timer-frequency = <0x298100>; - phandle = <0x59>; - }; - - apu_cpu@6 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x06>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 6"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xdf>; - memattr_ns = <0xe0>; - reset-gpios = <0x52 0x0c>; - gpios = <0x1b 0x46>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x06>; - mp-affinity = <0x1030000>; - generic-timer-frequency = <0x298100>; - phandle = <0x5a>; - }; - - apu_cpu@7 { - compatible = "cortex-a78-arm-cpu"; - device_type = "cpu"; - arm,ccsidr0 = <0x701fe00a>; - arm,ccsidr1 = <0x201fe012>; - reg = <0x07>; - core-count = <0x02>; - arm,reset-hivecs = <0x01>; - arm,rvbar = <0xffff0000>; - arm,reset-cbar = <0xe2060000>; - mr = <0xd2>; - memory = <0xd2>; - qemu,halt = <0x01>; - gdb-id = "Cortex-A78 7"; - #interrupt-cells = <0x01>; - direct-lnx-start-powered-off = <0x01>; - start-powered-off = <0x00>; - memattr_s = <0xe1>; - memattr_ns = <0xe2>; - reset-gpios = <0x52 0x0d>; - gpios = <0x1b 0x47>; - gpio-names = "wfi"; - power-gpios = <0x1b 0x07>; - mp-affinity = <0x1030100>; - generic-timer-frequency = <0x298100>; - phandle = <0x5b>; - }; - - rpu_a@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - phandle = <0x1df>; - - rpu_cpu_a@0 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x00>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xe3>; - qemu,halt = <0x01>; - memattr_ns = <0xe4>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #a0"; - gpios = <0x1a 0x23 0xe5 0x00 0x1b 0x48>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x08>; - phandle = <0x2a>; - }; - - rpu_cpu_a@1 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x01>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xe6>; - qemu,halt = <0x01>; - memattr_ns = <0xe7>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #a1"; - gpios = <0x1a 0x24 0xe8 0x00 0x1b 0x49>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x09>; - phandle = <0x2b>; - }; - }; - - rpu_b@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - phandle = <0x1e0>; - - rpu_cpu_b@0 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x100>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xe9>; - qemu,halt = <0x01>; - memattr_ns = <0xea>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #b0"; - gpios = <0x1a 0x25 0xeb 0x00 0x1b 0x4a>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0a>; - phandle = <0x2c>; - }; - - rpu_cpu_b@1 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x101>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xec>; - qemu,halt = <0x01>; - memattr_ns = <0xed>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #b1"; - gpios = <0x1a 0x26 0xee 0x00 0x1b 0x4b>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0b>; - phandle = <0x2d>; - }; - }; - - rpu_c@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - phandle = <0x1e1>; - - rpu_cpu_c@0 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x200>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xef>; - qemu,halt = <0x01>; - memattr_ns = <0xf0>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #c0"; - gpios = <0x1a 0x27 0xf1 0x00 0x1b 0x4c>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0c>; - phandle = <0x2e>; - }; - - rpu_cpu_c@1 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x201>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xf2>; - qemu,halt = <0x01>; - memattr_ns = <0xf3>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #c1"; - gpios = <0x1a 0x28 0xf4 0x00 0x1b 0x4d>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0d>; - phandle = <0x2f>; - }; - }; - - rpu_d@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - phandle = <0x1e2>; - - rpu_cpu_d@0 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x300>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xf5>; - qemu,halt = <0x01>; - memattr_ns = <0xf6>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #d0"; - gpios = <0x1a 0x29 0xf7 0x00 0x1b 0x4e>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0e>; - phandle = <0x30>; - }; - - rpu_cpu_d@1 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x301>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xf8>; - qemu,halt = <0x01>; - memattr_ns = <0xf9>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #d1"; - gpios = <0x1a 0x2a 0xfa 0x00 0x1b 0x4f>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x0f>; - phandle = <0x31>; - }; - }; - - rpu_e@0 { - #address-cells = <0x01>; - #size-cells = <0x00>; - phandle = <0x1e3>; - - rpu_cpu_e@0 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x400>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xfb>; - qemu,halt = <0x01>; - memattr_ns = <0xfc>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #e0"; - gpios = <0x1a 0x2b 0xfd 0x00 0x1b 0x50>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x10>; - phandle = <0x32>; - }; - - rpu_cpu_e@1 { - compatible = "cortex-r52-arm-cpu"; - device_type = "cpu"; - arm,tcmtr = <0x10001>; - arm,ctr = <0x8003c003>; - arm,clidr = <0x9200003>; - arm,ccsidr0 = <0xf01fe019>; - arm,ccsidr1 = <0xf01fe019>; - arm,mp-affinity = <0x401>; - arm,id_pfr0 = <0x131>; - arm,reset-hivecs = <0x01>; - #interrupt-cells = <0x01>; - memory = <0xfe>; - qemu,halt = <0x01>; - memattr_ns = <0xff>; - core-count = <0x02>; - gdb-id = "Cortex-R52 #e1"; - gpios = <0x1a 0x2c 0x100 0x00 0x1b 0x51>; - gpio-names = "reset\0halt\0wfi"; - reset-cbar = <0xe2000000>; - power-gpios = <0x1b 0x11>; - phandle = <0x33>; - }; - }; - }; - - amba_apu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xd2>; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <0x01>; - interrupts = <0x1000001 0x0d 0xffffff01 0x1000001 0x0e 0xffffff01 0x1000001 -0x0b 0xffffff01 0x1000001 0x0a 0xffffff01>; - clock-frequency = <0x5f5e100>; - phandle = <0x1e4>; - }; - }; - - amba_apu_gic@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - container = <0x0b>; - priority = <0xffffffff>; - phandle = <0x1e5>; - - interrupt-controller@0xe2000000 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0xe2000000 0x00 0x10000 0x00 0x00 0xe2060000 -0x00 0x400000 0x00>; - interrupt-controller; - interrupts-extended = <0x53 0x00 0x54 0x00 0x56 0x00 0x57 0x00 0x58 0x00 -0x59 0x00 0x5a 0x00 0x5b 0x00 0x53 0x01 0x54 0x01 0x56 0x01 0x57 0x01 0x58 0x01 0x59 0x01 0x5a -0x01 0x5b 0x01 0x53 0x02 0x54 0x02 0x56 0x02 0x57 0x02 0x58 0x02 0x59 0x02 0x5a 0x02 0x5b 0x02 -0x53 0x03 0x54 0x03 0x56 0x03 0x57 0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b 0x03 0x01 0x01 0x09 -0x104 0x01 0x01 0x09 0x204 0x01 0x01 0x09 0x404 0x01 0x01 0x09 0x804 0x01 0x01 0x09 0x1004 -0x01 0x01 0x09 0x2004 0x01 0x01 0x09 0x4004 0x01 0x01 0x09 0x8004>; - num-cpu = <0x08>; - num-irq = <0x220>; - has-security-extensions = <0x01>; - redist-region-count = <0x08>; - has-lpi = <0x01>; - sysmem = <0x0d>; - phandle = <0x01>; - }; - - git_its@0xe2040000 { - compatible = "arm-gicv3-its"; - reg = <0x00 0xe2040000 0x00 0x20000 0x00>; - parent-gicv3 = <0x01>; - }; - }; - - lpd_reset_domain@0 { - compatible = "qemu,reset-domain"; - mr0 = <0x0a>; - reset-gpios = <0x7e 0x07 0x7e 0x0a>; - }; - - fpd_reset_domain@0 { - compatible = "qemu,reset-domain"; - mr0 = <0x0b>; - reset-gpios = <0x7e 0x07 0x7e 0x0a 0x1a 0x1c 0x1a 0x1d>; - }; - - amba_alias@0 { - compatible = "qemu:memory-region"; - container = <0x101>; - alias = <0x0d>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x01>; - phandle = <0x1e6>; - }; - - qemu_sysmem@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:system-memory"; - phandle = <0x101>; - }; - - dummy_ppu0@0 { - #interrupt-cells = <0x01>; - phandle = <0xc0>; - }; - - dummy_ppu1@0 { - #interrupt-cells = <0x01>; - phandle = <0xc5>; - }; - - dummy_ddrmc0@0 { - #interrupt-cells = <0x01>; - phandle = <0xca>; - }; - - dummy_ddrmc1@0 { - #interrupt-cells = <0x01>; - phandle = <0x1e7>; - }; - - ddr@0x00000000 { - compatible = "qemu:memory-region"; - container = <0x102>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x80000000 0x00>; - phandle = <0xa2>; - }; - - ddr_2@0x800000000ULL { - compatible = "qemu:memory-region-spec"; - container = <0x103>; - qemu,ram = <0x01>; - reg = <0x08 0x00 0x08 0x00 0x00>; - phandle = <0x1e8>; - }; - - mdio { - #address-cells = <0x01>; - #size-cells = <0x00>; - #priority-cells = <0x00>; - compatible = "mdio"; - phandle = <0x1c>; - - phy@1 { - compatible = "dp83867"; - device_type = "ethernet-phy"; - reg = <0x01>; - phandle = <0x1e9>; - }; - - phy@2 { - compatible = "88e1118r"; - device_type = "ethernet-phy"; - reg = <0x02>; - phandle = <0x1ea>; - }; - }; - - cpu_dummy { - phandle = <0x55>; - }; - - tbu7_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x62>; - }; - - tbu8_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x63>; - }; - - tbu9_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x64>; - }; - - tbu10_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x65>; - }; - - tbu11_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x66>; - }; - - tbu12_slave@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x67>; - }; - - mr_rpu_gic_a@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - phandle = <0xd1>; - - rpu_gic_a@0x0 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; - interrupt-controller; - interrupts-extended = <0x2a 0x00 0x2b 0x00 0x2a 0x01 0x2b 0x01 0x2a 0x02 -0x2b 0x02 0x2a 0x03 0x2b 0x03 0x02 0x01 0x09 0x104 0x02 0x01 0x09 0x204>; - first-cpu-idx = <0x08>; - num-cpu = <0x02>; - num-irq = <0x120>; - redist-region-count = <0x02>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x02>; - }; - }; - - mr_rpu_gic_b@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - phandle = <0x104>; - - rpu_gic_b@0x0 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; - interrupt-controller; - interrupts-extended = <0x2c 0x00 0x2d 0x00 0x2c 0x01 0x2d 0x01 0x2c 0x02 -0x2d 0x02 0x2c 0x03 0x2d 0x03 0x03 0x01 0x09 0x104 0x03 0x01 0x09 0x204>; - first-cpu-idx = <0x0a>; - num-cpu = <0x02>; - num-irq = <0x120>; - redist-region-count = <0x02>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x03>; - }; - }; - - mr_rpu_gic_c@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - phandle = <0x105>; - - rpu_gic_c@0x0 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; - interrupt-controller; - interrupts-extended = <0x2e 0x00 0x2f 0x00 0x2e 0x01 0x2f 0x01 0x2e 0x02 -0x2f 0x02 0x2e 0x03 0x2f 0x03 0x04 0x01 0x09 0x104 0x04 0x01 0x09 0x204>; - first-cpu-idx = <0x0c>; - num-cpu = <0x02>; - num-irq = <0x120>; - redist-region-count = <0x02>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x04>; - }; - }; - - mr_rpu_gic_d@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - phandle = <0x106>; - - rpu_gic_d@0x0 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; - interrupt-controller; - interrupts-extended = <0x30 0x00 0x31 0x00 0x30 0x01 0x31 0x01 0x30 0x02 -0x31 0x02 0x30 0x03 0x31 0x03 0x05 0x01 0x09 0x104 0x05 0x01 0x09 0x204>; - first-cpu-idx = <0x0e>; - num-cpu = <0x02>; - num-irq = <0x120>; - redist-region-count = <0x02>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x05>; - }; - }; - - mr_rpu_gic_e@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - phandle = <0x107>; - - rpu_gic_e@0x0 { - #address-cells = <0x00>; - #size-cells = <0x00>; - #interrupt-cells = <0x03>; - compatible = "arm-gicv3"; - reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; - interrupt-controller; - interrupts-extended = <0x32 0x00 0x33 0x00 0x32 0x01 0x33 0x01 0x32 0x02 -0x33 0x02 0x32 0x03 0x33 0x03 0x06 0x01 0x09 0x104 0x06 0x01 0x09 0x204>; - first-cpu-idx = <0x10>; - num-cpu = <0x02>; - num-irq = <0x120>; - redist-region-count = <0x02>; - gpio-controller; - #gpio-cells = <0x01>; - phandle = <0x06>; - }; - }; - - tcm_core@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x35>; - - atcm_rpu_core0@0x00000 { - compatible = "qemu:memory-region"; - container = <0x35>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1eb>; - }; - - btcm_rpu_core0@0x00000 { - compatible = "qemu:memory-region"; - container = <0x35>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1ec>; - }; - - ctcm_rpu_core0@0x00000 { - compatible = "qemu:memory-region"; - container = <0x35>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1ed>; - }; - }; - - tcm_core@1 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x37>; - - atcm_rpu_core1@0x00000 { - compatible = "qemu:memory-region"; - container = <0x37>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1ee>; - }; - - btcm_rpu_core1@0x00000 { - compatible = "qemu:memory-region"; - container = <0x37>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1ef>; - }; - - ctcm_rpu_core1@0x00000 { - compatible = "qemu:memory-region"; - container = <0x37>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1f0>; - }; - }; - - tcm_core@2 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x39>; - - atcm_rpu_core2@0x00000 { - compatible = "qemu:memory-region"; - container = <0x39>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1f1>; - }; - - btcm_rpu_core2@0x00000 { - compatible = "qemu:memory-region"; - container = <0x39>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1f2>; - }; - - ctcm_rpu_core2@0x00000 { - compatible = "qemu:memory-region"; - container = <0x39>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1f3>; - }; - }; - - tcm_core@3 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x3b>; - - atcm_rpu_core3@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3b>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1f4>; - }; - - btcm_rpu_core3@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3b>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1f5>; - }; - - ctcm_rpu_core3@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3b>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1f6>; - }; - }; - - tcm_core@4 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x3d>; - - atcm_rpu_core4@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3d>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1f7>; - }; - - btcm_rpu_core4@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3d>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1f8>; - }; - - ctcm_rpu_core4@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3d>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1f9>; - }; - }; - - tcm_core@5 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x3f>; - - atcm_rpu_core5@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3f>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1fa>; - }; - - btcm_rpu_core5@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3f>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1fb>; - }; - - ctcm_rpu_core5@0x00000 { - compatible = "qemu:memory-region"; - container = <0x3f>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1fc>; - }; - }; - - tcm_core@6 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x41>; - - atcm_rpu_core6@0x00000 { - compatible = "qemu:memory-region"; - container = <0x41>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x1fd>; - }; - - btcm_rpu_core6@0x00000 { - compatible = "qemu:memory-region"; - container = <0x41>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x1fe>; - }; - - ctcm_rpu_core6@0x00000 { - compatible = "qemu:memory-region"; - container = <0x41>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x1ff>; - }; - }; - - tcm_core@7 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x43>; - - atcm_rpu_core7@0x00000 { - compatible = "qemu:memory-region"; - container = <0x43>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x200>; - }; - - btcm_rpu_core7@0x00000 { - compatible = "qemu:memory-region"; - container = <0x43>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x201>; - }; - - ctcm_rpu_core7@0x00000 { - compatible = "qemu:memory-region"; - container = <0x43>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x202>; - }; - }; - - tcm_core@8 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x45>; - - atcm_rpu_core8@0x00000 { - compatible = "qemu:memory-region"; - container = <0x45>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x203>; - }; - - btcm_rpu_core8@0x00000 { - compatible = "qemu:memory-region"; - container = <0x45>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x204>; - }; - - ctcm_rpu_core8@0x00000 { - compatible = "qemu:memory-region"; - container = <0x45>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x205>; - }; - }; - - tcm_core@9 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x47>; - - atcm_rpu_core9@0x00000 { - compatible = "qemu:memory-region"; - container = <0x47>; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x10000 0x00>; - phandle = <0x206>; - }; - - btcm_rpu_core9@0x00000 { - compatible = "qemu:memory-region"; - container = <0x47>; - qemu,ram = <0x01>; - reg = <0x00 0x10000 0x00 0x10000 0x00>; - phandle = <0x207>; - }; - - ctcm_rpu_core9@0x00000 { - compatible = "qemu:memory-region"; - container = <0x47>; - qemu,ram = <0x01>; - reg = <0x00 0x20000 0x00 0x10000 0x00>; - phandle = <0x208>; - }; - }; - - tcm_cluster_a@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x0f>; - - tcm_core_0 { - compatible = "qemu:memory-region"; - alias = <0x35>; - reg = <0x00 0x00 0x00 0x40000 0x00>; - }; - - tcm_core_1 { - compatible = "qemu:memory-region"; - alias = <0x37>; - reg = <0x00 0x40000 0x00 0x40000 0x00>; - }; - }; - - tcm_cluster_b@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x10>; - - tcm_core_0 { - compatible = "qemu:memory-region"; - alias = <0x39>; - reg = <0x00 0x00 0x00 0x40000 0x00>; - }; - - tcm_core_1 { - compatible = "qemu:memory-region"; - alias = <0x3b>; - reg = <0x00 0x40000 0x00 0x40000 0x00>; - }; - }; - - tcm_cluster_c@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x11>; - - tcm_core_0 { - compatible = "qemu:memory-region"; - alias = <0x3d>; - reg = <0x00 0x00 0x00 0x40000 0x00>; - }; - - tcm_core_1 { - compatible = "qemu:memory-region"; - alias = <0x3f>; - reg = <0x00 0x40000 0x00 0x40000 0x00>; - }; - }; - - tcm_cluster_d@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x12>; - - tcm_core_0 { - compatible = "qemu:memory-region"; - alias = <0x41>; - reg = <0x00 0x00 0x00 0x40000 0x00>; - }; - - tcm_core_1 { - compatible = "qemu:memory-region"; - alias = <0x43>; - reg = <0x00 0x40000 0x00 0x40000 0x00>; - }; - }; - - tcm_cluster_e@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "qemu:memory-region"; - phandle = <0x13>; - - tcm_core_0 { - compatible = "qemu:memory-region"; - alias = <0x45>; - reg = <0x00 0x00 0x00 0x40000 0x00>; - }; - - tcm_core_1 { - compatible = "qemu:memory-region"; - alias = <0x47>; - reg = <0x00 0x40000 0x00 0x40000 0x00>; - }; - }; - - amba_r5@2 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xe9>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x39>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic1 { - compatible = "qemu:memory-region"; - alias = <0x104>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@3 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xec>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x3b>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic1 { - compatible = "qemu:memory-region"; - alias = <0x104>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@4 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xef>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x3d>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic2 { - compatible = "qemu:memory-region"; - alias = <0x105>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@5 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xf2>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x3f>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic2 { - compatible = "qemu:memory-region"; - alias = <0x105>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@6 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xf5>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x41>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic3 { - compatible = "qemu:memory-region"; - alias = <0x106>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@7 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xf8>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x43>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic3 { - compatible = "qemu:memory-region"; - alias = <0x106>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@8 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xfb>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x45>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic4 { - compatible = "qemu:memory-region"; - alias = <0x107>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - amba_r5@9 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0xfe>; - - downstream_tcm { - compatible = "qemu:memory-region"; - alias = <0x47>; - reg = <0x00 0x00 0x00 0x400000 0x01>; - }; - - downstream_gic4 { - compatible = "qemu:memory-region"; - alias = <0x107>; - reg = <0x00 0xe2000000 0x00 0x140000 0x01>; - }; - - downstream_amba { - compatible = "qemu:memory-region"; - alias = <0xd0>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - rpu2_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x208>; - phandle = <0xea>; - }; - - rpu3_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x20c>; - phandle = <0xed>; - }; - - rpu4_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x208>; - phandle = <0xf0>; - }; - - rpu5_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x20c>; - phandle = <0xf3>; - }; - - rpu6_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x208>; - phandle = <0xf6>; - }; - - rpu7_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x20c>; - phandle = <0xf9>; - }; - - rpu8_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x208>; - phandle = <0xfc>; - }; - - rpu9_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x20c>; - phandle = <0xff>; - }; - - usb1_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x231>; - phandle = <0x48>; - }; - - apu2_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x262>; - phandle = <0xd7>; - }; - - apu2_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x262>; - phandle = <0xd8>; - }; - - apu3_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x263>; - phandle = <0xd9>; - }; - - apu3_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x263>; - phandle = <0xda>; - }; - - apu4_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x268>; - phandle = <0xdb>; - }; - - apu4_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x268>; - phandle = <0xdc>; - }; - - apu5_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x269>; - phandle = <0xdd>; - }; - - apu5_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x269>; - phandle = <0xde>; - }; - - apu6_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x26a>; - phandle = <0xdf>; - }; - - apu6_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x26a>; - phandle = <0xe0>; - }; - - apu7_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x26b>; - phandle = <0xe1>; - }; - - apu7_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x26b>; - phandle = <0xe2>; - }; - - apu8_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x270>; - phandle = <0x209>; - }; - - apu8_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x270>; - phandle = <0x20a>; - }; - - apu9_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x271>; - phandle = <0x20b>; - }; - - apu9_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x271>; - phandle = <0x20c>; - }; - - apu10_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x272>; - phandle = <0x20d>; - }; - - apu10_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x272>; - phandle = <0x20e>; - }; - - apu11_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x273>; - phandle = <0x20f>; - }; - - apu11_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x273>; - phandle = <0x210>; - }; - - apu12_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x278>; - phandle = <0x211>; - }; - - apu12_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x278>; - phandle = <0x212>; - }; - - apu13_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x279>; - phandle = <0x213>; - }; - - apu13_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x279>; - phandle = <0x214>; - }; - - apu14_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x27a>; - phandle = <0x215>; - }; - - apu14_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x27a>; - phandle = <0x216>; - }; - - apu15_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x27b>; - phandle = <0x217>; - }; - - apu15_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x27b>; - phandle = <0x218>; - }; - - apu16_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x280>; - phandle = <0x219>; - }; - - apu16_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x280>; - phandle = <0x21a>; - }; - - apu17_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x281>; - phandle = <0x21b>; - }; - - apu17_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x281>; - phandle = <0x21c>; - }; - - apu18_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x282>; - phandle = <0x21d>; - }; - - apu18_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x282>; - phandle = <0x21e>; - }; - - apu19_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x283>; - phandle = <0x21f>; - }; - - apu19_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x283>; - phandle = <0x220>; - }; - - apu20_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x288>; - phandle = <0x221>; - }; - - apu20_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x288>; - phandle = <0x222>; - }; - - apu21_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x289>; - phandle = <0x223>; - }; - - apu21_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x289>; - phandle = <0x224>; - }; - - apu22_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x28a>; - phandle = <0x225>; - }; - - apu22_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x28a>; - phandle = <0x226>; - }; - - apu23_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x28b>; - phandle = <0x227>; - }; - - apu23_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x28b>; - phandle = <0x228>; - }; - - apu24_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x290>; - phandle = <0x229>; - }; - - apu24_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x290>; - phandle = <0x22a>; - }; - - apu25_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x291>; - phandle = <0x22b>; - }; - - apu25_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x291>; - phandle = <0x22c>; - }; - - apu26_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x292>; - phandle = <0x22d>; - }; - - apu26_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x292>; - phandle = <0x22e>; - }; - - apu27_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x293>; - phandle = <0x22f>; - }; - - apu27_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x293>; - phandle = <0x230>; - }; - - apu28_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x298>; - phandle = <0x231>; - }; - - apu28_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x298>; - phandle = <0x232>; - }; - - apu29_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x299>; - phandle = <0x233>; - }; - - apu29_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x299>; - phandle = <0x234>; - }; - - apu30_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x29a>; - phandle = <0x235>; - }; - - apu30_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x29a>; - phandle = <0x236>; - }; - - apu31_s_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x01>; - requester-id = <0x29b>; - phandle = <0x237>; - }; - - apu31_ns_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x29b>; - phandle = <0x238>; - }; - - asu_cpu_ma { - doc-ignore = <0x01>; - compatible = "qemu:memory-transaction-attr"; - secure = <0x00>; - requester-id = <0x00>; - phandle = <0x239>; - }; - - lmb_amba_asu@0 { - #address-cells = <0x02>; - #size-cells = <0x02>; - #priority-cells = <0x01>; - compatible = "simple-bus"; - ranges; - phandle = <0x23a>; - - main_bus_for_asu { - compatible = "qemu:memory-region"; - alias = <0xb4>; - reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; - }; - }; - - ocm_mem@0xbbe00000 { - compatible = "qemu:memory-region"; - phandle = <0x0e>; - }; - - asu_data_ram_wrapper@0xebe40000 { - compatible = "qemu:memory-region"; - phandle = <0xbf>; - - asu_data_ram@0 { - compatible = "qemu:memory-region"; - device_type = "memory"; - qemu,ram = <0x01>; - reg = <0x00 0x00 0x00 0x20000 0x00>; - }; - }; - - psm_gic_proxy@0 { - #interrupt-cells = <0x03>; - interrupt-controller; - phandle = <0x23b>; - }; - - asu_cpu@0 { - #interrupt-cells = <0x01>; - phandle = <0xb5>; - }; - - __symbols__ { - pmc_ppu0_memattr = "/pmc_ppu0_ma"; - pmc_ppu1_memattr = "/pmc_ppu1_ma"; - psm_memattr = "/psm_ma"; - ddrmc_ub0_memattr = "/ddrmc_ub0_ma"; - ddrmc_ub1_memattr = "/ddrmc_ub1_ma"; - pmc_dma0_memattr = "/pmc_dma0_ma"; - pmc_dma1_memattr = "/pmc_dma1_ma"; - pmc_qspi_dma_memattr_smid = "/pmc_qspi_dma_ma_smid"; - pmc_qspi_dma_w_memattr_smid = "/pmc_qspi_dma_w_ma_smid"; - apu0_s_memattr = "/apu0_s_ma"; - apu0_ns_memattr = "/apu0_ns_ma"; - apu1_s_memattr = "/apu1_s_ma"; - apu1_ns_memattr = "/apu1_ns_ma"; - rpu0_s_memattr = "/rpu0_s_ma"; - rpu1_s_memattr = "/rpu1_s_ma"; - gem0_memattr_smid = "/gem0_ma_smid"; - gem0_w_memattr_smid = "/gem0_w_ma_smid"; - gem1_memattr_smid = "/gem1_ma_smid"; - gem1_w_memattr_smid = "/gem1_w_ma_smid"; - ospi_dma_memattr_smid = "/ospi_dma_ma_smid"; - ospi_dma_w_memattr_smid = "/ospi_dma_w_ma_smid"; - sd0_memattr_smid = "/sd0_ma_smid"; - sd0_w_memattr_smid = "/sd0_w_ma_smid"; - sd1_memattr_smid = "/sd1_ma_smid"; - sd1_w_memattr_smid = "/sd1_w_ma_smid"; - usb0_memattr = "/usb0_ma"; - amba_root = "/amba_root@0"; - amba = "/amba_root@0/amba@0"; - xmpu_ocm = "/amba_root@0/amba@0/xmpu_ocm@0"; - xmpu_ocm2 = "/amba_root@0/amba@0/xmpu_ocm2@0"; - loader_write_0xF1110880 = "/amba_root@0/amba@0/loader_write_cpu0_0x1@0xF1110880"; - loader_write_0xFD1A0050 = "/amba_root@0/amba@0/loader_write_cpu0_0x5@0xFD1A0050"; - loader_write_0xF111010C = "/amba_root@0/amba@0/loader_write_cpu0_0xFF@0xF111010C"; - s_axi_tcm_a = "/amba_root@0/amba@0/s_axi_tcm_a@0"; - s_axi_tcm_b = "/amba_root@0/amba@0/s_axi_tcm_b@0"; - s_axi_tcm_c = "/amba_root@0/amba@0/s_axi_tcm_c@0"; - s_axi_tcm_d = "/amba_root@0/amba@0/s_axi_tcm_d@0"; - s_axi_tcm_e = "/amba_root@0/amba@0/s_axi_tcm_e@0"; - loader_write_0xF12B0100 = "/amba_root@0/amba@0/loader_write_cpu0_0x80C@0xF12B0100"; - loader_write_0xF1260320 = "/amba_root@0/amba@0/loader_write_cpu0_0x77@0xF1260320"; - xmpu_ocm1 = "/amba_root@0/amba@0/xmpu_ocm1@0"; - xmpu_ocm3 = "/amba_root@0/amba@0/xmpu_ocm3@0"; - amba_lpd = "/amba_root@0/amba_lpd@0"; - xppu_lpd = "/amba_root@0/amba_lpd@0/xppu_lpd@0xeb990000"; - gem0 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a60000"; - gem1 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a70000"; - serial0 = "/amba_root@0/amba_lpd@0/serial@0xf1920000"; - serial1 = "/amba_root@0/amba_lpd@0/serial@0xf1930000"; - canfdbus0 = "/amba_root@0/amba_lpd@0/canfdbus@0"; - can0 = "/amba_root@0/amba_lpd@0/can@0xf19e0000"; - can1 = "/amba_root@0/amba_lpd@0/can@0xf19f0000"; - crl = "/amba_root@0/amba_lpd@0/crl@0xeb5e0000"; - lpd_iou_slcr = "/amba_root@0/amba_lpd@0/slcr@0xf1a20000"; - ipi = "/amba_root@0/amba_lpd@0/ipi@0xeb300000"; - spi0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000"; - spi0_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000/spi0_flash0@0"; - spi1 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000"; - spi1_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000/spi1_flash0@0"; - dwc3_0 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI"; - ttc0 = "/amba_root@0/amba_lpd@0/timer@0xf1e60000"; - ttc1 = "/amba_root@0/amba_lpd@0/timer@0xf1e70000"; - ttc2 = "/amba_root@0/amba_lpd@0/timer@0xf1e80000"; - ttc3 = "/amba_root@0/amba_lpd@0/timer@0xf1e90000"; - adma0_mattr = "/amba_root@0/amba_lpd@0/adma0mattr"; - adma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd00000"; - adma1_mattr = "/amba_root@0/amba_lpd@0/adma1mattr"; - adma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd10000"; - adma2_mattr = "/amba_root@0/amba_lpd@0/adma2mattr"; - adma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd20000"; - adma3_mattr = "/amba_root@0/amba_lpd@0/adma3mattr"; - adma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd30000"; - adma4_mattr = "/amba_root@0/amba_lpd@0/adma4mattr"; - adma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd40000"; - adma5_mattr = "/amba_root@0/amba_lpd@0/adma5mattr"; - adma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd50000"; - adma6_mattr = "/amba_root@0/amba_lpd@0/adma6mattr"; - adma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd60000"; - adma7_mattr = "/amba_root@0/amba_lpd@0/adma7mattr"; - adma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd70000"; - ps_i2c0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1940000"; - ps_i2c1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1950000"; - ps_i2c2 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1960000"; - ps_i2c3 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1970000"; - ps_i2c4 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1980000"; - ps_i2c5 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1990000"; - ps_i2c6 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19a0000"; - ps_i2c7 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19b0000"; - ocm_ctrl0 = "/amba_root@0/amba_lpd@0/ocm_ctrl@OCM"; - lpd_slcr = "/amba_root@0/amba_lpd@0/lpd_slcr@0xeb410000"; - lpd_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_slcr_secure@0xeb510000"; - lpd_iou_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_iou_slcr_secure@0xf1a40000"; - lpd_wwdt0 = "/amba_root@0/amba_lpd@0/wwdt@0xeb000000"; - lpd_gpio = "/amba_root@0/amba_lpd@0/lpd_gpio@0xf1a50000"; - rpu_ctrl = "/amba_root@0/amba_lpd@0/rpu_ctrl@0"; - rpu_ctrl_a = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb580000"; - rpu_ctrl_a0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a0@0xeb588000"; - rpu_ctrl_a1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a1@0xeb58c000"; - rpu_ctrl_b = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb590000"; - rpu_ctrl_b0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b0@0xeb598000"; - rpu_ctrl_b1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b1@0xeb59c000"; - rpu_ctrl_c = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5a0000"; - rpu_ctrl_c0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c0@0xeb5a8000"; - rpu_ctrl_c1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c1@0xeb5ac000"; - rpu_ctrl_d = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5b0000"; - rpu_ctrl_d0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d0@0xeb5b8000"; - rpu_ctrl_d1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d1@0xeb5bc000"; - rpu_ctrl_e = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5c0000"; - rpu_ctrl_e0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e0@0xeb5c8000"; - rpu_ctrl_e1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e1@0xeb5cc000"; - dwc3_1 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI1"; - psx_i3c0 = "/amba_root@0/amba_lpd@0/i3c0@0xf1940000"; - psx_i3c1 = "/amba_root@0/amba_lpd@0/i3c1@0xf1950000"; - ocm_ctrl1 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb960000"; - ocm_ctrl2 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb9d0000"; - ocm_ctrl3 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeaa00000"; - can2 = "/amba_root@0/amba_lpd@0/can@0xf1a00000"; - can3 = "/amba_root@0/amba_lpd@0/can@0xf1a10000"; - ttc4 = "/amba_root@0/amba_lpd@0/timer@0xf1ea0000"; - ttc5 = "/amba_root@0/amba_lpd@0/timer@0xf1eb0000"; - ttc6 = "/amba_root@0/amba_lpd@0/timer@0xf1ec0000"; - ttc7 = "/amba_root@0/amba_lpd@0/timer@0xf1ed0000"; - sdma0_mattr = "/amba_root@0/amba_lpd@0/sdma0mattr"; - sdma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd80000"; - sdma1_mattr = "/amba_root@0/amba_lpd@0/sdma1mattr"; - sdma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd90000"; - sdma2_mattr = "/amba_root@0/amba_lpd@0/sdma2mattr"; - sdma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebda0000"; - sdma3_mattr = "/amba_root@0/amba_lpd@0/sdma3mattr"; - sdma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdb0000"; - sdma4_mattr = "/amba_root@0/amba_lpd@0/sdma4mattr"; - sdma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdc0000"; - sdma5_mattr = "/amba_root@0/amba_lpd@0/sdma5mattr"; - sdma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdd0000"; - sdma6_mattr = "/amba_root@0/amba_lpd@0/sdma6mattr"; - sdma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebde0000"; - sdma7_mattr = "/amba_root@0/amba_lpd@0/sdma7mattr"; - sdma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdf0000"; - lpd_wwdt1 = "/amba_root@0/amba_lpd@0/wwdt@0xeb010000"; - lpd_afi_fs = "/amba_root@0/amba_lpd@0/lpd_afi_fs@0xeb560000"; - amba_fpd = "/amba_root@0/amba_fpd@0"; - wwdt0 = "/amba_root@0/amba_fpd@0/watchdog@0xecc10000"; - apu_cluster0 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecc00000"; - apu_cluster1 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecd00000"; - apu_cluster2 = "/amba_root@0/amba_fpd@0/apu_cluster@0xece00000"; - apu_cluster3 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecf00000"; - smmu = "/amba_root@0/amba_fpd@0/smmuv3@MM_FPD_SMMU"; - pcie = "/amba_root@0/amba_fpd@0/dummy_pcie@0x6_0000_0000"; - apu_pcil = "/amba_root@0/amba_fpd@0/apu_pcil@0xecb10000"; - fpd_afi_fs = "/amba_root@0/amba_fpd@0/lpd_afi_fs@0xec860000"; - mmi_gem_memattr = "/amba_root@0/amba_fpd@0/mmi_gem_ma"; - mmi_usb_memattr = "/amba_root@0/amba_fpd@0/mmi_usb_ma"; - amba_mmi = "/amba_root@0/amba_fpd@0/amba_mmi@0"; - mdio_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0"; - phy_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0/phy@1"; - mmi_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/ethernet@0xed920000"; - mmi_usb_drd = "/amba_root@0/amba_fpd@0/amba_mmi@0/usb_drd@0xedec0000"; - mmi_crx = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_crs@0xedc00000"; - mmi_pcsr = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_pcsr@0xeb2f0000"; - mmi_gtyp = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gtyp@0xed900000"; - mmi_slcr_secure = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_slcr_sec@0"; - mmi_trng = "/amba_root@0/amba_fpd@0/amba_mmi@0/trng@0xede80000"; - mmi_udh_slcr = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_slcr@0xedea0000"; - mmi_udh_pll = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_pll@0xede90000"; - mmi_gpu_a = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gpu_a@0"; - loader_write_0xEDC30440 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC30440"; - loader_write_0xEDC30444 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x7F@0xEDC30444"; - loader_write_0xEDC3044c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC3044c"; - loader_write_0xEDC30450 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC30450"; - loader_write_0xEDC30460 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC30460"; - loader_write_0xEDC30464 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x7f@0xEDC30464"; - loader_write_0xEDC3046c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC3046c"; - loader_write_0xEDC30470 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x1@0xEDC30470"; - loader_write_0xED0A0098 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ -loader_write_cpu0_0x3@0xED0A0098"; - amba_pmc_internal = "/amba_root@0/amba_pmc_internal@0"; - xmpu_pmc = "/amba_root@0/amba_pmc_internal@0/xmpu_pmc@0"; - xppu_pmc_npi = "/amba_root@0/amba_pmc_internal@0/xppu_pmc_npi@0xf1300000"; - xppu_pmc = "/amba_root@0/amba_pmc_internal@0/xppu_pmc@0xf1310000"; - amba_pmc = "/amba_root@0/amba_pmc@0"; - xmpu_pmc_cfu = "/amba_root@0/amba_pmc@0/xmpu_pmc_cfu@0xf1340000"; - pmx_err_mng = "/amba_root@0/amba_pmc@0/pmx_err_mng@0xf1110000"; - intpmxc_config = "/amba_root@0/amba_pmc@0/intpmxc_config@0xf1400000"; - amba_pmc_iou = "/amba_root@0/amba_pmc_iou@0"; - pmc_iou_slcr = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr@0xf1060000"; - pmc_iou_slcr_secure = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr_secure@0xf1070000"; - pmc_qspi_dma_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi_dma@QSPI_DMA"; - pmc_qspi_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000"; - qspi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ -qspi_flash_lcs_lb@0"; - qspi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ -qspi_flash_lcs_ub@0"; - qspi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ -qspi_flash_ucs_lb@0"; - qspi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ -qspi_flash_ucs_ub@0"; - ospi_dma_dst = "/amba_root@0/amba_pmc_iou@0/ospi_dst_dma@0"; - ospi_dma_src = "/amba_root@0/amba_pmc_iou@0/ospi_src_dma@0"; - ospi = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000"; - ospi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ -ospi_flash_lcs_lb@0"; - ospi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ -ospi_flash_lcs_ub@0"; - ospi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ -ospi_flash_ucs_lb@0"; - ospi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ -ospi_flash_ucs_ub@0"; - gpio_mr_mux = "/amba_root@0/amba_pmc_iou@0/gpio_mr_mux@0xc0000000"; - pmc_gpio = "/amba_root@0/amba_pmc_iou@0/pmc_gpio@0xf1020000"; - sdhci0 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1040000"; - sdhci1 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1050000"; - pmc_tap = "/amba_root@0/amba_pmc_iou@0/pmc_tap@0xf11a0000"; - pmc_i2c = "/amba_root@0/amba_pmc_iou@0/pmc_i2c_wrapper/pmc_i2c@0xf1000000"; - pmx_wwdt = "/amba_root@0/amba_pmc_iou@0/wwdt@0xf03f0000"; - pmc_ufshc = "/amba_root@0/amba_pmc_iou@0/pmc_ufshc@0xf10b0000"; - unipro = "/amba_root@0/amba_pmc_iou@0/unipro@0"; - ufs_dev = "/amba_root@0/amba_pmc_iou@0/ufs_dev@0"; - ufs_reg = "/amba_root@0/amba_pmc_iou@0/ufs_reg@0xf1060000"; - amba_pmc_sec = "/amba_root@0/amba_pmc_sec@0"; - pmc_dma0_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_src@0"; - pmc_dma0_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_dst@0"; - pmc_dma1_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_src@0"; - pmc_dma1_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_dst@0"; - pmc_stream_switch = "/amba_root@0/amba_pmc_sec@0/pmc_stream_switch@0"; - pmc_sha3 = "/amba_root@0/amba_pmc_sec@0/pmc_sha@0xf1210000"; - pmc_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000"; - xlnx_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000/xlnx_aes@0"; - pmc_rsa = "/amba_root@0/amba_pmc_sec@0/pmc_rsa@0xf1200000"; - xlnx_pmc_efuse_cache = "/amba_root@0/amba_pmc_sec@0/ -xlnx_pmc_efuse_cache@0xf1250000"; - pmc_puf_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_puf_ctrl@0"; - pmc_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000"; - xlnx_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000/xlnx_efuse@0"; - pmc_bbram_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_bbram@0xf11f0000"; - pmc_sbi = "/amba_root@0/amba_pmc_sec@0/pmc_sbi@0xf1220000"; - pmc_sha3_1 = "/amba_root@0/amba_pmc_sec@0/pmc_sha1@0xF1800000"; - amba_pmc_ppu = "/amba_root@0/amba_pmc_ppu@0"; - pmc_gic_proxy = "/amba_root@0/amba_pmc_ppu@0/pmc_gic_proxy@0"; - amba_pmc_sys = "/amba_root@0/amba_pmc_sys@0"; - pmc_clk_rst = "/amba_root@0/amba_pmc_sys@0/pmc_clk_rst@0xf1260000"; - pmc_int = "/amba_root@0/amba_pmc_sys@0/pmc_int@0xf1400000"; - pmc_global = "/amba_root@0/amba_pmc_sys@0/pmc_global@0xf1110000"; - pmc_stream_zero = "/amba_root@0/amba_pmc_sys@0/pmc_stream_zero@"; - pmx_analog = "/amba_root@0/amba_pmc_sys@0/pmc_analog@0xf1160000"; - pmc_sysmon = "/amba_root@0/amba_pmc_sys@0/pmc_sysmon@0xf1270000"; - pmc_ams_sat0 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@0"; - pmc_ams_sat1 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@1"; - pmc_global_tamper = "/amba_root@0/amba_pmc_sys@0/versal_pmc_tamper@"; - lpd_sysmon_sat = "/amba_root@0/amba_pmc_sys@0/lpd_ams_sat@0"; - fpd_sysmon_sat0 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@0"; - fpd_sysmon_sat1 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@1"; - fpd_sysmon_sat2 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@2"; - fpd_sysmon_sat3 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@3"; - amba_pmc_pl = "/amba_root@0/amba_pmc_pl@0"; - noc_npi_nir = "/amba_root@0/amba_pmc_pl@0/noc_npi_nir@0xf6000000"; - npi_ddrmc_ub0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub0@0xf62c0000"; - npi_ddrmc_main0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main0@0xf6290000"; - npi_ddrmc_noc0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc0@0xf62a0000"; - npi_ddrmc_ub1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub1@0xf63b0000"; - npi_ddrmc_main1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main1@0xf6380000"; - npi_ddrmc_noc1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc1@0xf6390000"; - npi_ddrmc_ub2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub2@0xf6940000"; - npi_ddrmc_main2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main2@0xf6910000"; - npi_ddrmc_noc2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc2@0xf6920000"; - npi_ddrmc_ub3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub3@0xf6a20000"; - npi_ddrmc_main3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main3@0xf69f0000"; - npi_ddrmc_noc3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc3@0xf6a00000"; - npi_ddrmc_xmpu0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_xmpu0@0xf62a0000"; - npi_me = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; - npi_me0 = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; - noc_npi_devs = "/amba_root@0/amba_pmc_pl@0/noc_npi_devs@0"; - cfu_fdro = "/amba_root@0/amba_pmc_pl@0/cfu_fdro@0xf12c2000"; - cfu_sfr = "/amba_root@0/amba_pmc_pl@0/cfu_sfr@0xf12c1000"; - cframe0_reg = "/amba_root@0/amba_pmc_pl@0/cframe0_reg@0xf12d0000"; - cframe1_reg = "/amba_root@0/amba_pmc_pl@0/cframe1_reg@0xf12d2000"; - cframe2_reg = "/amba_root@0/amba_pmc_pl@0/cframe2_reg@0xf12d4000"; - cframe3_reg = "/amba_root@0/amba_pmc_pl@0/cframe3_reg@0xf12d6000"; - cframe4_reg = "/amba_root@0/amba_pmc_pl@0/cframe4_reg@0xf12d8000"; - cframe5_reg = "/amba_root@0/amba_pmc_pl@0/cframe5_reg@0xf12da000"; - cframe6_reg = "/amba_root@0/amba_pmc_pl@0/cframe6_reg@0xf12dc000"; - cframe7_reg = "/amba_root@0/amba_pmc_pl@0/cframe7_reg@0xf12de000"; - cframe8_reg = "/amba_root@0/amba_pmc_pl@0/cframe8_reg@0xf12e0000"; - cframe9_reg = "/amba_root@0/amba_pmc_pl@0/cframe9_reg@0xf12e2000"; - cframe10_reg = "/amba_root@0/amba_pmc_pl@0/cframe10_reg@0xf12e4000"; - cframe11_reg = "/amba_root@0/amba_pmc_pl@0/cframe11_reg@0xf12e6000"; - cframe12_reg = "/amba_root@0/amba_pmc_pl@0/cframe12_reg@0xf12e8000"; - cframe13_reg = "/amba_root@0/amba_pmc_pl@0/cframe13_reg@0xf12ea000"; - cframe14_reg = "/amba_root@0/amba_pmc_pl@0/cframe14_reg@0xf12ec000"; - cframe_bcast_reg = "/amba_root@0/amba_pmc_pl@0/cframe_bcast_reg@0xf12ee000"; - dummy_cfu_mem = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000"; - cfu = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000/cfu@0x0"; - amba_pmc_bat = "/amba_root@0/amba_pmc_bat@0"; - rtc = "/amba_root@0/amba_pmc_bat@0/rtc@0xf12a0000"; - amba_psm = "/amba_root@0/amba_psm@0"; - amba_xram = "/amba_root@0/amba_xram@0"; - crf = "/amba_root@0/crf@0xec200000"; - amba_asu_cpu = "/amba_root@0/amba_asu_cpu@0"; - amba_asu = "/amba_root@0/amba_asu@0"; - asu_iram = "/amba_root@0/amba_asu@0/asu_instr_ram@0xebe00000"; - asu_io_module = "/amba_root@0/amba_asu@0/io-module@0xebe80000"; - asu_io_intc = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_io_intc@0C"; - asu_io_gpi1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpi@20"; - asu_io_gpo1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@10"; - asu_io_gpo2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@14"; - asu_io_pit1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@40"; - asu_io_pit2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@50"; - asu_io_pit3 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@60"; - asu_io_pit4 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@70"; - asu_mdm_uart = "/amba_root@0/amba_asu@0/asu_mdm_uart@0xebef0000"; - asu_global = "/amba_root@0/amba_asu@0/asu_global@0xebf80000"; - asu_global_pmc = "/amba_root@0/amba_asu@0/asu_global_pmc@0xebf80000"; - asu_local = "/amba_root@0/amba_asu@0/asu_local@0xebe8e000"; - asu_sss = "/amba_root@0/amba_asu@0/asu_sss@0xebe8e000"; - asu_dma_src = "/amba_root@0/amba_asu@0/asu_dma_src@0xebe8c000"; - asu_dma_dst = "/amba_root@0/amba_asu@0/asu_dma_dst@0xebe8c000"; - asu_dma1_src = "/amba_root@0/amba_asu@0/asu_dma1_src@0xebe8d000"; - asu_dma1_dst = "/amba_root@0/amba_asu@0/asu_dma1_dst@0xebe8d000"; - asu_xmpu = "/amba_root@0/amba_asu@0/asu_xmpu@0xebf60000"; - asu_aes = "/amba_root@0/amba_asu@0/asu_aes@0xebe88000"; - asu_kv = "/amba_root@0/amba_asu@0/asu_kv@0xebe8a000"; - asu_sha3 = "/amba_root@0/amba_asu@0/asu_sha3@0xebf40000"; - asu_sha2 = "/amba_root@0/amba_asu@0/asu_sha2@0xebf30000"; - asu_rsa = "/amba_root@0/amba_asu@0/pmc_rsa@0xebf50000"; - asu_trng = "/amba_root@0/amba_asu@0/trng@0xebf20000"; - asu_ecc = "/amba_root@0/amba_asu@0/asu_ecc@0xebf00000"; - lmb_pmc_ppu0 = "/lmb_pmc_ppu0@0"; - pmc_rom = "/lmb_pmc_ppu0@0/pmc_rom@0xf0000000"; - pmc_ppu0_ram = "/lmb_pmc_ppu0@0/ppu0_ram@0xf0060000"; - pmc_ppu0_io_module = "/lmb_pmc_ppu0@0/io-module@00"; - pmc_ppu0_io_intc = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_intc@0C"; - pmc_ppu0_io_gpi1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@20"; - pmc_ppu0_io_gpi2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@24"; - pmc_ppu0_io_gpi3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@28"; - pmc_ppu0_io_gpi4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@2c"; - pmc_ppu0_io_gpo1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@10"; - pmc_ppu0_io_gpo2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@14"; - pmc_ppu0_io_gpo3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@18"; - pmc_ppu0_io_gpo4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@1c"; - pmc_ppu0_io_pit1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@40"; - pmc_ppu0_io_pit2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@50"; - pmc_ppu0_io_pit3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@60"; - pmc_ppu0_io_pit4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@70"; - lmb_pmc_ppu1 = "/lmb_pmc_ppu1@0"; - pmc_ppu1_io_module = "/lmb_pmc_ppu1@0/io-module@00"; - pmc_ppu1_io_intc = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_intc@0C"; - pmc_ppu1_io_gpi1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@20"; - pmc_ppu1_io_gpi2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@24"; - pmc_ppu1_io_gpi3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@28"; - pmc_ppu1_io_gpi4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@2c"; - pmc_ppu1_io_gpo1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@10"; - pmc_ppu1_io_gpo2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@14"; - pmc_ppu1_io_gpo3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@18"; - pmc_ppu1_io_gpo4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@1c"; - pmc_ppu1_io_pit1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@40"; - pmc_ppu1_io_pit2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@50"; - pmc_ppu1_io_pit3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@60"; - pmc_ppu1_io_pit4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@70"; - lmb_psm = "/lmb_psm@0"; - lmb_ddrmc0 = "/lmb_ddrmc@0"; - ddrmc0_ram_data = "/lmb_ddrmc@0/ddrmc0_ram_data@0x1c000"; - ddrmc0_ram_instr = "/lmb_ddrmc@0/ddrmc0_ram_instr@0x20000"; - ddrmc0_ram_exchange = "/lmb_ddrmc@0/ddrmc0_ram_exchange@0x08000"; - ddrmc_0_io_module = "/lmb_ddrmc@0/io-module@00"; - ddrmc0_io_intc = "/lmb_ddrmc@0/io-module@00/ddrmc0_intc@0C"; - ddrmc0_io_gpo1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_gpo@10"; - ddrmc0_io_pit1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@40"; - ddrmc0_io_pit2 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@50"; - ddrmc0_io_pit3 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@60"; - ddrmc0_io_pit4 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@70"; - ddrmc_uart0 = "/lmb_ddrmc@0/ddrmc_uart0@0"; - lmb_ddrmc1 = "/lmb_ddrmc@1"; - ddrmc1_ram_data = "/lmb_ddrmc@1/ddrmc1_ram_data@0x1c000"; - ddrmc1_ram_instr = "/lmb_ddrmc@1/ddrmc1_ram_instr@0x20000"; - ddrmc1_ram_exchange = "/lmb_ddrmc@1/ddrmc1_ram_exchange@0x08000"; - amba_rpu = "/amba_rpu@0"; - amba_r5_0 = "/amba_r5@0"; - amba_r5_1 = "/amba_r5@1"; - dummy1 = "/dummy1@0"; - smmu_tbu0 = "/tbu0_slave@0"; - smmu_tbu1 = "/tbu1_slave@0"; - smmu_tbu2 = "/tbu2_slave@0"; - smmu_tbu3 = "/tbu3_slave@0"; - smmu_tbu4 = "/tbu4_slave@0"; - smmu_tbu5 = "/tbu5_slave@0"; - smmu_tbu6 = "/tbu6_slave@0"; - ddr_mem = "/memory@00000000"; - ddr_2_mem = "/memory@8_0000_0000"; - ddr_3_mem = "/memory@0x50000000000ULL"; - ocm_mem_bank_0 = "/ocm_mem_bank_0@"; - ocm_mem_bank_1 = "/ocm_mem_bank_1@"; - ocm_mem_bank_2 = "/ocm_mem_bank_2@"; - ocm_mem_bank_3 = "/ocm_mem_bank_3@"; - xram_mem = "/xram_mem@0xbbe00000"; - ipi_msgbuf = "/ipi_msgbuf@0"; - pmc_ram = "/pmc_ram@0xf2000000"; - pmc_ram_bank_0 = "/pmc_ram_bank_0@0x0"; - pmc_ppu1_insn_ram = "/pmc_ppu1_ram@0xf0200000"; - pmc_ppu1_data_ram = "/pmc_ppu1_ram@0xf0280000"; - lqspi_mr = "/lqspi_mr@0"; - lospi_mr = "/lospi_mr@0"; - cpu0 = "/cpus/apu_cpu@0"; - cpu1 = "/cpus/apu_cpu@1"; - cpu2 = "/cpus/apu_cpu@2"; - cpu3 = "/cpus/apu_cpu@3"; - cpu4 = "/cpus/apu_cpu@4"; - cpu5 = "/cpus/apu_cpu@5"; - cpu6 = "/cpus/apu_cpu@6"; - cpu7 = "/cpus/apu_cpu@7"; - rpu_a = "/cpus/rpu_a@0"; - rpu_cpu0 = "/cpus/rpu_a@0/rpu_cpu_a@0"; - rpu_cpu1 = "/cpus/rpu_a@0/rpu_cpu_a@1"; - rpu_b = "/cpus/rpu_b@0"; - rpu_cpu2 = "/cpus/rpu_b@0/rpu_cpu_b@0"; - rpu_cpu3 = "/cpus/rpu_b@0/rpu_cpu_b@1"; - rpu_c = "/cpus/rpu_c@0"; - rpu_cpu4 = "/cpus/rpu_c@0/rpu_cpu_c@0"; - rpu_cpu5 = "/cpus/rpu_c@0/rpu_cpu_c@1"; - rpu_d = "/cpus/rpu_d@0"; - rpu_cpu6 = "/cpus/rpu_d@0/rpu_cpu_d@0"; - rpu_cpu7 = "/cpus/rpu_d@0/rpu_cpu_d@1"; - rpu_e = "/cpus/rpu_e@0"; - rpu_cpu8 = "/cpus/rpu_e@0/rpu_cpu_e@0"; - rpu_cpu9 = "/cpus/rpu_e@0/rpu_cpu_e@1"; - amba_apu = "/amba_apu@0"; - timer = "/amba_apu@0/timer"; - amba_apu_gic = "/amba_apu_gic@0"; - gic = "/amba_apu_gic@0/interrupt-controller@0xe2000000"; - amba_alias = "/amba_alias@0"; - qemu_sysmem = "/qemu_sysmem@0"; - psm0 = "/dummy_ppu0@0"; - pmc_ppu0 = "/dummy_ppu0@0"; - pmc_ppu1 = "/dummy_ppu1@0"; - ddrmc_ub0 = "/dummy_ddrmc0@0"; - ddrmc_ub1 = "/dummy_ddrmc1@0"; - ddr = "/ddr@0x00000000"; - ddr_2 = "/ddr_2@0x800000000ULL"; - mdio0 = "/mdio"; - phy0 = "/mdio/phy@1"; - phy1 = "/mdio/phy@2"; - cpunone = "/cpu_dummy"; - smmu_tbu7 = "/tbu7_slave@0"; - smmu_tbu8 = "/tbu8_slave@0"; - smmu_tbu9 = "/tbu9_slave@0"; - smmu_tbu10 = "/tbu10_slave@0"; - smmu_tbu11 = "/tbu11_slave@0"; - smmu_tbu12 = "/tbu12_slave@0"; - mr_rpu_gic_a = "/mr_rpu_gic_a@0"; - rpu_gic_a = "/mr_rpu_gic_a@0/rpu_gic_a@0x0"; - mr_rpu_gic_b = "/mr_rpu_gic_b@0"; - rpu_gic_b = "/mr_rpu_gic_b@0/rpu_gic_b@0x0"; - mr_rpu_gic_c = "/mr_rpu_gic_c@0"; - rpu_gic_c = "/mr_rpu_gic_c@0/rpu_gic_c@0x0"; - mr_rpu_gic_d = "/mr_rpu_gic_d@0"; - rpu_gic_d = "/mr_rpu_gic_d@0/rpu_gic_d@0x0"; - mr_rpu_gic_e = "/mr_rpu_gic_e@0"; - rpu_gic_e = "/mr_rpu_gic_e@0/rpu_gic_e@0x0"; - tcm_core0 = "/tcm_core@0"; - atcm_rpu_core0 = "/tcm_core@0/atcm_rpu_core0@0x00000"; - btcm_rpu_core0 = "/tcm_core@0/btcm_rpu_core0@0x00000"; - ctcm_rpu_core0 = "/tcm_core@0/ctcm_rpu_core0@0x00000"; - tcm_core1 = "/tcm_core@1"; - atcm_rpu_core1 = "/tcm_core@1/atcm_rpu_core1@0x00000"; - btcm_rpu_core1 = "/tcm_core@1/btcm_rpu_core1@0x00000"; - ctcm_rpu_core1 = "/tcm_core@1/ctcm_rpu_core1@0x00000"; - tcm_core2 = "/tcm_core@2"; - atcm_rpu_core2 = "/tcm_core@2/atcm_rpu_core2@0x00000"; - btcm_rpu_core2 = "/tcm_core@2/btcm_rpu_core2@0x00000"; - ctcm_rpu_core2 = "/tcm_core@2/ctcm_rpu_core2@0x00000"; - tcm_core3 = "/tcm_core@3"; - atcm_rpu_core3 = "/tcm_core@3/atcm_rpu_core3@0x00000"; - btcm_rpu_core3 = "/tcm_core@3/btcm_rpu_core3@0x00000"; - ctcm_rpu_core3 = "/tcm_core@3/ctcm_rpu_core3@0x00000"; - tcm_core4 = "/tcm_core@4"; - atcm_rpu_core4 = "/tcm_core@4/atcm_rpu_core4@0x00000"; - btcm_rpu_core4 = "/tcm_core@4/btcm_rpu_core4@0x00000"; - ctcm_rpu_core4 = "/tcm_core@4/ctcm_rpu_core4@0x00000"; - tcm_core5 = "/tcm_core@5"; - atcm_rpu_core5 = "/tcm_core@5/atcm_rpu_core5@0x00000"; - btcm_rpu_core5 = "/tcm_core@5/btcm_rpu_core5@0x00000"; - ctcm_rpu_core5 = "/tcm_core@5/ctcm_rpu_core5@0x00000"; - tcm_core6 = "/tcm_core@6"; - atcm_rpu_core6 = "/tcm_core@6/atcm_rpu_core6@0x00000"; - btcm_rpu_core6 = "/tcm_core@6/btcm_rpu_core6@0x00000"; - ctcm_rpu_core6 = "/tcm_core@6/ctcm_rpu_core6@0x00000"; - tcm_core7 = "/tcm_core@7"; - atcm_rpu_core7 = "/tcm_core@7/atcm_rpu_core7@0x00000"; - btcm_rpu_core7 = "/tcm_core@7/btcm_rpu_core7@0x00000"; - ctcm_rpu_core7 = "/tcm_core@7/ctcm_rpu_core7@0x00000"; - tcm_core8 = "/tcm_core@8"; - atcm_rpu_core8 = "/tcm_core@8/atcm_rpu_core8@0x00000"; - btcm_rpu_core8 = "/tcm_core@8/btcm_rpu_core8@0x00000"; - ctcm_rpu_core8 = "/tcm_core@8/ctcm_rpu_core8@0x00000"; - tcm_core9 = "/tcm_core@9"; - atcm_rpu_core9 = "/tcm_core@9/atcm_rpu_core9@0x00000"; - btcm_rpu_core9 = "/tcm_core@9/btcm_rpu_core9@0x00000"; - ctcm_rpu_core9 = "/tcm_core@9/ctcm_rpu_core9@0x00000"; - tcm_cluster_a = "/tcm_cluster_a@0"; - tcm_cluster_b = "/tcm_cluster_b@0"; - tcm_cluster_c = "/tcm_cluster_c@0"; - tcm_cluster_d = "/tcm_cluster_d@0"; - tcm_cluster_e = "/tcm_cluster_e@0"; - amba_r5_2 = "/amba_r5@2"; - amba_r5_3 = "/amba_r5@3"; - amba_r5_4 = "/amba_r5@4"; - amba_r5_5 = "/amba_r5@5"; - amba_r5_6 = "/amba_r5@6"; - amba_r5_7 = "/amba_r5@7"; - amba_r5_8 = "/amba_r5@8"; - amba_r5_9 = "/amba_r5@9"; - rpu2_s_memattr = "/rpu2_s_ma"; - rpu3_s_memattr = "/rpu3_s_ma"; - rpu4_s_memattr = "/rpu4_s_ma"; - rpu5_s_memattr = "/rpu5_s_ma"; - rpu6_s_memattr = "/rpu6_s_ma"; - rpu7_s_memattr = "/rpu7_s_ma"; - rpu8_s_memattr = "/rpu8_s_ma"; - rpu9_s_memattr = "/rpu9_s_ma"; - usb1_memattr = "/usb1_ma"; - apu2_s_memattr = "/apu2_s_ma"; - apu2_ns_memattr = "/apu2_ns_ma"; - apu3_s_memattr = "/apu3_s_ma"; - apu3_ns_memattr = "/apu3_ns_ma"; - apu4_s_memattr = "/apu4_s_ma"; - apu4_ns_memattr = "/apu4_ns_ma"; - apu5_s_memattr = "/apu5_s_ma"; - apu5_ns_memattr = "/apu5_ns_ma"; - apu6_s_memattr = "/apu6_s_ma"; - apu6_ns_memattr = "/apu6_ns_ma"; - apu7_s_memattr = "/apu7_s_ma"; - apu7_ns_memattr = "/apu7_ns_ma"; - apu8_s_memattr = "/apu8_s_ma"; - apu8_ns_memattr = "/apu8_ns_ma"; - apu9_s_memattr = "/apu9_s_ma"; - apu9_ns_memattr = "/apu9_ns_ma"; - apu10_s_memattr = "/apu10_s_ma"; - apu10_ns_memattr = "/apu10_ns_ma"; - apu11_s_memattr = "/apu11_s_ma"; - apu11_ns_memattr = "/apu11_ns_ma"; - apu12_s_memattr = "/apu12_s_ma"; - apu12_ns_memattr = "/apu12_ns_ma"; - apu13_s_memattr = "/apu13_s_ma"; - apu13_ns_memattr = "/apu13_ns_ma"; - apu14_s_memattr = "/apu14_s_ma"; - apu14_ns_memattr = "/apu14_ns_ma"; - apu15_s_memattr = "/apu15_s_ma"; - apu15_ns_memattr = "/apu15_ns_ma"; - apu16_s_memattr = "/apu16_s_ma"; - apu16_ns_memattr = "/apu16_ns_ma"; - apu17_s_memattr = "/apu17_s_ma"; - apu17_ns_memattr = "/apu17_ns_ma"; - apu18_s_memattr = "/apu18_s_ma"; - apu18_ns_memattr = "/apu18_ns_ma"; - apu19_s_memattr = "/apu19_s_ma"; - apu19_ns_memattr = "/apu19_ns_ma"; - apu20_s_memattr = "/apu20_s_ma"; - apu20_ns_memattr = "/apu20_ns_ma"; - apu21_s_memattr = "/apu21_s_ma"; - apu21_ns_memattr = "/apu21_ns_ma"; - apu22_s_memattr = "/apu22_s_ma"; - apu22_ns_memattr = "/apu22_ns_ma"; - apu23_s_memattr = "/apu23_s_ma"; - apu23_ns_memattr = "/apu23_ns_ma"; - apu24_s_memattr = "/apu24_s_ma"; - apu24_ns_memattr = "/apu24_ns_ma"; - apu25_s_memattr = "/apu25_s_ma"; - apu25_ns_memattr = "/apu25_ns_ma"; - apu26_s_memattr = "/apu26_s_ma"; - apu26_ns_memattr = "/apu26_ns_ma"; - apu27_s_memattr = "/apu27_s_ma"; - apu27_ns_memattr = "/apu27_ns_ma"; - apu28_s_memattr = "/apu28_s_ma"; - apu28_ns_memattr = "/apu28_ns_ma"; - apu29_s_memattr = "/apu29_s_ma"; - apu29_ns_memattr = "/apu29_ns_ma"; - apu30_s_memattr = "/apu30_s_ma"; - apu30_ns_memattr = "/apu30_ns_ma"; - apu31_s_memattr = "/apu31_s_ma"; - apu31_ns_memattr = "/apu31_ns_ma"; - asu_cpu_memattr = "/asu_cpu_ma"; - lmb_amba_asu = "/lmb_amba_asu@0"; - ocm_mem = "/ocm_mem@0xbbe00000"; - asu_dram = "/asu_data_ram_wrapper@0xebe40000"; - psm_gic_proxy = "/psm_gic_proxy@0"; - asu_cpu = "/asu_cpu@0"; - }; -}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.dts b/boards/amd/versal2_rpu/versal2_rpu.dts deleted file mode 100644 index 36e8c2ed7e9e4..0000000000000 --- a/boards/amd/versal2_rpu/versal2_rpu.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2025, Advanced Micro Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,ocm = &ocm; - }; -}; - -&cpu0 { - clock-frequency = <100000000>; -}; - -&soc { - sram0: memory@30000 { - compatible = "mmio-sram"; - reg = <0x30000 0x7ffd0000>; - }; -}; - -&ocm { - status = "okay"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <100000000>; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <100000000>; -}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.yaml b/boards/amd/versal2_rpu/versal2_rpu.yaml deleted file mode 100644 index 91753bea822c9..0000000000000 --- a/boards/amd/versal2_rpu/versal2_rpu.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: versal2_rpu -name: AMD Development board for Versal Gen 2 RPU -arch: arm -toolchain: - - zephyr -supported: - - scsi - - ufs -testing: - ignore_tags: - - net - - bluetooth -vendor: amd diff --git a/boards/amd/versal2_rpu/versal2_rpu_defconfig b/boards/amd/versal2_rpu/versal2_rpu_defconfig deleted file mode 100644 index ed6209ff2afb7..0000000000000 --- a/boards/amd/versal2_rpu/versal2_rpu_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_PL011=y - -# Enable cache and arch timer -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ARM_ARCH_TIMER=y diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index e9f39b173aef7..0028128f8e231 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -225,7 +225,7 @@ zephyr_udc0: &usbotg_hs { port { gc2145_ep_out: endpoint { - remote-endpoint-label = "dcmi_ep_in"; + remote-endpoint = <&dcmi_ep_in>; }; }; @@ -240,13 +240,19 @@ zephyr_udc0: &usbotg_hs { pinctrl-names = "default"; status = "okay"; + sensor = <&gc2145>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + capture-rate = <1>; + dmas = <&dma1 0 38 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; + port { dcmi_ep_in: endpoint { - remote-endpoint-label = "gc2145_ep_out"; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <0>; + remote-endpoint = <&gc2145_ep_out>; }; }; }; diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts index c8676ebce825c..804abfd95660a 100644 --- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts @@ -19,9 +19,6 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - zephyr,ipc = &ipc0; - zephyr,ipc_shm = &ddr0; }; cpus { @@ -46,12 +43,6 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; - - ipc0: ipc { - compatible = "zephyr,mbox-ipm"; - mboxes = <&mbox1 0>, <&mbox1 1>; - mbox-names = "tx", "rx"; - }; }; &i2c6 { diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index ec24ee9f6bf44..3191eccb62522 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -23,7 +23,6 @@ mcuboot-button0 = &button0; sensor0 = &light; sensor1 = &humidity; - watchdog0 = &wdt0; }; chosen { @@ -286,7 +285,3 @@ zephyr,resolution = <12>; }; }; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts index b72290420e4d4..43dd64f9c1cdb 100644 --- a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts +++ b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts @@ -16,7 +16,6 @@ aliases { led0 = &led0; led1 = &led1; - watchdog0 = &wdt0; }; chosen { @@ -94,7 +93,3 @@ &ieee802154g { status = "okay"; }; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts index ac4d2b46e2ed6..5bf213b644453 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts @@ -18,9 +18,6 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,ipc = &ipc0; - zephyr,ipc_shm = &ddr0; }; cpus { @@ -45,12 +42,6 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; - - ipc0: ipc { - compatible = "zephyr,mbox-ipm"; - mboxes = <&mbox3 0>, <&mbox3 1>; - mbox-names = "tx", "rx"; - }; }; &uart1 { diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts index 2c6f9f8c5f4f2..e2957226a66e2 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts @@ -18,9 +18,6 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,ipc = &ipc0; - zephyr,ipc_shm = &ddr0; }; cpus { @@ -45,12 +42,6 @@ reg = <0xa1200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; - - ipc0: ipc { - compatible = "zephyr,mbox-ipm"; - mboxes = <&mbox1 0>, <&mbox1 1>; - mbox-names = "tx", "rx"; - }; }; &uart1 { diff --git a/boards/beagle/pocketbeagle_2/doc/index.rst b/boards/beagle/pocketbeagle_2/doc/index.rst index f75fbd3183268..ecd9542919c90 100644 --- a/boards/beagle/pocketbeagle_2/doc/index.rst +++ b/boards/beagle/pocketbeagle_2/doc/index.rst @@ -96,7 +96,7 @@ Debugging ********* The board supports debugging M4 core from the A53 cores running Linux. Since the target needs -superuser privilege, openocd needs to be launched separately for now: +superuser privilege, openocd needs to be launched seperately for now: .. code-block:: console diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig index a512dfb34f7c3..36e9122b1d352 100644 --- a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig @@ -6,4 +6,5 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y +CONFIG_UART_BFLB=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/common/nios2.board.cmake b/boards/common/nios2.board.cmake new file mode 100644 index 0000000000000..4a59927171bcd --- /dev/null +++ b/boards/common/nios2.board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(nios2) +board_set_debugger_ifnset(nios2) + +board_finalize_runner_args(nios2 + # TODO: merge this script into nios2.py + "--quartus-flash=${ZEPHYR_BASE}/scripts/support/quartus-flash.py" + ) diff --git a/boards/common/openocd-stm32.board.cmake b/boards/common/openocd-stm32.board.cmake index cecaba2352992..855411fa34b1d 100644 --- a/boards/common/openocd-stm32.board.cmake +++ b/boards/common/openocd-stm32.board.cmake @@ -18,5 +18,3 @@ elseif(CONFIG_SOC_SERIES_STM32F2X OR CONFIG_SOC_SERIES_STM32F7X) board_runner_args(openocd "--cmd-erase=stm32f2x mass_erase 0") endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/common/openocd.board.cmake b/boards/common/openocd.board.cmake index 14d32d4be2548..b1d09fe0a2dd9 100644 --- a/boards/common/openocd.board.cmake +++ b/boards/common/openocd.board.cmake @@ -20,3 +20,6 @@ board_finalize_runner_args(openocd --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" ) + +# Manufacturer common options +include(${CMAKE_CURRENT_LIST_DIR}/openocd-stm32.board.cmake) diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml index db5295b3b693f..24bcdb296fb6b 100644 --- a/boards/element14/warp7/warp7_mcimx7d_m4.yaml +++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml @@ -20,3 +20,4 @@ testing: supported: - gpio - i2c +vendor: nxp diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index ac62b9e2d52c8..225a2747ad584 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -10,5 +10,3 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake index e6055be6f37b5..0add658642610 100644 --- a/boards/intel/adsp/board.cmake +++ b/boards/intel/adsp/board.cmake @@ -1,4 +1,4 @@ -# Copyright (c) 2022-2025 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 @@ -47,12 +47,4 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI board_finalize_runner_args(intel_adsp) -elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM) - - board_set_rimage_target(wcl) - - set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") - - board_finalize_runner_args(intel_adsp) - endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index 5bc812edb37a6..c169a14487b02 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -17,6 +17,3 @@ boards: - name: 'ptl' variants: - name: 'sim' - - name: 'wcl' - variants: - - name: 'sim' diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl.dts b/boards/intel/adsp/intel_adsp_ace30_wcl.dts deleted file mode 100644 index e488d77181dd0..0000000000000 --- a/boards/intel/adsp/intel_adsp_ace30_wcl.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2025 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - model = "intel_adsp_ace30_wcl"; - compatible = "intel"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &mem_window3; - }; -}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig deleted file mode 100644 index 85f377409f7e0..0000000000000 --- a/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DAI_SSP_HAS_POWER_CONTROL=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts deleted file mode 100644 index fab0812265e06..0000000000000 --- a/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2025 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - model = "intel_adsp_ace30_wcl_sim"; - compatible = "intel"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &mem_window3; - }; -}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig deleted file mode 100644 index 5373f0c0bf841..0000000000000 --- a/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_INTEL_ADSP_SIM=y -CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DAI_SSP_HAS_POWER_CONTROL=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml index c5d8c9f2759c3..866f8ff7a90cc 100644 --- a/boards/intel/adsp/twister.yaml +++ b/boards/intel/adsp/twister.yaml @@ -12,20 +12,6 @@ testing: - bluetooth - mcumgr variants: - intel_adsp/ace30/wcl: - toolchain: - - xt-clang - - zephyr - intel_adsp/ace30/wcl/sim: - type: sim - simulation: - - name: custom - exec: acesim - toolchain: - - xt-clang - - zephyr - testing: - timeout_multiplier: 8 intel_adsp/ace30/ptl: toolchain: - xt-clang diff --git a/boards/intel/btl/intel_btl_s_crb.yaml b/boards/intel/btl/intel_btl_s_crb.yaml index cb340c11d1359..a569213d394ae 100644 --- a/boards/intel/btl/intel_btl_s_crb.yaml +++ b/boards/intel/btl/intel_btl_s_crb.yaml @@ -8,16 +8,6 @@ ram: 2048 supported: - acpi - smp - - spi - - nvme - - gpio - - uart - - tgpio - - pwm - - smbus - - rtc - - watchdog - - i2c testing: ignore_tags: - net diff --git a/boards/intel/rpl/board.yml b/boards/intel/rpl/board.yml index 58f24d3becd76..9f35b6486991e 100644 --- a/boards/intel/rpl/board.yml +++ b/boards/intel/rpl/board.yml @@ -7,11 +7,5 @@ boards: - name: intel_rpl_s_crb full_name: Raptor Lake S CRB vendor: intel - revision: - format: number - default: "600" - revisions: - - name: "600" - - name: "700" socs: - name: raptor_lake diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst index 9a256300050c1..e6bc4015256fe 100644 --- a/boards/intel/rpl/doc/index.rst +++ b/boards/intel/rpl/doc/index.rst @@ -12,10 +12,7 @@ architecture, utilizing P-cores for performance and E-Cores for efficiency. Raptor Lake S and Raptor Lake P processor lines are supported. The S-Processor line is a 2-Chip Platform that includes the Processor Die and -Platform Controller Hub (PCH-S) Die in the Package. There are 2 PCH-s versions -supported for S-Processor line 600 series (ADL) and 700 series (RPL). Default -600 series revision is selected, to select 700 series revision the board name -during build should be ``intel_rpl_s_crb@700``. +Platform Controller Hub (PCH-S) Die in the Package. The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the Processor Die and Platform Controller Hub (PCH-P) Die on the same package as diff --git a/boards/intel/rpl/intel_rpl_s_crb_700.overlay b/boards/intel/rpl/intel_rpl_s_crb_700.overlay deleted file mode 100644 index 7e1aa5ba8e6f4..0000000000000 --- a/boards/intel/rpl/intel_rpl_s_crb_700.overlay +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2024 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&smbus0 { - device-id = <0x7a23>; -}; - -&i2c0 { - device-id = <0x7a4c>; -}; - -&i2c1 { - device-id = <0x7a4c>; -}; - -&i2c2 { - device-id = <0x7a4d>; -}; - -&i2c3 { - device-id = <0x7a4e>; -}; - -&i2c4 { - device-id = <0x7a7c>; -}; - -&i2c5 { - device-id = <0x7a7d>; -}; - -&spi0 { - device-id = <0x7a2a>; -}; - -&spi1 { - device-id = <0x7a2b>; -}; - -&spi2 { - device-id = <0x7a7b>; -}; - -&uart0 { - device-id = <0x7a28>; -}; - -&uart1 { - device-id = <0x7a29>; -}; - -&uart2 { - device-id = <0x7a7e>; -}; diff --git a/boards/ite/it515xx_evb/it515xx_evb.dts b/boards/ite/it515xx_evb/it515xx_evb.dts index 926c93bd921f6..76801b4b5a2bf 100644 --- a/boards/ite/it515xx_evb/it515xx_evb.dts +++ b/boards/ite/it515xx_evb/it515xx_evb.dts @@ -18,7 +18,6 @@ i2c-0 = &i2c0; led0 = &led0; watchdog0 = &twd0; - pwm-0 = &pwm0; }; chosen { @@ -121,26 +120,6 @@ pinctrl-names = "default"; }; -/* - * test pwm: - * If we need pwm output in ITE chip power saving mode, - * then we should set pwm output frequency <=324Hz. - */ -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; - -/* test fan */ -&pwm7 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm7_gpa7_default>; - pinctrl-names = "default"; -}; - /* test fan tachometer sensor */ &tach0 { status = "okay"; @@ -149,7 +128,3 @@ pinctrl-0 = <&tach0a_gpd6_default>; pinctrl-names = "default"; }; - -&sha256 { - status = "okay"; -}; diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts index 8dc3188edc16b..3aa16d53df1cc 100644 --- a/boards/ite/it82xx2_evb/it82xx2_evb.dts +++ b/boards/ite/it82xx2_evb/it82xx2_evb.dts @@ -134,14 +134,15 @@ pinctrl-names = "default"; }; -/* - * pwm for test: - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ +/* pwm for test */ &pwm0 { status = "okay"; prescaler-cx = ; + /* + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ + pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -150,6 +151,7 @@ &pwm7 { status = "okay"; prescaler-cx = ; + pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; diff --git a/boards/ite/it8xxx2_evb/board.cmake b/boards/ite/it8xxx2_evb/board.cmake index a9763a8bad41f..6a3abe8ddd915 100644 --- a/boards/ite/it8xxx2_evb/board.cmake +++ b/boards/ite/it8xxx2_evb/board.cmake @@ -1,2 +1,4 @@ +set(SUPPORTED_EMU_PLATFORMS renode) +set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/it8xxx2_evb.resc) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts index 2116f89b20ce1..59b4af711c9fa 100644 --- a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts @@ -121,14 +121,15 @@ &uart2_tx_gph2_default>; pinctrl-names = "default"; }; -/* - * pwm for test: - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ +/* pwm for test */ &pwm0 { status = "okay"; prescaler-cx = ; + /* + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ + pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -136,6 +137,7 @@ &pwm7 { status = "okay"; prescaler-cx = ; + pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; diff --git a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc new file mode 100644 index 0000000000000..5ef1ae4e5bbc5 --- /dev/null +++ b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc @@ -0,0 +1,17 @@ +:name: ITE-evb +:description: This script is prepared to run Zephyr on a Mi-V RISC-V board. + +$name?="ITE-evb" + +using sysbus +mach create $name +machine LoadPlatformDescription @platforms/boards/it8xxx2_evb.repl + +showAnalyzer uart +cpu PerformanceInMips 80 + +macro reset +""" + sysbus LoadELF $elf +""" +runMacro $reset diff --git a/boards/kws/pico2_spe/doc/index.rst b/boards/kws/pico2_spe/doc/index.rst index 09302b967addc..48bccacea8679 100644 --- a/boards/kws/pico2_spe/doc/index.rst +++ b/boards/kws/pico2_spe/doc/index.rst @@ -44,19 +44,8 @@ Programming and Debugging .. zephyr:board-supported-runners:: -As with the Pico-SPE, the SWD interface can be used to program and debug the device, -e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . - -The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. -Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. - -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: pico2_spe/rp2350a/m33 - :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd +As with the Pico-SPE, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . References ********** diff --git a/boards/kws/pico_spe/doc/index.rst b/boards/kws/pico_spe/doc/index.rst index 1352905638b7e..3246d36a972a6 100644 --- a/boards/kws/pico_spe/doc/index.rst +++ b/boards/kws/pico_spe/doc/index.rst @@ -84,19 +84,144 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The SWD interface can be used to program and debug the device, -e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . +Flashing +======== -The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. -Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. +Using SEGGER JLink +------------------ -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. +You can Flash the pico_spe with a SEGGER JLink debug probe as described in +:ref:`Building, Flashing and Debugging `. + +Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: pico_spe + :goals: build + +.. code-block:: bash + + west flash --runner jlink + +Using OpenOCD +------------- + +To use CMSIS-DAP, you must configure **udev**. + +Create a file in /etc/udev.rules.d with any name, and write the line below. + +.. code-block:: bash + + ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" + +This example is valid for the case that the user joins to ``plugdev`` groups. + +The Pico-SPE has an SWD interface that can be used to program +and debug the on board RP2040. This interface can be utilized by OpenOCD. +To use it with the RP2040, OpenOCD version 0.12.0 or later is needed. + +If you are using a Debian based system (including RaspberryPi OS, Ubuntu. and more), +using the `pico_setup.sh`_ script is a convenient way to set up the forked version of OpenOCD. + +Depending on the interface used (such as JLink), you might need to +checkout to a branch that supports this interface, before proceeding. +Build and install OpenOCD as described in the README. + +Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky :board: pico_spe :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap + +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` +and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work +with the OpenOCD that was installed with the default configuration. +This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. + +**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. + +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``. +How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Pico-SPE-Series`_. +Any other SWD debug adapter maybe also work with this configuration. + +The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from +``west flash`` and ``west debug`` if it was previously set while running +``west build``. + +**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. +Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. + +You can also flash the board with the following +command that directly calls OpenOCD (assuming a SEGGER JLink adapter is used): + +.. code-block:: console + + $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' -c 'program path/to/zephyr.elf verify reset exit' + +Using UF2 +--------- + +If you don't have an SWD adapter, you can flash the Pico-SPE with +a UF2 file. By default, building an app for this board will generate a +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` +button pressed, it will appear on the host as a mass storage device. The +UF2 file should be drag-and-dropped to the device, which will flash the Pico. + +Debugging +========= + +The SWD interface can also be used to debug the board. To achieve this, you can +either use SEGGER JLink or OpenOCD. + +Using SEGGER JLink +------------------ + +Use a SEGGER JLink debug probe and follow the instruction in +:ref:`Building, Flashing and Debugging`. + + +Using OpenOCD +------------- + +Install OpenOCD as described for flashing the board. + +Here is an example for debugging the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: pico_spe + :maybe-skip-config: + :goals: debug + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd + +As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER** +at ``west build`` time. No needs to specify it at ``west debug`` time. + +You can also debug with OpenOCD and gdb launching from command-line. +Run the following command: + +.. code-block:: console + + $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' + +On another terminal, run: + +.. code-block:: console + + $ gdb-multiarch + +Inside gdb, run: + +.. code-block:: console + + (gdb) tar ext :3333 + (gdb) file path/to/zephyr.elf + +You can then start debugging the board. .. target-notes:: diff --git a/boards/lilygo/ttgo_tbeam/Kconfig b/boards/lilygo/ttgo_tbeam/Kconfig index c95a97a11aa2a..c52379f257a07 100644 --- a/boards/lilygo/ttgo_tbeam/Kconfig +++ b/boards/lilygo/ttgo_tbeam/Kconfig @@ -5,6 +5,3 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 4096 if BOARD_TTGO_TBEAM_ESP32_PROCPU default 256 if BOARD_TTGO_TBEAM_ESP32_APPCPU - -config GNSS_INIT_PRIORITY - default 87 diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts index 88deaae04d21a..7b7c1831e1291 100644 --- a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts @@ -125,10 +125,6 @@ constant-charge-current-max-microamp = <1000000>; constant-charge-voltage-max-microvolt = <4200000>; }; - - fuel_gauge: fuel_gauge { - compatible = "x-powers,axp2101-fuel-gauge"; - }; }; }; diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index cd398cc5234f0..ea9dd21d797a9 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -60,13 +60,11 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = <67108864>; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; }; }; @@ -173,12 +171,6 @@ pinctrl-2 = <&pinmux_usdhc1_med>; pinctrl-3 = <&pinmux_usdhc1_fast>; pinctrl-names = "default", "slow", "med", "fast"; - - mmc { - compatible = "zephyr,sdmmc-disk"; - disk-name = "SD"; - status = "okay"; - }; }; &edma0 { diff --git a/boards/madmachine/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml index dfd28db8b7ac2..a4541bc88a837 100644 --- a/boards/madmachine/mm_feather/mm_feather.yaml +++ b/boards/madmachine/mm_feather/mm_feather.yaml @@ -22,3 +22,4 @@ supported: - uart - pwm - spi +vendor: nxp diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index 54ad772396c55..814c448c1d86a 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -60,13 +60,11 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = <67108864>; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; }; }; diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml index fa4ad27a5c6b2..dbd5b79b7b63d 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.yaml +++ b/boards/madmachine/mm_swiftio/mm_swiftio.yaml @@ -16,3 +16,4 @@ flash: 8192 supported: - counter - sdhc +vendor: nxp diff --git a/boards/mikroe/quail/Kconfig.defconfig b/boards/mikroe/quail/Kconfig.defconfig deleted file mode 100644 index ea45af09da97a..0000000000000 --- a/boards/mikroe/quail/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# MikroE Quail board configuration - -# Copyright (c) 2025 ThoseBoards -# SPDX-License-Identifier: Apache-2.0 - -source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" - -config SPI_STM32_INTERRUPT - default y - depends on SPI diff --git a/boards/mikroe/quail/Kconfig.mikroe_quail b/boards/mikroe/quail/Kconfig.mikroe_quail deleted file mode 100644 index f711abe5738e1..0000000000000 --- a/boards/mikroe/quail/Kconfig.mikroe_quail +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 ThoseBoards -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIKROE_QUAIL - select SOC_STM32F427XX diff --git a/boards/mikroe/quail/board.cmake b/boards/mikroe/quail/board.cmake deleted file mode 100644 index 7718f87e84a94..0000000000000 --- a/boards/mikroe/quail/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") -board_runner_args(jlink "--device=STM32F427VIT6" "--speed=4000") - -include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/mikroe/quail/board.yml b/boards/mikroe/quail/board.yml deleted file mode 100644 index b363f83059c76..0000000000000 --- a/boards/mikroe/quail/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: mikroe_quail - full_name: MikroE Quail - vendor: mikroe - socs: - - name: stm32f427xx diff --git a/boards/mikroe/quail/doc/img/mikroe_quail.webp b/boards/mikroe/quail/doc/img/mikroe_quail.webp deleted file mode 100644 index 801b29d3a485b..0000000000000 Binary files a/boards/mikroe/quail/doc/img/mikroe_quail.webp and /dev/null differ diff --git a/boards/mikroe/quail/doc/mikroe_quail.rst b/boards/mikroe/quail/doc/mikroe_quail.rst deleted file mode 100644 index 5e2f7d82947fc..0000000000000 --- a/boards/mikroe/quail/doc/mikroe_quail.rst +++ /dev/null @@ -1,99 +0,0 @@ -.. zephyr:board:: mikroe_quail - -Overview -******** -MikroE Quail for STM32 is a development board containing an `STM32F427`_ -microcontroller. It is equipped with four mikroBUS sockets. -The edges of the board are lined with screw terminals and USB ports for -additional connectivity. - -Hardware -******** -The Quail board contains the following connections: - - - Four mikroBUS connectors - - 32 screw terminals - - two USB ports, one for programming and one for external storage - -Furthermore the board contains three LEDs that are connected -to the microcontroller. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Connections and IOs -=================== - -The four mikroBUS interfaces are aliased in the device tree so that their -peripherals can be accessed using ``mikrobus_N_INTERFACE`` so e.g. the SPI on -bus 2 can be found by the alias ``mikrobus_2_spi``. The numbering corresponds -with the marking on the board. - -For connections on the edge connectors, please refer to `Quail for STM32 User Manual`_. - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``mikroe_quail`` board can be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` for more details). - - -Flashing -======== -The board ships with a locked flash, and will fail with the message: - -.. code-block:: console - - Error: stm32x device protected - -Unlocking with OpenOCD makes it possible to flash. - -.. code-block:: console - - $ openocd -f /usr/share/openocd/scripts/interface/stlink-v2.cfg \ - -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ - -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mikroe_quail - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! mikroe_quail - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mikroe_quail - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Quail website: - https://www.mikroe.com/quail -.. _Quail for STM32 User Manual: - https://download.mikroe.com/documents/starter-boards/other/quail/quail-board-manual-v100.pdf -.. _STM32F427VIT6 Website: - https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html -.. _STM32F427: - https://www.st.com/resource/en/datasheet/stm32f427vg.pdf diff --git a/boards/mikroe/quail/mikroe_quail.dts b/boards/mikroe/quail/mikroe_quail.dts deleted file mode 100644 index c314f658c3895..0000000000000 --- a/boards/mikroe/quail/mikroe_quail.dts +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright (c) 2025 ThoseBoards - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "MikroE Quail for STM32"; - compatible = "mikroe,stm32-e427", "st,stm32f427"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,flash-controller = &flash1; - zephyr,ccm = &ccm0; - }; - - leds { - compatible = "gpio-leds"; - - ld1: led_1 { - gpios = <&gpioe 15 GPIO_ACTIVE_HIGH>; - label = "User LD1"; - }; - - ld2: led_2 { - gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; - label = "User LD2"; - }; - - ld3: led_3 { - gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; - label = "User LD3"; - }; - }; - - zephyr,user { - io-channels = <&adc1 0>, <&adc1 1>, <&adc2 0>, <&adc2 1>; - }; - - mikrobus_1_header: mikrobus-connector-1 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 6 0>, /* AN */ - <1 0 &gpioa 2 0>, /* RST */ - <2 0 &gpioa 3 0>, /* CS */ - <3 0 &gpiob 3 0>, /* SCK */ - <4 0 &gpiob 4 0>, /* MISO */ - <5 0 &gpiob 5 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpioe 9 0>, /* PWM */ - <7 0 &gpioa 1 0>, /* INT */ - <8 0 &gpiod 9 0>, /* RX */ - <9 0 &gpiod 8 0>, /* TX */ - <10 0 &gpiob 6 0>, /* SCL */ - <11 0 &gpiob 7 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - mikrobus_2_header: mikrobus-connector-2 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 4 0>, /* AN */ - <1 0 &gpioe 1 0>, /* RST */ - <2 0 &gpioe 0 0>, /* CS */ - <3 0 &gpiob 3 0>, /* SCK */ - <4 0 &gpiob 4 0>, /* MISO */ - <5 0 &gpiob 5 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpiod 15 0>, /* PWM */ - <7 0 &gpiob 9 0>, /* INT */ - <8 0 &gpiod 6 0>, /* RX */ - <9 0 &gpiod 5 0>, /* TX */ - <10 0 &gpiob 6 0>, /* SCL */ - <11 0 &gpiob 7 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - mikrobus_3_header: mikrobus-connector-3 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 7 0>, /* AN */ - <1 0 &gpiod 8 0>, /* RST */ - <2 0 &gpiod 11 0>, /* CS */ - <3 0 &gpioc 10 0>, /* SCK */ - <4 0 &gpioc 11 0>, /* MISO */ - <5 0 &gpioc 12 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpiod 13 0>, /* PWM */ - <7 0 &gpioc 8 0>, /* INT */ - <8 0 &gpioc 7 0>, /* RX */ - <9 0 &gpioc 6 0>, /* TX */ - <10 0 &gpiob 6 0>, /* SCL */ - <11 0 &gpiob 7 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - mikrobus_4_header: mikrobus-connector-4 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 5 0>, /* AN */ - <1 0 &gpiod 0 0>, /* RST */ - <2 0 &gpiod 1 0>, /* CS */ - <3 0 &gpioc 10 0>, /* SCK */ - <4 0 &gpioc 11 0>, /* MISO */ - <5 0 &gpioc 12 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpiod 14 0>, /* PWM */ - <7 0 &gpioa 14 0>, /* INT */ - <8 0 &gpioa 10 0>, /* RX */ - <9 0 &gpioa 9 0>, /* TX */ - <10 0 &gpiob 6 0>, /* SCL */ - <11 0 &gpiob 7 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - edge_header: connector { - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 5 0>, /* ,PC5 */ - <1 0 &gpiob 0 0>, /* ,PB0 */ - <2 0 &gpioe 7 0>, /* ,PE7 */ - <3 0 &gpioe 8 0>, /* ,PE8 */ - <4 0 &gpioe 11 0>, /* ,PE11 */ - <5 0 &gpioc 4 0>, /* ,PC4 */ - <6 0 &gpioe 13 0>, /* ,PE13 */ - <7 0 &gpioe 14 0>, /* ,PE14 */ - <8 0 &gpiob 10 0>, /* ,PB10 */ - <9 0 &gpiob 11 0>, /* ,PB11 */ - <10 0 &gpiob 12 0>, /* ,PB12 */ - <11 0 &gpiob 13 0>, /* ,PB13 */ - <12 0 &gpiob 6 0>, /* ,PB6 # I2C1 */ - <13 0 &gpiob 7 0>, /* ,PB7 # I2C1 */ - <14 0 &gpioc 10 0>, /* ,PC10 # SPI3 */ - <15 0 &gpioc 11 0>, /* ,PC11 # SPI3 */ - <16 0 &gpioc 12 0>, /* ,PC12 # SPI3 */ - <17 0 &gpiod 10 0>, /* ,PD10 # SPI3 */ - <18 0 &gpioa 15 0>, /* ,PA15 */ - <19 0 &gpioc 13 0>, /* ,PC13 */ - <20 0 &gpioe 6 0>, /* ,PE6 */ - <21 0 &gpioe 5 0>, /* ,PE5 */ - <22 0 &gpiod 2 0>, /* ,PD2 */ - <23 0 &gpiod 3 0>, /* ,PD3 */ - <24 0 &gpiod 4 0>, /* ,PD4 */ - <25 0 &gpiod 7 0>, /* ,PD7 */ - <26 0 &gpioe 2 0>, /* ,PE2 */ - <27 0 &gpioe 3 0>, /* ,PE3 */ - <28 0 &gpioe 4 0>; /* ,PE4 */ - }; - - aliases { - led0 = &ld1; - led1 = &ld2; - led2 = &ld3; - volt-sensor0 = &vref; - volt-sensor1 = &vbat; - }; - - skd1: socket_1_adc { - status = "okay"; - io-channels = <&adc2 0>; - }; - - skd2: socket_2_adc { - status = "okay"; - io-channels = <&adc1 0>; - }; - - skd3: socket_3_adc { - status = "okay"; - io-channels = <&adc2 1>; - }; - - skd4: socket_4_adc { - status = "okay"; - io-channels = <&adc1 1>; - }; -}; - -&clk_lsi { - status = "okay"; -}; - -&clk_hsi { - clock-frequency = ; - status = "okay"; -}; - -&pll { - div-m = <8>; - mul-n = <96>; - div-p = <2>; - div-q = <4>; - clocks = <&clk_hsi>; - status = "okay"; -}; - -&rcc { - clocks = <&pll>; - clock-frequency = ; - ahb-prescaler = <1>; - apb1-prescaler = <4>; - apb2-prescaler = <2>; -}; - -&usart1 { - pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&usart2 { - pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&usart3 { - pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&usart6 { - pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&rtc { - clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, - <&rcc STM32_SRC_LSI RTC_SEL(2)>; - status = "okay"; -}; - -zephyr_udc0: &usbotg_fs { - pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; - pinctrl-names = "default"; - status = "okay"; -}; - -#include <../boards/common/usb/cdc_acm_serial.dtsi> - -&spi1 { - pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>, <&gpioe 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&spi3 { - status = "okay"; - pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>; - pinctrl-names = "default"; - - cs-gpios = - <&gpiod 11 GPIO_ACTIVE_LOW>, // CS0 - <&gpiod 1 GPIO_ACTIVE_LOW>, // CS1 - <&gpioa 13 GPIO_ACTIVE_LOW>; // CS2 -}; - -/* Flash chip 1 (extra flash connected to CS2) */ -&spi3 { - flash1: flash@2 { - compatible = "jedec,spi-nor"; // Typical flash chip compatibility string - reg = <2>; // The CS0 pin on the SPI bus - // S25FL164K flash's actual JEDEC: Device ID = 16h, Device Type = 40h, - // Capacity = 17h - //jedec-id = [16 40 17]; - jedec-id = [01 60 17]; - spi-max-frequency = <50000000>; // Max frequency for the flash chip (e.g., 50 MHz) - size = <0x800000>; // Flash memory size (16MB example) - page-size = <256>; // Flash page size (usually 256 or 512 bytes) - status = "okay"; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; - pinctrl-names = "default"; - status = "okay"; -}; - -&adc1 { - status ="okay"; - pinctrl-0 = <&adc1_in4_pa4 &adc1_in5_pa5>; - pinctrl-names = "default"; - st,adc-clock-source = "SYNC"; - st,adc-prescaler = <2>; -}; - -&adc2 { - status ="okay"; - pinctrl-0 = <&adc2_in6_pa6 &adc2_in7_pa7>; - pinctrl-names = "default"; - st,adc-clock-source = "SYNC"; - st,adc-prescaler = <2>; -}; - -&vref { - status = "okay"; -}; - -&vbat { - status = "okay"; -}; - -mikrobus_1_adc: &skd1 {}; - -mikrobus_1_i2c: &i2c1 {}; - -mikrobus_1_spi: &spi1 {}; - -mikrobus_1_uart: &usart3 {}; - -mikrobus_2_adc: &skd2 {}; - -mikrobus_2_i2c: &i2c1 {}; - -mikrobus_2_spi: &spi1 {}; - -mikrobus_2_uart: &usart2 {}; - -mikrobus_3_adc: &skd3 {}; - -mikrobus_3_i2c: &i2c1 {}; - -mikrobus_3_spi: &spi3 {}; - -mikrobus_3_uart: &usart6 {}; - -mikrobus_4_adc: &skd4 {}; - -mikrobus_4_i2c: &i2c1 {}; - -mikrobus_4_spi: &spi3 {}; - -mikrobus_4_uart: &usart1 {}; - -mikrobus_adc: &skd1 {}; - -mikrobus_i2c: &i2c1 {}; - -mikrobus_spi: &spi1 {}; - -mikrobus_uart: &usart3 {}; - -mikrobus_header: &mikrobus_1_header {}; diff --git a/boards/mikroe/quail/mikroe_quail.yaml b/boards/mikroe/quail/mikroe_quail.yaml deleted file mode 100644 index f114861f6bc7a..0000000000000 --- a/boards/mikroe/quail/mikroe_quail.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: mikroe_quail -name: MikroE Quail for STM32 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -ram: 256 -flash: 2048 -supported: - - spi - - i2c - - uart - - adc - - gpio - - flash -vendor: mikroe diff --git a/boards/mikroe/quail/mikroe_quail_defconfig b/boards/mikroe/quail/mikroe_quail_defconfig deleted file mode 100644 index e5819cf795089..0000000000000 --- a/boards/mikroe/quail/mikroe_quail_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_SERIAL=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/native/common/extra_args/extra_args.c b/boards/native/common/extra_args/extra_args.c index aa71b95552ce9..b2e57dc674edd 100644 --- a/boards/native/common/extra_args/extra_args.c +++ b/boards/native/common/extra_args/extra_args.c @@ -14,7 +14,9 @@ static void remove_one_char(char *str) { - for (int i = 0; str[i] != 0; i++) { + int i; + + for (i = 0; str[i] != 0; i++) { str[i] = str[i+1]; } } diff --git a/boards/native/nrf_bsim/common/bsim_control.h b/boards/native/nrf_bsim/common/bsim_control.h deleted file mode 100644 index ee32ea80e9f05..0000000000000 --- a/boards/native/nrf_bsim/common/bsim_control.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H -#define BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H - -#include -#include "bsim_args_runner.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void bsim_set_terminate_on_exit(bool terminate); - -#ifdef __cplusplus -} -#endif - -#endif /* BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H */ diff --git a/boards/native/nrf_bsim/common/bstests.h b/boards/native/nrf_bsim/common/bstests.h index 7c892d0ead299..ee22240a38070 100644 --- a/boards/native/nrf_bsim/common/bstests.h +++ b/boards/native/nrf_bsim/common/bstests.h @@ -92,7 +92,7 @@ struct bst_test_instance { {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} struct bst_test_list { - const struct bst_test_instance *test_instance; + struct bst_test_instance *test_instance; struct bst_test_list *next; }; diff --git a/boards/native/nrf_bsim/common/bstests_entry.c b/boards/native/nrf_bsim/common/bstests_entry.c index 6822afb0a8c14..7b22a50ebf503 100644 --- a/boards/native/nrf_bsim/common/bstests_entry.c +++ b/boards/native/nrf_bsim/common/bstests_entry.c @@ -21,7 +21,7 @@ */ enum bst_result_t bst_result; -static const struct bst_test_instance *current_test; +static struct bst_test_instance *current_test; static struct bst_test_list *test_list_top; __attribute__((weak)) bst_test_install_t test_installers[] = { NULL }; @@ -42,7 +42,8 @@ struct bst_test_list *bst_add_tests(struct bst_test_list *tests, if (test_def[idx].test_id != NULL) { head = bs_malloc(sizeof(struct bst_test_list)); head->next = NULL; - head->test_instance = &test_def[idx++]; + head->test_instance = (struct bst_test_instance *) + &test_def[idx++]; tail = head; } } @@ -50,14 +51,16 @@ struct bst_test_list *bst_add_tests(struct bst_test_list *tests, while (test_def[idx].test_id != NULL) { tail->next = bs_malloc(sizeof(struct bst_test_list)); tail = tail->next; - tail->test_instance = &test_def[idx++]; + tail->test_instance = (struct bst_test_instance *) + &test_def[idx++]; tail->next = NULL; } return head; } -static const struct bst_test_instance *bst_test_find(struct bst_test_list *tests, char *test_id) +static struct bst_test_instance *bst_test_find(struct bst_test_list *tests, + char *test_id) { struct bst_test_list *top = tests; diff --git a/boards/native/nrf_bsim/common/runner_hooks.c b/boards/native/nrf_bsim/common/runner_hooks.c index 01ed27703a579..e63567634b4ab 100644 --- a/boards/native/nrf_bsim/common/runner_hooks.c +++ b/boards/native/nrf_bsim/common/runner_hooks.c @@ -16,20 +16,6 @@ #include "NRF_HWLowL.h" #include "bsim_args_runner.h" -static bool bsim_disconnect_on_exit; - -/* - * Control what will happen to the overall simulation when this executable exists. - * If is true (default behavior) the Phy will be told to end the simulation - * when this executable exits. - * If is false, this device will just disconnect, but let the simulation continue - * otherwise. - */ -void bsim_set_terminate_on_exit(bool terminate) -{ - bsim_disconnect_on_exit = !terminate; -} - static uint8_t main_clean_up_trace_wrap(void) { return nsi_exit_inner(0); @@ -54,33 +40,9 @@ NSI_TASK(open_dumps, PRE_BOOT_2, 500); static void exit_hooks(void) { - if (bsim_disconnect_on_exit) { - hwll_disconnect_phy(); - } else { - hwll_terminate_simulation(); - } + hwll_terminate_simulation(); bs_dump_files_close_all(); bs_clean_back_channels(); } NSI_TASK(exit_hooks, ON_EXIT_PRE, 500); - -static void exit_control_args(void) -{ - static bs_args_struct_t args_struct_toadd[] = { - { - .option = "disconnect_on_exit", - .type = 'b', - .name = "term", - .dest = (void *)&bsim_disconnect_on_exit, - .descript = "If set to 1, on exit only disconnect this device from the Phy and let " - "the simulation continue. Otherwise (default) on exit terminate the " - "whole simulation." - }, - ARG_TABLE_ENDMARKER - }; - - bs_add_extra_dynargs(args_struct_toadd); -} - -NSI_TASK(exit_control_args, PRE_BOOT_1, 10); diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig index 14367293292db..8daa29dc47326 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig @@ -6,6 +6,9 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig index 14367293292db..8daa29dc47326 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig @@ -6,6 +6,9 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig index 14367293292db..8daa29dc47326 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig @@ -6,6 +6,9 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig index 14367293292db..8daa29dc47326 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig @@ -6,6 +6,9 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig index 14367293292db..8daa29dc47326 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig @@ -6,6 +6,9 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 9cbc9035d4f88..f7870a2b169cd 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -143,16 +143,11 @@ }; &cpusec_cpuapp_ipc { - status = "okay"; mbox-names = "tx", "rx"; tx-region = <&cpuapp_cpusec_ipc_shm>; rx-region = <&cpusec_cpuapp_ipc_shm>; }; -&cpusec_bellboard { - status = "okay"; -}; - ipc0: &cpuapp_cpurad_ipc { status = "okay"; mbox-names = "rx", "tx"; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index ebeb2aeeafffb..55c5284001b78 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -60,16 +60,11 @@ }; &cpusec_cpurad_ipc { - status = "okay"; mbox-names = "tx", "rx"; tx-region = <&cpurad_cpusec_ipc_shm>; rx-region = <&cpusec_cpurad_ipc_shm>; }; -&cpusec_bellboard { - status = "okay"; -}; - ipc0: &cpuapp_cpurad_ipc { status = "okay"; mbox-names = "tx", "rx"; diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi index d8f78cfd40c0c..0243f07df1d60 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi @@ -56,12 +56,8 @@ , , , - ; - bias-pull-down; - }; - group2 { - psels = ; - bias-pull-up; + , + ; }; }; @@ -71,14 +67,10 @@ , , , - ; - bias-pull-down; - }; - group2 { - psels = ; - bias-pull-up; + , + ; + low-power-enable; }; - low-power-enable; }; uart1_default: uart1_default { diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi index b364e4e3d79fa..9139b82417e1d 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi @@ -25,14 +25,6 @@ }; }; - /* CAN TX/RX --> PJ10/PJ11 (J8) */ - canfd0_default: canfd0_default { - group0 { - pinmux = , - ; - }; - }; - /* EMAC multi-function pins for MDIO, TX, REFCLK, RX pins */ emac_default: emac_default { group0 { @@ -51,14 +43,4 @@ slew-rate = "fast"; }; }; - - /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ - usbd_default: usbd_default { - group0 { - pinmux = , - , - , - ; - }; - }; }; diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts index 9f912039eafac..edfb4bcc0a6d5 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts @@ -17,8 +17,6 @@ aliases { led0 = &green_led; led1 = &yellow_led; - sw0 = &btn0; - sw1 = &btn1; }; chosen { @@ -29,7 +27,6 @@ zephyr,itcm = &itcm; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; - zephyr,canbus = &canfd0; }; leds { @@ -45,34 +42,12 @@ label = "User LD1"; }; }; - - gpio_keys { - compatible = "gpio-keys"; - btn0: btn0 { - label = "BTN0"; - gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - btn1: btn1 { - label = "BTN1"; - gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; }; &gpiod { status = "okay"; }; -&gpioh { - status = "okay"; -}; - -&gpioi { - status = "okay"; -}; - &flash0 { partitions { compatible = "fixed-partitions"; @@ -112,21 +87,8 @@ status = "okay"; }; -&canfd0 { - pinctrl-0 = <&canfd0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - &emac { pinctrl-0 = <&emac_default>; pinctrl-names = "default"; status = "okay"; }; - -/* On enabled, usbd is required to be clocked in 48MHz. */ -zephyr_udc0: &usbd { - pinctrl-0 = <&usbd_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml index 34e3fc4a4e612..2563989c8ef7a 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml @@ -12,5 +12,4 @@ ram: 1536 flash: 2048 supported: - gpio - - can vendor: nuvoton diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index b779a0b1495bb..69439718a36de 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -204,26 +204,25 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 2KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(182)>; + reg = <0x00010000 (DT_SIZE_K(180) + DT_SIZE_K(6))>; }; - slot1_partition: partition@3D800 { + slot1_partition: partition@3E800 { label = "image-1"; - reg = <0x0003D800 DT_SIZE_K(182)>; + reg = <0x0003E800 DT_SIZE_K(180)>; }; - storage_partition: partition@6B000 { + storage_partition: partition@6B800 { label = "storage"; - reg = <0x0006B000 DT_SIZE_K(84)>; + reg = <0x0006B800 DT_SIZE_K(82)>; }; }; diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index bc9a440a8dc12..100dd6e69dc99 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -233,22 +233,21 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(420)>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; }; - slot1_partition: partition@79000 { + slot1_partition: partition@7a000 { label = "image-1"; - reg = <0x00079000 DT_SIZE_K(420)>; + reg = <0x0007a000 DT_SIZE_K(416)>; }; storage_partition: partition@e2000 { label = "storage"; diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index f2c5290da3579..d28c32e512751 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -158,21 +158,20 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(44)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@b000 { label = "image-0"; - reg = <0xb000 DT_SIZE_K(100)>; + reg = <0xb000 (DT_SIZE_K(96) + DT_SIZE_K(8))>; }; - slot1_partition: partition@24000 { + slot1_partition: partition@25000 { label = "image-1"; - reg = <0x24000 DT_SIZE_K(100)>; + reg = <0x25000 DT_SIZE_K(96)>; }; storage_partition: partition@3d000 { label = "storage"; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index adc5a836aa1ad..08590e6ee66e7 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -141,21 +141,20 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 2KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(44)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@b000 { label = "image-0"; - reg = <0xb000 DT_SIZE_K(100)>; + reg = <0xb000 (DT_SIZE_K(98) + DT_SIZE_K(4))>; }; - slot1_partition: partition@24000 { + slot1_partition: partition@24800 { label = "image-1"; - reg = <0x24000 DT_SIZE_K(100)>; + reg = <0x24800 DT_SIZE_K(98)>; }; storage_partition: partition@3d000 { label = "storage"; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index aa6eec2348a04..c4c42776e2964 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -158,27 +158,25 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 2KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(204)>; + reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(6))>; }; - slot1_partition: partition@43000 { + slot1_partition: partition@44000 { label = "image-1"; - reg = <0x00043000 DT_SIZE_K(204)>; + reg = <0x00044000 DT_SIZE_K(202)>; }; - storage_partition: partition@76000 { + storage_partition: partition@76800 { label = "storage"; - reg = <0x00076000 DT_SIZE_K(40)>; + reg = <0x00076800 DT_SIZE_K(38)>; }; }; }; diff --git a/boards/nxp/frdm_mcxa153/board.c b/boards/nxp/frdm_mcxa153/board.c index 8fbf1cd82dbef..a7c9de9f86505 100644 --- a/boards/nxp/frdm_mcxa153/board.c +++ b/boards/nxp/frdm_mcxa153/board.c @@ -10,8 +10,8 @@ #include /* Core clock frequency: 96MHz */ -#define CLOCK_INIT_CORE_CLOCK 96000000U -#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U +#define CLOCK_INIT_CORE_CLOCK 960000000U +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U /* System clock frequency. */ extern uint32_t SystemCoreClock; @@ -66,21 +66,6 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) - CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); - CLOCK_AttachClk(kFRO_HF_to_CTIMER0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) - CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); - CLOCK_AttachClk(kFRO_HF_to_CTIMER1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) - CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); - CLOCK_AttachClk(kFRO_HF_to_CTIMER2); -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0)) RESET_ReleasePeripheralReset(kDMA_RST_SHIFT_RSTn); #endif @@ -105,12 +90,6 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_GateGPIO3); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) - /* Attach FRO_HF_DIV clock to I3C, 96MHz / 4 = 24MHz. */ - CLOCK_SetClockDiv(kCLOCK_DivI3C0_FCLK, 4U); - CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) CLOCK_SetClockDiv(kCLOCK_DivADC0, 1u); CLOCK_AttachClk(kFRO12M_to_ADC0); @@ -124,40 +103,6 @@ void board_early_init_hook(void) SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); - CLOCK_AttachClk(kFRO12M_to_LPI2C0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) - CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); - CLOCK_AttachClk(kFRO12M_to_LPSPI0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) - CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); - CLOCK_AttachClk(kFRO12M_to_LPSPI1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) - -/* - * Clock Select Decides what input source the lptmr will clock from - * - * 0 <- Reserved - * 1 <- 16K FRO - * 2 <- Reserved - * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field - */ -#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 - CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN); -#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 - CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); - CLOCK_AttachClk(kFRO12M_to_LPTMR0); -#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ - -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0)) CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); CLOCK_AttachClk(kFRO12M_to_LPUART0); @@ -189,10 +134,6 @@ void board_early_init_hook(void) RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) - CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); -#endif - /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi index 5e52d22250b7c..22a4f32c6dde2 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi @@ -16,23 +16,6 @@ }; }; - pinmux_i3c0: pinmux_i3c0 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - }; - group1 { - pinmux = ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - }; - }; - pinmux_lpadc0: pinmux_lpadc0 { group0 { pinmux = , @@ -51,30 +34,6 @@ }; }; - pinmux_lpi2c0: pinmux_lpi2c0 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - - pinmux_lpspi0: pinmux_lpspi0 { - group0 { - pinmux = , - , - , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - }; - }; - pinmux_lpuart0: pinmux_lpuart0 { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts index 86650b4dbb6b5..6826457bd2f9a 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts @@ -9,7 +9,6 @@ #include #include "frdm_mcxa153-pinctrl.dtsi" #include -#include / { model = "NXP FRDM_MCXA153 board"; @@ -22,8 +21,6 @@ sw0 = &user_button_2; sw1 = &user_button_3; pwm-0 = &flexpwm0_pwm0; - watchdog0 = &wwdt0; - ambient-temp0 = &p3t1755; }; chosen { @@ -59,26 +56,18 @@ user_button_2: button_2 { label = "User SW2"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; zephyr,code = ; }; user_button_3: button_3 { label = "User SW3"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; zephyr,code = ; }; }; }; -&ctimer0 { - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - &flash { partitions { compatible = "fixed-partitions"; @@ -127,22 +116,6 @@ status = "okay"; }; -&i3c0 { - status = "okay"; - pinctrl-0 = <&pinmux_i3c0>; - pinctrl-names = "default"; - - i2c-scl-hz = ; - i3c-scl-hz = ; - i3c-od-scl-hz = ; - - p3t1755: p3t1755@4800000236152a0090 { - compatible = "nxp,p3t1755"; - reg = <0x48 0x0236 0x152a0090>; - status = "okay"; - }; -}; - &lpadc0 { status = "okay"; pinctrl-0 = <&pinmux_lpadc0>; @@ -155,22 +128,6 @@ pinctrl-names = "default"; }; -&lpi2c0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c0>; - pinctrl-names = "default"; -}; - -&lpspi0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpspi0>; - pinctrl-names = "default"; -}; - -&lptmr0 { - status = "okay"; -}; - &lpuart0 { status = "okay"; current-speed = <115200>; @@ -184,7 +141,3 @@ pinctrl-0 = <&pinmux_lpuart2>; pinctrl-names = "default"; }; - -&wwdt0 { - status = "okay"; -}; diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml index 78e3a1547c771..163f421c1aaa6 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml @@ -15,14 +15,9 @@ toolchain: - gnuarmemb supported: - adc - - counter - dma - flash - gpio - - i2c - - i3c - pwm - - spi - uart - - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxa166/board.c b/boards/nxp/frdm_mcxa166/board.c index 3e6904a7cd6a7..058a9c309c969 100644 --- a/boards/nxp/frdm_mcxa166/board.c +++ b/boards/nxp/frdm_mcxa166/board.c @@ -188,52 +188,6 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) - CLOCK_SetClockDiv(kCLOCK_DivADC, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_ADC); - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) - CLOCK_EnableClock(kCLOCK_GateADC0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) - CLOCK_EnableClock(kCLOCK_GateADC1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C2); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C3); -#endif - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) - /* Configure input clock to be able to reach the datasheet specified band rate. */ - CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) - /* Configure input clock to be able to reach the datasheet specified band rate. */ - CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) /* diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi index 97e4a8c2f5328..ed6e8de8186dd 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi @@ -26,58 +26,4 @@ input-enable; }; }; - - pinmux_lpadc0: pinmux_lpadc0 { - group0 { - pinmux = ; - slew-rate = "fast"; - drive-strength = "low"; - }; - }; - - pinmux_lpi2c1: pinmux_lpi2c1 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - pinmux_lpi2c2: pinmux_lpi2c2 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - pinmux_lpi2c3: pinmux_lpi2c3 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - - pinmux_lpspi0: pinmux_lpspi0 { - group0 { - pinmux = , - , - , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - }; - }; }; diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts index d926b02bcc31e..5a51d948c03f1 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts @@ -120,30 +120,6 @@ status = "okay"; }; -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -&lpi2c1 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; - pinctrl-names = "default"; -}; - -&lpi2c3 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c3>; - pinctrl-names = "default"; -}; - -&lpspi0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpspi0>; - pinctrl-names = "default"; -}; - &flash { partitions { compatible = "fixed-partitions"; diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml index bcabde47bdcc5..2b656a4a38718 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml @@ -17,9 +17,6 @@ supported: - gpio - uart - flash - - adc - - i2c - - spi - watchdog - counter - dma diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig index 7d2f14fdd3cb9..88297ae5c016a 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig @@ -9,5 +9,4 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_LPADC_DO_OFFSET_CALIBRATION=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/nxp/frdm_mcxa276/board.c b/boards/nxp/frdm_mcxa276/board.c index 3e6904a7cd6a7..058a9c309c969 100644 --- a/boards/nxp/frdm_mcxa276/board.c +++ b/boards/nxp/frdm_mcxa276/board.c @@ -188,52 +188,6 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) - CLOCK_SetClockDiv(kCLOCK_DivADC, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_ADC); - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) - CLOCK_EnableClock(kCLOCK_GateADC0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) - CLOCK_EnableClock(kCLOCK_GateADC1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C2); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) - CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C3); -#endif - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) - /* Configure input clock to be able to reach the datasheet specified band rate. */ - CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) - /* Configure input clock to be able to reach the datasheet specified band rate. */ - CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); - CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) /* diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi index 3d0eb7bc5e92c..4eb700d76b29e 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi @@ -26,58 +26,4 @@ input-enable; }; }; - - pinmux_lpadc0: pinmux_lpadc0 { - group0 { - pinmux = ; - slew-rate = "fast"; - drive-strength = "low"; - }; - }; - - pinmux_lpi2c1: pinmux_lpi2c1 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - pinmux_lpi2c2: pinmux_lpi2c2 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - pinmux_lpi2c3: pinmux_lpi2c3 { - group0 { - pinmux = , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - bias-pull-up; - drive-open-drain; - }; - }; - - pinmux_lpspi0: pinmux_lpspi0 { - group0 { - pinmux = , - , - , - ; - slew-rate = "fast"; - drive-strength = "low"; - input-enable; - }; - }; }; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts index 0e0618e38aa30..b0d41362a4fee 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts @@ -120,30 +120,6 @@ status = "okay"; }; -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -&lpi2c1 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; - pinctrl-names = "default"; -}; - -&lpi2c3 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c3>; - pinctrl-names = "default"; -}; - -&lpspi0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpspi0>; - pinctrl-names = "default"; -}; - &flash { partitions { compatible = "fixed-partitions"; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml index 075dfbac6949a..62d9bcc6b4bc5 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml @@ -17,9 +17,6 @@ supported: - gpio - uart - flash - - adc - - i2c - - spi - watchdog - counter - dma diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig index 7d2f14fdd3cb9..88297ae5c016a 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig @@ -9,5 +9,4 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_LPADC_DO_OFFSET_CALIBRATION=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c index f990251a4f335..fff4c085a96e5 100644 --- a/boards/nxp/frdm_mcxn236/board.c +++ b/boards/nxp/frdm_mcxn236/board.c @@ -13,13 +13,9 @@ #include "usb.h" /* USB PHY configuration */ -#define BOARD_USB_PHY_D_CAL (0x04U) -#define BOARD_USB_PHY_TXCAL45DP (0x07U) -#define BOARD_USB_PHY_TXCAL45DM (0x07U) - -usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, -}; +#define BOARD_USB_PHY_D_CAL 0x04U +#define BOARD_USB_PHY_TXCAL45DP 0x07U +#define BOARD_USB_PHY_TXCAL45DM 0x07U #endif /* Board xtal frequency in Hz */ @@ -223,7 +219,11 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_HF_to_ADC0); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; + SPC0->ACTIVE_VDELAY = 0x0500; /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, * CORELDO is 1.0V) @@ -259,10 +259,8 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_UsbHsPhy); CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhsClock(); -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig); #endif -#endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U); diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index 6751b42f87c93..01e64e970851c 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -130,14 +130,6 @@ zephyr_udc0: &usb1 { status = "okay"; - phy-handle = <&usbphy1>; -}; - -&usbphy1 { - status = "okay"; - tx-d-cal = <4>; - tx-cal-45-dp-ohms = <7>; - tx-cal-45-dm-ohms = <7>; }; &lpcmp0 { diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml index 1a234da09cde4..2453534b31815 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -25,6 +25,6 @@ supported: - pwm - regulator - spi - - usbd - watchdog + - usb_device vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index c1384e6c183ae..40efcb3ab81ca 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * SPDX-License-Identifier: Apache-2.0 */ #include @@ -84,6 +84,19 @@ __ramfunc static void enable_cache64(void) } #endif +static void unsecure_gpio(GPIO_Type * base) +{ + /* Enables CPU1 to access GPIO registers + * Pins and interrupts can be configured in non-secure access + */ + base->PCNS = 0xFFFFFFFFU; + base->ICNS = GPIO_ICNS_NSE1_MASK | GPIO_ICNS_NSE0_MASK; + + /* Pins and interrupts can be configured in non-privilege access */ + base->PCNP = 0xFFFFFFFFU; + base->ICNP = GPIO_ICNP_NPE1_MASK | GPIO_ICNP_NPE0_MASK; +} + void board_early_init_hook(void) { power_mode_od(); @@ -183,22 +196,27 @@ void board_early_init_hook(void) #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) CLOCK_EnableClock(kCLOCK_Gpio0); + unsecure_gpio(GPIO0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) CLOCK_EnableClock(kCLOCK_Gpio1); + unsecure_gpio(GPIO1); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) CLOCK_EnableClock(kCLOCK_Gpio2); + unsecure_gpio(GPIO2); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) CLOCK_EnableClock(kCLOCK_Gpio3); + unsecure_gpio(GPIO3); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) CLOCK_EnableClock(kCLOCK_Gpio4); + unsecure_gpio(GPIO4); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index bc96afa35ed2f..6867b44d27809 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -7,7 +7,6 @@ #include "frdm_mcxn947-pinctrl.dtsi" #include #include -#include / { aliases{ @@ -96,22 +95,38 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-0 = <&pinmux_flexcomm7_lpi2c>; pinctrl-names = "default"; clock-frequency = ; + ov7670: ov7670@21 { + compatible = "ovti,ov7670"; + reset-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + reg = <0x21>; + + port { + ov7670_ep_out: endpoint { + remote-endpoint-label = "sdma_ep_in"; + }; + }; + }; }; /* SmartDMA is used for video driver on this board */ &smartdma { - /* Shields do not enable video-sdma parent node so enable it by default */ status = "okay"; program-mem = <0x4000000>; - video_sdma: video-sdma { - status = "disabled"; + status = "okay"; compatible = "nxp,video-smartdma"; pinctrl-0 = <&pinmux_smartdma_camera>; pinctrl-names = "default"; vsync-pin = <4>; hsync-pin = <11>; pclk-pin = <5>; + + port { + sdma_ep_in: endpoint { + remote-endpoint-label = "ov7670_ep_out"; + }; + }; }; }; @@ -285,22 +300,3 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-0 = <&pinmux_sctimer>; pinctrl-names = "default"; }; - -/* - * Connection with camera modules such as the dvp_20pin_ov7670 shield - */ - -/ { - dvp_20pin_connector: dvp-20pin-connector { - compatible = "arducam,dvp-20pin-connector"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; - gpio-map = , - ; - }; -}; - -dvp_20pin_i2c: &flexcomm7_lpi2c7 {}; - -dvp_20pin_interface: &video_sdma {}; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index b8fc2e6aec476..9948163023989 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -135,19 +135,17 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 8KB. + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ boot_partition: partition@0 { reg = <0x0 DT_SIZE_K(64)>; }; slot0_partition: partition@10000 { - reg = <0x10000 DT_SIZE_K(424)>; + reg = <0x10000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; }; - slot1_partition: partition@7A000 { - reg = <0x7A000 DT_SIZE_K(424)>; + slot1_partition: partition@7C000 { + reg = <0x7C000 DT_SIZE_K(416)>; }; storage_partition: partition@E4000 { reg = <0xE4000 DT_SIZE_K(112)>; diff --git a/boards/nxp/frdm_rw612/CMakeLists.txt b/boards/nxp/frdm_rw612/CMakeLists.txt index a86e4225c289a..74480e24ba927 100644 --- a/boards/nxp/frdm_rw612/CMakeLists.txt +++ b/boards/nxp/frdm_rw612/CMakeLists.txt @@ -21,12 +21,3 @@ if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K) "mutually exclusive on FRDM_RW612 due to shared PCB nets " "between the ethernet PHY and the external oscillator") endif() - -# Set TX power limit file to override the default one -if (CONFIG_WIFI_NXP) - zephyr_include_directories( - tx_pwr_limits - ) - - zephyr_compile_definitions(WIFI_BT_TX_PWR_LIMITS_OVERRIDE="wlan_txpwrlimit_cfg_WW_rw610.h") -endif() diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi index 13611d653ca66..b54f0aa7e9166 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi @@ -79,24 +79,4 @@ slew-rate = "normal"; }; }; - - pinmux_hsgpio0: pinmux_hsgpio0 { - group0 { - pinmux = ; - slew-rate = "normal"; - }; - }; - - pinmux_hsgpio1: pinmux_hsgpio1 { - group0 { - pinmux = ; - slew-rate = "normal"; - }; - }; }; diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi index bfefa0e5b5025..cf039cd59e72c 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -75,14 +75,6 @@ &hsgpio0 { status = "okay"; - pinctrl-0 = <&pinmux_hsgpio0>; - pinctrl-names = "default"; -}; - -&hsgpio1 { - status = "okay"; - pinctrl-0 = <&pinmux_hsgpio1>; - pinctrl-names = "default"; }; &flexspi { @@ -109,25 +101,24 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; }; }; }; @@ -238,11 +229,6 @@ wakeup-source; }; -&imu { - status = "okay"; - wakeup-source; -}; - zephyr_udc0: &usb_otg { status = "okay"; }; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts index 430b8169893ce..b70479153d4ef 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.dts +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -187,23 +187,21 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(420)>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; }; - slot1_partition: partition@79000 { + slot1_partition: partition@7a000 { label = "image-1"; - reg = <0x00079000 DT_SIZE_K(420)>; + reg = <0x0007a000 DT_SIZE_K(416)>; }; storage_partition: partition@e2000 { label = "storage"; diff --git a/boards/nxp/imx93_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt index 29ba502833b46..39ae9ed0e4e72 100644 --- a/boards/nxp/imx93_evk/CMakeLists.txt +++ b/boards/nxp/imx93_evk/CMakeLists.txt @@ -5,3 +5,12 @@ zephyr_library() zephyr_library_sources(board.c) + +if(CONFIG_SOC_MIMX9352_A55) + file(WRITE ${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript + "LE + loadfile "${CMAKE_BINARY_DIR}/zephyr/zephyr.bin" ${CONFIG_SRAM_BASE_ADDRESS} + WReg PC ${CONFIG_SRAM_BASE_ADDRESS} + g + q") +endif() diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig index 46bd77e3c320a..06b3e06736d55 100644 --- a/boards/nxp/imx93_evk/Kconfig.defconfig +++ b/boards/nxp/imx93_evk/Kconfig.defconfig @@ -67,11 +67,4 @@ endif # NETWORKING endif # BOARD_IMX93_EVK_MIMX9352_A55 -if IMX_USDHC - -config GPIO - default y - -endif # IMX_USDHC - endif # BOARD_IMX93_EVK diff --git a/boards/nxp/imx93_evk/board.cmake b/boards/nxp/imx93_evk/board.cmake index dc8b9edc46a3d..97de8649143e4 100644 --- a/boards/nxp/imx93_evk/board.cmake +++ b/boards/nxp/imx93_evk/board.cmake @@ -5,7 +5,7 @@ if(CONFIG_SOC_MIMX9352_A55) -board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-sram") +board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-script=${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index 906e395bf21cd..ce5080d075556 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -62,37 +62,6 @@ Serial Port This board configuration uses a single serial communication channel with the CPU's UART2 for A55 core and M33 core. -uSDHC (SD or eMMC Interface on A55) ------------------------------------ - -i.MX 93 processor has three ultra secured digital host controller (uSDHC) modules -for SD/eMMC interface support. On the MCIMX93-EVK board, the uSDHC2 interface of -the processor connects to the MicroSD card slot (J1002), and uSDHC1 interface connects -to the eMMC memory (located at the SOM board). DTS overlay file "usdhc1.overlay" and -"usdhc2.overlay" are provided to enable specified the uSDHC controller. - -Currently it rely on U-boot or Linux to boot Zephyr on Cortex-A Core, so Zephyr need -to use different uSDHC controller from U-boot or Linux to avoid resource conflict. -For example, if EVK board boots from SD Card which uses uSDHC2, Zephyr can use MMC -which uses uSDHC1 for testing: - -.. zephyr-app-commands:: - :zephyr-app: tests/subsys/sd/mmc - :host-os: unix - :board: imx93_evk/mimx9352/a55 - :goals: build - :gen-args: -DEXTRA_DTC_OVERLAY_FILE=usdhc1.overlay - -And if EVK board boots from MMC which uses uSDHC1, Zephyr can use SD Card which uses -uSDHC2 for testing: - -.. zephyr-app-commands:: - :zephyr-app: tests/subsys/sd/sdmmc - :host-os: unix - :board: imx93_evk/mimx9352/a55 - :goals: build - :gen-args: -DEXTRA_DTC_OVERLAY_FILE=usdhc2.overlay - Board MUX Control ----------------- diff --git a/boards/nxp/imx93_evk/dts/usdhc1.overlay b/boards/nxp/imx93_evk/dts/usdhc1.overlay deleted file mode 100644 index d020f5e31e5f4..0000000000000 --- a/boards/nxp/imx93_evk/dts/usdhc1.overlay +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - aliases { - sdhc0 = &usdhc1; - }; -}; - -&usdhc1 { - status = "okay"; - sdmmc { - status = "okay"; - }; -}; diff --git a/boards/nxp/imx93_evk/dts/usdhc2.overlay b/boards/nxp/imx93_evk/dts/usdhc2.overlay deleted file mode 100644 index 8e32620412de5..0000000000000 --- a/boards/nxp/imx93_evk/dts/usdhc2.overlay +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - aliases { - sdhc0 = &usdhc2; - }; -}; - -&usdhc2 { - status = "okay"; - sdmmc { - status = "okay"; - }; -}; diff --git a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi index dbf35b8dc9861..8976def98b4b6 100644 --- a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi +++ b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi @@ -129,198 +129,4 @@ }; - pinmux_usdhc1: pinmux_usdhc1 { - group0 { - pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, - <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; - drive-strength = "x1"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, - <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, - <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, - <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, - <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, - <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, - <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, - <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, - <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; - drive-strength = "x1"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - }; - - pinmux_usdhc1_100mhz: pinmux_usdhc1_100mhz { - group0 { - pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, - <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; - drive-strength = "x3"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, - <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, - <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, - <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, - <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, - <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, - <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, - <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, - <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; - drive-strength = "x3"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - }; - - pinmux_usdhc1_200mhz: pinmux_usdhc1_200mhz { - group0 { - pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, - <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; - drive-strength = "x6"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, - <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, - <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, - <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, - <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, - <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, - <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, - <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, - <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; - drive-strength = "x6"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - }; - - pinmux_usdhc2: pinmux_usdhc2 { - group0 { - pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; - drive-strength = "x1"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, - <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, - <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, - <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, - <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; - drive-strength = "x1"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - - group2 { - pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - }; - - group3 { - pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - bias-pull-up; - }; - }; - - pinmux_usdhc2_100mhz: pinmux_usdhc2_100mhz { - group0 { - pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; - drive-strength = "x3"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, - <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, - <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, - <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, - <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; - drive-strength = "x3"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - - group2 { - pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - }; - - group3 { - pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - bias-pull-up; - }; - }; - - pinmux_usdhc2_200mhz: pinmux_usdhc2_200mhz { - group0 { - pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; - drive-strength = "x6"; - bias-pull-down; - slew-rate = "fast"; - input-schmitt-enable; - }; - - group1 { - pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, - <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, - <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, - <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, - <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; - drive-strength = "x6"; - slew-rate = "fast"; - input-schmitt-enable; - bias-pull-up; - input-enable; - }; - - group2 { - pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - }; - - group3 { - pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; - drive-strength = "x4"; - slew-rate = "slightly_fast"; - bias-pull-up; - }; - }; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index 20ed29fe6de81..67272c846b5fd 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -203,40 +203,3 @@ phys = <&can_phy0>; status = "okay"; }; - -&usdhc1 { - pinctrl-0 = <&pinmux_usdhc1>; - pinctrl-1 = <&pinmux_usdhc1_100mhz>; - pinctrl-2 = <&pinmux_usdhc1_200mhz>; - pinctrl-names = "default", "med", "fast"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - read-watermark = <0x10>; - write-watermark = <0x80>; - status = "disabled"; - sdmmc { - compatible = "zephyr,mmc-disk"; - disk-name = "SD2"; - status = "disabled"; - }; -}; - -&usdhc2 { - pinctrl-0 = <&pinmux_usdhc2>; - pinctrl-1 = <&pinmux_usdhc2_100mhz>; - pinctrl-2 = <&pinmux_usdhc2_200mhz>; - pinctrl-names = "default", "med", "fast"; - pwr-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - power-delay-ms = <20>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - read-watermark = <0x10>; - write-watermark = <0x80>; - status = "disabled"; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - disk-name = "SD"; - status = "disabled"; - }; -}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts index bfb4328408107..cdc053f5c94a4 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -79,7 +79,3 @@ pinctrl-names = "default"; status = "okay"; }; - -&lptmr2 { - status = "okay"; -}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml index 2d4eade0557f8..50cd837eb7b8c 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml @@ -19,5 +19,4 @@ supported: - pwm - spi - netif:eth - - counter vendor: nxp diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index 93c22b64a902b..fa2860dfe9bfe 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -105,26 +105,24 @@ arduino_serial: &lpuart1 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index f79a57c265255..319d1ddb3202c 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -102,26 +102,24 @@ arduino_serial: &lpuart4 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index 29d52275d8953..6c3d096ff8ecb 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -109,26 +109,24 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index 6ccdb91db4232..bc20298898a71 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -102,22 +102,20 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(1924)>; + reg = <0x00020000 (DT_SIZE_K(1920) + DT_SIZE_K(8))>; }; - slot1_partition: partition@201000 { + slot1_partition: partition@202000 { label = "image-1"; - reg = <0x00201000 DT_SIZE_K(1924)>; + reg = <0x00202000 DT_SIZE_K(1920)>; }; storage_partition: partition@3E2000 { label = "storage"; diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index 34579205e110f..db592aa16e8c2 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -293,7 +293,7 @@ steps: Bluetooth Module ---------------- -For the :ref:`nxp_m2_wifi_bt` shield, the following hardware rework needs to be applied, +For Murate 2EL M.2 Mdoule, the following hardware rework needs to be applied, Solder 0 ohm resistors for R96, and R93. Remove resistors from R497, R498, R456 and R457. diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index 744e8776dba03..d5a31991ab124 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -32,6 +32,7 @@ zephyr,flash-controller = &w25q64jvssiq; zephyr,code-partition = &slot0_partition; zephyr,uart-mcumgr = &lpuart1; + zephyr,bt-hci = &bt_hci_uart; }; sdram0: memory@80000000 { @@ -131,26 +132,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; @@ -234,6 +233,28 @@ lpi2c3: &lpi2c3 { status = "okay"; }; -m2_hci_bt_uart: &lpuart3 {}; +m2_hci_uart: &lpuart3 { + pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "sleep"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + + m2_bt_module { + compatible = "nxp,bt-hci-uart"; + sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + hci-operation-speed = <115200>; + hw-flow-control; + fw-download-primary-speed = <115200>; + fw-download-secondary-speed = <3000000>; + fw-download-secondary-flowcontrol; + }; + }; +}; -m2_wifi_sdio: &usdhc1 {}; +&m2_hci_uart { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts index fa124ba357006..e0aa389326aa4 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts @@ -48,26 +48,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 256KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 DT_SIZE_M(3)>; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; }; - slot1_partition: partition@340000 { + slot1_partition: partition@3C0000 { label = "image-1"; - reg = <0x00340000 DT_SIZE_M(3)>; + reg = <0x003C0000 DT_SIZE_M(3)>; }; - storage_partition: partition@640000 { + storage_partition: partition@6C0000 { label = "storage"; - reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; }; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts index 47e46ce6ee47d..ca5a924d282df 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts @@ -33,26 +33,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts index 392675c9a0b1d..125f0fecd185a 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts @@ -46,26 +46,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 256KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 DT_SIZE_M(3)>; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; }; - slot1_partition: partition@340000 { + slot1_partition: partition@3C0000 { label = "image-1"; - reg = <0x00340000 DT_SIZE_M(3)>; + reg = <0x003C0000 DT_SIZE_M(3)>; }; - storage_partition: partition@640000 { + storage_partition: partition@6C0000 { label = "storage"; - reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts index bf24282e161f3..1e2876fc45d93 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts @@ -36,26 +36,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index af31e2168e130..de159e4ce240a 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -207,26 +207,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 256KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 DT_SIZE_M(3)>; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; }; - slot1_partition: partition@340000 { + slot1_partition: partition@3C0000 { label = "image-1"; - reg = <0x00340000 DT_SIZE_M(3)>; + reg = <0x003C0000 DT_SIZE_M(3)>; }; - storage_partition: partition@640000 { + storage_partition: partition@6C0000 { label = "storage"; - reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; }; }; }; diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index 0ad5306452448..004c280362c0c 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -162,13 +162,11 @@ nxp_parallel_i2c: &lpi2c1 {}; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = <67108864>; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; partitions { compatible = "fixed-partitions"; @@ -188,22 +186,20 @@ nxp_parallel_i2c: &lpi2c1 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(1984)>; + reg = <0x00020000 (DT_SIZE_K(1980) + DT_SIZE_K(8))>; }; - slot1_partition: partition@210000 { + slot1_partition: partition@211000 { label = "image-1"; - reg = <0x00210000 DT_SIZE_K(1984)>; + reg = <0x00211000 DT_SIZE_K(1980)>; }; /* The storage partition is located in is25wp064 */ }; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index bf272c435fc66..575c605c2754b 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -105,26 +105,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index 0ec66b87b2fe0..91286ab6fb3ae 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -233,25 +233,24 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts index 25978af90dcca..5cd416c9c7372 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts @@ -35,17 +35,8 @@ device_type = "memory"; reg = <0x80000000 DT_SIZE_M(64)>; }; - - zephyr,user { - dac = <&dac>; - dac-channel-id = <0>; - dac-resolution = <12>; - }; }; -&dac { - status = "okay"; -}; &lpuart1 { status = "okay"; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml index 4056069d8aa99..dd213e258bfff 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -14,7 +14,6 @@ toolchain: ram: 128 flash: 128 supported: - - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 87486bc5cfaa9..b65621ee63261 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -36,25 +36,24 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml index af866754ca768..e967a26465dd2 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -14,7 +14,6 @@ toolchain: ram: 128 flash: 128 supported: - - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index 0da2e365a2504..6d4a76fe26095 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -75,16 +75,6 @@ gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */ <17 0 &gpio9 25 0>; /* Pin 17, PWDN */ }; - - zephyr,user { - dac = <&dac>; - dac-channel-id = <0>; - dac-resolution = <12>; - }; -}; - -&dac { - status = "okay"; }; zephyr_lcdif: &lcdif {}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml index 46587fb954779..976b0e71f124d 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -17,7 +17,6 @@ supported: - adc - can - counter - - dac - display - dma - flash diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index 2a13ccbd63571..c457d55fa54f8 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2023, 2025 NXP + * Copyright 2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,8 +16,6 @@ aliases { /delete-property/ magn0; /delete-property/ accel0; - i2s-codec-tx = &sai1; - i2s-tx = &sai1; }; }; @@ -41,25 +39,24 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; }; }; }; @@ -105,19 +102,3 @@ m2_hci_uart: &lpuart2 { status = "okay"; current-speed = <115200>; }; - -&lpi2c5 { - pinctrl-0 = <&pinmux_lpi2c5>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - audio_codec: wm8962@1a { - compatible = "wolfson,wm8962"; - reg = <0x1a>; - clock-source = "MCLK"; - clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>; - clock-names = "mclk"; - }; - -}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml index 009aebd98e20d..6765cf82f2557 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -17,7 +17,6 @@ supported: - adc - can - counter - - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi index 38afe5b044571..699c1a6457dac 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -199,25 +199,24 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@720000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00720000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index f0b56d3296ac6..efa9d9d244a69 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -406,25 +406,24 @@ zephyr_udc0: &usbhs { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt index 56b32b9456364..53eb5a6e13ee1 100644 --- a/boards/nxp/mimxrt685_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -1,19 +1,16 @@ # -# Copyright 2020-2022, 2025 NXP +# Copyright 2020-2022 NXP # # SPDX-License-Identifier: Apache-2.0 # if(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) - zephyr_library() - zephyr_library_sources(cm33/init.c) -elseif(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) - zephyr_library() - zephyr_library_sources(hifi4/init.c) +zephyr_library() +zephyr_library_sources(init.c) endif() if(CONFIG_NXP_IMXRT_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 AND NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) + if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) message(WARNING "It appears you are using the board definition for " "the MIMXRT685-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") diff --git a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk index 997ed67df849d..a324f1157ea7a 100644 --- a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk +++ b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk @@ -4,4 +4,3 @@ config BOARD_MIMXRT685_EVK select SOC_PART_NUMBER_MIMXRT685SFVKB select SOC_MIMXRT685S_CM33 if BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 - select SOC_MIMXRT685S_HIFI4 if BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4 diff --git a/boards/nxp/mimxrt685_evk/board.cmake b/boards/nxp/mimxrt685_evk/board.cmake index 141af41a6d0e9..79e6f768dd1d0 100644 --- a/boards/nxp/mimxrt685_evk/board.cmake +++ b/boards/nxp/mimxrt685_evk/board.cmake @@ -1,16 +1,11 @@ # -# Copyright 2020, 2025 NXP +# Copyright (c) 2020, NXP # # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) - board_runner_args(jlink "--device=MIMXRT685S_M33" "--reset-after-load") - board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") -elseif(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) - board_runner_args(jlink "--device=MIMXRT685S_HiFi4" "--reset-after-load") - board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") -endif() +board_runner_args(jlink "--device=MIMXRT685S_M33" "--reset-after-load") +board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 0c2caa9f1a6bb..6acc0cbdc6cd7 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -294,42 +294,6 @@ steps: #. Reset by pressing SW3 -HiFi 4 DSP core -=============== - -The Cadence HiFi 4 DSP core instantiated in the i.MX RT685 microcontroller is -supported and works with both the proprietary Xtensa toolchains (``xcc`` in -earlier packages and ``xt-lang`` newer ones) and the -``xtensa-nxp_rt600_adsp_zephyr-elf`` GCC variant distributed in the Zephyr SDK. - -To build a project: - -- Set up toolchain environment - - No special configuration needed for the GCC variant in the Zephyr SDK. - - For the proprietary Xtensa toolchain, set ``XTENSA_CORE``, - ``XTENSA_TOOLCHAIN_PATH`` and ``TOOLCHAIN_VER`` according to your - installed version. ``ZEPHYR_TOOLCHAIN_VARIANT`` should be either ``xcc`` - or ``xt-clang``. -- Build the project with: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk/mimxrt685s/hifi4 - :goals: build - -Debugging can be directly carried out using the J-Link GDB server with -``xt-gdb`` (Xtensa proprietary) or ``gdb`` (Zephyr SDK) connected. It's -also possible to debug the HiFi 4 DSP in tandem with the CM33 core using the -``xt-ocd`` daemon. See `RT600 Dual-Core Communication and Debugging`_ -for details. - -As the HiFi 4 DSP is positioned as a secondary core, explicit initialisation -must be done in order for it to be functional. The ``nxp_rtxxx_adsp_ctrl``, -instantiated in the RT685's CM33 domain, takes care of this. Power domains -and clocks are set up upon it initialising. This is sufficient for -attaching a debugger to the core. For the use in an AMP system, this driver -handles code loading and run control. - .. include:: ../../common/board-footer.rst :start-after: nxp-board-footer @@ -350,6 +314,3 @@ handles code loading and run control. .. _i.MX RT685 Reference Manual: https://www.nxp.com/webapp/Download?colCode=UM11147 - -.. _RT600 Dual-Core Communication and Debugging: - https://www.nxp.com/docs/en/application-note/AN12789.pdf diff --git a/boards/nxp/mimxrt685_evk/hifi4/init.c b/boards/nxp/mimxrt685_evk/hifi4/init.c deleted file mode 100644 index 77be78dfba186..0000000000000 --- a/boards/nxp/mimxrt685_evk/hifi4/init.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2020-2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -void board_early_init_hook(void) -{ -/* flexcomm1 and flexcomm3 are configured to loopback the TX signal to RX */ -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) && \ - (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) && \ - CONFIG_I2S - - /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ - SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) | - SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3); - -#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES - /* Select Data in from Transmit I2S - Flexcomm 3 */ - SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3); - /* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ - SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1); -#endif - - /* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */ - SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | - SYSCTL1_FCCTRLSEL_WSINSEL(1); - - /* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ - SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | - SYSCTL1_FCCTRLSEL_WSINSEL(1); - -#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES - /* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */ - SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1); - /* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ - SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1); -#endif - -#endif -} diff --git a/boards/nxp/mimxrt685_evk/cm33/init.c b/boards/nxp/mimxrt685_evk/init.c similarity index 100% rename from boards/nxp/mimxrt685_evk/cm33/init.c rename to boards/nxp/mimxrt685_evk/init.c diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index 4b244bc4ef691..a92f00d270063 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -35,7 +35,6 @@ sdhc0 = &usdhc0; dmic-dev = &dmic0; mcuboot-button0 = &user_button_1; - mbox = &mbox; }; chosen { @@ -268,25 +267,24 @@ i2s1: &flexcomm3 { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; }; }; }; @@ -413,10 +411,6 @@ zephyr_udc0: &usbhs { status = "okay"; }; -&mbox { - status = "okay"; -}; - &dmic0 { status = "okay"; pinctrl-0 = <&pinmux_dmic0>; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts deleted file mode 100644 index 5989b65dd8891..0000000000000 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2025 NXP - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -#include "mimxrt685_evk-pinctrl.dtsi" - -/ { - model = "NXP MIMXRT685-EVK board, HiFi 4 DSP domain"; - compatible = "nxp,mimxrt685"; - - chosen { - zephyr,console = &flexcomm0; - zephyr,shell-uart = &flexcomm0; - }; - - aliases { - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - sw0 = &user_button_1; - mbox = &mbox; - }; - - leds: leds { - compatible = "gpio-leds"; - - green_led: led_1 { - gpios = <&gpio0 14 0>; - label = "User LED_GREEN"; - }; - - blue_led: led_2 { - gpios = <&gpio0 26 0>; - label = "User LED_BLUE"; - }; - - red_led: led_3 { - gpios = <&gpio0 31 0>; - label = "User LED_RED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button_1: button_0 { - label = "User SW1"; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&dma1 { - status = "okay"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -/* I2S receive channel */ -i2s0: &flexcomm1 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma1 2>; - dma-names = "rx"; - pinctrl-0 = <&pinmux_flexcomm1_i2s>; - pinctrl-names = "default"; -}; - -/* I2S transmit channel */ -i2s1: &flexcomm3 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma1 7>; - dma-names = "tx"; - pinctrl-0 = <&pinmux_flexcomm3_i2s>; - pinctrl-names = "default"; -}; - -&i3c0 { - status = "okay"; - pinctrl-0 = <&pinmux_i3c>; - pinctrl-names = "default"; - - audio_codec: wm8904@1a0000000000000000 { - compatible = "wolfson,wm8904"; - reg = <0x1a 0 0>; - clock-source = "MCLK"; - - clocks = <&clkctl0 MCUX_AUDIO_MCLK>; - clock-names = "mclk"; - }; -}; - -&mbox { - status = "okay"; -}; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml deleted file mode 100644 index 86cd87801adbd..0000000000000 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt685_evk/mimxrt685s/hifi4 -name: NXP MIMXRT685-EVK (HiFi 4) -type: mcu -arch: xtensa -ram: 64 -flash: 64 -toolchain: - - zephyr - - xt-clang - - xtools -supported: - - dma - - gpio - - i2c - - i3c - - i2s - - spi -testing: - only_tags: - - kernel diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig deleted file mode 100644 index 88f19d4360b30..0000000000000 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y -CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt index 8935c6b1d3018..e7ec1b7f3619c 100644 --- a/boards/nxp/rd_rw612_bga/CMakeLists.txt +++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt @@ -23,12 +23,3 @@ if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K) "mutually exclusive on RD_RW612_BGA due to shared PCB nets " "between the ethernet PHY and the external oscillator") endif() - -# Set TX power limit file to override the default one -if (CONFIG_WIFI_NXP) - zephyr_include_directories( - tx_pwr_limits - ) - - zephyr_compile_definitions(WIFI_BT_TX_PWR_LIMITS_OVERRIDE="wlan_txpwrlimit_cfg_WW_rw610.h") -endif() diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 005a9fd14ce7d..4c050c63d91e5 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -149,25 +149,24 @@ arduino_i2c: &flexcomm2 { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; }; }; }; @@ -311,8 +310,3 @@ nxp_8080_touch_panel_i2c: &arduino_i2c { status = "okay"; wakeup-source; }; - -&imu { - status = "okay"; - wakeup-source; -}; diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts index 7bd4792d18f66..f984b75064db5 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts @@ -236,26 +236,25 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(932)>; + reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(12))>; }; - slot1_partition: partition@F9000 { + slot1_partition: partition@FB000 { label = "image-1"; - reg = <0x000F9000 DT_SIZE_K(932)>; + reg = <0x000FB000 DT_SIZE_K(928)>; }; - storage_partition: partition@1E2000 { + storage_partition: partition@1E3000 { label = "storage"; - reg = <0x001E2000 DT_SIZE_K(120)>; + reg = <0x001E3000 DT_SIZE_K(116)>; }; }; }; diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index c856b1bc12a02..66e1059452113 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -338,23 +338,21 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(204)>; + reg = <0x00010000 (DT_SIZE_K(200) + DT_SIZE_K(8))>; }; - slot1_partition: partition@43000 { + slot1_partition: partition@44000 { label = "image-1"; - reg = <0x00043000 DT_SIZE_K(204)>; + reg = <0x00044000 DT_SIZE_K(200)>; }; storage_partition: partition@76000 { label = "storage"; diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts index e8a11851cf0b6..4a920fb39b9fc 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts @@ -115,23 +115,21 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 8KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(424)>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; }; - slot1_partition: partition@7A000 { + slot1_partition: partition@7C000 { label = "image-1"; - reg = <0x0007A000 DT_SIZE_K(424)>; + reg = <0x0007C000 DT_SIZE_K(416)>; }; storage_partition: partition@E4000 { label = "storage"; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi index b8b8a0c06ae14..43dcb4b1d333c 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi @@ -212,26 +212,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 4KB. - */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; }; - slot1_partition: partition@320000 { + slot1_partition: partition@32E000 { label = "image-1"; - reg = <0x00320000 DT_SIZE_M(3)>; + reg = <0x0032E000 DT_SIZE_M(3)>; }; - storage_partition: partition@620000 { + storage_partition: partition@62E000 { label = "storage"; - reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; + reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini.dts b/boards/others/esp32c3_supermini/esp32c3_supermini.dts index ff3b19452361d..317494ca20039 100644 --- a/boards/others/esp32c3_supermini/esp32c3_supermini.dts +++ b/boards/others/esp32c3_supermini/esp32c3_supermini.dts @@ -42,7 +42,7 @@ leds { compatible = "gpio-leds"; blue_led_0: led_0 { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; label = "Blue LED 0"; }; }; diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index b10d7a2f007d4..af6c7c40cfa5a 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -111,14 +111,6 @@ The True Random-Number Generator (TRNG) of the NEORV32 is supported, but disable NEORV32 SoC implementations supporting the TRNG, support can be enabled by setting the ``status`` property of the ``trng`` devicetree node to ``okay``. -General Purpose Timer -===================== - -The General Purpose Timer (GPTMR) of the NEORV32 is supported, but disabled by default. For NEORV32 -SoC implementations supporting the GPTMR, support can be enabled by setting the ``status`` property -of the ``gptmr`` devicetree node to ``okay`` and selecting the desired GPTMR clock prescaler using -the node's ``prescaler`` property. - Programming and Debugging ************************* diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts index 690a5b16c4656..67f705765131d 100644 --- a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts +++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts @@ -8,7 +8,6 @@ #include #include -#include / { model = "NEORV32 MinimalBoot"; @@ -22,10 +21,6 @@ pwm-led0 = &pwm_led0; pwm-led1 = &pwm_led1; pwm-led2 = &pwm_led2; - sw0 = &btn0; - sw1 = &btn1; - sw3 = &btn2; - sw4 = &btn3; }; chosen { @@ -60,34 +55,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - - btn0: btn0 { - label = "BTN0"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn1: btn1 { - label = "BTN1"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn2: btn2 { - label = "BTN2"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn3: btn3 { - label = "BTN3"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - pwmleds { compatible = "pwm-leds"; diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts index 96f0546bcfaee..73f12b1072650 100644 --- a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts +++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts @@ -8,7 +8,6 @@ #include #include -#include / { model = "NEORV32 UP5KDemo"; @@ -22,10 +21,6 @@ pwm-led0 = &pwm_led0; pwm-led1 = &pwm_led1; pwm-led2 = &pwm_led2; - sw0 = &btn0; - sw1 = &btn1; - sw3 = &btn2; - sw4 = &btn3; }; chosen { @@ -60,34 +55,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - - btn0: btn0 { - label = "BTN0"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn1: btn1 { - label = "BTN1"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn2: btn2 { - label = "BTN2"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - - btn3: btn3 { - label = "BTN3"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - pwmleds { compatible = "pwm-leds"; diff --git a/boards/others/stm32f103_mini/board.cmake b/boards/others/stm32f103_mini/board.cmake index 12de9c0ee137a..20016aaba8e7e 100644 --- a/boards/others/stm32f103_mini/board.cmake +++ b/boards/others/stm32f103_mini/board.cmake @@ -2,5 +2,5 @@ board_runner_args(jlink "--device=STM32F103RC" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index 709934b9ad7df..35d5bf72a4b63 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -76,7 +76,7 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio0 4 0>, /* AN */ - <1 0 &gpio1 6 0>, /* RST */ + /* Not a GPIO*/ /* RST */ <2 0 &gpio1 12 0>, /* CS */ <3 0 &gpio1 15 0>, /* SCK */ <4 0 &gpio1 14 0>, /* MISO */ diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index fba45dba2aaf5..5e0f40b8a05fb 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -69,7 +69,7 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio0 4 0>, /* AN */ - <1 0 &gpio1 6 0>, /* RST */ + /* Not a GPIO*/ /* RST */ <2 0 &gpio1 12 0>, /* CS */ <3 0 &gpio1 15 0>, /* SCK */ <4 0 &gpio1 14 0>, /* MISO */ diff --git a/boards/panasonic/panb511evb/Kconfig b/boards/panasonic/panb511evb/Kconfig deleted file mode 100644 index 7b00e24412160..0000000000000 --- a/boards/panasonic/panb511evb/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -# PANB511EVB configuration - -if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS - -DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) - -config NRF_TRUSTZONE_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) - help - This defines the flash region size from the TrustZone perspective. - It is used when configuring the TrustZone and when setting alignments - requirements for the partitions. - This abstraction allows us to configure TrustZone without depending - on peripheral-specific symbols. - -config NRF_TRUSTZONE_RAM_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) - help - This defines the RAM region size from the TrustZone perspective. - It is used when configuring the TrustZone and when setting alignments - requirements for the partitions. - This abstraction allows us to configure TrustZone without depending - on peripheral specific symbols. - -endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb511evb/Kconfig.defconfig b/boards/panasonic/panb511evb/Kconfig.defconfig index 1c4e4be6637d4..03c84b8f538ee 100644 --- a/boards/panasonic/panb511evb/Kconfig.defconfig +++ b/boards/panasonic/panb511evb/Kconfig.defconfig @@ -1,31 +1,9 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - if BOARD_PANB511EVB_NRF54L15_CPUAPP config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_PANB511EVB_NRF54L15_CPUAPP - -if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS - -config BT_CTLR - default BT - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -# By default, if we build for a Non-Secure version of the board, -# enable building with TF-M as the Secure Execution Environment. -config BUILD_WITH_TFM - default y - -endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb511evb/Kconfig.panb511evb b/boards/panasonic/panb511evb/Kconfig.panb511evb index 12878fd47d4a0..2454aba6270c1 100644 --- a/boards/panasonic/panb511evb/Kconfig.panb511evb +++ b/boards/panasonic/panb511evb/Kconfig.panb511evb @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_PANB511EVB - select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP || BOARD_PANB511EVB_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP select SOC_NRF54L15_CPUFLPR if BOARD_PANB511EVB_NRF54L15_CPUFLPR || \ BOARD_PANB511EVB_NRF54L15_CPUFLPR_XIP diff --git a/boards/panasonic/panb511evb/board.cmake b/boards/panasonic/panb511evb/board.cmake index d6d51e58a39f6..3138d0b04d779 100644 --- a/boards/panasonic/panb511evb/board.cmake +++ b/boards/panasonic/panb511evb/board.cmake @@ -4,15 +4,8 @@ if(CONFIG_SOC_NRF54L15_CPUAPP) board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") elseif(CONFIG_SOC_NRF54L15_CPUFLPR) - board_runner_args(jlink "--device=nRF54L15_RV32") -endif() - -if(CONFIG_BOARD_PANB511EVB_NRF54L15_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l15_cpuflpr.JLinkScript) + board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") endif() include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) diff --git a/boards/panasonic/panb511evb/board.yml b/boards/panasonic/panb511evb/board.yml index 6e2d60bf4a079..a7e9a5901a4f5 100644 --- a/boards/panasonic/panb511evb/board.yml +++ b/boards/panasonic/panb511evb/board.yml @@ -7,42 +7,3 @@ board: variants: - name: xip cpucluster: cpuflpr - - name: ns - cpucluster: cpuapp -runners: - run_once: - '--recover': - - runners: - - nrfjprog - - nrfutil - run: first - groups: - - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip - '--erase': - - runners: - - nrfjprog - - jlink - - nrfutil - run: first - groups: - - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip - '--reset': - - runners: - - nrfjprog - - jlink - - nrfutil - run: last - groups: - - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi index 143a744e792e4..bc3a54459d978 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi @@ -75,24 +75,4 @@ low-power-enable; }; }; - - /* - * Note that P0.04 is the dedicated pin to output the LFCLK - * (32 KHz clock). Add the following line: - * - * to the grtc_default and grtc_sleep node. - * Note that this may will affect the uart30 (CTS) functionality. - */ - /omit-if-no-ref/ grtc_default: grtc_default { - group1 { - psels = ; - }; - }; - - /omit-if-no-ref/ grtc_sleep: grtc_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; }; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml index e911ee9e54c3f..b30e5ffa106b4 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml @@ -14,7 +14,6 @@ flash: 324 supported: - adc - counter - - dmic - gpio - i2c - pwm diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi index 634f758d531a7..bf7922d8069eb 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi @@ -27,12 +27,12 @@ &lfxo { load-capacitors = "internal"; - load-capacitance-femtofarad = <15000>; + load-capacitance-femtofarad = <15500>; }; &hfxo { load-capacitors = "internal"; - load-capacitance-femtofarad = <16000>; + load-capacitance-femtofarad = <15000>; }; ®ulators { diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig index 638fe33f5d475..41648ab5b23b0 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig @@ -16,3 +16,14 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable Cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts deleted file mode 100644 index f4aeab933f8cc..0000000000000 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#define USE_NON_SECURE_ADDRESS_MAP 1 - -#include -#include "panb511evb_nrf54l15_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN B511 EVB nRF54L15 Application MCU"; - compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp"; - - chosen { - zephyr,code-partition = &slot0_ns_partition; - zephyr,sram = &sram0_ns; - zephyr,entropy = &psa_rng; - }; - - /delete-node/ rng; - - psa_rng: psa-rng { - status = "okay"; - }; -}; - -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - -&cpuapp_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the - * last 96kB are reserved for the FLPR MCU. - * - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x0000000 DT_SIZE_K(512)>; - }; - - tfm_ps_partition: partition@80000 { - label = "tfm-ps"; - reg = <0x00080000 DT_SIZE_K(16)>; - }; - - tfm_its_partition: partition@84000 { - label = "tfm-its"; - reg = <0x00084000 DT_SIZE_K(16)>; - }; - - tfm_otp_partition: partition@88000 { - label = "tfm-otp"; - reg = <0x00088000 DT_SIZE_K(8)>; - }; - - slot0_ns_partition: partition@8A000 { - label = "image-0-nonsecure"; - reg = <0x0008A000 DT_SIZE_K(844)>; - }; - - storage_partition: partition@15D000 { - label = "storage"; - reg = <0x00015D000 DT_SIZE_K(32)>; - }; - }; -}; - -&uart20 { - /* Disable so that TF-M can use this UART */ - status = "disabled"; - - current-speed = <115200>; - pinctrl-0 = <&uart20_default>; - pinctrl-1 = <&uart20_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml deleted file mode 100644 index 2a092dea13dff..0000000000000 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -identifier: panb511evb/nrf54l15/cpuapp/ns -name: PANB511-EVB-nRF54l15-Application-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - zephyr -ram: 256 -flash: 1524 -supported: - - adc - - gpio - - i2c - - spi - - counter - - watchdog - - adc - - i2s diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig deleted file mode 100644 index 5f6e098f45287..0000000000000 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Don't enable the cache in the non-secure image as it is a -# secure-only peripheral on 54l -CONFIG_CACHE_MANAGEMENT=n -CONFIG_EXTERNAL_CACHE=n - -CONFIG_UART_CONSOLE=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y - -# Start SYSCOUNTER on driver init -CONFIG_NRF_GRTC_START_SYSCOUNTER=y - -# Disable TFM BL2 since it is not supported -CONFIG_TFM_BL2=n - -# Support for silence logging is not supported at the moment -# Tracked by: NCSDK-31930 -CONFIG_TFM_LOG_LEVEL_SILENCE=n - -# The oscillators are configured as secure and cannot be configured -# from the non secure application directly. This needs to be set -# otherwise nrfx will try to configure them, resulting in a bus -# fault. -CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml index 73d19a5a1807d..23d07a25c9928 100644 --- a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml @@ -22,3 +22,4 @@ supported: - spi - gpio - can +vendor: nxp diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml index e8e0208f8f67a..2af3d88b937a8 100644 --- a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml @@ -20,3 +20,4 @@ testing: supported: - uart - gpio +vendor: nxp diff --git a/boards/pimoroni/pico_plus2/doc/index.rst b/boards/pimoroni/pico_plus2/doc/index.rst index bf77934242d99..28f265e38988e 100644 --- a/boards/pimoroni/pico_plus2/doc/index.rst +++ b/boards/pimoroni/pico_plus2/doc/index.rst @@ -42,16 +42,15 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. -See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. - -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. +The overall explanation regarding flashing and debugging is the same as or ``rpi_pico``. +See :ref:`rpi_pico_flashing_using_openocd` and :ref:`rpi_pico_flashing_using_uf2` +in ``rpi_pico`` documentation. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: pico_plus2/rp2350b/m33 + :board: pico_plus2 :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd .. target-notes:: diff --git a/boards/pjrc/teensy4/Kconfig.defconfig b/boards/pjrc/teensy4/Kconfig.defconfig index fbd4928b386ba..2af9d12ef9f09 100644 --- a/boards/pjrc/teensy4/Kconfig.defconfig +++ b/boards/pjrc/teensy4/Kconfig.defconfig @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if BOARD_TEENSY40 || BOARD_TEENSY41 || BOARD_TEENSYMM +if BOARD_TEENSY40 || BOARD_TEENSY41 config BUILD_OUTPUT_HEX bool diff --git a/boards/pjrc/teensy4/Kconfig.teensymm b/boards/pjrc/teensy4/Kconfig.teensymm deleted file mode 100644 index 0e1f5da383c3e..0000000000000 --- a/boards/pjrc/teensy4/Kconfig.teensymm +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_TEENSYMM - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/pjrc/teensy4/board.cmake b/boards/pjrc/teensy4/board.cmake index b30dc4f716178..bd6ec2b59e041 100644 --- a/boards/pjrc/teensy4/board.cmake +++ b/boards/pjrc/teensy4/board.cmake @@ -3,11 +3,9 @@ board_set_flasher_ifnset(teensy) if(CONFIG_BOARD_TEENSY40) - board_runner_args(teensy "--mcu=TEENSY40") -elseif(CONFIG_BOARD_TEENSYMM) - board_runner_args(teensy "--mcu=TEENSY_MICROMOD") +board_runner_args(teensy "--mcu=TEENSY40") else() - board_runner_args(teensy "--mcu=TEENSY41") +board_runner_args(teensy "--mcu=TEENSY41") endif() include(${ZEPHYR_BASE}/boards/common/teensy.board.cmake) diff --git a/boards/pjrc/teensy4/board.yml b/boards/pjrc/teensy4/board.yml index 2c9d00574671f..0ae483ebc2c70 100644 --- a/boards/pjrc/teensy4/board.yml +++ b/boards/pjrc/teensy4/board.yml @@ -9,8 +9,3 @@ boards: vendor: pjrc socs: - name: mimxrt1062 - - name: teensymm - full_name: Teensy MicroMod - vendor: pjrc - socs: - - name: mimxrt1062 diff --git a/boards/pjrc/teensy4/doc/img/teensymm.webp b/boards/pjrc/teensy4/doc/img/teensymm.webp deleted file mode 100644 index 1a3267da23789..0000000000000 Binary files a/boards/pjrc/teensy4/doc/img/teensymm.webp and /dev/null differ diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst index 6e767f3701680..3517b1fb70fad 100644 --- a/boards/pjrc/teensy4/doc/index.rst +++ b/boards/pjrc/teensy4/doc/index.rst @@ -28,14 +28,6 @@ programming is done via the USB port. (Credit: https://www.pjrc.com) - .. group-tab:: Sparkfun Teensy Micromod - - .. figure:: img/teensymm.webp - :align: center - :alt: TEENSYMM - - (Credit: https://www.sparkfun.com) - Hardware ******** @@ -64,17 +56,6 @@ Hardware See the `Teensy 4.1 Website`_ for a complete hardware description. - .. group-tab:: Sparkfun Teensy Micromod - - - MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory) - - 128 Mbit QSPI Flash - - User LED - - USB 2.0 host connector - - USB 2.0 OTG connector - - TF socket for SD card - - See the `Teensy Micromod Website`_ for a complete hardware description. - For more information, check the `i.MX RT1060 Datasheet`_. Supported Features @@ -207,7 +188,7 @@ Pin mappings from Teensy to MIMXRT1062 SoC. | 33 | EMC_07 | GPIO4_7 | +-----+------------+-------------------------------------+ -Only Teensy 4.0 and Teensy Micromod: +Only Teensy 4.0: +-----+------------+-------------------------------------+ | 34 | SD_B0_03 | GPIO3_15 | @@ -223,22 +204,6 @@ Only Teensy 4.0 and Teensy Micromod: | 39 | SD_B0_04 | GPIO3_16 | +-----+------------+-------------------------------------+ -Only Teensy Micromod - -+-----+------------+-------------------------------------+ -| 40 | B0_04 | GPIO2_4 / I2C2 SCL | -+-----+------------+-------------------------------------+ -| 41 | B0_05 | GPIO2_5 / I2C2 SDA | -+-----+------------+-------------------------------------+ -| 42 | B0_06 | GPIO2_6 | -+-----+------------+-------------------------------------+ -| 43 | B0_07 | GPIO2_7 | -+-----+------------+-------------------------------------+ -| 44 | B0_08 | GPIO2_8 / UART3 TX | -+-----+------------+-------------------------------------+ -| 45 | B0_09 | GPIO2_9 / UART3 RX | -+-----+------------+-------------------------------------+ - Only Teensy 4.1: +-----+------------+-------------------------------------+ @@ -256,114 +221,8 @@ Only Teensy 4.1: +-----+------------+-------------------------------------+ | 40 | AD_B1_04 | GPIO1_20 | +-----+------------+-------------------------------------+ -| 41 | AD_B1_05 | GPIO1_21 / UART3_RX | -+-----+------------+-------------------------------------+ - -Pin mappings from Teensy Micromod pins to MIMXRT1062 SoC. - -Teensy Micromod only: - -+-----+-----+------+------------+-----------------------------------+ -|MMOD | MMC | Pin | Pad ID | Usage | -+=====+=====+======+============+===================================+ -| 8 | 16 | 27 | AD_B1_15 | / SPI3_SCK | -+-----+-----+------+------------+-----------------------------------+ -| 10 | 2 | 4 | EMC_06 | | -+-----+-----+------+------------+-----------------------------------+ -| 12 | | 18 | AD_B1_01 | / I2C1_SDA | -+-----+-----+------+------------+-----------------------------------+ -| 14 | | 19 | AD_B1_00 | / I2C1_SCL | -+-----+-----+------+------------+-----------------------------------+ -| 16 | 4 | 29 | EMC_31 | / UART7_TX | -+-----+-----+------+------------+-----------------------------------+ -| 17 | | 1 | AD_B0_02 | / UART6_TX / CAN2_TX | -+-----+-----+------+------------+-----------------------------------+ -| 18 | 3 | 5 | EMC_08 | | -+-----+-----+------+------------+-----------------------------------+ -| 19 | | 0 | AD_B0_03 | / UART6_RX / CAN2_RX | -+-----+-----+------+------------+-----------------------------------+ -| 20 | | 16 | AD_B1_07 | / UART3_RX / I2C3_SCL | -+-----+-----+------+------------+-----------------------------------+ -| 22 | | 17 | AD_B1_06 | / UART3_TX / I2C3_SDA | -+-----+-----+------+------------+-----------------------------------+ -| 32 | | 3 | EMC_05 | | -+-----+-----+------+------------+-----------------------------------+ -| 34 | 0 | 14 | AD_B1_02 | / UART2_TX | -+-----+-----+------+------------+-----------------------------------+ -| 38 | 1 | 15 | AD_B1_03 | / UART2_RX | -+-----+-----+------+------------+-----------------------------------+ -| 4 | | 28 | EMC_32 | / UART7_RX | -+-----+-----+------+------------+-----------------------------------+ -| 40 | 5 | 40 | B0_04 | / I2C2 SCL | -+-----+-----+------+------------+-----------------------------------+ -| 41 | | 30 | EMC_37 | / CAN3_RX | -+-----+-----+------+------------+-----------------------------------+ -| 42 | 6 | 41 | B0_05 | / I2C2 SDA | -+-----+-----+------+------------+-----------------------------------+ -| 43 | | 31 | EMC_36 | / CAN3_TX | -+-----+-----+------+------------+-----------------------------------+ -| 44 | 7 | 42 | B0_06 | | -+-----+-----+------+------------+-----------------------------------+ -| 46 | 8 | 43 | B0_07 | | -+-----+-----+------+------------+-----------------------------------+ -| 47 | | 2 | EMC_04 | | -+-----+-----+------+------------+-----------------------------------+ -| 48 | 9 | 44 | B0_08 | / UART3 TX | -+-----+-----+------+------------+-----------------------------------+ -| 49 | | 22 | AD_B1_08 | / CAN1_TX | -+-----+-----+------+------------+-----------------------------------+ -| 50 | | 21 | AD_B1_11 | / UART8_RX | -+-----+-----+------+------------+-----------------------------------+ -| 51 | | 25 | AD_B0_13 | / UART1_RX / I2C4_SDA | -+-----+-----+------+------------+-----------------------------------+ -| 52 | | 20 | AD_B1_10 | / UART8_TX | -+-----+-----+------+------------+-----------------------------------+ -| 53 | | 24 | AD_B0_12 | / UART1_TX / I2C4_SCL | -+-----+-----+------+------------+-----------------------------------+ -| 54 | | 8 | B1_00 | / UART4_TX | -+-----+-----+------+------------+-----------------------------------+ -| 55 | 17 | 10 | B0_00 | | -+-----+-----+------+------------+-----------------------------------+ -| 56 | | 7 | B1_01 | / UART4_RX | -+-----+-----+------+------------+-----------------------------------+ -| 57 | | 13 | B0_03 | / LED | -+-----+-----+------+------------+-----------------------------------+ -| 58 | | 23 | AD_B1_09 | / CAN1_RX | -+-----+-----+------+------------+-----------------------------------+ -| 59 | | 11 | B0_02 | | -+-----+-----+------+------------+-----------------------------------+ -| 60 | | 36 | SD_B0_01 | | -+-----+-----+------+------------+-----------------------------------+ -| 61 | | 12 | B0_01 | | -+-----+-----+------+------------+-----------------------------------+ -| 62 | | 37 | SD_B0_00 | | -+-----+-----+------+------------+-----------------------------------+ -| 63 | 15 | 33 | EMC_07 | | -+-----+-----+------+------------+-----------------------------------+ -| 64 | | 35 | SD_B0_02 | | -+-----+-----+------+------------+-----------------------------------+ -| 65 | 14 | 32 | B0_12 | | -+-----+-----+------+------------+-----------------------------------+ -| 66 | | 34 | SD_B0_03 | | -+-----+-----+------+------------+-----------------------------------+ -| 67 | 13 | 26 | AD_B1_14 | / SPI3_MOSI | -+-----+-----+------+------------+-----------------------------------+ -| 68 | | 38 | SD_B0_05 | | -+-----+-----+------+------------+-----------------------------------+ -| 69 | 12 | 9 | B0_11 | | -+-----+-----+------+------------+-----------------------------------+ -| 70 | | 39 | SD_B0_04 | | -+-----+-----+------+------------+-----------------------------------+ -| 71 | 11 | 6 | B0_10 | | -+-----+-----+------+------------+-----------------------------------+ -| 73 | 10 | 45 | B0_09 | / UART3 RX | -+-----+-----+------+------------+-----------------------------------+ - -MMOD = Physical Micromod pin number -MMC = Zephyr micromod_header connector pin number -Pin = Arduino Pin number -Pad ID = MIMXRT1062 pad id -Usage = Some usages of the pin +| 41 | AD_B1_05 | GPIO1_21 | ++-----+------------+-------------------------------------+ Programming and Debugging ************************* @@ -371,9 +230,9 @@ Programming and Debugging Flashing ======== -The Teensy 4.0 and Teensy 4.1 and Micromod ship with a dedicated bootloader -chip, which supports flashing using USB. This allows easy flashing of new -images, but does not support debugging the device. +Both the Teensy 4.0 and Teensy 4.1 ship with a dedicated bootloader chip, +which supports flashing using USB. This allows easy flashing of new images, +but does not support debugging the device. #. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. @@ -395,14 +254,6 @@ images, but does not support debugging the device. :goals: build :compact: - .. group-tab:: Teensy Micromod - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: teensymm - :goals: build - :compact: - #. Connect the board to your host computer using USB. #. Tap the reset button to enter bootloader mode. @@ -428,15 +279,6 @@ images, but does not support debugging the device. :goals: flash :compact: - .. group-tab:: Teensy Micromod - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: teensymm - :goals: flash - :compact: - - #. You should see the orange LED blink. Configuring a Console @@ -493,8 +335,5 @@ References .. _Teensy 4.1 Ethernet Kit: https://www.pjrc.com/store/ethernet_kit.html -.. _Teensy Micromod Website: - https://www.sparkfun.com/sparkfun-micromod-teensy-processor.html - .. _i.MX RT1060 Datasheet: https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf diff --git a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi index 16691972a416f..c12573cb6b38e 100644 --- a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi +++ b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi @@ -99,19 +99,6 @@ }; }; - /* LPI2C2 SCL, SDA on Teensy-Micromod-Pins 40/41 */ - pinmux_lpi2c2: pinmux_lpi2c2 { - group0 { - pinmux = <&iomuxc_gpio_b0_04_lpi2c2_scl>, - <&iomuxc_gpio_b0_05_lpi2c2_sda>; - drive-strength = "r0-6"; - drive-open-drain; - slew-rate = "slow"; - nxp,speed = "100-mhz"; - input-enable; - }; - }; - /* LPI2C3 SCL, SDA on Teensy-Pins 16/17 */ pinmux_lpi2c3: pinmux_lpi2c3 { group0 { diff --git a/boards/pjrc/teensy4/teensy40.yaml b/boards/pjrc/teensy4/teensy40.yaml index 7adb0e38fe0ef..a4908dc6abd3c 100644 --- a/boards/pjrc/teensy4/teensy40.yaml +++ b/boards/pjrc/teensy4/teensy40.yaml @@ -21,3 +21,4 @@ testing: ignore_tags: - net - posix +vendor: nxp diff --git a/boards/pjrc/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml index 78c71007aca2a..659f6838ffa91 100644 --- a/boards/pjrc/teensy4/teensy41.yaml +++ b/boards/pjrc/teensy4/teensy41.yaml @@ -23,3 +23,4 @@ testing: ignore_tags: - net - posix +vendor: nxp diff --git a/boards/pjrc/teensy4/teensymm.dts b/boards/pjrc/teensy4/teensymm.dts deleted file mode 100644 index cfaff007a3ebb..0000000000000 --- a/boards/pjrc/teensy4/teensymm.dts +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2020, Bernhard Kraemer - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "teensy40.dts" - -/ { - model = "PJRC TEENSY Micromod board"; - - chosen { - zephyr,flash-controller = &w25q128jvxgim; - zephyr,flash = &w25q128jvxgim; - }; - - micromod_header: connector { - compatible = "sparkfun,micromod-gpio"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 18 0>, /* A0 MMOD 34 */ - <1 0 &gpio1 19 0>, /* A1 MMOD 38 */ - <2 0 &gpio4 6 0>, /* D0 MMOD 10 */ - <3 0 &gpio4 8 0>, /* D1/CAM_TRIG MMOD 18 */ - <4 0 &gpio4 31 0>, /* I2C_INT# MMOD 16 */ - <5 0 &gpio2 4 0>, /* G0/BUS0 MMOD 40 */ - <6 0 &gpio2 5 0>, /* G1/BUS1 MMOD 42 */ - <7 0 &gpio2 6 0>, /* G2/BUS2 MMOD 44 */ - <8 0 &gpio2 7 0>, /* G3/BUS3 MMOD 46 */ - <9 0 &gpio2 8 0>, /* G4/BUS4 MMOD 48 */ - <10 0 &gpio2 9 0>, /* G5/BUS5 MMOD 73 */ - <11 0 &gpio2 10 0>, /* G6/BUS6 MMOD 71 */ - <12 0 &gpio2 11 0>, /* G7/BUS7 MMOD 69 */ - <13 0 &gpio1 30 0>, /* G8 MMOD 67 */ - <14 0 &gpio2 12 0>, /* G9/ADC_D-/ MMOD 65 */ - <15 0 &gpio4 7 0>, /* G10/ADC_D+ MMOD 63 */ - <16 0 &gpio1 31 0>, /* G11/SWO MMOD 8 */ - <17 0 &gpio2 0 0>; /* SPI_CS MMOD 55 */ - }; -}; - -/delete-node/ &w25q16jvuxim; -&flexspi { - status = "okay"; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - - /* WINBOND flash memory*/ - w25q128jvxgim: w25q128jvxgim@0 { - compatible = "nxp,imx-flexspi-nor"; - size = ; - reg = <0>; - spi-max-frequency = ; - status = "okay"; - jedec-id = [ef 70 18]; - - erase-block-size = <4096>; - write-block-size = <1>; - }; -}; - -&lpi2c2 { - pinctrl-0 = <&pinmux_lpi2c2>; - pinctrl-names = "default"; -}; - -&usdhc1 { - no-1-8-v; - pinctrl-0 = <&pinmux_usdhc1>; - pinctrl-1 = <&pinmux_usdhc1_slow>; - pinctrl-2 = <&pinmux_usdhc1_med>; - pinctrl-3 = <&pinmux_usdhc1_fast>; - pinctrl-names = "default", "slow", "med", "fast"; -}; - -// Sparkfun Micromod compatible pins -micromod_1_uart: &lpuart6 {}; -micromod_2_uart: &lpuart3 {}; -micromod_0_i2c: &lpi2c1 {}; -micromod_1_i2c: &lpi2c4 {}; -micromod_0_spi: &lpspi4 {}; diff --git a/boards/pjrc/teensy4/teensymm.yaml b/boards/pjrc/teensy4/teensymm.yaml deleted file mode 100644 index cd837fbfb323a..0000000000000 --- a/boards/pjrc/teensy4/teensymm.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: teensymm -name: PJRC TEENSY_MICROMOD -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 768 -flash: 8192 -supported: - - counter - - gpio - - usb_device -testing: - ignore_tags: - - net - - posix -vendor: sparkfun diff --git a/boards/pjrc/teensy4/teensymm_defconfig b/boards/pjrc/teensy4/teensymm_defconfig deleted file mode 100644 index e73b48be0a3aa..0000000000000 --- a/boards/pjrc/teensy4/teensymm_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_DEVICE_CONFIGURATION_DATA=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml index a6580f600cf48..d409cbf34b75e 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml @@ -12,5 +12,4 @@ testing: ignore_tags: - net - bluetooth -ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml index eb98b65327313..0e568f34a794c 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml @@ -13,5 +13,4 @@ testing: ignore_tags: - net - bluetooth -ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml index 580b580582323..819a8cf924960 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml @@ -12,5 +12,4 @@ testing: ignore_tags: - net - bluetooth -ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml index e7593464ba10d..901d15dd34f4c 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml @@ -12,5 +12,4 @@ testing: ignore_tags: - net - bluetooth -ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml index 1032fd47b1560..928ec24190e43 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml @@ -12,5 +12,4 @@ testing: ignore_tags: - net - bluetooth -ram: 4096 vendor: snps diff --git a/boards/qemu/nios2/Kconfig b/boards/qemu/nios2/Kconfig new file mode 100644 index 0000000000000..22dbe91795483 --- /dev/null +++ b/boards/qemu/nios2/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select QEMU_TARGET diff --git a/boards/qemu/nios2/Kconfig.defconfig b/boards/qemu/nios2/Kconfig.defconfig new file mode 100644 index 0000000000000..81494ff905ec4 --- /dev/null +++ b/boards/qemu/nios2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_NIOS2 + +config BUILD_OUTPUT_BIN + default n + +endif diff --git a/boards/qemu/nios2/Kconfig.qemu_nios2 b/boards/qemu/nios2/Kconfig.qemu_nios2 new file mode 100644 index 0000000000000..23292f07ffb12 --- /dev/null +++ b/boards/qemu/nios2/Kconfig.qemu_nios2 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select SOC_QEMU_NIOS2 diff --git a/boards/qemu/nios2/board.cmake b/boards/qemu/nios2/board.cmake new file mode 100644 index 0000000000000..9f9bf21124c84 --- /dev/null +++ b/boards/qemu/nios2/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} nios2) + +set(QEMU_FLAGS_${ARCH} + -machine altera_10m50_zephyr + -nographic + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/nios2/board.yml b/boards/qemu/nios2/board.yml new file mode 100644 index 0000000000000..aae1184806201 --- /dev/null +++ b/boards/qemu/nios2/board.yml @@ -0,0 +1,6 @@ +board: + name: qemu_nios2 + full_name: QEMU Emulation for Altera Nios-II + vendor: altr + socs: + - name: qemu_nios2 diff --git a/boards/qemu/nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst new file mode 100644 index 0000000000000..235b9b41be40f --- /dev/null +++ b/boards/qemu/nios2/doc/index.rst @@ -0,0 +1,127 @@ +.. zephyr:board:: qemu_nios2 + +Overview +******** + +This board configuration will use QEMU to emulate the Altera MAX 10 platform. + +This configuration provides support for an Altera Nios-II CPU and these devices: + +* Internal Interrupt Controller +* Altera Avalon Timer +* NS16550 UART + +.. note:: + This board configuration makes no claims about its suitability for use + with an actual ti_lm3s6965 hardware system, or any other hardware system. + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+============+======================+ +| IIC | on-chip | Internal interrupt | +| | | controller | ++--------------+------------+----------------------+ +| NS16550 | on-chip | serial port | +| UART | | | ++--------------+------------+----------------------+ +| TIMER | on-chip | system clock | ++--------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 50 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART0. + +If SLIP networking is enabled (see below), an additional serial port will be +used for it. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Memory protection through optional MPU. However, using a XIP kernel + effectively provides TEXT/RODATA write protection in ROM. +* Writing to the hardware's flash memory +* Serial port in Direct Memory Access (DMA) mode +* Serial Peripheral Interface (SPI) flash +* General-Purpose Input/Output (GPIO) +* Inter-Integrated Circuit (I2C) +* Ethernet + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_nios2 + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 ***** + threadA: Hello World from arm! + threadB: Hello World from arm! + threadA: Hello World from arm! + threadB: Hello World from arm! + threadA: Hello World from arm! + threadB: Hello World from arm! + threadA: Hello World from arm! + threadB: Hello World from arm! + threadA: Hello World from arm! + threadB: Hello World from arm! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +Networking +========== + +The board supports SLIP networking over an emulated serial port +(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in +:ref:`networking_with_qemu`. + +References +********** + +* `CPU Documentation `_ +* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ +* `Embedded Peripherals IP User Guide `_ +* `MAX 10 FPGA Configuration User Guide `_ +* `MAX 10 FPGA Development Kit User Guide `_ +* `Nios II Command-Line Tools `_ +* `Quartus II Scripting Reference Manual `_ + + +.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite diff --git a/boards/qemu/nios2/qemu_nios2.dts b/boards/qemu/nios2/qemu_nios2.dts new file mode 100644 index 0000000000000..4d9f14130b58b --- /dev/null +++ b/boards/qemu/nios2/qemu_nios2.dts @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + model = "qemu_nios2"; + compatible = "qemu,nios2"; + + aliases { + uart-0 = &jtag_uart; + uart-1 = &ns16550_uart; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &ns16550_uart; + zephyr,shell-uart = &ns16550_uart; + }; +}; + +&jtag_uart { + status = "okay"; + current-speed = <115200>; +}; + +&ns16550_uart { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/qemu/nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml new file mode 100644 index 0000000000000..816c280b5a024 --- /dev/null +++ b/boards/qemu/nios2/qemu_nios2.yaml @@ -0,0 +1,16 @@ +identifier: qemu_nios2 +name: QEMU Emulation for NIOS II +type: qemu +simulation: + - name: qemu +arch: nios2 +ram: 128 +flash: 128 +toolchain: + - zephyr +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: qemu diff --git a/boards/qemu/nios2/qemu_nios2_defconfig b/boards/qemu/nios2/qemu_nios2_defconfig new file mode 100644 index 0000000000000..feda1075277c3 --- /dev/null +++ b/boards/qemu/nios2/qemu_nios2_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HAS_ALTERA_HAL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_INCLUDE_RESET_VECTOR=n +CONFIG_EXTRA_EXCEPTION_INFO=y +CONFIG_QEMU_ICOUNT_SHIFT=4 diff --git a/boards/qemu/rx/Kconfig b/boards/qemu/rx/Kconfig deleted file mode 100644 index 7af558e1bc1ec..0000000000000 --- a/boards/qemu/rx/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RX - select QEMU_TARGET diff --git a/boards/qemu/rx/Kconfig.deconfig b/boards/qemu/rx/Kconfig.deconfig deleted file mode 100644 index ad7e4d2128570..0000000000000 --- a/boards/qemu/rx/Kconfig.deconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2025 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_RX - -config BUILD_OUTPUT_BIN - default n - -# DWT is not properly emulated in QEMU -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE -endchoice - -endif # BOARD_QEMU_RX diff --git a/boards/qemu/rx/Kconfig.qemu_rx b/boards/qemu/rx/Kconfig.qemu_rx deleted file mode 100644 index 625df6b783c37..0000000000000 --- a/boards/qemu/rx/Kconfig.qemu_rx +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RX - select SOC_R5F562N8 diff --git a/boards/qemu/rx/board.cmake b/boards/qemu/rx/board.cmake deleted file mode 100644 index 7f0dd6983398e..0000000000000 --- a/boards/qemu/rx/board.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_MACH gdbsim-r5f562n8) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine ${QEMU_MACH} - ) - -if(CONFIG_XIP) - set(QEMU_KERNEL_OPTION - -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ) -endif() - -board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/rx/board.yml b/boards/qemu/rx/board.yml deleted file mode 100644 index 2ecd19f7518d8..0000000000000 --- a/boards/qemu/rx/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: qemu_rx - full_name: QEMU Emulation for Renesas RX - vendor: renesas - socs: - - name: r5f562n8 diff --git a/boards/qemu/rx/doc/index.rst b/boards/qemu/rx/doc/index.rst deleted file mode 100644 index ac38e5906ce41..0000000000000 --- a/boards/qemu/rx/doc/index.rst +++ /dev/null @@ -1,86 +0,0 @@ -.. zephyr:board:: qemu_rx - -Overview -******** - -This board configuration will use QEMU to emulate the Renesas RXv1 platform. - -This configuration provides support for the R5F562N8 MCU and below devices: - -* On-chip memory (ROM 512KB, RAM 96KB) -* Interrupt Control Unit (ICUa) -* Compare Match Timer x 2CH (CMT0,1) -* Serial Communication Interface x 1CH (SCI0) - -Hardware -******** - -Supported Features -================== - -The following hardware features are supported: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| ICU | on-chip | interrupt controller | -+----------------+------------+----------------------+ -| CMT timer | on-chip | system clock | -+----------------+------------+----------------------+ -| SCI UART | on-chip | serial port | -+----------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 6 MHz generated by the CMT timer. - -Serial Port ------------ - -This board configuration uses a single serial communication channel -on the SCI UART channel 0. - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_rx - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build v4.1.0-3157-gb30f8b6a7327 *** - thread_a: Hello World from cpu 0 on qemu_rx! - thread_b: Hello World from cpu 0 on qemu_rx! - thread_a: Hello World from cpu 0 on qemu_rx! - thread_b: Hello World from cpu 0 on qemu_rx! - thread_a: Hello World from cpu 0 on qemu_rx! - thread_b: Hello World from cpu 0 on qemu_rx! - thread_a: Hello World from cpu 0 on qemu_rx! - thread_b: Hello World from cpu 0 on qemu_rx! - thread_a: Hello World from cpu 0 on qemu_rx! - thread_b: Hello World from cpu 0 on qemu_rx! - - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - - -References -********** - -https://www.qemu.org/ diff --git a/boards/qemu/rx/qemu_rx.dts b/boards/qemu/rx/qemu_rx.dts deleted file mode 100644 index 4b2f7672769fd..0000000000000 --- a/boards/qemu/rx/qemu_rx.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -/ { - model = "Renesas QEMU"; - compatible = "qemu,rx","renesas,rxv1"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &code_flash; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; - - aliases { - serial0 = &uart0; - }; -}; - -&sci0 { - status = "okay"; - - uart0: uart { - current-speed = <115200>; - status = "okay"; - }; -}; - -&xtal { - clock-frequency = ; - mosel = <0>; - #clock-cells = <0>; - status = "okay"; -}; - -&subclk { - status = "okay"; -}; - -&pll { - div = <2>; - mul = ; - status = "okay"; -}; - -&cmt { - clock-frequency = <6000000>; - status = "okay"; -}; diff --git a/boards/qemu/rx/qemu_rx.yaml b/boards/qemu/rx/qemu_rx.yaml deleted file mode 100644 index 86c6513f13897..0000000000000 --- a/boards/qemu/rx/qemu_rx.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -identifier: qemu_rx -name: QEMU Emulation for Renesas RX -type: qemu -simulation: - - name: qemu -arch: rx -toolchain: - - cross-compile -supported: - - serial -ram: 96 -flash: 512 diff --git a/boards/qemu/rx/qemu_rx_defconfig b/boards/qemu/rx/qemu_rx_defconfig deleted file mode 100644 index ebf97f4f75536..0000000000000 --- a/boards/qemu/rx/qemu_rx_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_QEMU_ICOUNT_SHIFT=5 -CONFIG_QEMU_ICOUNT=y diff --git a/boards/qemu/x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml index 7764194773093..3fa3fd18a3cc4 100644 --- a/boards/qemu/x86/qemu_x86_64.yaml +++ b/boards/qemu/x86/qemu_x86_64.yaml @@ -17,5 +17,4 @@ testing: ignore_tags: - net - bluetooth -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml index 221f5665891f7..c776a903163f1 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml @@ -13,8 +13,6 @@ testing: only_tags: - kernel - userspace - - llext ignore_tags: - benchmark -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml index 5a468d8d6bba9..83a396d06db3b 100644 --- a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml @@ -11,8 +11,6 @@ testing: only_tags: - kernel - userspace - - llext ignore_tags: - benchmark -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml index b1644407fffd5..dfb264fb4743a 100644 --- a/boards/qemu/x86/qemu_x86_atom_nopae.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml @@ -11,8 +11,6 @@ testing: only_tags: - kernel - userspace - - llext ignore_tags: - benchmark -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml index 156afae475f0f..8794d17df9faa 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt.yaml +++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml @@ -11,8 +11,6 @@ testing: only_tags: - kernel - userspace - - llext ignore_tags: - benchmark -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml index f498803c3de33..6607c68681fe6 100644 --- a/boards/qemu/x86/qemu_x86_atom_xip.yaml +++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml @@ -10,6 +10,4 @@ testing: default: true only_tags: - xip - - llext -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml index 0a00089884fc9..3d6103d940424 100644 --- a/boards/qemu/x86/qemu_x86_lakemont.yaml +++ b/boards/qemu/x86/qemu_x86_lakemont.yaml @@ -13,5 +13,4 @@ testing: - kernel ignore_tags: - benchmark -ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml index 6699515cdc154..29197ecd6d867 100644 --- a/boards/qemu/x86/qemu_x86_tiny.yaml +++ b/boards/qemu/x86/qemu_x86_tiny.yaml @@ -11,8 +11,6 @@ testing: only_tags: - kernel - userspace - - llext ignore_tags: - benchmark -ram: 256 vendor: qemu diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml index 32a806f43159c..9285fa04e9e40 100644 --- a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml @@ -4,8 +4,6 @@ type: qemu simulation: - name: qemu arch: xtensa -toolchain: - - zephyr testing: default: true ignore_tags: diff --git a/boards/rakwireless/rak3172/board.cmake b/boards/rakwireless/rak3172/board.cmake index 37a3c858d04d8..8d07af6287391 100644 --- a/boards/rakwireless/rak3172/board.cmake +++ b/boards/rakwireless/rak3172/board.cmake @@ -4,8 +4,6 @@ board_runner_args(pyocd "--target=stm32wle5ccux") board_runner_args(pyocd "--flash-opt=-O cmsis_dap.limit_packets=1") board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/rakwireless/rak3172/rak3172.dts b/boards/rakwireless/rak3172/rak3172.dts index 7685fa66af095..afd16df61c0b8 100644 --- a/boards/rakwireless/rak3172/rak3172.dts +++ b/boards/rakwireless/rak3172/rak3172.dts @@ -6,7 +6,6 @@ /dts-v1/; #include #include -#include / { model = "RAKWireless RAK3172 WisDuo LPWAN Module with a STM32WLE5CC SoC"; @@ -43,16 +42,20 @@ &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + status = "okay"; +}; + +&clk_lsi { status = "okay"; }; &pll { div-m = <1>; - mul-n = <3>; + mul-n = <6>; div-r = <2>; div-q = <2>; - clocks = <&clk_hse>; + clocks = <&clk_hsi>; status = "okay"; }; @@ -95,7 +98,7 @@ &rtc { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, - <&rcc STM32_SRC_LSE RTC_SEL(1)>; + <&rcc STM32_SRC_LSI RTC_SEL(2)>; status = "okay"; }; @@ -111,6 +114,26 @@ status = "okay"; }; +&clk_lse { + clock-frequency = <32768>; +}; + +&clk_hsi { + status = "okay"; +}; + +&subghzspi { + status = "okay"; + + lora: radio@0 { + status = "okay"; + tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */ + rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */ + power-amplifier-output = "rfo-lp"; + rfo-lp-max-power = <14>; + }; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5.dts index 339adba011c8f..3f942d4e6f501 100644 --- a/boards/raspberrypi/rpi_5/rpi_5.dts +++ b/boards/raspberrypi/rpi_5/rpi_5.dts @@ -24,7 +24,6 @@ zephyr,console = &uart10; zephyr,shell-uart = &uart10; zephyr,pcie-controller = &pcie1; - zephyr,entropy = &rng; }; leds { diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index ea279a9319201..b82b484f4f2ae 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -130,11 +130,20 @@ Raspberry Pi Pico's PIO is a programmable chip that can implement a variety of p - :kconfig:option:`CONFIG_LED_STRIP` - :dtcompatible:`worldsemi,ws2812-rpi_pico-pio` +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``rpi_pico`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + System requirements -******************* +=================== Prerequisites for the Pico W -============================ +---------------------------- Building for the Raspberry Pi Pico W requires the AIROC binary blobs provided by Infineon. Run the command below to retrieve those files: @@ -147,23 +156,26 @@ provided by Infineon. Run the command below to retrieve those files: It is recommended running the command above after :file:`west update`. -.. _rpi_pico_programming_and_debugging: - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``rpi_pico`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). +Debug Probe and Host Tools +-------------------------- Several debugging tools support the Raspberry Pi Pico. The `Raspberry Pi Debug Probe`_ is an easy-to-obtain CMSIS-DAP adapter officially provided by the Raspberry Pi Foundation, making it a convenient choice for debugging ``rpi_pico``. -It can be used with ``openocd`` or ``pyocd``. +It can be used with + +- :ref:`openocd-debug-host-tools` +- :ref:`pyocd-debug-host-tools` + +OpenOCD is the default for ``rpi_pico``. + +- `SEGGER J-Link`_ +- `Black Magic Debug Probe `_ + +can also be used. +These are used with dedicated probes. Flashing ======== @@ -171,6 +183,20 @@ Flashing The ``rpi_pico`` can flash with Zephyr's standard method. See also :ref:`Building, Flashing and Debugging`. +Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rpi_pico + :goals: build + +.. code-block:: console + + west flash --runner jlink + + +.. _rpi_pico_flashing_using_openocd: + Using OpenOCD ------------- @@ -190,14 +216,13 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app :zephyr-app: samples/basic/blinky :board: rpi_pico :goals: build flash - :gen-args: -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap - :flash-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap -Set the flash runner option **--openocd** to :file:`/usr/local/bin/openocd`. This should work +Set the CMake option **OPENOCD** to :file:`/usr/local/bin/openocd`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. -In this sample, **RPI_PICO_DEBUG_ADAPTER** specifies which debug adapter is used for debugging. +**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. If **RPI_PICO_DEBUG_ADAPTER** was not set, ``cmsis-dap`` is used by default. The ``raspberrypi-swd`` and ``jlink`` are verified to work. @@ -211,24 +236,7 @@ The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from **RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. - -Using JLink or other supported tools ------------------------------------- - -You can Flash with a `SEGGER J-Link`_ debug probe as described in -:ref:`Building, Flashing and Debugging `. - -Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: rpi_pico - :goals: build flash - :flash-args: --runner jlink - -You can also use other supported tools, such as `Black Magic Probe`_, -by changing the ``-- runner`` option. - +.. _rpi_pico_flashing_using_uf2: Using UF2 --------- @@ -236,15 +244,8 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a :file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` -button pressed, it will appear on the host as a mass storage device. -Run the following command, or drag-and-drop the uf2 file to the device, -which will flash the Pico. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: rpi_pico - :goals: flash - :flash-args: --runner uf2 +button pressed, it will appear on the host as a mass storage device. The +UF2 file should be drag-and-dropped to the device, which will flash the Pico. Debugging ========= @@ -259,12 +260,15 @@ the `Raspberry Pi Debug Probe`_. :board: rpi_pico :maybe-skip-config: :goals: debug - :debug-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap The default debugging tool is ``openocd``. If you use a different tool, specify it with the ``--runner``, such as ``jlink``. +If you use OpenOCD, see also the description about flashing :ref:`rpi_pico_flashing_using_uf2` +for more information. + .. target-notes:: @@ -289,5 +293,5 @@ such as ``jlink``. .. _SEGGER J-Link: https://www.segger.com/products/debug-probes/j-link/ -.. _Black Magic Probe: +.. _Black Magic Debug: https://black-magic.org/ diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst index 612497a0b3cc7..a6ed699a8203e 100644 --- a/boards/raspberrypi/rpi_pico2/doc/index.rst +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -42,16 +42,8 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. -See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. - -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: rpi_pico2/rp2350a/m33 - :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd +As with the Pico 1, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . References ********** diff --git a/boards/raytac/an54l15q_db/Kconfig b/boards/raytac/an54l15q_db/Kconfig deleted file mode 100644 index 69aa54f32207a..0000000000000 --- a/boards/raytac/an54l15q_db/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Raytac AN54L15Q-DB board configuration - -if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS - -DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) - -config NRF_TRUSTZONE_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) - help - This defines the flash region size from the TrustZone perspective. - It is used when configuring the TrustZone and when setting alignments - requirements for the partitions. - This abstraction allows us to configure TrustZone without depending - on peripheral-specific symbols. - -config NRF_TRUSTZONE_RAM_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) - help - This defines the RAM region size from the TrustZone perspective. - It is used when configuring the TrustZone and when setting alignments - requirements for the partitions. - This abstraction allows us to configure TrustZone without depending - on peripheral specific symbols. - -endif #BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS diff --git a/boards/raytac/an54l15q_db/Kconfig.defconfig b/boards/raytac/an54l15q_db/Kconfig.defconfig deleted file mode 100644 index 82d59ecdbe3b7..0000000000000 --- a/boards/raytac/an54l15q_db/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP - -config ROM_START_OFFSET - default 0x800 if BOOTLOADER_MCUBOOT - -endif # BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP - -if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS - -config BT_CTLR - default BT - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -# By default, if we build for a Non-Secure version of the board, -# enable building with TF-M as the Secure Execution Environment. -config BUILD_WITH_TFM - default y - -endif # BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS diff --git a/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db b/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db deleted file mode 100644 index 58f42ef31d9d9..0000000000000 --- a/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAYTAC_AN54L15Q_DB - select SOC_NRF54L15_CPUAPP if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP || BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS - select SOC_NRF54L15_CPUFLPR if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUFLPR || \ - BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUFLPR_XIP diff --git a/boards/raytac/an54l15q_db/board.cmake b/boards/raytac/an54l15q_db/board.cmake deleted file mode 100644 index 368bcc9d2fee1..0000000000000 --- a/boards/raytac/an54l15q_db/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_NRF54L15_CPUAPP) - board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") -elseif (CONFIG_SOC_NRF54L15_CPUFLPR) - board_runner_args(jlink "--device=nRF54L15_RV32") -endif() - -if(BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/an54l15q_db/board.yml b/boards/raytac/an54l15q_db/board.yml deleted file mode 100644 index 08d0e2398e7bc..0000000000000 --- a/boards/raytac/an54l15q_db/board.yml +++ /dev/null @@ -1,45 +0,0 @@ -board: - name: raytac_an54l15q_db - full_name: AN54L15Q-DB - vendor: raytac - socs: - - name: nrf54l15 - variants: - - name: xip - cpucluster: cpuflpr - - name: ns - cpucluster: cpuapp -runners: - run_once: - '--recover': - - runners: - - nrfjprog - - nrfutil - run: first - groups: - - boards: - - raytac_an54l15q_db/nrf54l15/cpuapp - - raytac_an54l15q_db/nrf54l15/cpuflpr - - raytac_an54l15q_db/nrf54l15/cpuflpr/xip - '--erase': - - runners: - - nrfjprog - - jlink - - nrfutil - run: first - groups: - - boards: - - raytac_an54l15q_db/nrf54l15/cpuapp - - raytac_an54l15q_db/nrf54l15/cpuflpr - - raytac_an54l15q_db/nrf54l15/cpuflpr/xip - '--reset': - - runners: - - nrfjprog - - jlink - - nrfutil - run: last - groups: - - boards: - - raytac_an54l15q_db/nrf54l15/cpuapp - - raytac_an54l15q_db/nrf54l15/cpuflpr - - raytac_an54l15q_db/nrf54l15/cpuflpr/xip diff --git a/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp b/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp deleted file mode 100644 index 35ecd0b4e90da..0000000000000 Binary files a/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp and /dev/null differ diff --git a/boards/raytac/an54l15q_db/doc/index.rst b/boards/raytac/an54l15q_db/doc/index.rst deleted file mode 100644 index 415b8ef51df39..0000000000000 --- a/boards/raytac/an54l15q_db/doc/index.rst +++ /dev/null @@ -1,150 +0,0 @@ -.. zephyr:board:: raytac_an54l15q_db - -Overview -******** - -The Raytac AN54L15Q-DB demonstration board is a development board based on the Raytac AN54L15Q module. -It uses the Nordic Semiconductor nRF54L15 SoC solution. The idea is to connect all the module's pins -to a 2.54mm pin header. It can easily open the verification module functions and connect with other -peripheral devices and sensor pins, making it a useful tool for early software development. - -.. note:: - You can find more information about the nRF54L15 SoC on the `nRF54L15 website`_. - For the nRF54L15 technical documentation and other resources (such as - SoC Datasheet), see the `nRF54L15 documentation`_ page. - -Hardware -******** - -The Raytac AN54L15Q-DB has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -The crystal oscillators can be configured to use either -internal or external capacitors. - -- Module Demo Board built by AN54L15Q -- Nordic nRF54L15 SoC Solution -- A recommended 3rd-party module by Nordic Semiconductor. -- Intended for Bluetooth specification BT6 -- Intended for FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- 128 MHz ARM® Cortexâ„¢-M33 processor with TrustZone® technology -- 128 MHz RISC-V coprocessor with TrustZone® technology -- 1.5MB Flash Memory / 256KB RAM -- RoHS & Reach Compliant. -- 31 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PDM, PWM, ADC, and NFC -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, - ANT+, Zigbee, Thread (802.15.4), and Matter ultra low-power wireless applications. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P2.09 -* LED1 (green) = P1.10 -* LED2 (green) = P2.07 -* LED3 (green) = P1.14 - -Push buttons ------------- - -* BUTTON1 = SW0 = P1.13 -* BUTTON2 = SW1 = P1.09 -* BUTTON3 = SW2 = P1.08 -* BUTTON4 = SW3 = P0.04 - -UART ----- -* RX = P1.05 -* TX = P1.04 -* RTS = P1.06 -* CTS = P1.07 - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``raytac_an54l15q_db/nrf54l15/cpuapp`` board can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -.. note:: - The ``raytac_an54l15q_db`` board does not have an on-board J-Link debug IC; - Use the Debug out connector of the nRF5340-DK or nRF54L15-DK to connect to the J1 - or J9 SWD connector, and use SEGGER J-Link OB IF to debug. - -Flashing -======== - -As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` -application. - -.. warning:: - - When programming the device, you might get an error similar to the following message:: - - ERROR: The operation attempted is unavailable due to readback protection in - ERROR: your device. Please use --recover to unlock the device. - - This error occurs when readback protection is enabled. - To disable the readback protection, you must *recover* your device. - - Enter the following command to recover the core:: - - west flash --recover - - The ``--recover`` command erases the flash memory and then writes a small binary into - the recovered flash memory. - This binary prevents the readback protection from enabling itself again after a pin - reset or power cycle. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the Raytac AN54L15Q-DB, complete the following steps: - -First, connect the Raytac AN54L15Q-DB's J10 connector to you computer using a USB to TTL -converter. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_an54l15q_db/nrf54l15/cpuapp - :goals: build flash - -References -********** - -.. target-notes:: - -.. _Raytac AN54L15Q-DB website: - https://www.raytac.com/product/ins.php?index_id=139 -.. _Raytac AN54L15Q-DB Specification: - https://www.raytac.com/download/index.php?index_id=60 -.. _Raytac AN54L15Q-DB Schematic: - https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg -.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15 -.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi deleted file mode 100644 index 447143c6a8ae2..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * Copyright (c) 2025 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "raytac_an54l15q_db_pinctrl.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; - label = "Green LED 0"; - }; - - led1: led_1 { - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; - - led2: led_2 { - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - label = "Green LED 2"; - }; - - led3: led_3 { - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - label = "Green LED 3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - /* - * PWM signal can be exposed on GPIO pin only within same domain. - * There is only one domain which contains both PWM and GPIO: - * PWM20/21/22 and GPIO Port P1. - * Only LEDs connected to P1 can work with PWM, for example LED1. - */ - - pwm_led1: pwm_led_1 { - pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 0"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - pwm-led0 = &pwm_led1; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - watchdog0 = &wdt31; - }; -}; - -&uart20 { - current-speed = <115200>; - pinctrl-0 = <&uart20_default>; - pinctrl-1 = <&uart20_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart30 { - current-speed = <115200>; - pinctrl-0 = <&uart30_default>; - pinctrl-1 = <&uart30_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm20 { - status = "okay"; - pinctrl-0 = <&pwm20_default>; - pinctrl-1 = <&pwm20_sleep>; - pinctrl-names = "default", "sleep"; -}; - -/* Get a node label for wi-fi spi to use in shield files */ -wifi_spi: &spi22 {}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi deleted file mode 100644 index 952a8f6d7aeb2..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * Copyright (c) 2024 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* This file is common to the secure and non-secure domain */ - -#include "raytac_an54l15q_db_common.dtsi" - -/ { - chosen { - zephyr,console = &uart20; - zephyr,shell-uart = &uart20; - zephyr,uart-mcumgr = &uart20; - zephyr,bt-mon-uart = &uart20; - zephyr,bt-c2h-uart = &uart20; - zephyr,flash-controller = &rram_controller; - zephyr,flash = &cpuapp_rram; - zephyr,ieee802154 = &ieee802154; - }; -}; - -&cpuapp_sram { - status = "okay"; -}; - -&lfxo { - load-capacitors = "internal"; - load-capacitance-femtofarad = <15500>; -}; - -&hfxo { - load-capacitors = "internal"; - load-capacitance-femtofarad = <15000>; -}; - -®ulators { - status = "okay"; -}; - -&vregmain { - status = "okay"; - regulator-initial-mode = ; -}; - -&grtc { - owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; - /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ - child-owned-channels = <3 4 7 8 9 10 11>; - status = "okay"; -}; - -&uart20 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpiote20 { - status = "okay"; -}; - -&gpiote30 { - status = "okay"; -}; - -&radio { - status = "okay"; -}; - -&ieee802154 { - status = "okay"; -}; - -&temp { - status = "okay"; -}; - -&clock { - status = "okay"; -}; - -&spi00 { - status = "okay"; - cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi00_default>; - pinctrl-1 = <&spi00_sleep>; - pinctrl-names = "default", "sleep"; - - mx25r64: mx25r6435f@0 { - compatible = "jedec,spi-nor"; - status = "okay"; - reg = <0>; - spi-max-frequency = <8000000>; - jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -&adc { - status = "okay"; -}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts deleted file mode 100644 index d9362a6ddb0e4..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * Copyright (c) 2024 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "raytac_an54l15q_db_cpuapp_common.dtsi" - -/ { - compatible = "raytac,an54l15q_db_nrf54l15-cpuapp"; - - model = "Raytac AN54L15Q-DB nRF54L15 Application MCU"; - - chosen { - zephyr,code-partition = &slot0_partition; - zephyr,sram = &cpuapp_sram; - }; -}; - -&cpuapp_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(64)>; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x10000 DT_SIZE_K(324)>; - }; - - slot0_ns_partition: partition@61000 { - label = "image-0-nonsecure"; - reg = <0x61000 DT_SIZE_K(324)>; - }; - - slot1_partition: partition@b2000 { - label = "image-1"; - reg = <0xb2000 DT_SIZE_K(324)>; - }; - - slot1_ns_partition: partition@103000 { - label = "image-1-nonsecure"; - reg = <0x103000 DT_SIZE_K(324)>; - }; - - /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ - storage_partition: partition@15c000 { - label = "storage"; - reg = <0x15c000 DT_SIZE_K(36)>; - }; - }; -}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml deleted file mode 100644 index 4e3b906747581..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2024 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -identifier: raytac_an54l15q_db/nrf54l15/cpuapp -name: Raytac-AN54L15Q-DB-nRF54l15-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -sysbuild: true -ram: 188 -flash: 324 -supported: - - adc - - counter - - gpio - - i2c - - pwm - - retained_mem - - spi - - watchdog - - i2s diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig deleted file mode 100644 index 299496280d227..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2024 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts deleted file mode 100644 index db7a01aead83c..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * Copyright (c) 2024 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#define USE_NON_SECURE_ADDRESS_MAP 1 - -#include -#include "raytac_an54l15q_db_cpuapp_common.dtsi" - -/ { - compatible = "raytac,raytac_an54l15q_db_nrf54l15-cpuapp"; - model = "Raytac AN54L15Q-DB nRF54L15 Application MCU"; - - chosen { - zephyr,code-partition = &slot0_ns_partition; - zephyr,sram = &sram0_ns; - zephyr,entropy = &psa_rng; - }; - - /delete-node/ rng; - - psa_rng: psa-rng { - status = "okay"; - }; -}; - -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - -&cpuapp_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the - * last 96kB are reserved for the FLPR MCU. - * - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x0000000 DT_SIZE_K(512)>; - }; - - tfm_ps_partition: partition@80000 { - label = "tfm-ps"; - reg = <0x00080000 DT_SIZE_K(16)>; - }; - - tfm_its_partition: partition@84000 { - label = "tfm-its"; - reg = <0x00084000 DT_SIZE_K(16)>; - }; - - tfm_otp_partition: partition@88000 { - label = "tfm-otp"; - reg = <0x00088000 DT_SIZE_K(8)>; - }; - - slot0_ns_partition: partition@8A000 { - label = "image-0-nonsecure"; - reg = <0x0008A000 DT_SIZE_K(844)>; - }; - - storage_partition: partition@15D000 { - label = "storage"; - reg = <0x00015D000 DT_SIZE_K(32)>; - }; - }; -}; - -&uart30 { - /* Disable so that TF-M can use this UART */ - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&uart30_default>; - pinctrl-1 = <&uart30_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml deleted file mode 100644 index 11ee50ba277f4..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - -identifier: raytac_an54l15q_db/nrf54l15/cpuapp/ns -name: Raytac-AN54L15Q-DB-nRF54l15-Application-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - zephyr -ram: 256 -flash: 1524 -supported: - - adc - - gpio - - i2c - - spi - - counter - - watchdog - - adc - - i2s -vendor: raytac -sysbuild: true diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig deleted file mode 100644 index 866a03cd8687a..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Don't enable the cache in the non-secure image as it is a -# secure-only peripheral on 54l -CONFIG_CACHE_MANAGEMENT=n -CONFIG_EXTERNAL_CACHE=n - -CONFIG_UART_CONSOLE=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y - -# Start SYSCOUNTER on driver init -CONFIG_NRF_GRTC_START_SYSCOUNTER=y - -# Disable TFM BL2 since it is not supported -CONFIG_TFM_BL2=n - -# Support for silence logging is not supported at the moment -# Tracked by: NCSDK-31930 -CONFIG_TFM_LOG_LEVEL_SILENCE=n - -# The oscillators are configured as secure and cannot be configured -# from the non secure application directly. This needs to be set -# otherwise nrfx will try to configure them, resulting in a bus -# fault. -CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts deleted file mode 100644 index d7c1a0cbbe007..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * Copyright (c) 2025 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "raytac_an54l15q_db_common.dtsi" - -/ { - model = "Raytac AN54L15Q-DB nRF54L15 FLPR MCU"; - compatible = "raytac,raytac_an54l15q_db_nrf54l15-cpuflpr"; - - chosen { - zephyr,console = &uart30; - zephyr,shell-uart = &uart30; - zephyr,code-partition = &cpuflpr_code_partition; - zephyr,flash = &cpuflpr_rram; - zephyr,sram = &cpuflpr_sram; - }; -}; - -&cpuflpr_sram { - status = "okay"; - /* size must be increased due to booting from SRAM */ - reg = <0x20028000 DT_SIZE_K(96)>; - ranges = <0x0 0x20028000 0x18000>; -}; - -&cpuflpr_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - cpuflpr_code_partition: partition@0 { - label = "image-0"; - reg = <0x0 DT_SIZE_K(96)>; - }; - }; -}; - -&grtc { - owned-channels = <3 4>; - status = "okay"; -}; - -&uart30 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpiote20 { - status = "okay"; -}; - -&gpiote30 { - status = "okay"; -}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml deleted file mode 100644 index 3a4f07f907e84..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -identifier: raytac_an54l15q_db/nrf54l15/cpuflpr -name: Raytac-AN54L15Q-DB-nRF54L15-Fast-Lightweight-Peripheral-Processor -type: mcu -arch: riscv -toolchain: - - zephyr -sysbuild: true -ram: 96 -flash: 96 -supported: - - counter - - gpio - - i2c - - spi - - watchdog diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig deleted file mode 100644 index f76cea10065b3..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Execute from SRAM -CONFIG_XIP=n diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts deleted file mode 100644 index 3e700be42dae4..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * Copyright (c) 2025 Raytac Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "raytac_an54l15q_db_nrf54l15_cpuflpr.dts" - -&cpuflpr_sram { - reg = <0x2002f000 DT_SIZE_K(68)>; - ranges = <0x0 0x2002f000 0x11000>; -}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml deleted file mode 100644 index ee996f4a9a1db..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -identifier: raytac_an54l15q_db/nrf54l15/cpuflpr/xip -name: Raytac-AN54L15Q-DB-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) -type: mcu -arch: riscv -toolchain: - - zephyr -sysbuild: true -ram: 68 -flash: 96 -supported: - - counter - - gpio - - i2c - - spi - - watchdog diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig deleted file mode 100644 index 883b58986b159..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Execute from RRAM -CONFIG_XIP=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi deleted file mode 100644 index 3f114bd6767d9..0000000000000 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - /omit-if-no-ref/ uart20_default: uart20_default { - group1 { - psels = , - ; - }; - - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart20_sleep: uart20_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ uart30_default: uart30_default { - group1 { - psels = , - ; - }; - - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart30_sleep: uart30_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ spi00_default: spi00_default { - group1 { - psels = , - , - ; - }; - }; - - /omit-if-no-ref/ spi00_sleep: spi00_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ pwm20_default: pwm20_default { - group1 { - psels = ; - }; - }; - - /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ grtc_default: grtc_default { - group1 { - psels = , - ; - }; - }; - - /omit-if-no-ref/ grtc_sleep: grtc_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index ec2fca6b8f4e8..21c5eb62f805f 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -191,16 +191,3 @@ &wdt { status = "okay"; }; - -&flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - storage_partition: partition@0 { - label = "storage"; - reg = <0x0 DT_SIZE_K(8)>; - }; - }; -}; diff --git a/boards/renesas/rcar_h3ulcb/board.yml b/boards/renesas/rcar_h3ulcb/board.yml index 6b2016e77365b..a0e38a44a9061 100644 --- a/boards/renesas/rcar_h3ulcb/board.yml +++ b/boards/renesas/rcar_h3ulcb/board.yml @@ -1,6 +1,6 @@ board: name: rcar_h3ulcb - full_name: R-Car H3ULCB + full_name: R-CAR H3 ARM CA57 (ARMv8) vendor: renesas socs: - name: r8a77951 diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg new file mode 100644 index 0000000000000..55f8ccde660fc Binary files /dev/null and b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg differ diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg new file mode 100644 index 0000000000000..3f788baf4860c Binary files /dev/null and b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg differ diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg similarity index 100% rename from boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg new file mode 100644 index 0000000000000..6b37aea51dee2 Binary files /dev/null and b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg differ diff --git a/boards/renesas/rcar_h3ulcb/doc/index.rst b/boards/renesas/rcar_h3ulcb/doc/index.rst deleted file mode 100644 index 44a126bd28ee1..0000000000000 --- a/boards/renesas/rcar_h3ulcb/doc/index.rst +++ /dev/null @@ -1,295 +0,0 @@ -.. zephyr:board:: rcar_h3ulcb - -Overview -******** -R-Car H3ULCB starter kit board is based on the R-Car H3 SoC that features basic -functions for next-generation car navigation systems. -It is composed of a quad Cortex |reg|-A57, a quad Cortex |reg|-A53 cluster and a -dual lockstep Cortex |reg|-R7. - -Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R7 core. - -More information about the H3 SoC can be fount at `Renesas R-Car H3 chip`_. - -Hardware -******** - -- H3ULCB features: - - - Storage: - - - 384KB System RAM - - 4/8 GB LPDDR4 - - 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S) - - 16MB QSPI FLASH (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI MODULE - - 8/32/64/128 GB EMMC (HS400 240 MBYTES/S) - - MICROSD-CARD SLOT (SDR104 100 MBYTES/S) - - Connectors - - - CN1 COM Express type connector 440pin - - CN2 QSPI Flash module - - CN3 DEBUG JTAG - - CN4 HDMI (HDMI-0) - - CN5 USB 2.0 (USB2.0-1) - - CN6 Push-Pull microSD Card Socket (SDHI-0) - - CN7 Ethernet, Connector, RJ45 - - CN8 LINE Out - - CN9 MIC Input - - CN10 DEBUG SERIAL (not populated) - - CN11 CPLD Programming JTAG - - CN12 DEBUG SERIAL (serial) - - CN13 Main Power Supply input (5VDC) - - CN14 CPU Fan - - Input - - - SW1 Hyper Flash - - SW2 Software Readable DIPSWITCHES (4x) - - SW3 Software Readable Push button - - SW4 Software Readable Push button - - SW5 Software Readable Push button - - SW6 Mode Settings - - SW7 CPLD Reset - - SW8 Power - - SW9 Reset - - Output - - - LED1 HDMI / Hot Plug Sync Detect - - LED4 Software Controllable LED - - LED5 Software Controllable LED - - LED6 Software Controllable LED - - LED9 5V Main Supply - - LED14 Backup LED - - LED15 System Reset - - -Complete list of the H3ULCB board capabilities can be found on the `eLinux H3SK page`_ of the board. - -More information about the board can be found at `Renesas R-Car Starter Kit website`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -.. note:: - - It is recommended to disable peripherals used by the R7 core on the Linux host. - -Connections and IOs -=================== - -The H3ULCB Starter Kit can be plugged on a Kingfisher daughter board. - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -`H3SK top view`_ - -`H3SK bottom view`_ - -Kingfisher Infotainment daughter board --------------------------------------- - -When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. - -Here are official IOs figures from eLinux for Kingfisher Infotainment board: - -`Kingfisher top view`_ - -`Kingfisher bottom view`_ - -GPIO ----- - -By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. - -UART ----- - -H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. - -Here is information about these serial ports: - -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| Physical Interface | Physical Location | Software Interface | Converter | Further Information | -+====================+===================+====================+===========+======================================+ -| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ - -H3ULCB A53 support is assigning SCIF2 as UART while R7 supports is using SCIF1. In both cases, console are set to 115200 8N1 without hardware flow control by default. - -To access SCIF1 using CN04 UART interface, please follow the following pinout (depending on your Kingfisher board version): - -+--------+----------+----------+ -| Signal | Pin KF03 | Pin KF04 | -+========+==========+==========+ -| RXD | 3 | 4 | -+--------+----------+----------+ -| TXD | 5 | 2 | -+--------+----------+----------+ -| RTS | 4 | 1 | -+--------+----------+----------+ -| CTS | 6 | 3 | -+--------+----------+----------+ -| GND | 9 | 6 | -+--------+----------+----------+ - -CAN ---- - -H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. - -+--------------------+--------------------+--------------+ -| Physical Interface | Software Interface | Transceiver | -+====================+====================+==============+ -| CN17 | CAN0 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ -| CN18 | CAN1 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ - -.. note:: Interfaces are set to 125 kbit/s by default. - -The following table lists CAN physical interfaces pinout: - -+-----+--------+ -| Pin | Signal | -+=====+========+ -| 1 | CANH | -+-----+--------+ -| 2 | CANL | -+-----+--------+ -| 3 | GND | -+-----+--------+ - -I2C ---- - -H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. - -I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. - -Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. - -PWM ---- - -ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. - -When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. - -Programming and Debugging (A53) -******************************* - -Flashing -======== - -At that time, no flashing method is officially supported by this Zephyr port. - -Programming and Debugging (R7) -****************************** - -.. zephyr:board-supported-runners:: - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. - -.. note:: - See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb/r8a77951/r7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb/r8a77951/r7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb - -References -********** - -- `Renesas R-Car Starter Kit website`_ -- `Renesas R-Car H3 chip`_ -- `eLinux H3SK page`_ -- `eLinux Kingfisher page`_ - -.. _Renesas R-Car Starter Kit website: - https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _eLinux H3SK page: - https://elinux.org/R-Car/Boards/H3SK - -.. _H3SK top view: - https://elinux.org/images/1/1f/R-Car-H3-topview.jpg - -.. _H3SK bottom view: - https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg - -.. _eLinux Kingfisher page: - https://elinux.org/R-Car/Boards/Kingfisher - -.. _Kingfisher top view: - https://elinux.org/images/0/08/Kfisher_top_specs.png - -.. _Kingfisher bottom view: - https://elinux.org/images/0/06/Kfisher_bot_specs.png diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst new file mode 100644 index 0000000000000..aefe429f5c88d --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst @@ -0,0 +1,87 @@ +.. _rcar_h3ulcb_ca57: + +R-CAR H3 ARM CA57 (ARMv8) +######################### + +Overview +******** +The R-Car H3 is an SOC that features the basic functions for next-generation +car navigation systems. + +Hardware +******** +The R-Car H3 includes: + +* four 1.5-GHz ARM Cortex-A57 MPCore cores; +* four 1.2-GHz ARM Cortex-A53 MPCore cores; +* memory controller for LPDDR4-3200 with 32 bits x 4 channels; +* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; +* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; +* serial ATA interface; +* USB3.0 x 2ch and USB2.0 x 3ch interfaces; +* 800-MHz ARM Cortex-R7 core; +* two- and three-dimensional graphics engines; +* video processing units; +* sound processing units; +* MediaLB interface; +* SD card host interface; +* USB3.0 and USB2.0 interfaces; +* PCI Express interface; +* CAN interface; +* EtherAVB. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +.. figure:: img/rcar_h3ulcb_top.jpg + :align: center + +.. figure:: img/rcar_h3ulcb_bottom.jpg + :align: center + +Supported Features +================== +The Renesas rcar_h3ulcb_ca57 board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ +| MMC | renesas_rcar_mmc | DMA and SCC | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux R-Car Starter Kit page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux R-Car Starter Kit page: + https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst new file mode 100644 index 0000000000000..f77c16196fa1c --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst @@ -0,0 +1,276 @@ +.. _rcar_h3ulcb_boards: + +Renesas R-Car H3ULCB +#################### + +Overview +******** +- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. + +- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. + +It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. + +.. figure:: img/rcar_h3ulcb_starter_kit.jpg + :align: center + :alt: R-Car starter kit + +.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. + +More information about the board can be found at `Renesas R-Car Starter Kit website`_. + +Hardware +******** + +Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. + +.. figure:: img/rcar_h3ulcb_features.jpg + :align: center + :alt: R-Car starter kit features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINMUX | pinmux | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ +| PWM | pwm | All channels | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +More features will be supported soon. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +`H3SK top view`_ + +`H3SK bottom view`_ + +Kingfisher Infotainment daughter board +-------------------------------------- + +When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. + +Here are official IOs figures from eLinux for Kingfisher Infotainment board: + +`Kingfisher top view`_ + +`Kingfisher bottom view`_ + +GPIO +---- + +By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. + +UART +---- + +H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. + +Here is information about these serial ports: + ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| Physical Interface | Physical Location | Software Interface | Converter | Further Information | ++====================+===================+====================+===========+======================================+ +| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ + +.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. + +Here is CN04 UART interface pinout (depending on your Kingfisher board version): + ++--------+----------+----------+ +| Signal | Pin KF03 | Pin KF04 | ++========+==========+==========+ +| RXD | 3 | 4 | ++--------+----------+----------+ +| TXD | 5 | 2 | ++--------+----------+----------+ +| RTS | 4 | 1 | ++--------+----------+----------+ +| CTS | 6 | 3 | ++--------+----------+----------+ +| GND | 9 | 6 | ++--------+----------+----------+ + +CAN +--- + +H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. + ++--------------------+--------------------+--------------+ +| Physical Interface | Software Interface | Transceiver | ++====================+====================+==============+ +| CN17 | CAN0 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ +| CN18 | CAN1 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ + +.. note:: Interfaces are set to 125 kbit/s by default. + +The following table lists CAN physical interfaces pinout: + ++-----+--------+ +| Pin | Signal | ++=====+========+ +| 1 | CANH | ++-----+--------+ +| 2 | CANL | ++-----+--------+ +| 3 | GND | ++-----+--------+ + +I2C +--- + +H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. + +I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. + +Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. + +PWM +--- + +ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. + +When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. + +.. note:: + See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +References +********** + +- `Renesas R-Car Starter Kit website`_ +- `Renesas R-Car H3 chip`_ +- `eLinux H3SK page`_ +- `eLinux Kingfisher page`_ + +.. _Renesas R-Car Starter Kit website: + https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _eLinux H3SK page: + https://elinux.org/R-Car/Boards/H3SK + +.. _H3SK top view: + https://elinux.org/images/1/1f/R-Car-H3-topview.jpg + +.. _H3SK bottom view: + https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg + +.. _eLinux Kingfisher page: + https://elinux.org/R-Car/Boards/Kingfisher + +.. _Kingfisher top view: + https://elinux.org/images/0/08/Kfisher_top_specs.png + +.. _Kingfisher bottom view: + https://elinux.org/images/0/06/Kfisher_bot_specs.png + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_x/board.yml b/boards/renesas/rcar_salvator_x/board.yml index c307356ac7dd7..11166fb0a2c3d 100644 --- a/boards/renesas/rcar_salvator_x/board.yml +++ b/boards/renesas/rcar_salvator_x/board.yml @@ -1,6 +1,6 @@ board: name: rcar_salvator_x - full_name: R-Car Salvator-X + full_name: R-Car H3 Salvator-X vendor: renesas socs: - name: r8a77951 diff --git a/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg new file mode 100644 index 0000000000000..3f788baf4860c Binary files /dev/null and b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg differ diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg similarity index 100% rename from boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.jpg rename to boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg diff --git a/boards/renesas/rcar_salvator_x/doc/index.rst b/boards/renesas/rcar_salvator_x/doc/index.rst deleted file mode 100644 index ae248486db747..0000000000000 --- a/boards/renesas/rcar_salvator_x/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. zephyr:board:: rcar_salvator_x - -Overview -******** -- The H3 Salvator-X board is designed for evaluating the features and performance - of the R-CAR H3 device from Renesas Electronics and it is also used for developing - and evaluating application software for these R-CAR H3. - -- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, - each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces - like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, - via 440pin connector on bottom side. - -More information about the H3 SoC can be found here: `Renesas R-Car H3 chip`_ - -Hardware -******** - -Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_. - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the board can be found at `Renesas R-Car Development Support website`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -.. note:: - - It is recommended to disable peripherals used by the R7 core on the Linux host. - -Connections and IOs -=================== - -.. figure:: img/r-car-h3-salvator-x-connections.jpg - :align: center - :alt: R-Car Salvator-X connections - -GPIO ----- - -By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', -'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', -'LED5', 'LED6' can be used as output. - -UART ----- - -Salvator-X board is providing two serial ports: - -- one is for A53/A57 processors -- the other one is for CR7 - -Both ports are converted to USB through CP2102 converters and they are exposed -as follows: - -+-----------+-----------+ -| Connector | Processor | -+===========+===========+ -| CN25 | A53/A57 | -+-----------+-----------+ -| CN26 | CR7 | -+-----------+-----------+ - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This -probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN25 and/or CN26 then use the following -settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_salvator_x`` board configuration can be built -in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_salvator_x - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_salvator_x - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_salvator_x - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_salvator_x - -References -********** - -- `Renesas R-Car H3 chip`_ -- `Renesas R-Car Development Support website`_ -- `eLinux H3 Salvator-X page`_ - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux H3 Salvator-X page: - https://elinux.org/R-Car/Boards/Salvator-X - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst new file mode 100644 index 0000000000000..3e7b57729444f --- /dev/null +++ b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst @@ -0,0 +1,183 @@ +.. _rcar_h3_salvatorx_boards: + +Renesas R-Car H3 Salvator-X +########################### + +Overview +******** +- The H3 Salvator-X board is designed for evaluating the features and performance + of the R-CAR H3 device from Renesas Electronics and it is also used for developing + and evaluating application software for these R-CAR H3. + +- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, + each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces + like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, + via 440pin connector on bottom side. + +.. figure:: img/rcar_h3_salvatorx.jpg + :align: center + :alt: R-Car Salvator-X kit + +More information about the board can be found at `Renesas R-Car Development Support website`_. + +Hardware +******** + +Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ +of the board. + +.. figure:: img/rcar_h3_features.jpg + :align: center + :alt: R-Car Salvator-X features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +Connections and IOs +=================== + +.. figure:: img/r-car-h3-salvator-x-connections.jpg + :align: center + :alt: R-Car Salvator-X connections + +GPIO +---- + +By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', +'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', +'LED5', 'LED6' can be used as output. + +UART +---- + +Salvator-X board is providing two serial ports: + +- one is for A53/A57 processors +- the other one is for CR7 + +Both ports are converted to USB through CP2102 converters and they are exposed +as follows: + ++-----------+-----------+ +| Connector | Processor | ++===========+===========+ +| CN25 | A53/A57 | ++-----------+-----------+ +| CN26 | CR7 | ++-----------+-----------+ + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This +probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN25 and/or CN26 then use the following +settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_salvator_x`` board configuration can be built +in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +References +********** + +- `Renesas R-Car H3 chip`_ +- `Renesas R-Car Development Support website`_ +- `eLinux H3 Salvator-X page`_ + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux H3 Salvator-X page: + https://elinux.org/R-Car/Boards/Salvator-X + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_xs/board.yml b/boards/renesas/rcar_salvator_xs/board.yml index a6face8931ad0..2b8ded23f8a26 100644 --- a/boards/renesas/rcar_salvator_xs/board.yml +++ b/boards/renesas/rcar_salvator_xs/board.yml @@ -1,6 +1,6 @@ board: name: rcar_salvator_xs - full_name: R-Car Salvator-XS + full_name: R-CAR Salvator XS M3 ARM CA57 (ARMv8) vendor: renesas socs: - name: r8a77961 diff --git a/boards/renesas/rcar_salvator_xs/doc/index.rst b/boards/renesas/rcar_salvator_xs/doc/index.rst index 60f53324ac642..464b4e659d714 100644 --- a/boards/renesas/rcar_salvator_xs/doc/index.rst +++ b/boards/renesas/rcar_salvator_xs/doc/index.rst @@ -1,4 +1,7 @@ -.. zephyr:board:: rcar_salvator_xs +.. _rcar_salvator_xs: + +R-CAR Salvator XS M3 ARM CA57 (ARMv8) +##################################### Overview ******** @@ -26,12 +29,27 @@ The R-Car M3-W includes: * CAN interface; * EtherAVB. -Hardware capabilities for the Salvator-XS for can be found on the `eLinux Salvator-XS page`_. - Supported Features ================== +The Renesas rcar_salvator_xs board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ +| MMC | renesas_rcar_mmc | DMA and SCC | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. -.. zephyr:board-supported-hw:: +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig` Programming and Debugging ************************* diff --git a/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg b/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg deleted file mode 100644 index 31b725981ff66..0000000000000 Binary files a/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg and /dev/null differ diff --git a/boards/renesas/rcar_spider_s4/board.yml b/boards/renesas/rcar_spider_s4/board.yml index 2a4ebdfb1ab3c..caf9b8cf5ad7d 100644 --- a/boards/renesas/rcar_spider_s4/board.yml +++ b/boards/renesas/rcar_spider_s4/board.yml @@ -1,6 +1,6 @@ board: name: rcar_spider_s4 - full_name: R-Car Spider + full_name: R-CAR Spider S4 (ARM64) vendor: renesas socs: - name: r8a779f0 diff --git a/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg new file mode 100644 index 0000000000000..76bda515cfb83 Binary files /dev/null and b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg differ diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_s4.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg similarity index 100% rename from boards/renesas/rcar_spider_s4/doc/rcar_spider_s4.jpg rename to boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg diff --git a/boards/renesas/rcar_spider_s4/doc/index.rst b/boards/renesas/rcar_spider_s4/doc/index.rst deleted file mode 100644 index 7edf20bca23dc..0000000000000 --- a/boards/renesas/rcar_spider_s4/doc/index.rst +++ /dev/null @@ -1,265 +0,0 @@ -.. zephyr:board:: rcar_spider_s4 - -Overview -******** - -R-Car S4 Spider board is based on the R-Car S4 SoC made for Car -Server/Communication Gateway and that is composed of a octo Cortex |reg|-A55, a -dual lockstep Cortex |reg|-R52 and a double dual lockstep G4MH. - -The R-Car S4 SoC enables the launch of Car Server/CoGW with high performance, -high-speed networking, high security and high functional safety levels that are -required as E/E architectures evolve into domains and zones. - -The R-Car S4 solution allows designers to re-use up to 88 percent of software -code developed for 3rd generation R-Car SoCs and RH850 MCU applications. -The software package supports the real-time cores with various drivers and -basic software such as Linux BSP and hypervisors. - -The Renesas R-Car Spider board is the Renesas R-Car S4 reference board and is designed for -evaluating features and performance of this SoC. - -Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R52 core. - -More information about the S4 SoC can be fount at `Renesas R-Car S4 chip`_. - -Hardware -******** - -- Spider features: - - - Connectors - - - CPU Board: - - - CN1 JTAG1 - - CN2 JTAG2 - - CN3 EX-SPI (QSPI0) - - CN4 MicroSD Slot (back side) - - CN11 EXIO Connector A (back side) - - CN12 EXIO Connector B (back side) - - CN14 EVT - - CN16 OcuLink (PCIe0,PCIe1) - - CN24 CAN 4pin - - CN20 USB microAB (SCIF0) - - CN21 USB microAB (HSCIF0) - - CN22 SW Board - - CN23 CPLD JTAG - - CN27 FAN - - CN30 Buck3 - - CN31 Buck1 - - CN32 CAN 8pin (back side) - - Breakout Board: - - - CN11 EXIO Connector A - - CN12 EXIO Connector B - - CN13 CAN 0/1 - - CN15 CAN 3/4/5 - - CN18 CAN 6/7/8 - - CN21 CAN 2/9/10/11 - - CN24 CAN 12/13/14/15 - - CN28 LIN0 - - CN29 LIN1 - - CN30 LIN2 - - CN31 LIN3 - - CN32 LIN4 - - CN33 LIN5 - - CN34 LIN6 - - CN35 LIN7 - - CN36 EtherTS - - CN37 MSIOF0 - - CN38 CAN/LIN BOARD - - CN39 GPIO CN_A - - CN40 GPIO - - CN41 I2C - - CN42 HSCIF0 - - CN43 SCIF0 - - CN44 TSN_CN - - CN45 Legacy 12V-in - - CN46 AC Adapter - - CN48 POWER CONTROL - - CN50 Debug Serial - - CN51 FAN - - Input - - - SW1 (SPI Flash Memory / EX-SPI connector) - - SW2 (Hyper Flash Memory / SPI Flash Memory) - - SW3 (MicroSD Card Slot / eMMC Memory) - - SW4 (PRESETn) - - SW6 (Interface Voltage Setting for MMC/JTAG2) - - SW8 Mode Setting - - SW10 (Software Switch) - - SW11 (Board Power-Supply Circuit Control) - - SW12 (AURORES#) - - SW13 (CANFD0 RX) - - SW14 (CANFD0 TX) - - SW15 (System Reset Switch) - - Output - - - LED7 Software Controllable LED - - LED8 Software Controllable LED - - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -.. note:: - - It is recommended to disable peripherals used by the R52 core on the Linux host. - -Connections and IOs -=================== - -The Spider board consists of a CPU board plugged on top of a Breakout board. - -Here are the official IOs figures from eLinux for S4 board: - -`S4 Spider CPU board IOs`_ - -`S4 Spider breakout board IOs`_ - -GPIO ----- - -By running Zephyr on S4 Spider, the software controllable LED 'LED8' can be used as output. - -UART ----- - -Here is information about both serial ports provided on the S4 Spider board : - -+--------------------+----------+--------------------+-------------+------------------------+ -| Physical Interface | Location | Software Interface | Converter | Further Information | -+====================+==========+====================+=============+========================+ -| CN20 USB Port | CPU Board| SCIF0/HSCIF1 | FT232HQ | Default Zephyr serial | -+--------------------+----------+--------------------+-------------+------------------------+ -| CN21 USB Port | CPU Board| SCIF3/HSCIF0 | FT2232H-56Q | Used by U-BOOT & Linux | -+--------------------+----------+--------------------+-------------+------------------------+ - -.. note:: - The Zephyr console output is assigned to SCIF0 (CN20 USB Port) with settings: - 115200 8N1 without hardware flow control by default. - -I2C ---- - -I2C is mainly used to manage and power-on some onboard chips on the S4 Spider board. - -Embedded I2C devices and I/O expanders are not yet supported. -The current I2C support therefore does not make any devices available to the user at this time. - -Programming and Debugging (A55) -******************************* - -At that time, no direct flashing method is officially supported by this Zephyr port. -However, it is possible to load the Zephyr binary using U-Boot commands. - -One of the ways to load Zephyr is shown below. - -.. code-block:: console - - tftp 0x48000000 - booti 0x48000000 - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/a55 - :goals: build - -Programming and Debugging (R52) -******************************* - -.. zephyr:board-supported-runners:: - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -| The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. -| This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a "Coresight 20 pins" -adapter to CN1 connector on Spider board. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN20 USB port of your Spider board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_spider_s4/r8a779f0/r52`` board configuration can be built in the -usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/r52 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_s4 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/r52 - :goals: debug - -You will then get access to a GDB session for debugging. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_s4 - - -References -********** - -- `Renesas R-Car S4 Spider`_ -- `Renesas R-Car S4 chip`_ -- `eLinux S4 Spider`_ - -.. _Renesas R-Car S4 Spider: - https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/rtp8a779f0askb0sp2s-r-car-s4-reference-boardspider - -.. _Renesas R-Car S4 chip: - https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-s4-automotive-system-chip-soc-car-servercommunication-gateway - -.. _eLinux S4 Spider: - https://elinux.org/R-Car/Boards/Spider - -.. _S4 Spider CPU board IOs: - https://elinux.org/images/6/6d/Rcar_s4_spider_cpu_board.jpg - -.. _S4 Spider breakout board IOs: - https://elinux.org/images/2/29/Rcar_s4_spider_breakout_board.jpg diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst new file mode 100644 index 0000000000000..b66975af164b9 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst @@ -0,0 +1,83 @@ +.. _rcar_spider_a55: + +R-CAR Spider S4 (ARM64) +####################### + +Overview +******** +R-Car S4 enables to launch Car Server/CoGW with high performance, high-speed networking, +high security and high functional safety levels that are required as E/E architectures +evolve into domains and zones. The R-Car S4 solution allows designers to re-use up to 88 +percent of software code developed for 3rd generation R-Car SoCs and RH850 MCU applications. +The software package supports the real-time cores with various drivers and basic software +such as Linux BSP and hypervisors. + +Hardware +******** +The R-Car S4 includes: + +* eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters; +* 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported); +* two 400MHz G4MH cores (hardware Lock step is supported); +* memory controller for LPDDR4X-3200 with 32bit bus (16bit x 1ch + 16bit x 1ch) with ECC; +* SD card host interface / eMMC; +* UFS 3.0 x 1 channel; +* PCI Express Gen4.0 interface (Dual lane x 2ch); +* ICUMX; +* ICUMH; +* SHIP-S x 3 channels; +* AES Accerator x 8 channels; +* CAN FD interface x 16 channels; +* R-Switch2 (Ether); +* 100base EtherAVB x 1 channel; +* Gbit-EtherTSN x 3 channels; +* 1 unit FlexRay (A,B 2ch) interface. + +Supported Features +================== +The Renesas ``rcar_spider_s4/r8a779f0/a55`` board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | serial | interrupt-driven/polling | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +The onboard flash is not supported by Zephyr at this time. However, it is possible to +load the Zephyr binary using U-Boot commands. + +One of the ways to load Zephyr is shown below. + +.. code-block:: console + + tftp 0x48000000 + booti 0x48000000 + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/a55 + :goals: build + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux Spider page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux Spider page: + https://elinux.org/R-Car/Boards/Spider diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst new file mode 100644 index 0000000000000..9c7be4d8f99b7 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst @@ -0,0 +1,200 @@ +.. _rcar_spider_boards: + +Renesas R-Car Spider +#################### + +Overview +******** + +| R-Car S4 enables the launch of Car Server/CoGW with high performance, high-speed networking, +| high security and high functional safety levels that are required as E/E architectures +| evolve into domains and zones. + +| The R-Car S4 solution allows designers to re-use up to 88 percent of software code developed +| for 3rd generation R-Car SoCs and RH850 MCU applications.\ +| The software package supports the real-time cores with various drivers and basic software +| such as Linux BSP and hypervisors. + +The Renesas R-Car Spider board is the Renesas R-Car S4 reference board and is designed for +evaluating features and performance of this SoC. + +.. figure:: img/rcar_s4_spider_full.jpg + :align: center + :alt: R-Car S4 Spider + +More information about the board can be found at `Renesas R-Car S4 Spider`_ website. + +Hardware +******** + +Hardware capabilities for the S4 Spider board can be found on the `eLinux S4 Spider`_ page. + +.. figure:: img/rcar_s4_block_diagram.jpg + :align: center + :alt: R-Car S4 Spider block diagram + +.. note:: We support Zephyr running on the CR52 processor that is provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car S4 chip`_ + +Supported Features +================== + +Here are the current supported features when running Zephyr Project on the R-Car S4 Spider CR52: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINMUX | pinmux | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ +| PWM | pwm | All channels | ++-----------+------------------------------+--------------------------------+ + +It is also currently possible to write on the ram console. + +More features will be supported soon. + +Connections and IOs +=================== + +| The "Spider board" consists of a CPU board and a Breakout board. +| The CPU board is stuck on top of the Breakout board. + +Here are the official IOs figures from eLinux for S4 board: + +`S4 Spider CPU board IOs`_ + +`S4 Spider breakout board IOs`_ + +GPIO +---- + +By running Zephyr on S4 Spider, the software controllable LED 'LED8' can be used as output. + +UART +---- + +Here is information about both serial ports provided on the S4 Spider board : + ++--------------------+----------+--------------------+-------------+------------------------+ +| Physical Interface | Location | Software Interface | Converter | Further Information | ++====================+==========+====================+=============+========================+ +| CN20 USB Port | CPU Board| SCIF0/HSCIF1 | FT232HQ | Default Zephyr serial | ++--------------------+----------+--------------------+-------------+------------------------+ +| CN21 USB Port | CPU Board| SCIF3/HSCIF0 | FT2232H-56Q | Used by U-BOOT & Linux | ++--------------------+----------+--------------------+-------------+------------------------+ + +.. note:: + The Zephyr console output is assigned to SCIF0 (CN20 USB Port) with settings: + 115200 8N1 without hardware flow control by default. + +I2C +--- + +I2C is mainly used to manage and power-on some onboard chips on the S4 Spider board. + +Embedded I2C devices and I/O expanders are not yet supported. +The current I2C support therefore does not make any devices available to the user at this time. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +| The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. +| This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a "Coresight 20 pins" +adapter to CN1 connector on Spider board. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN20 USB port of your Spider board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_spider_s4/r8a779f0/r52`` board configuration can be built in the +usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/r52 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.3.0-rc2 *** + Hello World! rcar_spider_s4 + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/r52 + :goals: debug + +You will then get access to a GDB session for debugging. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.3.0-rc2 *** + Hello World! rcar_spider_s4 + +References +********** + +- `Renesas R-Car S4 Spider`_ +- `Renesas R-Car S4 chip`_ +- `eLinux S4 Spider`_ + +.. _Renesas R-Car S4 Spider: + https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/rtp8a779f0askb0sp2s-r-car-s4-reference-boardspider + +.. _Renesas R-Car S4 chip: + https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-s4-automotive-system-chip-soc-car-servercommunication-gateway + +.. _eLinux S4 Spider: + https://elinux.org/R-Car/Boards/Spider + +.. _S4 Spider CPU board IOs: + https://elinux.org/images/6/6d/Rcar_s4_spider_cpu_board.jpg + +.. _S4 Spider breakout board IOs: + https://elinux.org/images/2/29/Rcar_s4_spider_breakout_board.jpg diff --git a/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 b/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 deleted file mode 100644 index 3587994f266e6..0000000000000 --- a/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RSK_RX130 - select SOC_R5F513083XFB diff --git a/boards/renesas/rsk_rx130/board.cmake b/boards/renesas/rsk_rx130/board.cmake deleted file mode 100644 index 0fb228f3dd8c5..0000000000000 --- a/boards/renesas/rsk_rx130/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" -board_runner_args(jlink "--device=R5F51308" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1") - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rsk_rx130/board.yml b/boards/renesas/rsk_rx130/board.yml deleted file mode 100644 index 90573aed2235c..0000000000000 --- a/boards/renesas/rsk_rx130/board.yml +++ /dev/null @@ -1,13 +0,0 @@ -board: - name: rsk_rx130 - full_name: Renesas Starter Kit for RX130 - vendor: renesas - revision: - format: custom - default: 512kb - exact: true - revisions: - - name: 512kb - - name: 128kb - socs: - - name: r5f513083xfb diff --git a/boards/renesas/rsk_rx130/doc/index.rst b/boards/renesas/rsk_rx130/doc/index.rst deleted file mode 100644 index c76d4b9bcb89f..0000000000000 --- a/boards/renesas/rsk_rx130/doc/index.rst +++ /dev/null @@ -1,149 +0,0 @@ -.. zephyr:board:: rsk_rx130 - -Overview -******** - -The Renesas Starter Kit for RX130-512KB is the perfect starter kit for -developers who are new to the RX130 (Program Flash 512KB, Pin Count 100-pin), -which operates at up to 32 MHz and is based on the RXv1 core architecture, -making it suitable for various embedded applications - -**MCU Native Pin Access** - -The RSKRX130-512KB includes: - -- 32-MHz, 32-bit RX MCUs in 100 pins LFQFP package, Micon Pin Headers -- Direct MCU pin access through standard headers for easy peripheral integration -- Internal high-speed oscillator and low-speed on-chip oscillators -- Three low power consumption modes - -**System Control and Debugging** - -- USB Full-Speed Device (mini-B connector) for communication and power - -- Power source options: - - - USB-powered (debug port) - - External power supply via standard input - -- Debugging support: - - - Via Jlink debugger with RX adapter boards. - -- User LEDs and buttons: - - - Four User LEDs (red x2, yellow, green) - - Power LED (green) indicating availability of regulated power - - One Reset button, three User buttons - -- Ecosystems expansions: - - - Two Digilent Pmod (LCD and Spare) connectors - - 2Kbit I2C EEPROM - -**Special Feature Access** - -- IEC60730 compliance -- Capacitive touch sensing unit -- LCD drive capability for displaying data or status in real-time applications - -Hardware -******** -Detailed hardware features can be found at: - -- RX130 MCU: `RX130 Group User's Manual Hardware`_ -- RSK-RX130-512KB: `RSK_RX130_512KB - User's Manual`_ - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``rsk_rx130@512kb`` board target configuration can be -built, flashed, and debugged as below. - -Currently, the Zephyr SDK hasn't added support for RX builds yet, so the GCC for RX toolchain is required and build system need to be set to use "cross-compile". - - - Download and install GCC for RX v8.3.0.202405 toolchain: - - https://llvm-gcc-renesas.com/rx-download-toolchains/ - - - Set env variable: - - .. code-block:: console - - export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - export CROSS_COMPILE=/bin/rx-elf- - - - Build the Blinky Sample for RSK-RX130-512KB: - - .. code-block:: console - - cd ~/zephyrproject/zephyr - west build -p always -b rsk_rx130@512kb samples/basic/blinky - -Flashing -======== - -Program can be flashed to RSKRX130-512KB via Jlink with RX adapter boards. - -To flash the program to board - - 1. Connect from board's debug connector port to host PC using Jlink debugger. - - 2. Execute west command - - .. code-block:: console - - west flash - -Debugging -========= - -You can use `Renesas Debug extension`_ on Visual Studio code for a visual debug interface. -The configuration for launch.json is as below. - -.. code-block:: json - - { - "version": "0.2.0", - "configurations": [ - { - "type": "renesas-hardware", - "request": "launch", - "name": "Renesas GDB Hardware Debugging", - "target": { - "deviceFamily": "RX", - "device": "R5F51308", - "debuggerType": "SEGGERJLINKRX", - } - } - ] - } - - -References -********** - -- `RSK_RX130_512KB Website`_ -- `RX130 MCU group Website`_ - -.. _RSK_RX130_512KB Website: - https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx130-512kb-starter-kit-renesas-starter-kit-rx130-512kb - -.. _RX130 MCU group Website: - https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx130-cost-optimized-high-performance-32-bit-microcontroller-enhanced-touch-key-function-and-5v-operation - -.. _RSK_RX130_512KB - User's Manual: - https://www.renesas.com/en/document/mat/renesas-starter-kit-rx130-512kb-users-manual-rev100 - -.. _RX130 Group User's Manual Hardware: - https://www.renesas.com/en/document/mah/rx130-group-users-manual-hardware-rev300 - -.. _Renesas Debug extension: - https://marketplace.visualstudio.com/items?itemName=RenesasElectronicsCorporation.renesas-debug diff --git a/boards/renesas/rsk_rx130/doc/rsk_rx130.webp b/boards/renesas/rsk_rx130/doc/rsk_rx130.webp deleted file mode 100644 index e112958c0f003..0000000000000 Binary files a/boards/renesas/rsk_rx130/doc/rsk_rx130.webp and /dev/null differ diff --git a/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp b/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp deleted file mode 100644 index 563d828491700..0000000000000 Binary files a/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp and /dev/null differ diff --git a/boards/renesas/rsk_rx130/revision.cmake b/boards/renesas/rsk_rx130/revision.cmake deleted file mode 100644 index f9ba58ee9aff9..0000000000000 --- a/boards/renesas/rsk_rx130/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -set(RX130_REVISIONS "512kb" "128kb") -if (NOT DEFINED BOARD_REVISION) - set(BOARD_REVISION "RX130_REVISIONS") -else() - if (NOT BOARD_REVISION IN_LIST RX130_REVISIONS) - message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for Legend. Accepted revisions: ${RX130_REVISIONS}") - endif() -endif() \ No newline at end of file diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts deleted file mode 100644 index 1ca2ac91d8152..0000000000000 --- a/boards/renesas/rsk_rx130/rsk_rx130.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "rsk_rx130_512kb-pinctrl.dtsi" - -/ { - model = "Renesas RSK+RX130-512KB KIT"; - compatible = "renesas,rsk_rx130_512kb","renesas,rxv1"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &code_flash; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - leds { - compatible = "gpio-leds"; - - led1: led1 { - gpios = <&ioportd 3 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - - led3: led3 { - gpios = <&ioporte 6 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - }; - - aliases { - led0 = &led1; - led1 = &led3; - }; -}; - -&xtal { - clock-frequency = ; - mosel = <0>; - #clock-cells = <0>; - status = "okay"; -}; - -&subclk { - status = "okay"; -}; - -&pll { - div = <2>; - mul = ; - status = "okay"; -}; - -&cmt { - clock-frequency = <4000000>; - status = "okay"; -}; - -&ioportd { - status = "okay"; -}; - -&ioporte { - status = "okay"; -}; - -&sci1 { - pinctrl-0 = <&sci1_default>; - pinctrl-names = "default"; - status = "okay"; - - uart1: uart { - current-speed = <115200>; - status = "okay"; - }; -}; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi b/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi deleted file mode 100644 index 8b4006931bc36..0000000000000 --- a/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - sci1_default: sci1_default { - group1 { - psels = , /* TX */ - ; /* RX */ - }; - }; -}; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml b/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml deleted file mode 100644 index 49890d8e2fbb6..0000000000000 --- a/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -identifier: rsk_rx130@512kb -name: Renesas Starter Kit+ RX130-512KB -type: mcu -arch: rx -toolchain: - - cross-compile -supported: - - gpio - - serial - - timer -ram: 48 -flash: 512 diff --git a/boards/renesas/rsk_rx130/rsk_rx130_defconfig b/boards/renesas/rsk_rx130/rsk_rx130_defconfig deleted file mode 100644 index 95b9befa6dc9e..0000000000000 --- a/boards/renesas/rsk_rx130/rsk_rx130_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/rzg3s_smarc/doc/index.rst b/boards/renesas/rzg3s_smarc/doc/index.rst index 2f2eeeab7f227..d69f9686e2c1e 100644 --- a/boards/renesas/rzg3s_smarc/doc/index.rst +++ b/boards/renesas/rzg3s_smarc/doc/index.rst @@ -58,7 +58,40 @@ Please see :zephyr:code-sample:`rz-openamp-linux-zephyr` sample for reference. Supported Features ================== -.. zephyr:board-supported-hw:: +The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core without FPU +and the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| GTM | on-chip | counter | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| INTC | on-chip | external interrupt controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+-------------------------------------+ +| MHU | on-chip | mbox | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. Programming and Debugging ************************* diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi index a5d105ac29c21..72a243947cd1b 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi @@ -55,27 +55,4 @@ pinmux = ; /* GTIOCA */ }; }; - - /omit-if-no-ref/ can0_pins: can0 { - can0-pinmux { - pinmux = , /* TX */ - ; /* RX */ - }; - }; - - /omit-if-no-ref/ can1_pins: can1 { - can1-pinmux { - pinmux = , /* TX */ - ; /* RX */ - }; - }; - - /omit-if-no-ref/ spi0_pins: spi0 { - spi0-pinmux { - pinmux = , /* CK */ - , /* MOSI */ - , /* MISO */ - ; /* SSL */ - }; - }; }; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts index 5440eeaa5e427..1f2bd49c9b9e3 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts @@ -22,7 +22,6 @@ zephyr,flash = &spi_flash; zephyr,console = &scif1; zephyr,shell-uart = &scif1; - zephyr,canbus = &canfd0; }; aliases { @@ -75,19 +74,6 @@ reg = <0x80200000 DT_SIZE_K(256)>; }; - transceiver0: can-phy0 { - compatible = "can-transceiver-gpio"; - standby-gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>; - max-bitrate = <8000000>; - #phy-cells = <0>; - }; - - transceiver1: can-phy1 { - compatible = "can-transceiver-gpio"; - standby-gpios = <&gpio13 1 GPIO_ACTIVE_HIGH>; - max-bitrate = <8000000>; - #phy-cells = <0>; - }; }; &scif1 { @@ -97,36 +83,14 @@ status = "okay"; }; -&spi0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; +&gpio0{ status = "okay"; }; -&gpio0 { - status = "okay"; -}; - -&gpio13{ - status = "okay"; -}; - -&gpio18 { +&gpio18{ status = "okay"; }; &adc { status = "okay"; }; - -&canfd_global { - status = "okay"; -}; - -&canfd0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; - rx-max-filters = <32>; - phys = <&transceiver0>; -}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml index cf2b6a3e8d47c..ad2a7687a937f 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml @@ -13,5 +13,3 @@ supported: - gpio - counter - pwm - - spi - - can diff --git a/boards/seeed/xiao_mg24/xiao_mg24.dts b/boards/seeed/xiao_mg24/xiao_mg24.dts index 73ffce9c2d589..24a2cc570ea1b 100644 --- a/boards/seeed/xiao_mg24/xiao_mg24.dts +++ b/boards/seeed/xiao_mg24/xiao_mg24.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "xiao_mg24-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" diff --git a/boards/segger/ip_k66f/ip_k66f.yaml b/boards/segger/ip_k66f/ip_k66f.yaml index 19455195664f4..0ce51cd967d55 100644 --- a/boards/segger/ip_k66f/ip_k66f.yaml +++ b/boards/segger/ip_k66f/ip_k66f.yaml @@ -14,3 +14,4 @@ supported: - netif:eth ram: 256 flash: 2048 +vendor: nxp diff --git a/boards/shields/amg88xx/doc/amg88xx_eval_kit.png b/boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_kit.png similarity index 100% rename from boards/shields/amg88xx/doc/amg88xx_eval_kit.png rename to boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_kit.png diff --git a/boards/shields/amg88xx/doc/amg88xx_grid_eye_eval_shield.png b/boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_shield.png similarity index 100% rename from boards/shields/amg88xx/doc/amg88xx_grid_eye_eval_shield.png rename to boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_shield.png diff --git a/boards/shields/amg88xx/doc/index.rst b/boards/shields/amg88xx/doc/index.rst index a307c3e00ea34..166b64dd5e2d3 100644 --- a/boards/shields/amg88xx/doc/index.rst +++ b/boards/shields/amg88xx/doc/index.rst @@ -24,7 +24,7 @@ For sensor evaluation and rapid prototyping multiple shields are available: - `Panasonic Grid-EYE Evaluation Shield`_ - .. figure:: amg88xx_grid_eye_eval_shield.png + .. figure:: AMG88XX_panasonic_grid_eye_evaluation_shield.png :width: 300px :align: center :alt: Panasonic Grid-EYE Evaluation Shield @@ -45,7 +45,7 @@ also could be used as an Arduino shield. - Panasonic Grid-EYE Evaluation Kit - .. figure:: amg88xx_eval_kit.png + .. figure:: AMG88XX_panasonic_grid_eye_evaluation_kit.png :width: 250px :align: center :alt: Panasonic Grid-EYE Evaluation Kit (deprecated) diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf index 27961f09f2ffb..881770e9f68d1 100644 --- a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf +++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf @@ -6,3 +6,4 @@ CONFIG_STM32_LTDC_RGB565=y CONFIG_DISPLAY_INIT_PRIORITY=87 CONFIG_STM32_LTDC_DISABLE_FMC_BANK1=y CONFIG_INPUT_GT911_INTERRUPT=y +CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP=y diff --git a/boards/shields/arduino_giga_display_shield/doc/index.rst b/boards/shields/arduino_giga_display_shield/doc/index.rst index 6ef0cc47e04d1..b2834b23520de 100644 --- a/boards/shields/arduino_giga_display_shield/doc/index.rst +++ b/boards/shields/arduino_giga_display_shield/doc/index.rst @@ -40,7 +40,7 @@ for projects utilizing this shield. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: arduino_giga_r1/stm32h747xx/m7 + :board: arduino_giga_r1_wifi :shield: arduino_giga_display_shield :goals: build diff --git a/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay b/boards/shields/arduino_giga_display_shield/giga_display_shield.overlay similarity index 100% rename from boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay rename to boards/shields/arduino_giga_display_shield/giga_display_shield.overlay diff --git a/boards/shields/arduino_modulino_buttons/Kconfig.shield b/boards/shields/arduino_modulino_buttons/Kconfig.shield deleted file mode 100644 index 1389b0d503663..0000000000000 --- a/boards/shields/arduino_modulino_buttons/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2025 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_ARDUINO_MODULINO_BUTTONS - def_bool $(shields_list_contains,arduino_modulino_buttons) diff --git a/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay b/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay deleted file mode 100644 index 96c84cbfb433a..0000000000000 --- a/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -&qwiic_i2c { - modulino-buttons@3e { - compatible = "i2c-device"; - reg = <0x3e>; - - modulino_buttons: modulino-buttons { - compatible = "arduino,modulino-buttons"; - zephyr,codes = , - , - ; - }; - - modulino_leds: modulino-leds { - compatible = "arduino,modulino-buttons-leds"; - }; - }; - -}; diff --git a/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp b/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp deleted file mode 100644 index c003d3358a59a..0000000000000 Binary files a/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp and /dev/null differ diff --git a/boards/shields/arduino_modulino_buttons/doc/index.rst b/boards/shields/arduino_modulino_buttons/doc/index.rst deleted file mode 100644 index 3d5f428b1d9cd..0000000000000 --- a/boards/shields/arduino_modulino_buttons/doc/index.rst +++ /dev/null @@ -1,30 +0,0 @@ -.. _arduino_modulino_buttons: - -Arduino Modulino Buttons -######################## - -Overview -******** - -The Arduino Modulino Buttons is a QWIIC compatible module with three buttons -and three LEDs. - - -.. image:: img/arduino_modulino_buttons.webp - :align: center - :alt: Arduino Modulino Buttons module - -Programming -*********** - -Set ``--shield arduino_modulino_buttons`` when you invoke ``west build``, the -buttons will be available through the input subsystem and the LEDs through the -LED subsystem. - -For example, - -.. zephyr-app-commands:: - :zephyr-app: samples/subsys/input - :board: arduino_uno_r4@wifi - :shield: arduino_modulino_buttons - :goals: build diff --git a/boards/shields/arduino_modulino_smartleds/Kconfig.shield b/boards/shields/arduino_modulino_smartleds/Kconfig.shield deleted file mode 100644 index 8ae103464053d..0000000000000 --- a/boards/shields/arduino_modulino_smartleds/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2025 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_ARDUINO_MODULINO_SMARTLEDS - def_bool $(shields_list_contains,arduino_modulino_smartleds) diff --git a/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay b/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay deleted file mode 100644 index 8873c1312bbed..0000000000000 --- a/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/ { - aliases { - led-strip = &modulino_smartleds; - }; -}; - -&qwiic_i2c { - modulino_smartleds: modulino-smartleds@36 { - compatible = "arduino,modulino-smartleds"; - reg = <0x36>; - chain-length = <8>; - color-mapping = ; - }; -}; diff --git a/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp b/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp deleted file mode 100644 index 7e5d6c5a54bb2..0000000000000 Binary files a/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp and /dev/null differ diff --git a/boards/shields/arduino_modulino_smartleds/doc/index.rst b/boards/shields/arduino_modulino_smartleds/doc/index.rst deleted file mode 100644 index f0f70ac4d3dda..0000000000000 --- a/boards/shields/arduino_modulino_smartleds/doc/index.rst +++ /dev/null @@ -1,29 +0,0 @@ -.. _arduino_modulino_smartleds: - -Arduino Modulino smart LEDs -########################### - -Overview -******** - -The Arduino Modulino smart LEDs is a QWIIC compatible module with 8 addressable -LEDs. - - -.. image:: img/arduino_modulino_smartleds.webp - :align: center - :alt: Arduino Modulino Smart LEDs - -Programming -*********** - -Set ``--shield arduino_modulino_smartleds`` when you invoke ``west build``, the -leds will be available through the LED strip subsystem. - -For example, - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/led/led_strip - :board: arduino_uno_r4@wifi - :shield: arduino_modulino_smartleds - :goals: build diff --git a/boards/shields/dvp_20pin_ov7670/Kconfig.shield b/boards/shields/dvp_20pin_ov7670/Kconfig.shield deleted file mode 100644 index f063d3d731e08..0000000000000 --- a/boards/shields/dvp_20pin_ov7670/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2025 tinyVision.ai Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_DVP_20PIN_OV7670 - def_bool $(shields_list_contains,dvp_20pin_ov7670) diff --git a/boards/shields/dvp_20pin_ov7670/doc/index.rst b/boards/shields/dvp_20pin_ov7670/doc/index.rst deleted file mode 100644 index 88e0d1bf28d7c..0000000000000 --- a/boards/shields/dvp_20pin_ov7670/doc/index.rst +++ /dev/null @@ -1,81 +0,0 @@ -.. _dvp_20pin_ov7670: - -DVP 20-pin OV7670 Camera Module -############################### - -Overview -******** - -This series of shields supports the camera modules which use a 18-pin connector compatible with -the :dtcompatible:`arducam,dvp-20pin-connector` to connect a devkit to an OV7670 image sensor via -DVP (Digital Video Port), also known as "parallel interface". - -Only 18 pins out of the 20-pin connector are present. - -It was originally produced by `Arducam`_ but is discontinuited, and now `Olimex`_ provides it. - -Pins assignment -=============== - -+-----+--------------+-----+--------------+ -| Pin | Function | Pin | Function | -+=====+==============+=====+==============+ -| 1 | 3V3 | 2 | GND | -+-----+--------------+-----+--------------+ -| 3 | SCL | 4 | SDA | -+-----+--------------+-----+--------------+ -| 5 | VS | 6 | HS | -+-----+--------------+-----+--------------+ -| 7 | PCLK | 8 | XCLK | -+-----+--------------+-----+--------------+ -| 9 | D7 | 10 | D6 | -+-----+--------------+-----+--------------+ -| 11 | D5 | 12 | D4 | -+-----+--------------+-----+--------------+ -| 13 | D3 | 14 | D2 | -+-----+--------------+-----+--------------+ -| 15 | D1 | 16 | D0 | -+-----+--------------+-----+--------------+ -| 17 | POWER_EN | 18 | POWER_DOWN | -+-----+--------------+-----+--------------+ - -Requirements -************ - -This shield can be used with any board that provides an 18 or 20-pin header spread over two rows -of 9 or 10 pins each with the above pinout, such as the `arduino Giga R1`_, `NXP FRDM-MCXN947`_, -ST boards with the `ST-CAMS-OMV`_ adapter, or any other board with a compatible connector. - -Alternatively, it is possible to use jumper wires to connect the module to any devkit that -exposes their camera parallel port to pin headers. - -Programming -*********** - -Set ``--shield dvp_20pin_ov7670`` when you invoke ``west build``. For example: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/video/capture - :board: frdm_mcxn947 - :shield: dvp_20pin_ov7670 - :goals: build - -References -********** - -.. target-notes:: - -.. _ST-CAMS-OMV: - https://www.st.com/en/evaluation-tools/b-cams-omv.html - -.. _Arducam: - https://docs.arducam.com/DVP-Camera-Module/Arduino-GIGA/Arduino-GIGA/Quick-Start-Guide/ - -.. _Arduino Giga R1: - https://docs.arduino.cc/tutorials/giga-r1-wifi/giga-camera/ - -.. _NXP FRDM-MCXN947: - https://www.nxp.com/docs/en/application-note/AN14191.pdf - -.. _Olimex: - https://www.olimex.com/Products/Components/Camera/CAMERA-OV7670/ diff --git a/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay b/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay deleted file mode 100644 index 234c33c2d5f83..0000000000000 --- a/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright 2024 NXP - * Copyright 2025 tinyVision.ai Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,camera = &dvp_20pin_interface; - }; -}; - -&dvp_20pin_i2c { - ov7670: ov7670@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - reset-gpios = <&dvp_20pin_connector DVP_20PIN_PEN GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&dvp_20pin_connector DVP_20PIN_PDN GPIO_ACTIVE_HIGH>; - - port { - ov7670_ep_out: endpoint { - remote-endpoint-label = "dvp_20pin_ep_in"; - }; - }; - }; -}; - -&dvp_20pin_interface { - status = "okay"; - - port { - dvp_20pin_ep_in: endpoint { - remote-endpoint-label = "ov7670_ep_out"; - }; - }; -}; diff --git a/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield index ebcc4f73c02f8..187fbec05cba6 100644 --- a/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield +++ b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config SHIELD_DVP_FPC24_MT9M114 - def_bool $(shields_list_contains,dvp_fpc24_mt9m114) + def_bool $(shields_list_contains,DVP_FPC24_MT9M114) diff --git a/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp b/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp deleted file mode 100644 index 27a9fe4f7d9c7..0000000000000 Binary files a/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp and /dev/null differ diff --git a/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp b/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp deleted file mode 100644 index 1a941d26e65a5..0000000000000 Binary files a/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp and /dev/null differ diff --git a/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp b/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp deleted file mode 100644 index 8f3e5beeaa172..0000000000000 Binary files a/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp and /dev/null differ diff --git a/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp b/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp deleted file mode 100644 index 8f3e5beeaa172..0000000000000 Binary files a/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp and /dev/null differ diff --git a/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig b/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig deleted file mode 100644 index 580faa75d33ad..0000000000000 --- a/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2025 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -if SHIELD_MIKROE_LTE_IOT10_CLICK - -if MODEM_CELLULAR - -# Using regulator-fixed driver to pull RTS low and effectively disable flow control since it can't -# really be setup in a generic way when using shields. -config REGULATOR - default y - -endif # MODEM_CELLULAR - -endif # SHIELD_MIKROE_LTE_IOT10_CLICK diff --git a/boards/shields/mikroe_lte_iot10_click/Kconfig.shield b/boards/shields/mikroe_lte_iot10_click/Kconfig.shield deleted file mode 100644 index b685be96c9113..0000000000000 --- a/boards/shields/mikroe_lte_iot10_click/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_MIKROE_LTE_IOT10_CLICK - def_bool $(shields_list_contains,mikroe_lte_iot10_click) diff --git a/boards/shields/mikroe_lte_iot10_click/doc/index.rst b/boards/shields/mikroe_lte_iot10_click/doc/index.rst deleted file mode 100644 index 5fc87969e8a9c..0000000000000 --- a/boards/shields/mikroe_lte_iot10_click/doc/index.rst +++ /dev/null @@ -1,55 +0,0 @@ -.. _mikroe_lte_iot10_click_shield: - -MikroElektronika LTE IoT 10 Click -################################# - -Overview -******** - -The MikroElektronika LTE IoT 10 Click is a compact add-on board that provides reliable LTE-M and -NB-IoT connectivity for industrial and commercial IoT applications. - -This board features the Monarch 2 GM02S, a dual-mode LTE-M/NB-IoT module from Sequans (based on -Sequans SQN3430 Chipset), offering global band support from 617MHz to 2.2GHz. - -.. figure:: mikroe_lte_iot10_click.webp - :align: center - :alt: MikroElektronika LTE IoT 10 Click - - MikroElektronika LTE IoT 10 Click (Credit: MikroElektronika) - -Requirements -************ - -This shield can only be used with a development board that provides a configuration for mikroBUS -connectors and defines a ``mikrobus_serial`` node alias for the mikroBUS UART interface -(see :ref:`shields` for more details). - -For more information about the GM02S module and the LTE IoT 10 Click, you may refer to the following -documentation: - -- `GM02S Datasheet`_ -- `LTE IoT 10 Click`_ - -Programming -*********** - -Set ``--shield mikroe_lte_iot10_click`` when you invoke ``west build``. Here is an example with the -:zephyr:code-sample:`cellular-modem` code sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/net/cellular_modem - :board: ek_ra6m4 - :shield: mikroe_lte_iot10_click - :goals: build - -References -********** - -.. target-notes:: - -.. _GM02S Datasheet: - https://www.sequans.com/products-solutions/gm02s/ - -.. _LTE IoT 10 Click: - https://www.mikroe.com/lte-iot-10-click diff --git a/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp b/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp deleted file mode 100644 index c145040f63665..0000000000000 Binary files a/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp and /dev/null differ diff --git a/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay b/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay deleted file mode 100644 index 0ca4040a38171..0000000000000 --- a/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2025 Benjamin Cabé - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - aliases { - modem = &modem; - modem-uart = &mikrobus_serial; - }; - - en_rts { - compatible = "regulator-fixed"; - regulator-name = "enable-rts"; - enable-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; -}; - -&mikrobus_serial { - status = "okay"; - current-speed = <115200>; - modem: modem { - status = "okay"; - compatible = "sqn,gm02s"; - mdm-wake-gpios = <&mikrobus_header 0 (GPIO_OPEN_SOURCE | GPIO_ACTIVE_HIGH)>; - mdm-reset-gpios = <&mikrobus_header 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - }; -}; diff --git a/boards/shields/npm2100_ek/Kconfig.shield b/boards/shields/npm2100_ek/Kconfig.shield deleted file mode 100644 index cbd8fff0a1c69..0000000000000 --- a/boards/shields/npm2100_ek/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_NPM2100_EK - def_bool $(shields_list_contains,npm2100_ek) diff --git a/boards/shields/npm2100_ek/doc/index.rst b/boards/shields/npm2100_ek/doc/index.rst deleted file mode 100644 index 0edf2a8da21f9..0000000000000 --- a/boards/shields/npm2100_ek/doc/index.rst +++ /dev/null @@ -1,30 +0,0 @@ -.. _npm2100_ek: - -nPM2100 EK -########## - -Overview -******** - -The nPM2100 EK lets you test different functions and features of the nPM2100 -Power Management Integrated Circuit (PMIC). - -Requirements -************ - -The nPM2100 EK board is not a direct fit into an Arduino connector. However, -the Zephyr shield must be connected to the Arduino shield connectors. That is, -you need to connect the I2C lines to the ``arduino_i2c`` bus. This allows to -use the shield with any host board that supports the Arduino connector. - -Usage -***** - -To use the shield in any application, build it with the following command: - -.. zephyr-app-commands:: - :board: your_board - :shield: npm2100_ek - :goals: build - -For a comprehensive sample, refer to :zephyr:code-sample:`npm2100_ek`. diff --git a/boards/shields/npm2100_ek/npm2100_ek.overlay b/boards/shields/npm2100_ek/npm2100_ek.overlay deleted file mode 100644 index 5db980a9afcf4..0000000000000 --- a/boards/shields/npm2100_ek/npm2100_ek.overlay +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2025 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -&arduino_i2c { - npm2100_pmic: pmic@74 { - compatible = "nordic,npm2100"; - reg = <0x74>; - - npm2100_gpio: gpio-controller { - compatible = "nordic,npm2100-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <2>; - }; - - npm2100_regulators: regulators { - compatible = "nordic,npm2100-regulator"; - - /* limits are set to min/max allowed values */ - npm2100_boost: BOOST { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - npm2100_ldosw: LDOSW { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - npm2100_wdt: watchdog { - compatible = "nordic,npm2100-wdt"; - }; - - npm2100_vbat: vbat { - compatible = "nordic,npm2100-vbat"; - }; - - npm2100_buttons: buttons { - compatible = "gpio-keys"; - - pmic_button0: pmic_button_0 { - gpios = <&npm2100_gpio 0 GPIO_ACTIVE_LOW>; - label = "Pmic button switch 0"; - zephyr,code = ; - }; - - pmic_button1: pmic_button_1 { - gpios = <&npm2100_gpio 1 GPIO_ACTIVE_LOW>; - label = "Pmic button switch 1"; - zephyr,code = ; - }; - }; - }; -}; diff --git a/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay b/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay index 357de43f2ecd6..ada3a5c61d24a 100644 --- a/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -13,24 +13,3 @@ &gpio_fwd { status = "disabled"; }; - -/* - * Override the default pinctrl settings for SPI4 when used with the nRF7002 EK - * to pull down the SPIM lines. This is needed to avoid floating inputs when - * the SPI4 is not used. The default pinctrl settings are defined in the - * nrf5340_cpuapp_common_pinctrl.dtsi file. - */ -&pinctrl { - spi4_default: spi4_default { - group1 { - bias-pull-down; - }; - }; - - spi4_sleep: spi4_sleep { - group1 { - bias-pull-down; - low-power-enable; - }; - }; -}; diff --git a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay deleted file mode 100644 index 7a5a33dda7626..0000000000000 --- a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&m2_hci_bt_uart { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-1; - /delete-property/ pinctrl-2; - /delete-property/ pinctrl-names; - pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; - pinctrl-1 = <&pinmux_lpuart3_sleep>; - pinctrl-names = "default", "sleep"; - - bt_hci_uart: bt_hci_uart { - m2_bt_module: m2_bt_module { - sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&m2_wifi_sdio { - /* TODO: Unsupported; Fix pinctrl */ -}; diff --git a/boards/shields/nxp_m2_wifi_bt/doc/index.rst b/boards/shields/nxp_m2_wifi_bt/doc/index.rst index 19c3355faf1f9..eaf57ac01e534 100644 --- a/boards/shields/nxp_m2_wifi_bt/doc/index.rst +++ b/boards/shields/nxp_m2_wifi_bt/doc/index.rst @@ -38,16 +38,6 @@ This shield works with below host platform, - :zephyr:board:`mimxrt1060_evk` Rev-C. -Fetch Binary Blobs -****************** - -To support Bluetooth or Wi-Fi, nxp_m2_wifi_bt requires fetching binary blobs, -using the following command: - -.. code-block:: console - - west blobs fetch hal_nxp - Programming *********** diff --git a/boards/shields/pmod_acl/pmod_acl.overlay b/boards/shields/pmod_acl/pmod_acl.overlay index 9f290496dcd87..935655b1971a2 100644 --- a/boards/shields/pmod_acl/pmod_acl.overlay +++ b/boards/shields/pmod_acl/pmod_acl.overlay @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - &pmod_spi { status = "okay"; @@ -13,9 +11,6 @@ compatible = "adi,adxl345"; reg = <0x0>; spi-max-frequency = ; - int2-gpios = <&pmod_header 4 GPIO_ACTIVE_HIGH>; status = "okay"; - odr = ; - fifo-watermark = <31>; }; }; diff --git a/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay b/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay index 553d296e5aade..fd54db448fdd4 100644 --- a/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay +++ b/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay @@ -17,7 +17,7 @@ lora_semtech_sx1262mb2das: sx1262@0 { compatible = "semtech,sx1262"; reg = <0>; - spi-max-frequency = ; + spi-max-frequency = <16000000>; label = "SX1262"; reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; busy-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; diff --git a/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay index 19b9aaa6eaf2c..c6e629d23425b 100644 --- a/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay +++ b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay @@ -17,6 +17,10 @@ &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9 &dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9>; pinctrl-names = "default"; + + dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; }; &dma1 { diff --git a/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay index 06b4ac0f9f7ee..0ffb5669dadfe 100644 --- a/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay +++ b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay @@ -33,14 +33,17 @@ &st_cam_dvp { status = "okay"; + sensor = <&ov5640>; + + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + capture-rate = <1>; port { dcmi_ep_in: endpoint { remote-endpoint-label = "ov5640_ep_out"; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; }; }; }; diff --git a/boards/shields/waveshare_ups/doc/index.rst b/boards/shields/waveshare_ups/doc/index.rst index 3757f7bf9193d..49493db298f99 100644 --- a/boards/shields/waveshare_ups/doc/index.rst +++ b/boards/shields/waveshare_ups/doc/index.rst @@ -39,6 +39,69 @@ Hardware - Raspberry Pi Pico compatible (I2C) - 2 pin jst header for Li-po battery +-------+-----------------------+---------------------------+ +| Name | Function | Usage | ++=======+=======================+===========================+ +| GP0 | None | | ++-------+-----------------------+---------------------------+ +| GP1 | None | | ++-------+-----------------------+---------------------------+ +| GP2 | None | | ++-------+-----------------------+---------------------------+ +| GP3 | None | | ++-------+-----------------------+---------------------------+ +| GP4 | None | | ++-------+-----------------------+---------------------------+ +| GP5 | None | | ++-------+-----------------------+---------------------------+ +| GP6 | I2C1_SDA ACTIVE_LOW | INA219 | ++-------+-----------------------+---------------------------+ +| GP7 | I2C1_SCL ACTIVE_LOW | INA219 | ++-------+-----------------------+---------------------------+ +| GP8 | None | | ++-------+-----------------------+---------------------------+ +| GP9 | None | | ++-------+-----------------------+---------------------------+ +| GP10 | None | | ++-------+-----------------------+---------------------------+ +| GP11 | None | | ++-------+-----------------------+---------------------------+ +| GP12 | None | | ++-------+-----------------------+---------------------------+ +| GP13 | None | | ++-------+-----------------------+---------------------------+ +| GP14 | None | | ++-------+-----------------------+---------------------------+ +| GP15 | None | | ++-------+-----------------------+---------------------------+ +| GP16 | None | | ++-------+-----------------------+---------------------------+ +| GP17 | None | | ++-------+-----------------------+---------------------------+ +| GP18 | None | | ++-------+-----------------------+---------------------------+ +| GP19 | None | | ++-------+-----------------------+---------------------------+ +| GP20 | None | | ++-------+-----------------------+---------------------------+ +| GP21 | None | | ++-------+-----------------------+---------------------------+ +| GP22 | None | | ++-------+-----------------------+---------------------------+ +| GP23 | None | | ++-------+-----------------------+---------------------------+ +| GP24 | None | | ++-------+-----------------------+---------------------------+ +| GP25 | None | | ++-------+-----------------------+---------------------------+ +| GP26 | None | | ++-------+-----------------------+---------------------------+ +| GP27 | None | | ++-------+-----------------------+---------------------------+ +| GP28 | None | | ++-------+-----------------------+---------------------------+ + + - Power Supply - 3.3V ~ 5V @@ -63,6 +126,7 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/ina219 + :tool: all :board: rpi_pico :shield: waveshare_pico_ups_b :goals: build flash diff --git a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay index 80e3dbc962037..e99237276078b 100644 --- a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay +++ b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay @@ -44,6 +44,12 @@ }; }; +&zephyr_camera_dvp { + dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; +}; + &dma1 { status = "okay"; }; diff --git a/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay b/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay index 5b0eb2abdbb41..bc8c6ebddb288 100644 --- a/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay +++ b/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay @@ -21,7 +21,7 @@ port { ov2640_ep_out: endpoint { - remote-endpoint-label = "zephyr_camera_dvp_in"; + remote-endpoint = <&zephyr_camera_dvp_in>; }; }; }; @@ -29,14 +29,16 @@ &zephyr_camera_dvp { status = "okay"; + sensor = <&ov2640>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + capture-rate = <1>; port { zephyr_camera_dvp_in: endpoint { - remote-endpoint-label = "ov2640_ep_out"; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; + remote-endpoint = <&ov2640_ep_out>; }; }; }; diff --git a/boards/shields/x_nucleo_gfx01m2/Kconfig.defconfig b/boards/shields/x_nucleo_gfx01m2/Kconfig.defconfig deleted file mode 100644 index 4ed49d123baa6..0000000000000 --- a/boards/shields/x_nucleo_gfx01m2/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2025 Christian Rask -# SPDX-License-Identifier: Apache-2.0 - -if SHIELD_X_NUCLEO_GFX01M2 - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config SPI_STM32_DMA - default y - depends on SPI - -endif # SHIELD_X_NUCLEO_GFX01M2 diff --git a/boards/shields/x_nucleo_gfx01m2/Kconfig.shield b/boards/shields/x_nucleo_gfx01m2/Kconfig.shield deleted file mode 100644 index e9295393541fa..0000000000000 --- a/boards/shields/x_nucleo_gfx01m2/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Christian Rask -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_X_NUCLEO_GFX01M2 - def_bool $(shields_list_contains,x_nucleo_gfx01m2) diff --git a/boards/shields/x_nucleo_gfx01m2/boards/nucleo_g071rb.overlay b/boards/shields/x_nucleo_gfx01m2/boards/nucleo_g071rb.overlay deleted file mode 100644 index 5966db2625523..0000000000000 --- a/boards/shields/x_nucleo_gfx01m2/boards/nucleo_g071rb.overlay +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2025 Christian Rask - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&st_morpho_lcd_spi { - pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; - pinctrl-names = "default"; - dmas = <&dmamux1 0 17 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_LOW)>, - <&dmamux1 1 16 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_LOW)>; - dma-names = "tx", "rx"; -}; - -&st_morpho_flash_spi { - pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pc2 &spi2_mosi_pc3>; - pinctrl-names = "default"; - dmas = <&dmamux1 2 19 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_LOW)>, - <&dmamux1 3 18 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_LOW)>; - dma-names = "tx", "rx"; -}; - -&dma1 { - status = "okay"; -}; - -&dmamux1 { - status = "okay"; -}; - -&spi1_miso_pa6 { - slew-rate = "very-high-speed"; -}; - -&spi1_mosi_pa7 { - slew-rate = "very-high-speed"; -}; - -&spi2_miso_pc2 { - slew-rate = "very-high-speed"; -}; - -&spi2_mosi_pc3 { - slew-rate = "very-high-speed"; -}; diff --git a/boards/shields/x_nucleo_gfx01m2/doc/index.rst b/boards/shields/x_nucleo_gfx01m2/doc/index.rst deleted file mode 100644 index fe060b019a18e..0000000000000 --- a/boards/shields/x_nucleo_gfx01m2/doc/index.rst +++ /dev/null @@ -1,83 +0,0 @@ -.. _x_nucleo_gfx01m2_shield: - -X-NUCLEO-GFX01M2 Display expansion board -############################################## - -Overview -******** - -The X-NUCLEO-GFX01M1 and X-NUCLEO-GFX01M2 expansion boards (X-NUCLEO-GFX01Mx) -add graphic user interface (GUI) capability to STM32 Nucleo-64 boards. -They feature a 2.2" SPI QVGA TFT display as well as a 64-Mbit SPI NOR Flash -memory for storing graphic images, texts and texture. The expansion boards -also offer a joystick for GUI navigation. - -X-NUCLEO-GFX01M2 uses the ST morpho connector and supports up to two SPIs. - -The SPI Display is compatible with the ``ilitek,ili9341`` driver and -the SPI FLASH is compatible with the ``jedec,spi-nor`` driver. - -.. figure:: x_nucleo_gfx01m2.webp - :align: center - :alt: X-NUCLEO-GFX01M2 - -More information about the board can be found at the -`X-NUCLEO-GFX01M2 website`_. - -Requirements -************ - -This shield can only be used with STM32 Nucleo-64 boards that provide -a configuration for ST Morpho connectors. This shield supports up to two SPIs. -Two node aliases for the LCD SPI and FLASH SPI are defined in the device tree -overlay that must reference the appropriate SPI controllers on the Nucleo -board. Consult the X-NUCLEO-GFX01M2 user manual for more information about the -SPI pinouts used on your development board: - -- `X-NUCLEO-GFX01M2 SPI display expansion board User Manual`_ - -The SPI FLASH device does not support the Write Protection and Pause features. - -For more information about interfacing the MX25L6433F FLASH device and the -ILI9341 display controller, see these documents: - -- `ILI9341 Serial SPI bus TFT LCD Display Datasheet`_ -- `MX25L6433F Serial SPI bus NOR FLASH Datasheet`_ - -Hardware configuration -********************** - -The default SPI pin control of your development board may not be compatible -with the X-NUCLEO-GFX01M2 expansion board. Additionally, it is recommended -to configure the SPI pins to high speed and configure DMA channels for the -best graphics performance. See boards/nucleo_g071rb.overlay for an example -of how to do this. - -Samples -******* - -The :zephyr:code-sample:`display` and :zephyr:code-sample:`spi-nor` samples -can be used to test out the expansion boards functionality. - -Programming -*********** - -Set ``--shield x_nucleo_gfx01m2`` when you invoke ``west build``. For example: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/display/ - :board: nucleo_g071rb - :shield: x_nucleo_gfx01m2 - :goals: build - -.. _X-NUCLEO-GFX01M2 website: - https://www.st.com/en/evaluation-tools/x-nucleo-gfx01m2.html#overview - -.. _X-NUCLEO-GFX01M2 SPI display expansion board User Manual: - https://www.st.com/resource/en/user_manual/um2750-spi-display-expansion-boards-for-stm32-nucleo64-stmicroelectronics.pdf - -.. _ILI9341 Serial SPI bus TFT LCD Display Datasheet: - https://cdn-shop.adafruit.com/datasheets/ILI9341.pdf - -.. _MX25L6433F Serial SPI bus NOR FLASH Datasheet: - https://www1.futureelectronics.com/doc/Macronix/MX25L6433FZNI-08G.pdf diff --git a/boards/shields/x_nucleo_gfx01m2/doc/x_nucleo_gfx01m2.webp b/boards/shields/x_nucleo_gfx01m2/doc/x_nucleo_gfx01m2.webp deleted file mode 100644 index ca3f6dcf2e45c..0000000000000 Binary files a/boards/shields/x_nucleo_gfx01m2/doc/x_nucleo_gfx01m2.webp and /dev/null differ diff --git a/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay b/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay deleted file mode 100644 index 0f3d0261a71c6..0000000000000 --- a/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2025 Christian Rask - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -/ { - chosen { - zephyr,display = &ili9341; - }; - - aliases { - sw0 = &joy_sel; - }; - - gpio_keys { - compatible = "gpio-keys"; - - joy_sel: joystick_selection { - label = "joystick selection"; - gpios = <&st_morpho_header ST_MORPHO_R_19 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - - joy_down: joystick_down { - label = "joystick down"; - gpios = <&st_morpho_header ST_MORPHO_R_27 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - - joy_up: joystick_up { - label = "joystick up"; - gpios = <&st_morpho_header ST_MORPHO_L_38 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - - joy_left: joystick_left { - label = "joystick left"; - gpios = <&st_morpho_header ST_MORPHO_R_17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - - joy_right: joystick_right { - label = "joystick right"; - gpios = <&st_morpho_header ST_MORPHO_L_34 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - spi-dev = <&st_morpho_lcd_spi>; - dc-gpios = <&st_morpho_header ST_MORPHO_R_25 GPIO_ACTIVE_HIGH>; - reset-gpios = <&st_morpho_header ST_MORPHO_L_30 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - write-only; - - ili9341: ili9341@0 { - compatible = "ilitek,ili9341"; - mipi-max-frequency = ; - mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; - reg = <0>; - width = <240>; - height = <320>; - rotation = <180>; - pixel-format = ; - frmctr1 = [00 1f]; /* 60Hz frame rate */ - }; - }; -}; - -st_morpho_lcd_spi: &spi1 {}; -st_morpho_flash_spi: &spi2 {}; - -&st_morpho_lcd_spi { - cs-gpios = <&st_morpho_header ST_MORPHO_R_21 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - status = "okay"; -}; - -&st_morpho_flash_spi { - cs-gpios = <&st_morpho_header ST_MORPHO_R_23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - status = "okay"; - - mx25l6433f: mx25l6433f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = ; - size = ; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <100000>; - jedec-id = [c2 20 17]; - }; -}; diff --git a/boards/shields/x_nucleo_wb05kn1/doc/index.rst b/boards/shields/x_nucleo_wb05kn1/doc/index.rst index a723f90ed6056..5247294f5f37b 100644 --- a/boards/shields/x_nucleo_wb05kn1/doc/index.rst +++ b/boards/shields/x_nucleo_wb05kn1/doc/index.rst @@ -11,14 +11,6 @@ The RF module is FCC (FCC ID: YCP-MB203202) and IC certified (IC: 8976A-MB203202 The X-NUCLEO-WB05KN1 is compatible out of the box with the Arduino UNO R3 connector. The board interfaces with the host microcontroller via UART (default) or SPI peripheral. -However, the out-of-the-box firmware is not compatible with Zephyr; therefore, a controller-only -image should be flashed on the board using CN8 pin headers. -For more information about how to change the firmware, please refer to `UM3406`_ section 3.3. - -.. note:: - The `X-CUBE-WB05N`_ package provided by ST contains firmware compatible with Zephyr - in the ``Utilities/BLE_Transparent_Mode_STM32WB05_controller_only`` directory - (``SPI`` or ``UART`` subdirectories depending on which interface you want to use). .. image:: img/x-nucleo-wb05kn1.webp :align: center @@ -46,14 +38,9 @@ The UART default settings are: | TX | D1 | +----------+-----------------------+ -The SPI default settings are: - -* Mode: Full-duplex slave -* Frame format: Motorola -* Data size: 8 bits, MSB first -* Clock Polarity: High (CPOL=1) -* Clock Phase: 2 Edge (CPHA=1) -* CS type: Software-controlled +.. note:: + Please, bear in mind in order to use SPI interface you need to change the shield firmware + to ``DTM_SPI_WITH_UPDATER_CONTROLLER`` according to the SDK provided by ST at `X-CUBE-WB05N`_. IRQ and reset pins are also necessary in addition to SPI pins. @@ -89,7 +76,7 @@ Activate the presence of the shield for the project build by adding the :shield: x_nucleo_wb05kn1_uart :goals: build -Or +or .. zephyr-app-commands:: :app: your_app @@ -102,14 +89,11 @@ References .. target-notes:: -.. _UM3406: - https://www.st.com/resource/en/user_manual/um3406-getting-started-with-the-xcubewb05n-bluetooth-low-energy-software-expansion-for-stm32cube-stmicroelectronics.pdf +.. _X-NUCLEO-WB05KN1 website: + https://www.st.com/en/evaluation-tools/x-nucleo-wb05kn1.html .. _X-CUBE-WB05N: https://www.st.com/en/embedded-software/x-cube-wb05n.html -.. _X-NUCLEO-WB05KN1 website: - https://www.st.com/en/evaluation-tools/x-nucleo-wb05kn1.html - .. _X-NUCLEO-WB05KN1 datasheet: https://www.st.com/resource/en/datasheet/stm32wb05kn.pdf diff --git a/boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi b/boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi index 89f46066e1b6c..c071820bfc00b 100644 --- a/boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi +++ b/boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi @@ -10,10 +10,10 @@ /* configuration for usart0 device, default state - operating as UART */ usart0_default: usart0_default { group1 { - psels = , - , - , - ; + psels = , + , + , + ; }; }; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a.dts b/boards/silabs/dev_kits/sltb010a/sltb010a.dts index 0e368a0a57843..520d9837d74cd 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a.dts +++ b/boards/silabs/dev_kits/sltb010a/sltb010a.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "sltb010a-pinctrl.dtsi" #include "thunderboard.dtsi" #include diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts index d327ca290f468..9fafecd6df1ce 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include #include #include "xg24_dk2601b-pinctrl.dtsi" diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts index 2332948ac0202..7ebddf29945eb 100644 --- a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include #include #include "xg24_ek2703a-pinctrl.dtsi" diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts index a1468ef7c92d8..7bd14874e9b89 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "xg27_dk2602a-pinctrl.dtsi" #include "thunderboard.dtsi" #include diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml index 65c3ff39c1e04..29a0ddccea59c 100644 --- a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml +++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml @@ -16,9 +16,5 @@ supported: - i2c - pwm - watchdog - - spi - - uart - - i2s - wifi - - rtc vendor: silabs diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/Kconfig.siwx917_rb4342a b/boards/silabs/radio_boards/siwx917_rb4342a/Kconfig.siwx917_rb4342a deleted file mode 100644 index 0cfcbbf7cda8a..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/Kconfig.siwx917_rb4342a +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Silicon Laboratories Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SIWX917_RB4342A - select SOC_PART_NUMBER_SIWG917M111MGTBA diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/board.cmake b/boards/silabs/radio_boards/siwx917_rb4342a/board.cmake deleted file mode 100644 index f901065afa1f8..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2025 Silicon Laboratories Inc. -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(silabs_commander "--device=SiWG917M111GTBA" "--file-type=bin" - "--file=${PROJECT_BINARY_DIR}/${KERNEL_BIN_NAME}.rps") -include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) - -# It is not possible to load/flash a firmware using JLink, but it is possible to -# debug a firmware with: -# west attach -r jlink -# Once started, it should be possible to reset the device with "monitor reset" -board_runner_args(jlink "--device=Si917" "--speed=10000") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/board.yml b/boards/silabs/radio_boards/siwx917_rb4342a/board.yml deleted file mode 100644 index 12af7646529d5..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: siwx917_rb4342a - full_name: SiWx917 Wi-Fi 6 and Bluetooth LE 8 MB Flash + 8 MB ext PSRAM Radio Board (SLWRB4342A) - vendor: silabs - socs: - - name: siwg917m111mgtba diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst b/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst deleted file mode 100644 index c865938ecb7a7..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst +++ /dev/null @@ -1,100 +0,0 @@ -.. zephyr:board:: siwx917_rb4342a - - -Overview -******** - -The SiWx917-RB4342A (aka BRD4342A) radio board provides support for the Silicon -Labs SiWG917 SoC. This board cannot be used stand-alone and requires a a -`Wireless Pro Kit`_ Mainboard (Si-MB4002A aka BRD4002A), for power, debug -options etc. - -SiWG917 is an ultra-low power SoC that includes hardware support for Single-Band -Wi-Fi 6 + Bluetooth LE 5.4, Matter... - -Hardware -******** - -For more information about the SiWG917 SoC and BRD4342A board, refer to these -documents: - -- `SiWG917 Website`_ -- `SiWG917 Datasheet`_ -- `SiWG917 Reference Manual`_ -- `BRD4342A Website`_ -- `BRD4342A User Guide`_ - - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Programming and Debugging -************************* - -Flashing -======== - -Applications for the ``siwx917_rb4342a`` board can be built in the usual -way. The flash method requires on `Simplicity Commander`_ installed on the host. - -Then, connect the BRD4002A board with a mounted BRD4342A radio module to your -host computer using the USB port. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: siwx917_rb4342a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! siwx917_rb4342a - - -Debugging -========= - -Debuggning relies on JLink tool. JLink is not able to flash the firmware. So -debug session has to be done in two steps. ``west flash`` will flahs the -firmware using Simplicity Commander. Then ``west attach`` will use JLink to -attach to the board. The Zephyr image may has already booted when user runs -``west attach``. User may execute ``monitor reset`` in the gdb prompt to reset -the board. - - - -.. _SiWx917-PK6031A: - https://www.silabs.com/development-tools/wireless/wi-fi/siwx917-pk6031a-wifi-6-bluetooth-le-soc-pro-kit - -.. _Wireless Pro Kit: - https://www.silabs.com/development-tools/wireless/wireless-pro-kit-mainboard - -.. _BRD4342A Website: - https://www.silabs.com/development-tools/wireless/wi-fi/siwx91x-rb4342a-wifi-6-bluetooth-le-soc-radio-board - -.. _BRD4342A User Guide: - https://www.silabs.com/documents/public/user-guides/ug564-brd4342a-user-guide.pdf - -.. _SiWG917 Website: - https://www.silabs.com/wireless/wi-fi/siwx917-wireless-socs - -.. _SiWG917 Datasheet: - https://www.silabs.com/documents/public/data-sheets/siwg917-datasheet.pdf - -.. _SiWG917 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/siw917x-family-rm.pdf - -.. _Simplicity Commander: - https://www.silabs.com/developer-tools/simplicity-studio/simplicity-commander diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/doc/siwx917_rb4342a.webp b/boards/silabs/radio_boards/siwx917_rb4342a/doc/siwx917_rb4342a.webp deleted file mode 100644 index 80bb6f8a3467b..0000000000000 Binary files a/boards/silabs/radio_boards/siwx917_rb4342a/doc/siwx917_rb4342a.webp and /dev/null differ diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.dts b/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.dts deleted file mode 100644 index 7b850b460cffc..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.dts +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2023 Antmicro - * Copyright (c) 2025 Silicon Laboratories Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include - -/ { - model = "Silicon Labs BRD4342A (SiWG917 Radio Board)"; - compatible = "silabs,x917_rb4342a", "silabs,siwg917"; - - chosen { - zephyr,sram = &sram0; - zephyr,code-partition = &code_partition; - zephyr,console = &ulpuart; - zephyr,shell-uart = &ulpuart; - zephyr,uart-pipe = &ulpuart; - zephyr,bt-hci = &bt_hci0; - }; - - aliases { - led0 = &led0; - sw0 = &button0; - dht0 = &si7021; - }; - - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&ulpgpio 2 GPIO_ACTIVE_HIGH>; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&uulpgpio 2 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&pinctrl0 { - psram_default: psram_default { - group { - pinmux = , - , - , - , - , - ; - }; - }; - - ulpuart_default: ulpuart_default { - out { - pinmux = ; - }; - in { - pinmux = ; - }; - }; - - ulpi2c_default: ulpi2c_default { - group { - pinmux = , ; - }; - }; -}; - -&ulpuart { - status = "okay"; - pinctrl-0 = <&ulpuart_default>; - pinctrl-names = "default"; -}; - -&ulpi2c { - status = "okay"; - pinctrl-0 = <&ulpi2c_default>; - pinctrl-names = "default"; - clock-frequency = ; - - si7021: si7021@40 { - compatible = "silabs,si7006"; - reg = <0x40>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - code_partition: partition@0 { - label = "code_partition"; - reg = <0x0000000 DT_SIZE_K(2008)>; - }; - - storage_partition: partition@1f6000 { - label = "storage"; - reg = <0x001f6000 DT_SIZE_K(32)>; - }; - }; -}; - -&psramctrl0 { - status = "okay"; - clocks = <&clock0 SIWX91X_CLK_QSPI>; - pinctrl-0 = <&psram_default>; - pinctrl-names = "default"; - device-id = [ 0d 5d 00 00 00 00 00 00 ]; - normal-freq = ; - fast-freq = ; - - psram: psram@a000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0xa000000 DT_SIZE_M(8)>; - zephyr,memory-region = "psram"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; - }; -}; - -&bt_hci0 { - status = "okay"; -}; - -&wifi0 { - status = "okay"; -}; diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.yaml b/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.yaml deleted file mode 100644 index 17180fdf042b8..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: siwx917_rb4342a -name: | - SiWx917 Wi-Fi 6 and Bluetooth LE 8 MB Flash + 8 MB ext PSRAM Radio Board - (SLWRB4342A, BRD4342A) -type: mcu -arch: arm -ram: 8864 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - bluetooth - - dma - - entropy - - flash - - gpio - - i2c - - pwm - - uart - - watchdog - - wifi -vendor: silabs diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a_defconfig b/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a_defconfig deleted file mode 100644 index 783bf82d3022d..0000000000000 --- a/boards/silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2025 Silicon Laboratories Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CLOCK_CONTROL=y -CONFIG_MEMC=y - -CONFIG_CLOCK_CONTROL_INIT_PRIORITY=28 -CONFIG_MEMC_INIT_PRIORITY=29 diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts index bfb1ceb03bcd7..48154c0b87984 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include #include "slwrb4180a-pinctrl.dtsi" diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts index 3fdf643718724..77654a1f0336d 100644 --- a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts +++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include #include "slwrb4180b-pinctrl.dtsi" diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts index 35a485cb70c48..dd94b0dfa360e 100644 --- a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include #include #include "xg23_rb4210a-pinctrl.dtsi" diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts index bb6a4ef86fdd7..ba9e0a1420a25 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include #include #include "xg24_rb4187c-pinctrl.dtsi" diff --git a/boards/sipeed/longan_nano/board.cmake b/boards/sipeed/longan_nano/board.cmake index 7cfcf34f48ffa..f58ea4369587d 100644 --- a/boards/sipeed/longan_nano/board.cmake +++ b/boards/sipeed/longan_nano/board.cmake @@ -7,8 +7,6 @@ board_runner_args(openocd "--cmd-pre-load=gd32vf103-pre-load") board_runner_args(openocd "--cmd-load=gd32vf103-load") board_runner_args(openocd "--cmd-post-verify=gd32vf103-post-verify") board_runner_args(dfu-util "--pid=28e9:0189" "--alt=0" "--dfuse") -board_runner_args(jlink "--device=GD32VF103CBT6" "--speed=4000" "--iface=jtag" "--tool-opt=-jtagconf -1,-1 -autoconnect 1" "--reset-after-load") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts index bd4753506c693..e24f97961a563 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include "sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi" #include #include diff --git a/boards/st/b_l072z_lrwan1/board.cmake b/boards/st/b_l072z_lrwan1/board.cmake index fb47b89a7f3aa..d08734fa6c149 100644 --- a/boards/st/b_l072z_lrwan1/board.cmake +++ b/boards/st/b_l072z_lrwan1/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L072CZ" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/b_l4s5i_iot01a/board.cmake b/boards/st/b_l4s5i_iot01a/board.cmake index 8318bf2e66042..9985ccb50b019 100644 --- a/boards/st/b_l4s5i_iot01a/board.cmake +++ b/boards/st/b_l4s5i_iot01a/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L4S5VI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/b_u585i_iot02a/board.cmake b/boards/st/b_u585i_iot02a/board.cmake index bb801eaae547d..84bf22d1162cd 100644 --- a/boards/st/b_u585i_iot02a/board.cmake +++ b/boards/st/b_u585i_iot02a/board.cmake @@ -30,5 +30,5 @@ board_runner_args(jlink "--device=STM32U585AI" "--reset-after-load") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) # FIXME: openocd runner requires use of STMicro openocd fork. # Check board documentation for more details. -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/disco_l475_iot1/board.cmake b/boards/st/disco_l475_iot1/board.cmake index 6ef3d18c39c0b..6eae838ebe335 100644 --- a/boards/st/disco_l475_iot1/board.cmake +++ b/boards/st/disco_l475_iot1/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L475VG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_c071rb/board.cmake b/boards/st/nucleo_c071rb/board.cmake index daa77274ae172..716846e4923c4 100644 --- a/boards/st/nucleo_c071rb/board.cmake +++ b/boards/st/nucleo_c071rb/board.cmake @@ -5,4 +5,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.dts b/boards/st/nucleo_c071rb/nucleo_c071rb.dts index 2344c71a1aaaa..3d4bcd0a12e46 100644 --- a/boards/st/nucleo_c071rb/nucleo_c071rb.dts +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.dts @@ -165,9 +165,3 @@ &dmamux1 { status = "okay"; }; - -zephyr_udc0: &usb { - pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.yaml b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml index c6fb56c823443..50ca9ed00ee24 100644 --- a/boards/st/nucleo_c071rb/nucleo_c071rb.yaml +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml @@ -16,8 +16,6 @@ supported: - rtc - spi - watchdog - - usb_device - - usbd ram: 24 flash: 128 vendor: st diff --git a/boards/st/nucleo_f030r8/board.cmake b/boards/st/nucleo_f030r8/board.cmake index 9c20b630831e8..cd75a64d08742 100644 --- a/boards/st/nucleo_f030r8/board.cmake +++ b/boards/st/nucleo_f030r8/board.cmake @@ -7,6 +7,6 @@ board_runner_args(probe-rs "--chip=STM32F030R8Tx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) diff --git a/boards/st/nucleo_f031k6/board.cmake b/boards/st/nucleo_f031k6/board.cmake index c3f7448688b5f..da308d3659a5e 100644 --- a/boards/st/nucleo_f031k6/board.cmake +++ b/boards/st/nucleo_f031k6/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F031K6" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f042k6/board.cmake b/boards/st/nucleo_f042k6/board.cmake index fd92c7b5edc30..3b4c81fc1513a 100644 --- a/boards/st/nucleo_f042k6/board.cmake +++ b/boards/st/nucleo_f042k6/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F042K6" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f070rb/board.cmake b/boards/st/nucleo_f070rb/board.cmake index 0d7cb7040adbb..720e4e00ab53c 100644 --- a/boards/st/nucleo_f070rb/board.cmake +++ b/boards/st/nucleo_f070rb/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F070RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f072rb/board.cmake b/boards/st/nucleo_f072rb/board.cmake index f85a8e424bab5..136bd345f6afa 100644 --- a/boards/st/nucleo_f072rb/board.cmake +++ b/boards/st/nucleo_f072rb/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F072RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f091rc/board.cmake b/boards/st/nucleo_f091rc/board.cmake index a05a4ed62f643..f465bc737b1e5 100644 --- a/boards/st/nucleo_f091rc/board.cmake +++ b/boards/st/nucleo_f091rc/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F091RC" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f103rb/board.cmake b/boards/st/nucleo_f103rb/board.cmake index 9b122cd0c3a6c..724e7b7141f5c 100644 --- a/boards/st/nucleo_f103rb/board.cmake +++ b/boards/st/nucleo_f103rb/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F103RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f207zg/board.cmake b/boards/st/nucleo_f207zg/board.cmake index c25042bcd146d..8c62e3ccbbf72 100644 --- a/boards/st/nucleo_f207zg/board.cmake +++ b/boards/st/nucleo_f207zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F207ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f302r8/board.cmake b/boards/st/nucleo_f302r8/board.cmake index aa2e632bf8bdc..4a80e30f04f4c 100644 --- a/boards/st/nucleo_f302r8/board.cmake +++ b/boards/st/nucleo_f302r8/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F302R8" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f303k8/board.cmake b/boards/st/nucleo_f303k8/board.cmake index 2ee7dcf79ead6..179e15cfcab3b 100644 --- a/boards/st/nucleo_f303k8/board.cmake +++ b/boards/st/nucleo_f303k8/board.cmake @@ -10,5 +10,5 @@ board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f303re/board.cmake b/boards/st/nucleo_f303re/board.cmake index f7b8c33c3186f..a080f9119e15a 100644 --- a/boards/st/nucleo_f303re/board.cmake +++ b/boards/st/nucleo_f303re/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F303RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f334r8/board.cmake b/boards/st/nucleo_f334r8/board.cmake index 2ebdf5163f132..e98f17692eccd 100644 --- a/boards/st/nucleo_f334r8/board.cmake +++ b/boards/st/nucleo_f334r8/board.cmake @@ -10,5 +10,5 @@ board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f401re/board.cmake b/boards/st/nucleo_f401re/board.cmake index 0702d8e78e5d8..65321107f3a58 100644 --- a/boards/st/nucleo_f401re/board.cmake +++ b/boards/st/nucleo_f401re/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F401RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f410rb/board.cmake b/boards/st/nucleo_f410rb/board.cmake index 721238610c8aa..5eb1ca023450e 100644 --- a/boards/st/nucleo_f410rb/board.cmake +++ b/boards/st/nucleo_f410rb/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F410RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f411re/board.cmake b/boards/st/nucleo_f411re/board.cmake index a1e8a2d1e07aa..2015a3f497aac 100644 --- a/boards/st/nucleo_f411re/board.cmake +++ b/boards/st/nucleo_f411re/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F411RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f412zg/board.cmake b/boards/st/nucleo_f412zg/board.cmake index 2aa3b0baed3a3..be8b35e82c82d 100644 --- a/boards/st/nucleo_f412zg/board.cmake +++ b/boards/st/nucleo_f412zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F412ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f413zh/board.cmake b/boards/st/nucleo_f413zh/board.cmake index 60c93ad815c35..800b779a42dbc 100644 --- a/boards/st/nucleo_f413zh/board.cmake +++ b/boards/st/nucleo_f413zh/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F413ZH" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f429zi/board.cmake b/boards/st/nucleo_f429zi/board.cmake index ece0ab69e179f..49ab35806cabd 100644 --- a/boards/st/nucleo_f429zi/board.cmake +++ b/boards/st/nucleo_f429zi/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F429ZI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f439zi/board.cmake b/boards/st/nucleo_f439zi/board.cmake index cf35442892b1d..b7761f24ff315 100644 --- a/boards/st/nucleo_f439zi/board.cmake +++ b/boards/st/nucleo_f439zi/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F439ZI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f446re/board.cmake b/boards/st/nucleo_f446re/board.cmake index 14ae70bb37f38..b7d889530e829 100644 --- a/boards/st/nucleo_f446re/board.cmake +++ b/boards/st/nucleo_f446re/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F446RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f446ze/board.cmake b/boards/st/nucleo_f446ze/board.cmake index 252e8c3b3838f..33af015beeb9d 100644 --- a/boards/st/nucleo_f446ze/board.cmake +++ b/boards/st/nucleo_f446ze/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F446ZE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f722ze/board.cmake b/boards/st/nucleo_f722ze/board.cmake index e4df7aa605f9a..fc8e64fe0b56f 100644 --- a/boards/st/nucleo_f722ze/board.cmake +++ b/boards/st/nucleo_f722ze/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F722ZE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f722ze/nucleo_f722ze.dts b/boards/st/nucleo_f722ze/nucleo_f722ze.dts index 377d32c9ae125..00faeae1dbc2e 100644 --- a/boards/st/nucleo_f722ze/nucleo_f722ze.dts +++ b/boards/st/nucleo_f722ze/nucleo_f722ze.dts @@ -97,7 +97,6 @@ &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &adc1 { diff --git a/boards/st/nucleo_f746zg/board.cmake b/boards/st/nucleo_f746zg/board.cmake index 61dd9764578ab..d1b2798ccdda7 100644 --- a/boards/st/nucleo_f746zg/board.cmake +++ b/boards/st/nucleo_f746zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F746ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f756zg/board.cmake b/boards/st/nucleo_f756zg/board.cmake index 31f05e4c8645f..d6a50cef168c2 100644 --- a/boards/st/nucleo_f756zg/board.cmake +++ b/boards/st/nucleo_f756zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F756ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f767zi/board.cmake b/boards/st/nucleo_f767zi/board.cmake index b4c75553386f8..3df233b4a75ed 100644 --- a/boards/st/nucleo_f767zi/board.cmake +++ b/boards/st/nucleo_f767zi/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F767ZI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g031k8/board.cmake b/boards/st/nucleo_g031k8/board.cmake index 611111dc2cdc5..332fe061efd00 100644 --- a/boards/st/nucleo_g031k8/board.cmake +++ b/boards/st/nucleo_g031k8/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32G031K8" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g070rb/board.cmake b/boards/st/nucleo_g070rb/board.cmake index 5d9754c7567a7..e8ff9cd0ccbfa 100644 --- a/boards/st/nucleo_g070rb/board.cmake +++ b/boards/st/nucleo_g070rb/board.cmake @@ -9,6 +9,6 @@ board_runner_args(jlink "--device=STM32G070RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g071rb/board.cmake b/boards/st/nucleo_g071rb/board.cmake index 111c105af2360..14262985a8ce5 100644 --- a/boards/st/nucleo_g071rb/board.cmake +++ b/boards/st/nucleo_g071rb/board.cmake @@ -9,6 +9,6 @@ board_runner_args(jlink "--device=STM32G071RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g0b1re/board.cmake b/boards/st/nucleo_g0b1re/board.cmake index 67456b7b6a5d2..40365ef68854c 100644 --- a/boards/st/nucleo_g0b1re/board.cmake +++ b/boards/st/nucleo_g0b1re/board.cmake @@ -10,6 +10,6 @@ board_runner_args(jlink "--device=STM32G0B1RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g431kb/board.cmake b/boards/st/nucleo_g431kb/board.cmake index 830889c5a0764..7d054ec941f1c 100644 --- a/boards/st/nucleo_g431kb/board.cmake +++ b/boards/st/nucleo_g431kb/board.cmake @@ -8,5 +8,5 @@ board_runner_args(jlink "--device=STM32G431KB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g431rb/board.cmake b/boards/st/nucleo_g431rb/board.cmake index 5d80995288e12..19ba91a4a2541 100644 --- a/boards/st/nucleo_g431rb/board.cmake +++ b/boards/st/nucleo_g431rb/board.cmake @@ -8,5 +8,5 @@ board_runner_args(jlink "--device=STM32G431RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g474re/Kconfig.defconfig b/boards/st/nucleo_g474re/Kconfig.defconfig index e6cb7b85d3e18..fb93e1098d1ac 100644 --- a/boards/st/nucleo_g474re/Kconfig.defconfig +++ b/boards/st/nucleo_g474re/Kconfig.defconfig @@ -9,4 +9,4 @@ config SPI_STM32_INTERRUPT default y depends on SPI -endif # BOARD_NUCLEO_G474RE +endif # BOARD_NUCLEO_G431RB diff --git a/boards/st/nucleo_g474re/board.cmake b/boards/st/nucleo_g474re/board.cmake index 2dc259d0cc47a..9e4f74239feef 100644 --- a/boards/st/nucleo_g474re/board.cmake +++ b/boards/st/nucleo_g474re/board.cmake @@ -7,6 +7,6 @@ board_runner_args(jlink "--device=STM32G474RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h503rb/board.cmake b/boards/st/nucleo_h503rb/board.cmake index f6a2fdfb91b36..5ac7cb17f66fc 100644 --- a/boards/st/nucleo_h503rb/board.cmake +++ b/boards/st/nucleo_h503rb/board.cmake @@ -12,5 +12,5 @@ board_runner_args(pyocd "--target=stm32h503rbtx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) # FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb.dts b/boards/st/nucleo_h503rb/nucleo_h503rb.dts index f95e33b78845d..f9576eea88e52 100644 --- a/boards/st/nucleo_h503rb/nucleo_h503rb.dts +++ b/boards/st/nucleo_h503rb/nucleo_h503rb.dts @@ -100,13 +100,6 @@ status = "okay"; }; -&spi1 { - pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; - pinctrl-names = "default"; - cs-gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - &rng { status = "okay"; }; diff --git a/boards/st/nucleo_h533re/board.cmake b/boards/st/nucleo_h533re/board.cmake index ef9b8848c8d32..963b13b03b227 100644 --- a/boards/st/nucleo_h533re/board.cmake +++ b/boards/st/nucleo_h533re/board.cmake @@ -15,5 +15,5 @@ board_runner_args(openocd "--no-halt") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) # FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h563zi/board.cmake b/boards/st/nucleo_h563zi/board.cmake index f8974ae2be22a..be01446199a38 100644 --- a/boards/st/nucleo_h563zi/board.cmake +++ b/boards/st/nucleo_h563zi/board.cmake @@ -15,5 +15,5 @@ board_runner_args(openocd "--no-halt") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -#include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) # FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi index 12f4f74dd25eb..37f7a293f4757 100644 --- a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi @@ -36,4 +36,4 @@ arduino_i2c: &i2c1 {}; arduino_spi: &spi1 {}; -arduino_serial: &lpuart1 {}; +arduino_serial: &uart8 {}; diff --git a/boards/st/nucleo_h723zg/board.cmake b/boards/st/nucleo_h723zg/board.cmake index 68f24ee9e7d54..b9e6be6fda52a 100644 --- a/boards/st/nucleo_h723zg/board.cmake +++ b/boards/st/nucleo_h723zg/board.cmake @@ -7,5 +7,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts index 97f70aef6d7fc..8c49c833e7152 100644 --- a/boards/st/nucleo_h723zg/nucleo_h723zg.dts +++ b/boards/st/nucleo_h723zg/nucleo_h723zg.dts @@ -119,13 +119,6 @@ d3ppre = <2>; /* APB4: 137.5 MHz */ }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi index e9107b9adb9b9..0c6754fc8c39a 100644 --- a/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi @@ -38,4 +38,3 @@ arduino_i2c: &i2c1 {}; arduino_spi: &spi1 {}; -arduino_serial: &lpuart1 {}; diff --git a/boards/st/nucleo_h743zi/board.cmake b/boards/st/nucleo_h743zi/board.cmake index dcb50881c78d0..004ae3551ce9e 100644 --- a/boards/st/nucleo_h743zi/board.cmake +++ b/boards/st/nucleo_h743zi/board.cmake @@ -9,6 +9,6 @@ board_runner_args(pyocd "--target=stm32h743zitx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts index f0af8ef11b843..e774b728c213d 100644 --- a/boards/st/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/st/nucleo_h743zi/nucleo_h743zi.dts @@ -110,13 +110,6 @@ d3ppre = <2>; }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi index 0d39ecdd33f1f..5cd745344e19a 100644 --- a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi @@ -37,4 +37,4 @@ arduino_i2c: &i2c1 {}; -arduino_serial: &lpuart1 {}; +arduino_serial: &uart8 {}; diff --git a/boards/st/nucleo_h745zi_q/board.cmake b/boards/st/nucleo_h745zi_q/board.cmake index 6c604e1385e26..00797ab426f87 100644 --- a/boards/st/nucleo_h745zi_q/board.cmake +++ b/boards/st/nucleo_h745zi_q/board.cmake @@ -12,5 +12,5 @@ endif() # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts index 75cf85bb69a15..bca10943e9c66 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts @@ -74,13 +74,6 @@ clock-frequency = ; }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi index 8af74373f23fa..c9ac7b3e8c7ef 100644 --- a/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi @@ -37,4 +37,3 @@ arduino_i2c: &i2c1 {}; arduino_spi: &spi1 {}; -arduino_serial: &lpuart1 {}; diff --git a/boards/st/nucleo_h753zi/board.cmake b/boards/st/nucleo_h753zi/board.cmake index d4a4d56a6f757..aa65b88b81ab0 100644 --- a/boards/st/nucleo_h753zi/board.cmake +++ b/boards/st/nucleo_h753zi/board.cmake @@ -7,5 +7,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts index 289342f2eda75..e411028579b45 100644 --- a/boards/st/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/st/nucleo_h753zi/nucleo_h753zi.dts @@ -54,7 +54,6 @@ }; aliases { - die-temp0 = &die_temp; led0 = &green_led; led1 = &yellow_led; pwm-led0 = &red_pwm_led; @@ -108,13 +107,6 @@ d3ppre = <2>; }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; @@ -160,18 +152,6 @@ zephyr_udc0: &usbotg_fs { status = "okay"; }; -&adc3 { - pinctrl-0 = <&adc3_inp5_pf3>; - pinctrl-names = "default"; - st,adc-clock-source = "SYNC"; - st,adc-prescaler = <4>; - status = "okay"; -}; - -&die_temp { - status = "okay"; -}; - &rng { status = "okay"; }; diff --git a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi index 1b1bf1877932f..aaa4cec058326 100644 --- a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi @@ -37,4 +37,4 @@ arduino_i2c: &i2c1 {}; -arduino_serial: &lpuart1 {}; +arduino_serial: &uart8 {}; diff --git a/boards/st/nucleo_h755zi_q/board.cmake b/boards/st/nucleo_h755zi_q/board.cmake index bc87412503ab6..e703f23d14712 100644 --- a/boards/st/nucleo_h755zi_q/board.cmake +++ b/boards/st/nucleo_h755zi_q/board.cmake @@ -11,5 +11,5 @@ endif() # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts index 6f1ef44730d01..bda0b08c27448 100644 --- a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts @@ -92,13 +92,6 @@ clock-frequency = ; }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi index d56a9f4e58557..53ea27130430e 100644 --- a/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi @@ -34,5 +34,3 @@ <21 0 &gpiob 8 0>; /* D15 */ }; }; - -arduino_serial: &lpuart1 {}; diff --git a/boards/st/nucleo_h7a3zi_q/board.cmake b/boards/st/nucleo_h7a3zi_q/board.cmake index 1b4afb944a61a..e0cb9e0aac870 100644 --- a/boards/st/nucleo_h7a3zi_q/board.cmake +++ b/boards/st/nucleo_h7a3zi_q/board.cmake @@ -7,5 +7,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts index 96c7a1b612bed..71ee9ccf017b5 100644 --- a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts +++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts @@ -91,13 +91,6 @@ d3ppre = <2>; }; -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pb6 &lpuart1_rx_pb7>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - &usart3 { pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h7s3l8/board.cmake b/boards/st/nucleo_h7s3l8/board.cmake index e0005d1dc8255..6c18b45b35edc 100644 --- a/boards/st/nucleo_h7s3l8/board.cmake +++ b/boards/st/nucleo_h7s3l8/board.cmake @@ -7,4 +7,4 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts index 6d2b9ef80bf5f..e5d817bea578d 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts @@ -85,19 +85,6 @@ status = "okay"; }; -/* PLL2 for clocking the xspi peripheral */ -&pll2 { - div-m = <12>; - mul-n = <200>; - div-p = <2>; - div-q = <2>; - div-r = <2>; - div-s = <2>; - div-t = <2>; - clocks = <&clk_hse>; - status = "okay"; -}; - &rcc { clocks = <&pll>; clock-frequency = ; @@ -152,62 +139,3 @@ status = "okay"; clock-frequency = ; }; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set the partitions with first MB to make use of the whole Bank1 */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - }; -}; - -&xspi2 { - pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 - &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 - &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 - &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 - &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 - &xspim_p2_dqs0_pn0>; - pinctrl-names = "default"; - - status = "okay"; - - mx25uw25645: xspi-nor-flash@0 { - compatible = "st,stm32-xspi-nor"; - reg = <0>; - size = ; /* 256Mbits */ - ospi-max-frequency = ; - spi-bus-width = ; - data-rate = ; - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x00000000 DT_SIZE_K(512)>; - }; - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x0080000 DT_SIZE_K(512)>; - }; - scratch_partition: partition@100000 { - label = "image-scratch"; - reg = <0x00100000 DT_SIZE_K(64)>; - }; - storage_partition: partition@110000 { - label = "storage"; - reg = <0x00110000 DT_SIZE_K(64)>; - }; - }; - }; -}; diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml index 4601260e27a52..f7b72a70d9237 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml @@ -12,5 +12,4 @@ supported: - watchdog - entropy - adc - - octospi vendor: st diff --git a/boards/st/nucleo_l011k4/board.cmake b/boards/st/nucleo_l011k4/board.cmake index e6e48d0da4150..ed2af84d31edd 100644 --- a/boards/st/nucleo_l011k4/board.cmake +++ b/boards/st/nucleo_l011k4/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L011K4" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l031k6/board.cmake b/boards/st/nucleo_l031k6/board.cmake index 6bce6845dc985..90c28655ceb48 100644 --- a/boards/st/nucleo_l031k6/board.cmake +++ b/boards/st/nucleo_l031k6/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L031K6" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l053r8/board.cmake b/boards/st/nucleo_l053r8/board.cmake index 6ece30ff63467..f6b83f8387603 100644 --- a/boards/st/nucleo_l053r8/board.cmake +++ b/boards/st/nucleo_l053r8/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L053R8" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l073rz/board.cmake b/boards/st/nucleo_l073rz/board.cmake index d9a28a2a5870f..bd12f7d933b45 100644 --- a/boards/st/nucleo_l073rz/board.cmake +++ b/boards/st/nucleo_l073rz/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L073RZ" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l152re/board.cmake b/boards/st/nucleo_l152re/board.cmake index daa77274ae172..716846e4923c4 100644 --- a/boards/st/nucleo_l152re/board.cmake +++ b/boards/st/nucleo_l152re/board.cmake @@ -5,4 +5,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_l412rb_p/board.cmake b/boards/st/nucleo_l412rb_p/board.cmake index b012ee275ffbc..0ee007da3c5e8 100644 --- a/boards/st/nucleo_l412rb_p/board.cmake +++ b/boards/st/nucleo_l412rb_p/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L412RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l432kc/board.cmake b/boards/st/nucleo_l432kc/board.cmake index b7b34dd5ac451..20c7aec7e062f 100644 --- a/boards/st/nucleo_l432kc/board.cmake +++ b/boards/st/nucleo_l432kc/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L432KC" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l433rc_p/board.cmake b/boards/st/nucleo_l433rc_p/board.cmake index 25dedfd7a4d02..cabd763429f90 100644 --- a/boards/st/nucleo_l433rc_p/board.cmake +++ b/boards/st/nucleo_l433rc_p/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L433RC" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l452re/board.cmake b/boards/st/nucleo_l452re/board.cmake index c5c4870747c18..61fc4681587b0 100644 --- a/boards/st/nucleo_l452re/board.cmake +++ b/boards/st/nucleo_l452re/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L452RE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l476rg/board.cmake b/boards/st/nucleo_l476rg/board.cmake index 416dde58a05df..8dd9a43847845 100644 --- a/boards/st/nucleo_l476rg/board.cmake +++ b/boards/st/nucleo_l476rg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L476RG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l496zg/board.cmake b/boards/st/nucleo_l496zg/board.cmake index 80e172d1986c3..eab553680b02e 100644 --- a/boards/st/nucleo_l496zg/board.cmake +++ b/boards/st/nucleo_l496zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L496ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l4a6zg/board.cmake b/boards/st/nucleo_l4a6zg/board.cmake index be21d7cfcc453..293f2736a0701 100644 --- a/boards/st/nucleo_l4a6zg/board.cmake +++ b/boards/st/nucleo_l4a6zg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L4A6ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l4r5zi/board.cmake b/boards/st/nucleo_l4r5zi/board.cmake index 9a6daaf352455..2d7ce04b87ec9 100644 --- a/boards/st/nucleo_l4r5zi/board.cmake +++ b/boards/st/nucleo_l4r5zi/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L4R5ZI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l552ze_q/board.cmake b/boards/st/nucleo_l552ze_q/board.cmake index 5d9c266860f74..4308af48306ba 100644 --- a/boards/st/nucleo_l552ze_q/board.cmake +++ b/boards/st/nucleo_l552ze_q/board.cmake @@ -24,4 +24,4 @@ board_runner_args(pyocd "--target=stm32l552zetxq") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi index 4232538817fdb..b249d2ab84772 100644 --- a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi +++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi @@ -235,10 +235,9 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - mx25um51245g: ospi-nor-flash@0 { + mx25um51245g: ospi-nor-flash@70000000 { compatible = "st,stm32-xspi-nor"; - reg = <0>; - size = ; /* 512 Mbits */ + reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; diff --git a/boards/st/nucleo_u083rc/board.cmake b/boards/st/nucleo_u083rc/board.cmake index 0a9ce749ed05f..2195ba62540ed 100644 --- a/boards/st/nucleo_u083rc/board.cmake +++ b/boards/st/nucleo_u083rc/board.cmake @@ -2,8 +2,6 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32u083rctx") -board_runner_args(pyocd "--flash-opt=-O reset_type=hw") -board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") board_runner_args(jlink "--device=STM32U083RC" "--reset-after-load") diff --git a/boards/st/nucleo_u575zi_q/board.cmake b/boards/st/nucleo_u575zi_q/board.cmake index 14b6e98db674b..17127a40101b4 100644 --- a/boards/st/nucleo_u575zi_q/board.cmake +++ b/boards/st/nucleo_u575zi_q/board.cmake @@ -11,6 +11,6 @@ board_runner_args(jlink "--device=STM32U575ZI" "--reset-after-load") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_u5a5zj_q/board.cmake b/boards/st/nucleo_u5a5zj_q/board.cmake index e846f79f3817b..eeef658184f36 100644 --- a/boards/st/nucleo_u5a5zj_q/board.cmake +++ b/boards/st/nucleo_u5a5zj_q/board.cmake @@ -11,6 +11,6 @@ board_runner_args(jlink "--device=STM32U5A5ZJ" "--reset-after-load") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_wb05kz/board.cmake b/boards/st/nucleo_wb05kz/board.cmake index c7de0154aa783..84605805bbab8 100644 --- a/boards/st/nucleo_wb05kz/board.cmake +++ b/boards/st/nucleo_wb05kz/board.cmake @@ -5,5 +5,5 @@ board_runner_args(pyocd "--target=stm32wb05kzvx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_wb07cc/board.cmake b/boards/st/nucleo_wb07cc/board.cmake index ec142ba8afd10..d68dc28916557 100644 --- a/boards/st/nucleo_wb07cc/board.cmake +++ b/boards/st/nucleo_wb07cc/board.cmake @@ -5,5 +5,5 @@ board_runner_args(pyocd "--target=stm32wb07ccvx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_wb55rg/board.cmake b/boards/st/nucleo_wb55rg/board.cmake index ecde7d77aa487..13002e7ade41f 100644 --- a/boards/st/nucleo_wb55rg/board.cmake +++ b/boards/st/nucleo_wb55rg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(pyocd "--target=stm32wb55rgvx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_wba55cg/board.cmake b/boards/st/nucleo_wba55cg/board.cmake index 0c8a7e50ed109..9c612e9d0b07a 100644 --- a/boards/st/nucleo_wba55cg/board.cmake +++ b/boards/st/nucleo_wba55cg/board.cmake @@ -3,4 +3,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wba65ri/board.cmake b/boards/st/nucleo_wba65ri/board.cmake index 828d1f367ab24..5243407fcc0d1 100644 --- a/boards/st/nucleo_wba65ri/board.cmake +++ b/boards/st/nucleo_wba65ri/board.cmake @@ -3,4 +3,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi index 331817e0a4000..93c9694a6063c 100644 --- a/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi @@ -30,8 +30,8 @@ <17 0 &gpioa 7 0>, /* D11 */ <18 0 &gpioa 6 0>, /* D12 */ <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpioa 11 0>, /* D14 */ - <21 0 &gpioa 12 0>; /* D15 */ + <20 0 &gpiob 11 0>, /* D14 */ + <21 0 &gpiob 12 0>; /* D15 */ }; }; diff --git a/boards/st/nucleo_wl55jc/board.cmake b/boards/st/nucleo_wl55jc/board.cmake index daa77274ae172..716846e4923c4 100644 --- a/boards/st/nucleo_wl55jc/board.cmake +++ b/boards/st/nucleo_wl55jc/board.cmake @@ -5,4 +5,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts index 99a85f6e32c25..85f01ab2a08b9 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro.dts +++ b/boards/st/sensortile_box_pro/sensortile_box_pro.dts @@ -320,7 +320,6 @@ zephyr_udc0: &usbotg_fs { pwr-gpios = <&gpioh 10 GPIO_ACTIVE_LOW>; bus-width = <4>; clk-div = <4>; - disk-name = "SD"; }; &flash0 { diff --git a/boards/st/st25dv_mb1283_disco/board.cmake b/boards/st/st25dv_mb1283_disco/board.cmake index e1c11dddd8aa4..16ce5db67ad10 100644 --- a/boards/st/st25dv_mb1283_disco/board.cmake +++ b/boards/st/st25dv_mb1283_disco/board.cmake @@ -2,5 +2,5 @@ board_runner_args(jlink "--device=STM32F405RG" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/steval_fcu001v1/board.cmake b/boards/st/steval_fcu001v1/board.cmake index d2cac8292e158..79f93bd9e6de1 100644 --- a/boards/st/steval_fcu001v1/board.cmake +++ b/boards/st/steval_fcu001v1/board.cmake @@ -2,7 +2,7 @@ board_runner_args(jlink "--device=STM32F401CC" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/steval_stwinbx1/board.cmake b/boards/st/steval_stwinbx1/board.cmake index d11c7565bfc96..1335413cee7cf 100644 --- a/boards/st/steval_stwinbx1/board.cmake +++ b/boards/st/steval_stwinbx1/board.cmake @@ -16,4 +16,4 @@ board_runner_args(openocd "--no-halt") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/steval_stwinbx1/steval_stwinbx1.dts b/boards/st/steval_stwinbx1/steval_stwinbx1.dts index 5ab30c62f02ae..c9ef1b4299bc4 100644 --- a/boards/st/steval_stwinbx1/steval_stwinbx1.dts +++ b/boards/st/steval_stwinbx1/steval_stwinbx1.dts @@ -294,7 +294,6 @@ zephyr_udc0: &usbotg_fs { cd-gpios = <&gpiog 1 GPIO_ACTIVE_LOW>; bus-width = <4>; clk-div = <4>; - disk-name = "SD"; }; &flash0 { diff --git a/boards/st/stm3210c_eval/board.cmake b/boards/st/stm3210c_eval/board.cmake index 47550f8c812f5..dace1b1db63b9 100644 --- a/boards/st/stm3210c_eval/board.cmake +++ b/boards/st/stm3210c_eval/board.cmake @@ -2,5 +2,5 @@ board_runner_args(jlink "--device=STM32F107VC" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32373c_eval/board.cmake b/boards/st/stm32373c_eval/board.cmake index b6a443b6bc3de..c4303e2c4811d 100644 --- a/boards/st/stm32373c_eval/board.cmake +++ b/boards/st/stm32373c_eval/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F373VC" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f072_eval/board.cmake b/boards/st/stm32f072_eval/board.cmake index 8876830a8e5a5..f49b17d83bbe4 100644 --- a/boards/st/stm32f072_eval/board.cmake +++ b/boards/st/stm32f072_eval/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F072VB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f072b_disco/board.cmake b/boards/st/stm32f072b_disco/board.cmake index f85a8e424bab5..136bd345f6afa 100644 --- a/boards/st/stm32f072b_disco/board.cmake +++ b/boards/st/stm32f072b_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F072RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f0_disco/board.cmake b/boards/st/stm32f0_disco/board.cmake index 888d731fe97d9..d36f83beb8ffd 100644 --- a/boards/st/stm32f0_disco/board.cmake +++ b/boards/st/stm32f0_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F051R8" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f3_disco/board.cmake b/boards/st/stm32f3_disco/board.cmake index b2747a7cc46f6..553a53bf9ce04 100644 --- a/boards/st/stm32f3_disco/board.cmake +++ b/boards/st/stm32f3_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F303VC" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f411e_disco/board.cmake b/boards/st/stm32f411e_disco/board.cmake index 64d7eeb27d438..b0408356c87fa 100644 --- a/boards/st/stm32f411e_disco/board.cmake +++ b/boards/st/stm32f411e_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F411VE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f412g_disco/board.cmake b/boards/st/stm32f412g_disco/board.cmake index 2aa3b0baed3a3..be8b35e82c82d 100644 --- a/boards/st/stm32f412g_disco/board.cmake +++ b/boards/st/stm32f412g_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F412ZG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f413h_disco/board.cmake b/boards/st/stm32f413h_disco/board.cmake index 60c93ad815c35..800b779a42dbc 100644 --- a/boards/st/stm32f413h_disco/board.cmake +++ b/boards/st/stm32f413h_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F413ZH" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f429i_disc1/board.cmake b/boards/st/stm32f429i_disc1/board.cmake index 836afa988e33d..9f872edd54668 100644 --- a/boards/st/stm32f429i_disc1/board.cmake +++ b/boards/st/stm32f429i_disc1/board.cmake @@ -9,6 +9,6 @@ board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/stm32f469i_disco/board.cmake b/boards/st/stm32f469i_disco/board.cmake index a71f6bc4b44d1..327c95da4fa6c 100644 --- a/boards/st/stm32f469i_disco/board.cmake +++ b/boards/st/stm32f469i_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F469NI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f469i_disco/stm32f469i_disco.dts b/boards/st/stm32f469i_disco/stm32f469i_disco.dts index c096dad9a86c6..7311417c3ce5e 100644 --- a/boards/st/stm32f469i_disco/stm32f469i_disco.dts +++ b/boards/st/stm32f469i_disco/stm32f469i_disco.dts @@ -137,5 +137,4 @@ zephyr_udc0: &usbotg_fs { &sdio_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; diff --git a/boards/st/stm32f4_disco/board.cmake b/boards/st/stm32f4_disco/board.cmake index 3788e6369a8a1..a2c5eefa38cce 100644 --- a/boards/st/stm32f4_disco/board.cmake +++ b/boards/st/stm32f4_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F407VG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f723e_disco/board.cmake b/boards/st/stm32f723e_disco/board.cmake index ed50a01ca8a5c..7a99727f26636 100644 --- a/boards/st/stm32f723e_disco/board.cmake +++ b/boards/st/stm32f723e_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F723IE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f746g_disco/board.cmake b/boards/st/stm32f746g_disco/board.cmake index 05504d0772271..968e8cfa890d5 100644 --- a/boards/st/stm32f746g_disco/board.cmake +++ b/boards/st/stm32f746g_disco/board.cmake @@ -8,5 +8,5 @@ board_runner_args(jlink "--device=STM32F746NG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts index e73decc909954..eafd8bd6be221 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/st/stm32f746g_disco/stm32f746g_disco.dts @@ -173,7 +173,6 @@ zephyr_udc0: &usbotg_fs { &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &mac { diff --git a/boards/st/stm32f7508_dk/board.cmake b/boards/st/stm32f7508_dk/board.cmake index 8565d87dc51d3..83aae9337d670 100644 --- a/boards/st/stm32f7508_dk/board.cmake +++ b/boards/st/stm32f7508_dk/board.cmake @@ -7,5 +7,5 @@ board_runner_args(jlink "--device=STM32F750N8" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts index c23629063b8b8..2add12eb8ec45 100644 --- a/boards/st/stm32f7508_dk/stm32f7508_dk.dts +++ b/boards/st/stm32f7508_dk/stm32f7508_dk.dts @@ -160,7 +160,6 @@ zephyr_udc0: &usbotg_fs { &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &mac { diff --git a/boards/st/stm32f769i_disco/board.cmake b/boards/st/stm32f769i_disco/board.cmake index ba101beac0839..6df48aa7403bf 100644 --- a/boards/st/stm32f769i_disco/board.cmake +++ b/boards/st/stm32f769i_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F769NI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts index 2a1c263c5c237..ba6837339c828 100644 --- a/boards/st/stm32f769i_disco/stm32f769i_disco.dts +++ b/boards/st/stm32f769i_disco/stm32f769i_disco.dts @@ -181,7 +181,6 @@ arduino_serial: &usart6 {}; &sdmmc2_ck_pd6 &sdmmc2_cmd_pd7>; pinctrl-names = "default"; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &quadspi { diff --git a/boards/st/stm32g0316_disco/board.cmake b/boards/st/stm32g0316_disco/board.cmake index 3b7b8e59217c7..30495593070d2 100644 --- a/boards/st/stm32g0316_disco/board.cmake +++ b/boards/st/stm32g0316_disco/board.cmake @@ -7,6 +7,6 @@ board_runner_args(jlink "--device=STM32G031J6" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h573i_dk/Kconfig.defconfig b/boards/st/stm32h573i_dk/Kconfig.defconfig index 035419a218e07..428337e59e4cf 100644 --- a/boards/st/stm32h573i_dk/Kconfig.defconfig +++ b/boards/st/stm32h573i_dk/Kconfig.defconfig @@ -21,22 +21,4 @@ config SDMMC_STM32_CLOCK_CHECK endif # DISK_DRIVER_SDMMC -if DISPLAY - -choice ST7789V_PIXEL_FORMAT - default ST7789V_BGR565 -endchoice - -# Required to enable LCD backlight -config REGULATOR - default y - -config INPUT - default y if LVGL - -config I2C_STM32_V2_TIMING - default y if INPUT - -endif # DISPLAY - endif # BOARD_STM32H573I_DK diff --git a/boards/st/stm32h573i_dk/board.cmake b/boards/st/stm32h573i_dk/board.cmake index 1ce1627e7eb74..dedf7ebcd0ae3 100644 --- a/boards/st/stm32h573i_dk/board.cmake +++ b/boards/st/stm32h573i_dk/board.cmake @@ -20,5 +20,5 @@ board_runner_args(openocd "--no-halt") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) # FIXME: official openocd runner not yet available. diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst index 9201bb7cf7e29..3bbabc2f28f63 100644 --- a/boards/st/stm32h573i_dk/doc/index.rst +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -180,16 +180,6 @@ Serial Port STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1. Default settings are 115200 8N1. -TFT LCD screen and touch panel ------------------------------- - -The TFT LCD screen and touch panel are supported for the STM32H573I-DK Discovery board. -They can be tested using :zephyr:code-sample:`lvgl` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/subsys/display/lvgl - :board: stm32h573i_dk - :goals: build Programming and Debugging ************************* diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 717f6e5c5e39e..896da6606d2b3 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -11,8 +11,6 @@ #include #include #include -#include -#include / { model = "STMicroelectronics STM32H573I DISCOVERY KIT board"; compatible = "st,stm32h573i-dk"; @@ -24,7 +22,6 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,canbus = &fdcan1; - zephyr,display = &st7789v; }; leds { @@ -56,13 +53,6 @@ }; }; - lcd_bl_ctrl { - compatible = "regulator-fixed"; - regulator-name = "LCD Backlight Driver"; - enable-gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - aliases { led0 = &blue_led_0; sw0 = &user_button; @@ -80,84 +70,6 @@ /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; - - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft3267>; - display = <&st7789v>; - invert-y; - }; -}; - -&fmc { - pinctrl-0 = <&fmc_a0_pf0 &fmc_ne1_pc7 &fmc_nwe_pd5 &fmc_noe_pd4 - &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 - &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 - &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 - &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>; - pinctrl-names = "default"; - status = "okay"; - - sram { - compatible = "st,stm32-fmc-nor-psram"; - - #address-cells = <1>; - #size-cells = <0>; - - bank@0 { - reg = <0x0>; - st,control = ; - st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>; - - fmc-mipi-dbi { - compatible = "st,stm32-fmc-mipi-dbi"; - reset-gpios = <&gpioh 13 GPIO_ACTIVE_LOW>; - power-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>; - register-select-pin = <0>; - #address-cells = <1>; - #size-cells = <0>; - - st7789v: lcd-panel@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - mipi-mode = "MIPI_DBI_MODE_8080_BUS_16_BIT"; - /* A write cycle should be 68ns */ - mipi-max-frequency = <14705882>; - width = <240>; - height = <240>; - x-offset = <0>; - y-offset = <0>; - vcom = <0x1F>; - gctrl = <0x35>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x05>; - lcm = <0x2c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 00]; - pwctrl1-param = [a4 a1]; - pvgam-param = [D0 08 11 08 0C 15 39 33 50 36 13 14 29 2D]; - nvgam-param = [D0 08 10 08 06 06 39 44 51 0B 16 14 2F 31]; - ram-param = [00 F0]; - rgb-param = [40 02 14]; - }; - }; - }; - }; }; &clk_hsi48 { @@ -207,20 +119,6 @@ status = "okay"; }; -&i2c4 { - pinctrl-0 = <&i2c4_scl_pb8 &i2c4_sda_pb9>; - pinctrl-names = "default"; - clock-frequency = ; - status = "okay"; - - ft3267: ft3267@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpiog 3 GPIO_ACTIVE_LOW>; - }; -}; - &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; @@ -375,10 +273,9 @@ status = "okay"; - mx25lm51245: ospi-nor-flash@0 { + mx25lm51245: ospi-nor-flash@90000000 { compatible = "st,stm32-xspi-nor"; - reg = <0>; - size = ; /* 512 Mbits */ + reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; @@ -404,7 +301,6 @@ &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioh 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/st/stm32h735g_disco/board.cmake b/boards/st/stm32h735g_disco/board.cmake index 1762b3e72b7d0..ef05a214927c3 100644 --- a/boards/st/stm32h735g_disco/board.cmake +++ b/boards/st/stm32h735g_disco/board.cmake @@ -8,5 +8,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts index 764d07b419c4a..06afe9fb6450b 100644 --- a/boards/st/stm32h735g_disco/stm32h735g_disco.dts +++ b/boards/st/stm32h735g_disco/stm32h735g_disco.dts @@ -163,7 +163,6 @@ &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &octospi1 { diff --git a/boards/st/stm32h745i_disco/board.cmake b/boards/st/stm32h745i_disco/board.cmake index effd920d464b0..d9453fbb53450 100644 --- a/boards/st/stm32h745i_disco/board.cmake +++ b/boards/st/stm32h745i_disco/board.cmake @@ -19,5 +19,5 @@ endif() # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h747i_disco/board.cmake b/boards/st/stm32h747i_disco/board.cmake index 145a1bf9e78a2..6b22ac5021743 100644 --- a/boards/st/stm32h747i_disco/board.cmake +++ b/boards/st/stm32h747i_disco/board.cmake @@ -21,5 +21,5 @@ endif() # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h750b_dk/board.cmake b/boards/st/stm32h750b_dk/board.cmake index 7ca52afb25fa9..479fe1abc2ebd 100644 --- a/boards/st/stm32h750b_dk/board.cmake +++ b/boards/st/stm32h750b_dk/board.cmake @@ -13,5 +13,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h757i_eval/board.cmake b/boards/st/stm32h757i_eval/board.cmake index f5a0f5f38cc71..b0a38149731a3 100644 --- a/boards/st/stm32h757i_eval/board.cmake +++ b/boards/st/stm32h757i_eval/board.cmake @@ -17,5 +17,5 @@ endif() # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts index 645c166db3cee..4640468048c5e 100644 --- a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts +++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts @@ -255,7 +255,6 @@ zephyr_udc0: &usbotg_hs { &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; - disk-name = "SD"; }; &quadspi { diff --git a/boards/st/stm32h7b3i_dk/board.cmake b/boards/st/stm32h7b3i_dk/board.cmake index 054803a1ed568..88f340c93314b 100644 --- a/boards/st/stm32h7b3i_dk/board.cmake +++ b/boards/st/stm32h7b3i_dk/board.cmake @@ -14,5 +14,5 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index c3c8efb55bbb8..c76f7b7f238f9 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -231,7 +231,6 @@ &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/st/stm32h7s78_dk/board.cmake b/boards/st/stm32h7s78_dk/board.cmake index 9de6ed63802b9..79bb6fcc70bef 100644 --- a/boards/st/stm32h7s78_dk/board.cmake +++ b/boards/st/stm32h7s78_dk/board.cmake @@ -7,4 +7,4 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) # FIXME: openocd runner not yet available. -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32h7s78_dk/doc/index.rst b/boards/st/stm32h7s78_dk/doc/index.rst index 969ab76315f9b..ae69379abdd7c 100644 --- a/boards/st/stm32h7s78_dk/doc/index.rst +++ b/boards/st/stm32h7s78_dk/doc/index.rst @@ -183,7 +183,6 @@ Default Zephyr Peripheral Mapping: - LD4 (blue) : PM3 - ADC1 channel 6 input : PF12 - USB OTG FS DM/DP : PM12/PM11 -- XSPI1 NCS/DQS0/DQS1/CLK/IO: PO0/PO2/PO3/PO4/PP0..15 System Clock ------------ diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index 4c66cb4c99791..792b48ccd8be4 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -21,13 +21,6 @@ zephyr,sram = &sram0; }; - psram: memory@90000000 { - compatible = "zephyr,memory-region"; - reg = <0x90000000 DT_SIZE_M(32)>; - zephyr,memory-region = "PSRAM"; - zephyr,memory-attr = ; - }; - leds { compatible = "gpio-leds"; green_led: led_1 { @@ -180,92 +173,6 @@ pinctrl-names = "default"; }; -&xspi1 { - pinctrl-0 = <&xspim_p1_ncs1_po0 &xspim_p1_dqs0_po2 - &xspim_p1_dqs1_po3 &xspim_p1_clk_po4 - &xspim_p1_io0_pp0 &xspim_p1_io1_pp1 &xspim_p1_io2_pp2 - &xspim_p1_io3_pp3 &xspim_p1_io4_pp4 &xspim_p1_io5_pp5 - &xspim_p1_io6_pp6 &xspim_p1_io7_pp7 &xspim_p1_io8_pp8 - &xspim_p1_io9_pp9 &xspim_p1_io10_pp10 &xspim_p1_io11_pp11 - &xspim_p1_io12_pp12 &xspim_p1_io13_pp13 &xspim_p1_io14_pp14 - &xspim_p1_io15_pp15>; - - pinctrl-names = "default"; - status = "okay"; - - memc: aps256xxn-obr@0 { - compatible = "st,stm32-xspi-psram"; - reg = <0>; - size = ; /* 256 Mbits */ - max-frequency = ; - fixed-latency; - io-x16-mode; - read-latency = <4>; - write-latency = <1>; - burst-length = <0>; - status = "okay"; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set the partitions with first MB to make use of the whole Bank1 */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - }; -}; - -&xspi2 { - pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 - &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 - &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 - &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 - &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 - &xspim_p2_dqs0_pn0>; - pinctrl-names = "default"; - - status = "okay"; - - mx66uw1g45: xspi-nor-flash@0 { - compatible = "st,stm32-xspi-nor"; - reg = <0>; - size = ; /* 1 Gbits */ - ospi-max-frequency = ; - spi-bus-width = ; - data-rate = ; - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x00000000 DT_SIZE_K(512)>; - }; - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x0080000 DT_SIZE_K(512)>; - }; - scratch_partition: partition@100000 { - label = "image-scratch"; - reg = <0x00100000 DT_SIZE_K(64)>; - }; - storage_partition: partition@110000 { - label = "storage"; - reg = <0x00110000 DT_SIZE_K(64)>; - }; - }; - }; -}; - &die_temp { status = "okay"; }; diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml index 6e9cc6c401afd..7e14a410259ff 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml @@ -13,7 +13,6 @@ supported: - watchdog - entropy - adc - - octospi + - usb_device - usbd - - memc vendor: st diff --git a/boards/st/stm32l1_disco/board.cmake b/boards/st/stm32l1_disco/board.cmake index 502c057f7c0fc..c8967fe8139c3 100644 --- a/boards/st/stm32l1_disco/board.cmake +++ b/boards/st/stm32l1_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L151RB" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l476g_disco/board.cmake b/boards/st/stm32l476g_disco/board.cmake index 8b833a9e8ccb2..76b5877ddfe07 100644 --- a/boards/st/stm32l476g_disco/board.cmake +++ b/boards/st/stm32l476g_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L476VG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l496g_disco/board.cmake b/boards/st/stm32l496g_disco/board.cmake index 3f7e680f9bc37..b6f4be86151e1 100644 --- a/boards/st/stm32l496g_disco/board.cmake +++ b/boards/st/stm32l496g_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L496AG" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts index 7fd2f89ab9a34..4a942a5ab066c 100644 --- a/boards/st/stm32l496g_disco/stm32l496g_disco.dts +++ b/boards/st/stm32l496g_disco/stm32l496g_disco.dts @@ -158,7 +158,6 @@ &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/st/stm32l4r9i_disco/board.cmake b/boards/st/stm32l4r9i_disco/board.cmake index d6e0951248575..ea87b4f95481f 100644 --- a/boards/st/stm32l4r9i_disco/board.cmake +++ b/boards/st/stm32l4r9i_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32L4R9AI" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts index 94b46040ef755..2e6175dd171e0 100644 --- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts @@ -220,7 +220,6 @@ &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; - disk-name = "SD"; }; &adc1 { diff --git a/boards/st/stm32l562e_dk/board.cmake b/boards/st/stm32l562e_dk/board.cmake index da9e4b1709257..e3f5f878df228 100644 --- a/boards/st/stm32l562e_dk/board.cmake +++ b/boards/st/stm32l562e_dk/board.cmake @@ -20,5 +20,5 @@ board_runner_args(jlink "--device=STM32L562QE" "--speed=4000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi index 3991e360bab55..47c678db786e5 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi @@ -314,7 +314,7 @@ zephyr_udc0: &usb { &sdmmc1 { status = "okay"; - disk-name = "SD"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 &sdmmc1_d2_pc10 diff --git a/boards/st/stm32mp135f_dk/board.cmake b/boards/st/stm32mp135f_dk/board.cmake index 8dbfad9db3c30..af21b18031704 100644 --- a/boards/st/stm32mp135f_dk/board.cmake +++ b/boards/st/stm32mp135f_dk/board.cmake @@ -1,6 +1,6 @@ # Copyright (c) 2025 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg") diff --git a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts index b5814fca00a70..5d2f343835568 100644 --- a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts +++ b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts @@ -8,7 +8,6 @@ #include #include -#include "zephyr/dt-bindings/display/panel.h" #include / { @@ -20,7 +19,6 @@ zephyr,sram = &ddr_data; zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,display = <dc; }; gpio_keys { @@ -37,24 +35,14 @@ compatible = "gpio-leds"; blue_led_1: led_1 { - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; label = "LD3"; }; red_led_2: led_2 { - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; label = "LD4"; }; - - green_led_3: led_3 { - gpios = <&mcp23017 14 GPIO_ACTIVE_HIGH>; - label = "LD7"; - }; - - orange_led_4: led_4 { - gpios = <&mcp23017 15 GPIO_ACTIVE_HIGH>; - label = "LD6"; - }; }; aliases { @@ -85,7 +73,7 @@ div-m = <2>; mul-n = <83>; div-p = <1>; - fracn = <2730>; + frac-v = <2730>; status = "okay"; }; @@ -103,64 +91,3 @@ current-speed = <115200>; status = "okay"; }; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_scl_pd12 &i2c1_sda_pe8>; - status = "okay"; - - mcp23017: pinctrl@21 { - compatible = "microchip,mcp23017"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_scl_pe15 &i2c4_sda_pb9>; - status = "okay"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_scl_pd1 &i2c5_sda_ph6>; - status = "okay"; -}; - -<dc { - pinctrl-0 = <<dc_r2_pg7 <dc_r3_pb12 - <dc_r4_pd14 <dc_r5_pe7 <dc_r6_pe13 <dc_r7_pe9 - <dc_g2_ph13 <dc_g3_pf3 - <dc_g4_pd5 <dc_g5_pg0 <dc_g6_pc7 <dc_g7_pa15 - <dc_b2_pd10 <dc_b3_pf2 - <dc_b4_ph14 <dc_b5_pe0 <dc_b6_pb6 <dc_b7_pf1 - <dc_de_ph9 <dc_clk_pd9 <dc_hsync_pc6 <dc_vsync_pg4>; - pinctrl-names = "default"; - disp-on-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; - bl-ctrl-gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; - - status = "okay"; - - width = <480>; - height = <272>; - pixel-format = ; - display-timings { - compatible = "zephyr,panel-timing"; - de-active = <0>; - pixelclk-active = <0>; - hsync-active = <0>; - vsync-active = <0>; - hsync-len = <41>; - vsync-len = <10>; - hback-porch = <13>; - vback-porch = <2>; - hfront-porch = <32>; - vfront-porch = <2>; - }; - def-back-color-red = <0xFF>; - def-back-color-green = <0xFF>; - def-back-color-blue = <0xFF>; -}; diff --git a/boards/st/stm32mp157c_dk2/board.cmake b/boards/st/stm32mp157c_dk2/board.cmake index 50b0e205692ae..4c4c6aacb5eb2 100644 --- a/boards/st/stm32mp157c_dk2/board.cmake +++ b/boards/st/stm32mp157c_dk2/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg") diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi index 310ae12619933..48ee7e4a22aad 100644 --- a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi +++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi @@ -202,7 +202,6 @@ bus-width = <4>; cd-gpios = <&gpion 12 GPIO_ACTIVE_HIGH>; pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>; - disk-name = "SD"; }; &spi5 { @@ -250,11 +249,9 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - memc: aps256xxn_obr: memory@0 { + memc: aps256xxn_obr: memory@90000000 { compatible = "st,stm32-xspi-psram"; - reg = <0>; - size = ; /* 256 Mbits */ - max-frequency = ; + reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */ fixed-latency; io-x16-mode; read-latency = <4>; @@ -275,10 +272,9 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - mx66uw1g45g: ospi-nor-flash@0 { + mx66uw1g45g: ospi-nor-flash@70000000 { compatible = "st,stm32-xspi-nor"; - reg = <0>; - size = ; /* 1Gbits */ + reg = <0x70000000 DT_SIZE_M(128)>; /* 1 Gbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; diff --git a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi index bb444e44c2b85..f2b85867b89ec 100644 --- a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi @@ -26,7 +26,7 @@ <13 0 &gpioa 8 0>, /* D7 */ <14 0 &gpioa 9 0>, /* D8 */ <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ + <16 0 &gpiob 6 0>, /* D10 */ <17 0 &gpioa 7 0>, /* D11 */ <18 0 &gpioa 6 0>, /* D12 */ <19 0 &gpioa 5 0>, /* D13 */ diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts index 6f9c959729be2..c5cbfb93a2e07 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.dts +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts @@ -38,15 +38,15 @@ }; }; -&usart2 { - pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; current-speed = <115200>; status = "okay"; }; -&usart3 { - pinctrl-0 = <&usart3_tx_pc4 &usart3_rx_pc5>; +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; pinctrl-names = "default"; current-speed = <115200>; status = "okay"; @@ -104,13 +104,6 @@ clock-frequency = ; }; -&spi3 { - pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pc10 - &spi3_miso_pc11 &spi3_mosi_pc12>; - pinctrl-names = "default"; - status = "okay"; -}; - &timers1 { st,prescaler = <10000>; status = "okay"; diff --git a/boards/st/stm32u5a9j_dk/board.cmake b/boards/st/stm32u5a9j_dk/board.cmake index de8a4cb955304..5bb38a1d9c659 100644 --- a/boards/st/stm32u5a9j_dk/board.cmake +++ b/boards/st/stm32u5a9j_dk/board.cmake @@ -10,4 +10,4 @@ board_runner_args(openocd "--no-halt") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts index 96726131f641a..5696253f93cfa 100644 --- a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts @@ -198,7 +198,6 @@ uart0: &usart3 { &sdmmc1_d6_pc6 &sdmmc1_d7_pc7 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/st/stm32u5g9j_dk1/Kconfig.stm32u5g9j_dk1 b/boards/st/stm32u5g9j_dk1/Kconfig.stm32u5g9j_dk1 deleted file mode 100644 index 4c4a125a1295c..0000000000000 --- a/boards/st/stm32u5g9j_dk1/Kconfig.stm32u5g9j_dk1 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32U5G9J_DK1 - select SOC_STM32U5G9XX diff --git a/boards/st/stm32u5g9j_dk1/board.cmake b/boards/st/stm32u5g9j_dk1/board.cmake deleted file mode 100644 index de8a4cb955304..0000000000000 --- a/boards/st/stm32u5g9j_dk1/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -# keep first -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") - -board_runner_args(openocd "--tcl-port=6666") -board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") -board_runner_args(openocd "--no-halt") - -# keep first -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) diff --git a/boards/st/stm32u5g9j_dk1/board.yml b/boards/st/stm32u5g9j_dk1/board.yml deleted file mode 100644 index 18fa6147d34f2..0000000000000 --- a/boards/st/stm32u5g9j_dk1/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: stm32u5g9j_dk1 - full_name: STM32U5G9J Discovery Kit 1 - vendor: st - socs: - - name: stm32u5g9xx diff --git a/boards/st/stm32u5g9j_dk1/doc/img/stm32u5g9j_dk1.webp b/boards/st/stm32u5g9j_dk1/doc/img/stm32u5g9j_dk1.webp deleted file mode 100644 index 3e1c52da1bdac..0000000000000 Binary files a/boards/st/stm32u5g9j_dk1/doc/img/stm32u5g9j_dk1.webp and /dev/null differ diff --git a/boards/st/stm32u5g9j_dk1/doc/index.rst b/boards/st/stm32u5g9j_dk1/doc/index.rst deleted file mode 100644 index acf94a5f13732..0000000000000 --- a/boards/st/stm32u5g9j_dk1/doc/index.rst +++ /dev/null @@ -1,162 +0,0 @@ -.. zephyr:board:: stm32u5g9j_dk1 - -Overview -******** - -The STM32U5G9J-DK1 Discovery kit is a complete demonstration and development -platform for the STM32U5G9NJH6Q microcontroller, featuring an Arm |reg| Cortex |reg|-M33 -core with Arm |reg| TrustZone |reg|. - -Leveraging the innovative ultra-low-power oriented features, 3 Mbytes of -embedded SRAM, 4 Mbytes of embedded flash memory, and rich graphics features, -the STM32U5G9J-DK1 Discovery kit enables users to easily prototype applications -with state-of-the-art energy efficiency, as well as providing stunning and -optimized graphics rendering with the support of the 2.5D NeoChrom Accelerator, -Chrom-ART Accelerator, and Chrom-GRCâ„¢ MMU. - -The full range of hardware features available on the board helps users to enhance -their application development by an evaluation of all the peripherals such as a -2.47-inch RGB 480 x 480 pixels TFT round LCD module with MIPI DSI |reg| interface and -capacitive touch panel, USB Type-C |reg| HS, Octo-SPI flash memory device, Hexadeca-SPI -PSRAM memory device, eMMC flash memory device, Time-of-Flight and gesture detection -sensor, temperature sensor, 20-pin audio MEMS connector, and two 2.54 mm pitch -double-row flexible expansion connectors for easy prototyping with daughterboards -for specific applications (USART, LPUART, two SPIs, SAI, three I2C, SDMMC, ADCs, -timers, and GPIOs). - -The STM32U5G9J-DK1 Discovery kits integrate an STLINK-V3E embedded in-circuit -debugger and programmer for the STM32 microcontroller with a USB Virtual COM port -bridge and comes with the STM32CubeU5 MCU Package, which provides an STM32 -comprehensive software HAL library as well as various software. - -More information about the board can be found at the `STM32U5G9J-DK1 website`_. -More information about STM32U5A9NJH6Q can be found here: - -- `STM32U5G9NJ on www.st.com`_ -- `STM32U5 Series reference manual`_ -- `STM32U5Gxxx datasheet`_ - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Pin Mapping -=========== - -For more details please refer to `STM32U5G9J-DK1 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- LD3 (GREEN) : PE0 -- LD4 (RED) : PE1 -- User Button: PC13 -- USART_3 TX/RX : PB10/PB11 -- LPUART_1 TX/RX : PG7/PG8 -- I2C1 SCL/SDA : PG14/PG13 -- I2C2 SCL/SDA : PF1/PF0 -- I2C6 SCL/SDA : PD1/PD0 -- SPI2 SCK/MISO/MOSI/CS : PB13/PD3/PD4/PB12 -- SPI3 SCK/MISO/MOSI/CS : PG9/PG10/PG11/PG15 -- ADC1 : channel5 PA0, channel14 PC5 -- ADC2 : channel9 PA4 -- ADC4 : channel5 PF14 - -System Clock -============ - -The STM32U5G9J-DK1 Discovery kit relies on an HSE oscillator (16 MHz crystal) -and an LSE oscillator (32.768 kHz crystal) as clock references. -Using the HSE (instead of HSI) is mandatory to manage the DSI interface for -the LCD module and the USB high-speed interface. - -Serial Port -=========== - -The STM32U5G9J Discovery kit has up to 4 USARTs, 2 UARTs, and 1 LPUART. -The Zephyr console output is assigned to USART1 is which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. - - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -STM32U5G9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash and debug the board using various tools. - -Flashing -======== - -The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, -so its :ref:`installation ` is required. - -Alternatively, OpenOCD can also be used to flash the board using -the ``--runner`` (or ``-r``) option: - -.. code-block:: console - - $ west flash --runner openocd - -Flashing an application to STM32U5G9J_DK ----------------------------------------- - -Connect the STM32U5G9J Discovery board to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 -b 115200 - -Then, build and flash in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32u5g9j_dk1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32u5g9j_dk1 - -Debugging -========= - -Default debugger for this board is OpenOCD. It could be used in the usual way -with "west debug" command. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32u5g9j_dk1 - :goals: debug - - -.. _STM32U5G9J-DK1 website: - https://www.st.com/en/evaluation-tools/stm32u5g9j-dk1.html - -.. _STM32U5G9J-DK1 board User Manual: - https://www.st.com/resource/en/user_manual/um2967-discovery-kits-with-stm32u5x9nj-mcus-stmicroelectronics.pdf - -.. _STM32U5G9NJ on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u5g9nj.html - -.. _STM32U5 Series reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32U5Gxxx datasheet: - https://www.st.com/resource/en/datasheet/stm32u5g9nj.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STM32U5G9J_DK1 board schematics: - https://www.st.com/resource/en/schematic_pack/mb1829-u5a9njq-b01-schematic.pdf diff --git a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts b/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts deleted file mode 100644 index 0a8ae6ed9c3ee..0000000000000 --- a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2025 Charles Dias - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "STMicroelectronics STM32U5G9J DISCOVERY KIT board"; - compatible = "st,stm32u5g9j-dk1"; - - chosen { - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - - green_led_0: led_3 { - gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; - label = "User LD3"; - }; - - red_led_0: led_4 { - gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>; - label = "User LD4"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button: button_0 { - label = "User"; - gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - zephyr,code = ; - }; - }; - - dsi_lcd_qsh_030: connector_dsi_lcd { - compatible = "st,dsi-lcd-qsh-030"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <4 0 &gpioe 8 0>, /* TOUCH_INT */ - <22 0 &gpiod 8 0>, /* SPI chip SEL */ - <24 0 &gpiob 13 0>, /* SPI CLK */ - <26 0 &gpiod 4 0>, /* SPI MOSI */ - <28 0 &gpiod 11 0>, /* SPI DCX */ - <35 0 &gpioe 5 0>, /* SCLK/MCLK */ - <37 0 &gpioe 4 0>, /* LRCLK */ - <40 0 &gpioh 4 0>, /* I2C5_SDA */ - <43 0 &gpioi 7 0>, /* SWIRE */ - <44 0 &gpioh 5 0>, /* I2C5_SCL */ - <49 0 &gpiof 11 0>, /* DSI_TE */ - <53 0 &gpioi 6 0>, /* LCD_BL_CTRL */ - <57 0 &gpiod 5 0>; /* DSI_RESET */ - }; - - aliases { - led0 = &green_led_0; - led1 = &red_led_0; - sw0 = &user_button; - sdhc0 = &sdmmc1; - watchdog0 = &iwdg; - die-temp0 = &die_temp; - volt-sensor0 = &vref1; - volt-sensor1 = &vbat4; - }; -}; - -&clk_hsi48 { - status = "okay"; -}; - -&clk_hse { - clock-frequency = ; - status = "okay"; -}; - -&clk_msis { - status = "okay"; - msi-range = <4>; /* 4MHz (reset value) */ - msi-pll-mode; -}; - -&clk_lse { - status = "okay"; -}; - -&pll1 { - div-m = <1>; - mul-n = <80>; - div-p = <2>; - div-q = <2>; - div-r = <2>; - clocks = <&clk_msis>; - status = "okay"; -}; - -&rcc { - clocks = <&pll1>; - clock-frequency = ; - ahb-prescaler = <1>; - apb1-prescaler = <1>; - apb2-prescaler = <1>; - apb3-prescaler = <1>; -}; - -&usart1 { - pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&usart3 { - pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&lpuart1 { - pinctrl-0 = <&lpuart1_tx_pg7 &lpuart1_rx_pg8>; - pinctrl-names = "default"; - current-speed = <9600>; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_scl_pg14 &i2c1_sda_pg13>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; - -&i2c6 { - pinctrl-0 = <&i2c6_scl_pd1 &i2c6_sda_pd0>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; - -&spi2 { - pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pd3 &spi2_mosi_pd4>; - pinctrl-names = "default"; - cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - status = "okay"; -}; - -&spi3 { - pinctrl-0 = <&spi3_sck_pg9 &spi3_miso_pg10 &spi3_mosi_pg11>; - pinctrl-names = "default"; - cs-gpios = <&gpiog 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - status = "okay"; -}; - -&timers1 { - st,prescaler = <1>; - status = "okay"; - - pwm1: pwm { - status = "okay"; - pinctrl-0 = <&tim1_ch2_pe11>; - pinctrl-names = "default"; - }; -}; - -&timers2 { - st,prescaler = <1>; - status = "okay"; - - pwm2: pwm { - status = "okay"; - pinctrl-0 = <&tim2_ch4_pa3>; - pinctrl-names = "default"; - }; -}; - -/* Connected to onboard 4-Gbyte eMMC flash memory */ -&sdmmc1 { - pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 - &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 - &sdmmc1_d4_pb8 &sdmmc1_d5_pb9 - &sdmmc1_d6_pc6 &sdmmc1_d7_pc7 - &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; - pinctrl-names = "default"; - disk-name = "SD"; - status = "okay"; -}; - -&adc1 { - pinctrl-0 = <&adc1_in5_pa0 &adc1_in14_pc5>; - pinctrl-names = "default"; - st,adc-clock-source = "ASYNC"; - st,adc-prescaler = <1>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - channel@5 { - reg = <0x5>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <14>; - }; - - channel@e { - reg = <0xe>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <14>; - }; -}; - -&adc4 { - pinctrl-0 = <&adc4_in5_pf14>; - pinctrl-names = "default"; - st,adc-clock-source = "ASYNC"; - st,adc-prescaler = <1>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - channel@5 { - reg = <0x5>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; -}; - -zephyr_udc0: &usbotg_hs { - pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; - pinctrl-names = "default"; - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * Following flash partition is dedicated to the use of bootloader - */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 DT_SIZE_K(1952)>; - }; - - slot1_partition: partition@1f8000 { - label = "image-1"; - reg = <0x001f8000 DT_SIZE_K(1960)>; - }; - - storage_partition: partition@3e2000 { - label = "storage"; - reg = <0x003e2000 DT_SIZE_K(120)>; - }; - }; -}; - -&rtc { - clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>, - <&rcc STM32_SRC_LSE RTC_SEL(1)>; - status = "okay"; -}; - -&iwdg { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&die_temp { - status = "okay"; -}; - -&vref1 { - status = "okay"; -}; - -&vbat4 { - status = "okay"; -}; diff --git a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.yaml b/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.yaml deleted file mode 100644 index 8b86655f32169..0000000000000 --- a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.yaml +++ /dev/null @@ -1,26 +0,0 @@ -identifier: stm32u5g9j_dk1 -name: ST STM32U5G9J-DK1 Discovery Kit -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - led - - button - - adc - - uart - - usart - - lpuart - - watchdog - - spi - - i2c - - flash - - sdmmc - - timer - - rng - - rtc -ram: 3072 -flash: 4096 -vendor: st diff --git a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1_defconfig b/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1_defconfig deleted file mode 100644 index 163131eaaf97f..0000000000000 --- a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2025 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable serial -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/st/stm32u5g9j_dk1/support/openocd.cfg b/boards/st/stm32u5g9j_dk1/support/openocd.cfg deleted file mode 100644 index 75b6eb3438273..0000000000000 --- a/boards/st/stm32u5g9j_dk1/support/openocd.cfg +++ /dev/null @@ -1,46 +0,0 @@ -source [find interface/stlink-dap.cfg] - -set WORKAREASIZE 0x8000 - -transport select "dapdirect_swd" - -set CHIPNAME STM32U5G9NJHxQ -set BOARDNAME STM32U5G9J_DK1 - -# Enable debug when in low power modes -set ENABLE_LOW_POWER 1 - -# Stop Watchdog counters when halt -set STOP_WATCHDOG 1 - -# STlink Debug clock frequency -set CLOCK_FREQ 8000 - -# Reset configuration -# use hardware reset, connect under reset -# connect_assert_srst needed if low power mode application running (WFI...) -reset_config srst_only srst_nogate connect_assert_srst -set CONNECT_UNDER_RESET 1 -set CORE_RESET 0 - -# ACCESS PORT NUMBER -set AP_NUM 0 -# GDB PORT -set GDB_PORT 3333 - -# BCTM CPU variables - -source [find target/stm32u5x.cfg] - -$_TARGETNAME configure -event gdb-attach { - echo "Debugger attaching: halting execution" - reset halt - gdb_breakpoint_override hard -} - -$_TARGETNAME configure -event gdb-detach { - echo "Debugger detaching: resuming execution" - resume -} - -gdb_memory_map disable diff --git a/boards/st/stm32u5g9j_dk2/board.cmake b/boards/st/stm32u5g9j_dk2/board.cmake index 2bce8d8fc436f..c3617f2cfb135 100644 --- a/boards/st/stm32u5g9j_dk2/board.cmake +++ b/boards/st/stm32u5g9j_dk2/board.cmake @@ -10,4 +10,4 @@ board_runner_args(openocd "--no-halt") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32vl_disco/board.cmake b/boards/st/stm32vl_disco/board.cmake index bf19c690fb32b..7d5a94fd80fcd 100644 --- a/boards/st/stm32vl_disco/board.cmake +++ b/boards/st/stm32vl_disco/board.cmake @@ -6,5 +6,5 @@ board_runner_args(jlink "--device=STM32F100RB" "--speed=8000") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32wb5mm_dk/board.cmake b/boards/st/stm32wb5mm_dk/board.cmake index 834976c5dd454..5220869e9f096 100644 --- a/boards/st/stm32wb5mm_dk/board.cmake +++ b/boards/st/stm32wb5mm_dk/board.cmake @@ -6,5 +6,5 @@ board_runner_args(pyocd "--target=stm32wb55vgyx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/stm32wb5mmg/board.cmake b/boards/st/stm32wb5mmg/board.cmake index 834976c5dd454..5220869e9f096 100644 --- a/boards/st/stm32wb5mmg/board.cmake +++ b/boards/st/stm32wb5mmg/board.cmake @@ -6,5 +6,5 @@ board_runner_args(pyocd "--target=stm32wb55vgyx") # keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml index 079683ca7ade1..231a61b748d7d 100644 --- a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml @@ -17,3 +17,4 @@ testing: ignore_tags: - net - bluetooth +vendor: nxp diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts index c799c0b788c6e..90288e5ba8f51 100644 --- a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts +++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts @@ -30,7 +30,6 @@ led1 = &led1; sw0 = &btn0; sw1 = &btn1; - watchdog0 = &wdt0; }; leds { @@ -91,7 +90,3 @@ &spi0_cs_default>; pinctrl-names = "default"; }; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/ti/lp_mspm0g3507/Kconfig.lp_mspm0g3507 b/boards/ti/lp_mspm0g3507/Kconfig.lp_mspm0g3507 deleted file mode 100644 index 1875699447165..0000000000000 --- a/boards/ti/lp_mspm0g3507/Kconfig.lp_mspm0g3507 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Texas Instruments -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LP_MSPM0G3507 - select SOC_MSPM0G3507 diff --git a/boards/ti/lp_mspm0g3507/board.cmake b/boards/ti/lp_mspm0g3507/board.cmake deleted file mode 100644 index 2b2b64ba4f74b..0000000000000 --- a/boards/ti/lp_mspm0g3507/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=MSPM0G3507" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ti/lp_mspm0g3507/board.yml b/boards/ti/lp_mspm0g3507/board.yml deleted file mode 100644 index f2763be9b23e7..0000000000000 --- a/boards/ti/lp_mspm0g3507/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: lp_mspm0g3507 - full_name: MSPM0G3507 Launchpad - vendor: ti - socs: - - name: mspm0g3507 diff --git a/boards/ti/lp_mspm0g3507/doc/img/lp_mspm0g3507.webp b/boards/ti/lp_mspm0g3507/doc/img/lp_mspm0g3507.webp deleted file mode 100644 index dba82b8bb9112..0000000000000 Binary files a/boards/ti/lp_mspm0g3507/doc/img/lp_mspm0g3507.webp and /dev/null differ diff --git a/boards/ti/lp_mspm0g3507/doc/index.rst b/boards/ti/lp_mspm0g3507/doc/index.rst deleted file mode 100644 index db58807f21bf9..0000000000000 --- a/boards/ti/lp_mspm0g3507/doc/index.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. zephyr:board:: lp_mspm0g3507 - -Overview -******** - -MSPM0G350x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU -family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform operating at up to 80-MHz frequency. -These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature -ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V. - -The MSPM0G350x devices provide up to 128KB embedded flash program memory with built-in error correction -code (ECC) and up to 32KB SRAM with a hardware parity option. These MCUs also incorporate a -memory protection unit, 7-channel DMA, math accelerator, and a variety of peripherals including - -* Analog. - - * Two 12-bit 4-Msps ADCs. - - * Configurable internal shared voltage reference. - - * One 12-bit 1-Msps DAC. - - * Three high speed comparators with built-in reference DACs. - - * Two zero-drift zero-crossover op-amps with programmable gain. - -* Digital. - - * Two 16-bit advanced control timers. - - * Five general-purpose timers. - - * One 16-bit general-purpose timer for QEI interface. - - * One 32-bit high resolution general-purpose timer. - - * Two 16-bit timers with deadband support and up to 12 PWM Channels. - - * Two windowed-watchdog timers. - - * One RTC with alarm and calendar modes. - -* Data Integrity and Encryption. - - * One AES HW accelerator capable of CTR, CBC, and ECB modes. - - * One Cyclic Redundancy Check (CRC) accelerator. - - * One True Random Number Generator (TRNG). - -* Communication. - - * Four UARTs, one with support for advanced modes such as LIN and Manchester. - - * Two I2C supporting SMBUS/PMBUS and speeds up to FM+ (1Mbits/s). - - * Two SPI, one with max speed 32Mbits/s. - - * One CAN interface supporting CAN 2.0 A or B and CAN-FD. - -.. image:: img/lp_mspm0g3507.webp - :align: center - :alt: MSPM0G3507 LaunchPad development board - -Zephyr uses the ``lp_mspm0g3507`` board for building LP_MSPM0G3507 - -Features: -********* - -- Onboard XDS110 debug probe -- EnergyTrace technology available for ultra-low-power debugging -- 2 buttons, 1 LED and 1 RGB LED for user interaction -- Temperature sensor circuit -- Light sensor circuit -- External OPA2365 (default buffer mode) for ADC (up to 4 Msps) evaluation -- Onboard 32.768-kHz and 40-MHz crystals -- RC filter for ADC input (unpopulated by default) - -Details on the MSPM0G3507 LaunchPad can be found on the `TI LP_MSPM0G3507 Product Page`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Building and Flashing -********************* - -Building -======== - -Follow the :ref:`getting_started` instructions for Zephyr application development. - -For example, to build the blinky application for the MSPM0G3507 LaunchPad: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lp_mspm0g3507 - :goals: build - -The resulting ``zephyr.bin`` binary in the build directory can be flashed onto -MSPM0G3507 LaunchPad using the steps mentioned below. - -Flashing -======== - -Open OCD is used to program the flash memory on the devices. It may be necessary in -earlier versions to use a branch of open OCD onto the device. - -Before OpenOCD is public, one can clone `This Repo `_, -and then this can be built with - -``` -cd -./bootstrap (when building from the git repository) -./configure -make -sudo make install -``` - -Then after the build, it is possible to flash the device by passing additional arguments to the flash command - -``` -west flash --openocd /src/openocd --openocd-search /tcl -``` - -Flashing using JLINK - -``` -west flash --runner=jlink -``` - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lp_mspm0g3507 - :goals: debug - -References -********** - -TI MSPM0 MCU Page: - https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html - -TI MSPM0G3507 Product Page: - https://www.ti.com/product/MSPM0G3507 - -TI MSPM0 SDK: - https://www.ti.com/tool/MSPM0-SDK - -.. _MSPM0G3507 TRM: - https://www.ti.com/lit/slau846 - -.. _TI LP_MSPM0G3507 Product Page: - https://www.ti.com/tool/LP-MSPM0G3507 diff --git a/boards/ti/lp_mspm0g3507/lp_mspm0g3507.dts b/boards/ti/lp_mspm0g3507/lp_mspm0g3507.dts deleted file mode 100644 index 900bff2706400..0000000000000 --- a/boards/ti/lp_mspm0g3507/lp_mspm0g3507.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments - * Copyright (c) 2025 Linumiz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include -#include - -/ { - model = "TI LP_MSPM0G3507/MSPM0G3507"; - compatible = "ti,mspm0g3507"; - - aliases { - led0 = &led0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpiob 22 GPIO_ACTIVE_HIGH>; - label = "Blue LED"; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&ulpclk { - clock-frequency = ; - clk-div = <2>; -}; - -&mclk { - clock-frequency = ; - clocks = <&hsclk 0>; -}; - -&hsclk { - clocks = <&syspll2x 0>; - status = "okay"; -}; - -&syspll2x { - status = "okay"; -}; - -&flash0 { - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x8000>; - }; - - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0xC000>; - }; - - slot1_partition: partition@14000 { - label = "image-1"; - reg = <0x00014000 0xC000>; - }; - }; -}; - -&pinctrl { - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&uart0 { - status = "okay"; - - current-speed = <115200>; - pinctrl-0 = <&uart0_tx_pa10 &uart0_rx_pa11>; - pinctrl-names = "default"; -}; diff --git a/boards/ti/lp_mspm0g3507/lp_mspm0g3507.yaml b/boards/ti/lp_mspm0g3507/lp_mspm0g3507.yaml deleted file mode 100644 index 0847dde8f4050..0000000000000 --- a/boards/ti/lp_mspm0g3507/lp_mspm0g3507.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: lp_mspm0g3507 -name: TI MSPM0G3507 Launchpad -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 128 -supported: - - uart - - gpio -vendor: ti diff --git a/boards/ti/lp_mspm0g3507/lp_mspm0g3507_defconfig b/boards/ti/lp_mspm0g3507/lp_mspm0g3507_defconfig deleted file mode 100644 index b916bd908277d..0000000000000 --- a/boards/ti/lp_mspm0g3507/lp_mspm0g3507_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/ti/lp_mspm0g3507/support/openocd.cfg b/boards/ti/lp_mspm0g3507/support/openocd.cfg deleted file mode 100644 index 0356c7705cf1b..0000000000000 --- a/boards/ti/lp_mspm0g3507/support/openocd.cfg +++ /dev/null @@ -1,4 +0,0 @@ -source [find interface/xds110.cfg] -adapter speed 10000 - -source [find target/ti_mspm0.cfg] diff --git a/boards/ti/sk_am62/Kconfig.sk_am62 b/boards/ti/sk_am62/Kconfig.sk_am62 index c5001d13618a3..fab6d88450897 100644 --- a/boards/ti/sk_am62/Kconfig.sk_am62 +++ b/boards/ti/sk_am62/Kconfig.sk_am62 @@ -6,5 +6,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_SK_AM62 - select SOC_AM6234_A53 if BOARD_SK_AM62_AM6234_A53 select SOC_AM6234_M4 if BOARD_SK_AM62_AM6234_M4 diff --git a/boards/ti/sk_am62/board.yml b/boards/ti/sk_am62/board.yml index 7201cf894d776..f0083b004343e 100644 --- a/boards/ti/sk_am62/board.yml +++ b/boards/ti/sk_am62/board.yml @@ -1,6 +1,6 @@ board: name: sk_am62 - full_name: SK-AM62 Evaluation board + full_name: SK-AM62 M4F Core vendor: ti socs: - name: am6234 diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst index 0e8b065b92029..248c16e66b69c 100644 --- a/boards/ti/sk_am62/doc/index.rst +++ b/boards/ti/sk_am62/doc/index.rst @@ -4,20 +4,11 @@ Overview ******** The SK-AM62 board configuration is used by Zephyr applications that run on -the TI AM62x platform. The board configuration provides support for: +the TI AM62x platform. The board configuration provides support for the ARM +Cortex-M4F MCU core and the following features: -- ARM Cortex-M4F MCU core and the following features: - - - Nested Vector Interrupt Controller (NVIC) - - System Tick System Clock (SYSTICK) - -- ARM Cortex-A53 core and the following features: - - - General Interrupt Controller (GIC) - - ARM Generic Timer (arch_timer) - - On-chip SRAM (oc_sram) - - UART interfaces (uart0 to uart6) - - Mailbox interface (mbox0) +- Nested Vector Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) The board configuration also enables support for the semihosting debugging console. @@ -27,9 +18,8 @@ Hardware ******** The SK-AM62 EVM features the AM62x SoC, which is composed of a quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on -the M4F and A53 cores. The following listed hardware specifications are used: +the M4F core and the following listed hardware specifications are used: -- High-performance ARM Cortex-A53 - Low-power ARM Cortex-M4F - Memory @@ -69,12 +59,15 @@ SD Card Download TI's official `WIC`_ and flash the WIC file with an etching software onto an SD-card. This will boot Linux on the A53 application cores of the EVM. -While programming for the M4 core, the A53 cores will then load the zephyr binary on the M4 core using remoteproc. +These cores will then load the zephyr binary on the M4 core using remoteproc. -Programming for M4F Core -************************ +The default configuration can be found in +:zephyr_file:`boards/ti/sk_am62/sk_am62_am6234_m4_defconfig` + +Flashing +******** -The board can use remoteproc, and uses the OpenAMP resource table to accomplish this. +The board can using remoteproc, and uses the OpenAMP resource table to accomplish this. The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. @@ -105,42 +98,17 @@ To allow the board to boot using the SD card, set the boot pins to the SD Card b After changing the boot mode, the board should go through the boot sequence on powering up. The binary will run and print Hello world to the MCU_UART0 port. -Programming for A53 Core -************************ - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - fatload mmc 1:1 0x82000000 zephyr.bin; go 0x82000000 - -The Zephyr application should start running on the A53 core. - Debugging ********* The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the ``debug`` build target: -- M4F Core - .. zephyr-app-commands:: :app: :board: sk_am62/am6234/m4 :maybe-skip-config: :goals: debug -- A53 Core - -.. zephyr-app-commands:: - :app: - :board: sk_am62/am6234/a53 - :maybe-skip-config: - :goals: debug - .. hint:: To utilize this feature, you'll need OpenOCD version 0.12 or higher. Due to the possibility of older versions being available in package feeds, it's advisable to `build OpenOCD from source`_. @@ -155,7 +123,8 @@ AM62x SK EVM TRM: https://www.ti.com/product/AM625 .. _WIC: - https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/10.01.10.04/tisdk-default-image-am62xx-evm-10.01.10.04.rootfs.wic.xz + https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/08.06.00.42/tisdk-default-image-am62xx-evm.wic.xz + .. _AM62x SK EVM TRM: https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf diff --git a/boards/ti/sk_am62/sk-am62_am6234_a53-pinctrl.dts b/boards/ti/sk_am62/sk-am62_am6234_a53-pinctrl.dts deleted file mode 100644 index 2bbcb890d7172..0000000000000 --- a/boards/ti/sk_am62/sk-am62_am6234_a53-pinctrl.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - uart0_rx_default: uart0_rx_default { - pinmux = ; - }; - - uart0_tx_default: uart0_tx_default { - pinmux = ; - }; -}; diff --git a/boards/ti/sk_am62/sk_am62_am6234_a53.dts b/boards/ti/sk_am62/sk_am62_am6234_a53.dts deleted file mode 100644 index 8c88cf1e128a2..0000000000000 --- a/boards/ti/sk_am62/sk_am62_am6234_a53.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sk-am62_am6234_a53-pinctrl.dts" -/ { - model = "TI AM62X STARTER KIT (SK) EVALUATION MODULE (EVM)"; - compatible = "ti,am62x_a53_sk"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ddr0; - }; - - cpus { - - cpu@0 { - status = "okay"; - }; - - cpu@1 { - status = "disabled"; - }; - - cpu@2 { - status = "disabled"; - }; - - cpu@3 { - status = "disabled"; - }; - }; - - ddr0: memory@82000000 { - /* Note: This board actually has 2GB DRAM available */ - reg = <0x82000000 DT_SIZE_M(1)>; - }; -}; - - -&uart0 { - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/ti/sk_am62/sk_am62_am6234_a53.yaml b/boards/ti/sk_am62/sk_am62_am6234_a53.yaml deleted file mode 100644 index 75390238c1162..0000000000000 --- a/boards/ti/sk_am62/sk_am62_am6234_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: sk_am62/am6234/a53 -name: TI AM62X A53 Starter Kit (SK) -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: ti diff --git a/boards/ti/sk_am62/sk_am62_am6234_a53_defconfig b/boards/ti/sk_am62/sk_am62_am6234_a53_defconfig deleted file mode 100644 index 5f0314b439182..0000000000000 --- a/boards/ti/sk_am62/sk_am62_am6234_a53_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-A53 EVM -# -# Copyright (c) 2025 Texas Instruments Incorporated -# Copyright (c) 2025 Dave Paul Joseph -# -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Driver -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/ti/sk_am64/doc/index.rst b/boards/ti/sk_am64/doc/index.rst index b0fece31845b2..fa87ea3590c62 100644 --- a/boards/ti/sk_am64/doc/index.rst +++ b/boards/ti/sk_am64/doc/index.rst @@ -46,11 +46,7 @@ DDR RAM ------- The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr: - -- 1MB for IPC (VirtIO / Vrings) -- 4KB for Linux RemoteProc resource table -- 15MB for general usage +allocates Zephyr 4kB of RAM (only for resource table: 0xa4100000 to 0xa4100400). Serial Port ----------- diff --git a/boards/ti/sk_am64/sk_am64_am6442_m4.dts b/boards/ti/sk_am64/sk_am64_am6442_m4.dts index ad94503d9de8f..93073c26e737e 100644 --- a/boards/ti/sk_am64/sk_am64_am6442_m4.dts +++ b/boards/ti/sk_am64/sk_am64_am6442_m4.dts @@ -44,10 +44,10 @@ zephyr,memory-region = "RSC_TABLE"; }; - ddr1: memory@a4101000 { + ddr1: memory@a4200000 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0xa4101000 (DT_SIZE_M(15) - DT_SIZE_K(4))>; - zephyr,memory-region = "DRAM"; + reg = <0xa4200000 (DT_SIZE_M(15) - DT_SIZE_K(4))>; + zephyr,memory-region = "DDR"; }; leds: leds { diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml index e03484b4943e7..616be08775c1e 100644 --- a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml @@ -19,3 +19,4 @@ testing: - bluetooth supported: - pwm +vendor: nxp diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml index 635cc93120f9b..6a1ee179451e4 100644 --- a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml @@ -17,3 +17,4 @@ supported: - counter - gpio - uart +vendor: nxp diff --git a/boards/variscite/imx8mp_var_dart/Kconfig.imx8mp_var_dart b/boards/variscite/imx8mp_var_dart/Kconfig.imx8mp_var_dart deleted file mode 100644 index f3c27443507ad..0000000000000 --- a/boards/variscite/imx8mp_var_dart/Kconfig.imx8mp_var_dart +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2025 Variscite Ltd. -# Copyright 2021-2022, 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IMX8MP_VAR_DART - select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_VAR_DART_MIMX8ML8_A53 - select SOC_MIMX8ML8_M7 if BOARD_IMX8MP_VAR_DART_MIMX8ML8_M7 || BOARD_IMX8MP_VAR_DART_MIMX8ML8_M7_DDR - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/variscite/imx8mp_var_dart/board.cmake b/boards/variscite/imx8mp_var_dart/board.cmake deleted file mode 100644 index 3ca8045e96ff2..0000000000000 --- a/boards/variscite/imx8mp_var_dart/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_SOC_MIMX8ML8_M7) - board_set_debugger_ifnset(jlink) - board_set_flasher_ifnset(jlink) - - board_runner_args(jlink "--device=MIMX8ML8_M7") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/variscite/imx8mp_var_dart/board.yml b/boards/variscite/imx8mp_var_dart/board.yml deleted file mode 100644 index 7851143aaecac..0000000000000 --- a/boards/variscite/imx8mp_var_dart/board.yml +++ /dev/null @@ -1,9 +0,0 @@ -boards: - - name: imx8mp_var_dart - full_name: DART-MX8M-PLUS - vendor: variscite - socs: - - name: mimx8ml8 - variants: - - name: ddr - cpucluster: m7 diff --git a/boards/variscite/imx8mp_var_dart/doc/imx8mp_var_dart.webp b/boards/variscite/imx8mp_var_dart/doc/imx8mp_var_dart.webp deleted file mode 100644 index faab69b33a9bb..0000000000000 Binary files a/boards/variscite/imx8mp_var_dart/doc/imx8mp_var_dart.webp and /dev/null differ diff --git a/boards/variscite/imx8mp_var_dart/doc/index.rst b/boards/variscite/imx8mp_var_dart/doc/index.rst deleted file mode 100644 index 3a18833d275c6..0000000000000 --- a/boards/variscite/imx8mp_var_dart/doc/index.rst +++ /dev/null @@ -1,276 +0,0 @@ -.. zephyr:board:: imx8mp_var_dart - -Overview -******** - -Variscite's DART-MX8M-PLUS System on Module (SoM) is based on the i.MX 8M Plus family, -which is a set of NXP products built to achieve both high performance and low power -consumption and relies on a powerful, fully coherent core complex based on a quad Cortex®-A53 -cluster and Cortex®-M7 low-power coprocessor, audio digital signal processor, machine learning -and graphics accelerators. - -Zephyr OS is ported to run on either the Cortex®-A53 or the Cortex®-M7. - -Specs Summary -*************** - - - CPU - - - NXP i.MX8M Plus: - - Up to 4x Cortex®-A53 @ 1.8GHz - - 1x Cortex®-M7 @ 800 MHz - - 1x NPU 2.3 TOPS - - Memory - - - Up to 8GB LPDDR4 RAM @ 2000MHz - - 8-bit up to 128GB eMMC boot and storage - - GPU - - - 3D: Vivanteâ„¢ GC7000UltraLite (2 shaders) OpenGL ES 3.0, OpenCL1.2, Vulkan - - 2D: Vivanteâ„¢ GC520L - - NPU (Neural Processing Unit) - - - 2.3 TOPS Neural Network performance - - Display - - - 2x LVDS interface 4-lane each up to 1080p60 - - HDMI 2.0a up to 4Kp30 - - 1x MIPI DSI with up to 4 data lanes 1080p60 - - Network - - - 2x 10/100/1000 Mbit/s Ethernet Interface - - Certified Wi-Fi 6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 - - Bluetooth/BLE 5.4 - - Camera - - - Up to 2x MIPI CSI – CMOS Serial camera Interface 4 lanes - - 375 Mpixel/s HDR ISP (Image Sensor Processor) - - Audio - - - Headphones - - Microphone: Digital, Analog (stereo) - - 6x I2S(SAI), S/PDIF RX TX, PDM 8CH, Line In/Out - - USB - - - 2x USB 3.0/2.0 Host/Device - - Serial interfaces - - - SPI: x3 - - I2C: x5 - - UART: x4, up to 5 Mbps - - CAN: x2 - - Temperature range - - - -40°C to 85°C - -More information about the SoM can be found at the -`Variscite Wiki`_ and -`Variscite website`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -.. note:: - - It is recommended to disable peripherals used by the M7 core on the Linux host. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -The M7 core is configured to run at an 800 MHz clock speed. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART3. - -Programming and Debugging (A53) -******************************* - -Copy the compiled ``zephyr.bin`` to the boot directory of the SD card and -plug the SD card into the board. Power it up and stop the U-Boot execution at -prompt. - -Use U-Boot to load and run zephyr.bin on the Cortex-A53: - -.. code-block:: console - - load mmc $mmcdev:$mmcpart $loadaddr /boot/zephyr.bin - dcache flush; icache flush; go $loadaddr - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`hello_world` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :host-os: unix - :board: imx8mp_var_dart/mimx8ml8/a53 - :goals: build - -This will build an image with the hello_world sample app. When loaded and executed -it will display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_dart/mimx8ml8/a53 - - -Programming and Debugging (M7) -****************************** - -.. zephyr:board-supported-runners:: - -The DART-MX8M-PLUS doesn't have QSPI flash for the M7, and it needs to be -started by the A53 core. The A53 core is responsible to load the M7 binary -application into the RAM, put the M7 in reset, set the M7 Program Counter and -Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x7B200000-0x7B3FFFFF | 0x7B000000-0x7B1FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done based on board name (e.g. imx8mp_var_dart/mimx8ml8/m7 -for ITCM and imx8mp_var_dart/mimx8ml8/m7/ddr for DDR). - -There are two methods to load M7 Core images: U-Boot command and Linux remoteproc. - -Load and Run M7 Zephyr Image from U-Boot -======================================== - -Load and run Zephyr on M7 from A53 using U-Boot by copying the compiled -``zephyr.bin`` to the boot directory of the SD card and plug the SD -card into the board. Power it up and stop the U-Boot execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -==== - -.. code-block:: console - - load mmc 1:1 0x48000000 /boot/zephyr.bin - cp.b 0x48000000 0x7e0000 20000 - bootaux 0x7e0000 - -DDR -=== - -.. code-block:: console - - load mmc 1:1 0x7b000000 /boot/zephyr.bin - dcache flush - bootaux 0x7b000000 - -Load and Run M7 Zephyr Image by using Linux remoteproc -====================================================== - -Transfer built binaries ``zephyr.bin`` and ``zephyr.elf`` to the SoM's ``/boot`` and -``/lib/firmware`` respectively using ``scp`` or through an USB drive. - -It is possible to execute Zephyr binaries using Variscite remoteproc scripts made -for MCUXpresso binaries: - -.. code-block:: console - - root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-linux -f /lib/firmware/zephyr.elf - [ 212.888118] remoteproc remoteproc0: powering up imx-rproc - [ 212.899215] remoteproc remoteproc0: Booting fw image zephyr.elf, size 515836 - [ 212.912070] remoteproc remoteproc0: No resource table in elf - [ 213.444675] remoteproc remoteproc0: remote processor imx-rproc is now up - -Which should yield the following result on the UART3 serial console: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_dart/mimx8ml8/m7 - -If the device tree dedicated to be used with Cortex-M7 applications is not being -currently used, the script will give instructions on how to do so: - -.. code-block:: console - - Error: /sys/class/remoteproc/remoteproc0 not found. - Please enable remoteproc driver. - Most likely you need to use the correct device tree, for example: - fw_setenv fdt_file imx8mp-var-dart-dt8mcustomboard-m7.dtb && reboot - -You can also configure U-Boot to load firmware on boot: - -.. code-block:: console - - root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-u-boot -f /boot/zephyr.bin - Configuring for TCM memory - + fw_setenv m7_addr 0x7E0000 - + fw_setenv fdt_file imx8mp-var-dart-dt8mcustomboard-m7.dtb - + fw_setenv use_m7 yes - + fw_setenv m7_bin zephyr.bin - - Finished: Please reboot, the m7 firmware will run during U-Boot - -For more information about Variscite remoteproc scripts and general Cortex-M7 -support, visit `Variscite Wiki`_. - -Debugging -========= - -DART-MX8M-PLUS board can be debugged by connecting an external -JLink JTAG debugger to the J29 of the DT8MCustomBoard and to the PC. -Then the application can be debugged using the usual way. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: imx8mp_var_dart/mimx8ml8/m7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_dart/mimx8ml8/m7 - -References -========== - -- `Variscite Wiki`_ -- `Variscite website`_ -- `i.MX 8M Applications Processor Reference Manual`_ - -.. _Variscite Wiki: - https://variwiki.com/index.php?title=DART-MX8M-PLUS - -.. _Variscite website: - https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/dart-mx8m-plus-nxp-i-mx-8m-plus - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart-pinctrl.dtsi b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart-pinctrl.dtsi deleted file mode 100644 index 20cf2d1bdf409..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart-pinctrl.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright 2022-2024 NXP - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include - -&pinctrl { - uart1_default: uart1_default { - group0 { - pinmux = <&iomuxc_uart1_rxd_uart_rx_uart1_rx>, - <&iomuxc_uart1_txd_uart_tx_uart1_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - - uart3_default: uart3_default { - group0 { - pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, - <&iomuxc_uart3_txd_uart_tx_uart3_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; -}; diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_m7-common.dtsi b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_m7-common.dtsi deleted file mode 100644 index eca22eda33a2b..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_m7-common.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/ { - soc { - uart3: uart@30880000 { - compatible = "nxp,imx-iuart"; - reg = <0x30880000 0x10000>; - interrupts = <28 3>; - clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>; - status = "disabled"; - }; - }; -}; diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.dts b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.dts deleted file mode 100644 index 431a19c684270..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.dts +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright 2021-2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_dart-pinctrl.dtsi" -#include -#include - -/ { - model = "Variscite DART-MX8M-PLUS A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart3; - zephyr,shell-uart = &uart3; - /* sram node actually locates at DDR DRAM */ - zephyr,sram = &dram; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - - cpu@1 { - status = "disabled"; - }; - - cpu@2 { - status = "disabled"; - }; - }; - - dram: memory@40480000 { - reg = <0x40480000 DT_SIZE_M(1)>; - }; - - soc { - uart3: uart@30880000 { - compatible = "nxp,imx-iuart"; - reg = <0x30880000 DT_SIZE_K(64)>; - interrupts = ; - interrupt-names = "irq_0"; - interrupt-parent = <&gic>; - clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; - }; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 8 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&gpio3 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.yaml b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.yaml deleted file mode 100644 index 70fd41a8f9381..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_dart/mimx8ml8/a53 -name: Variscite DART-MX8M-PLUS A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - uart - - net - - gpio -testing: - ignore_tags: - - bluetooth diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53_defconfig b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53_defconfig deleted file mode 100644 index 75fd5682c6033..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_a53_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright 2025 Variscite Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_KERNEL_DIRECT_MAP=y - -# Serial Drivers -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.dts b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.dts deleted file mode 100644 index 5345ed31e88b8..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.dts +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_dart-pinctrl.dtsi" -#include "imx8mp_var_dart_m7-common.dtsi" -#include -#include - -/ { - model = "Variscite DART-MX8M-PLUS M7"; - compatible = "nxp,imx8mp_var_dart"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart3; - zephyr,shell-uart = &uart3; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 8 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&uart3 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.yaml b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.yaml deleted file mode 100644 index e4d0648e9d358..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_dart/mimx8ml8/m7 -name: Variscite DART-MX8M-PLUS M7 -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb -supported: - - uart - - gpio diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.dts b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.dts deleted file mode 100644 index fb9d2df39a1a1..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_dart-pinctrl.dtsi" -#include "imx8mp_var_dart_m7-common.dtsi" -#include -#include - -/delete-node/ &ddr_code; -/delete-node/ &ddr_sys; - -/ { - model = "Variscite DART-MX8M-PLUS M7 (DDR)"; - compatible = "nxp,imx8mp_var_dart"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart3; - zephyr,shell-uart = &uart3; - }; - - soc { - ddr_code: code@7b000000 { - device_type = "memory"; - compatible = "nxp,imx-code-bus"; - reg = <0x7b000000 DT_SIZE_M(2)>; - }; - - ddr_sys: memory@7b200000 { - device_type = "memory"; - compatible = "nxp,imx-sys-bus"; - reg = <0x7b200000 DT_SIZE_M(2)>; - }; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 8 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&uart3 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.yaml b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.yaml deleted file mode 100644 index 9a33dc64d309a..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_dart/mimx8ml8/m7/ddr -name: Variscite DART-MX8M-PLUS M7 (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb -supported: - - uart - - gpio diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr_defconfig b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr_defconfig deleted file mode 100644 index cce273e97fdff..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_ddr_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_FLASH_BASE_ADDRESS=0x7b000000 -CONFIG_FLASH_SIZE=2048 diff --git a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_defconfig b/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_defconfig deleted file mode 100644 index 6c7e489b8b5cb..0000000000000 --- a/boards/variscite/imx8mp_var_dart/imx8mp_var_dart_mimx8ml8_m7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y diff --git a/boards/variscite/imx8mp_var_som/Kconfig.imx8mp_var_som b/boards/variscite/imx8mp_var_som/Kconfig.imx8mp_var_som deleted file mode 100644 index ce40f0feab158..0000000000000 --- a/boards/variscite/imx8mp_var_som/Kconfig.imx8mp_var_som +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2025 Variscite Ltd. -# Copyright 2021-2022, 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IMX8MP_VAR_SOM - select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_VAR_SOM_MIMX8ML8_A53 - select SOC_MIMX8ML8_M7 if BOARD_IMX8MP_VAR_SOM_MIMX8ML8_M7 || BOARD_IMX8MP_VAR_SOM_MIMX8ML8_M7_DDR - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/variscite/imx8mp_var_som/board.cmake b/boards/variscite/imx8mp_var_som/board.cmake deleted file mode 100644 index 3ca8045e96ff2..0000000000000 --- a/boards/variscite/imx8mp_var_som/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_SOC_MIMX8ML8_M7) - board_set_debugger_ifnset(jlink) - board_set_flasher_ifnset(jlink) - - board_runner_args(jlink "--device=MIMX8ML8_M7") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/variscite/imx8mp_var_som/board.yml b/boards/variscite/imx8mp_var_som/board.yml deleted file mode 100644 index ea0924566159a..0000000000000 --- a/boards/variscite/imx8mp_var_som/board.yml +++ /dev/null @@ -1,9 +0,0 @@ -boards: - - name: imx8mp_var_som - full_name: VAR-SOM-MX8M-PLUS - vendor: variscite - socs: - - name: mimx8ml8 - variants: - - name: ddr - cpucluster: m7 diff --git a/boards/variscite/imx8mp_var_som/doc/imx8mp_var_som.webp b/boards/variscite/imx8mp_var_som/doc/imx8mp_var_som.webp deleted file mode 100644 index ac3c537f00f53..0000000000000 Binary files a/boards/variscite/imx8mp_var_som/doc/imx8mp_var_som.webp and /dev/null differ diff --git a/boards/variscite/imx8mp_var_som/doc/index.rst b/boards/variscite/imx8mp_var_som/doc/index.rst deleted file mode 100644 index 00e2a88c108d7..0000000000000 --- a/boards/variscite/imx8mp_var_som/doc/index.rst +++ /dev/null @@ -1,277 +0,0 @@ -.. zephyr:board:: imx8mp_var_som - -Overview -******** - -Variscite's VAR-SOM-MX8M-PLUS System on Module (SoM) is based on the i.MX 8M Plus family, -which is a set of NXP products built to achieve both high performance and low power -consumption and relies on a powerful, fully coherent core complex based on a quad Cortex®-A53 -cluster and Cortex®-M7 low-power coprocessor, audio digital signal processor, machine learning -and graphics accelerators. - -Zephyr OS is ported to run on either the Cortex®-A53 or the Cortex®-M7. - -Specs Summary -*************** - - - CPU - - - NXP i.MX8M Plus: - - Up to 4x Cortex®-A53 @ 1.8GHz - - 1x Cortex®-M7 @ 800 MHz - - 1x NPU 2.3 TOPS - - Memory - - - Up to 8GB LPDDR4 RAM @ 2000MHz - - 8-bit up to 128GB eMMC boot and storage - - GPU - - - 3D: Vivanteâ„¢ GC7000UltraLite (2 shaders) OpenGL ES 3.0, OpenCL1.2, Vulkan - - 2D: Vivanteâ„¢ GC520L - - NPU (Neural Processing Unit) - - - 2.3 TOPS Neural Network performance - - Display - - - 2x LVDS interface 4-lane each up to 1080p60 - - HDMI 2.0a up to 4Kp30 - - 1x MIPI DSI with up to 4 data lanes 1080p60 - - Network - - - 2x 10/100/1000 Mbit/s Ethernet Interface - - Certified Wi-Fi 6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 - - Bluetooth/BLE 5.4 - - Camera - - - Up to 2x MIPI CSI – CMOS Serial camera Interface 4 lanes - - 375 Mpixel/s HDR ISP (Image Sensor Processor) - - Audio - - - Headphones - - Microphone: Digital, Analog (stereo) - - 6x I2S(SAI), S/PDIF RX TX, PDM 8CH, Line In/Out - - USB - - - 2x USB 3.0/2.0 Host/Device - - Serial interfaces - - - SPI: x3 - - I2C: x5 - - UART: x4, up to 5 Mbps - - CAN: x2 - - Temperature range - - - -40°C to 85°C - -More information about the SoM can be found at the -`Variscite Wiki`_ and -`Variscite website`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -.. note:: - - It is recommended to disable peripherals used by the M7 core on the Linux host. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -The M7 core is configured to run at an 800 MHz clock speed. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging (A53) -******************************* - -Copy the compiled ``zephyr.bin`` to the boot directory of the SD card and -plug the SD card into the board. Power it up and stop the U-Boot execution at -prompt. - -Use U-Boot to load and run zephyr.bin on the Cortex-A53: - -.. code-block:: console - - load mmc $mmcdev:$mmcpart $loadaddr /boot/zephyr.bin - dcache flush; icache flush; go $loadaddr - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`hello_world` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :host-os: unix - :board: imx8mp_var_som/mimx8ml8/a53 - :goals: build - -This will build an image with the hello_world sample app. When loaded and executed -it will display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_som/mimx8ml8/a53 - - -Programming and Debugging (M7) -****************************** - -.. zephyr:board-supported-runners:: - -The VAR-SOM-MX8M-PLUS don't have QSPI flash for the M7, and it needs to be -started by the A53 core. The A53 core is responsible to load the M7 binary -application into the RAM, put the M7 in reset, set the M7 Program Counter and -Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x7B200000-0x7B3FFFFF | 0x7B000000-0x7B1FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done based on board name (e.g. imx8mp_var_som/mimx8ml8/m7 -for ITCM and imx8mp_var_som/mimx8ml8/m7/ddr for DDR). - -There are two methods to load M7 Core images: U-Boot command and Linux remoteproc. - -Load and Run M7 Zephyr Image from U-Boot -======================================== - -Load and run Zephyr on M7 from A53 using U-Boot by copying the compiled -``zephyr.bin`` to the boot directory of the SD card and plug the SD -card into the board. Power it up and stop the U-Boot execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -==== - -.. code-block:: console - - load mmc 1:1 0x48000000 /boot/zephyr.bin - cp.b 0x48000000 0x7e0000 20000 - bootaux 0x7e0000 - -DDR -=== - -.. code-block:: console - - load mmc 1:1 0x7b000000 /boot/zephyr.bin - dcache flush - bootaux 0x7b000000 - -Load and Run M7 Zephyr Image by using Linux remoteproc -====================================================== - -Transfer built binaries ``zephyr.bin`` and ``zephyr.elf`` to the SoM's ``/boot`` and -``/lib/firmware`` respectively using ``scp`` or through an USB drive. - -It is possible to execute Zephyr binaries using Variscite remoteproc scripts made -for MCUXpresso binaries: - -.. code-block:: console - - root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-linux -f /lib/firmware/zephyr.elf - [ 212.888118] remoteproc remoteproc0: powering up imx-rproc - [ 212.899215] remoteproc remoteproc0: Booting fw image zephyr.elf, size 515836 - [ 212.912070] remoteproc remoteproc0: No resource table in elf - [ 213.444675] remoteproc remoteproc0: remote processor imx-rproc is now up - -Which should yield the following result on the UART4 serial console: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_som/mimx8ml8/m7 - -If the device tree dedicated to be used with Cortex-M7 applications is not being -currently used, the script will give instructions on how to do so: - -.. code-block:: console - - Error: /sys/class/remoteproc/remoteproc0 not found. - Please enable remoteproc driver. - Most likely you need to use the correct device tree, for example: - fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb && reboot - -You can also configure U-Boot to load firmware on boot: - -.. code-block:: console - - root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-u-boot -f /boot/zephyr.bin - Configuring for TCM memory - + fw_setenv m7_addr 0x7E0000 - + fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb - + fw_setenv use_m7 yes - + fw_setenv m7_bin zephyr.bin - - Finished: Please reboot, the m7 firmware will run during U-Boot - -For more information about Variscite remoteproc scripts and general Cortex-M7 -support, visit `Variscite Wiki`_. - -Debugging -========= - -VAR-SOM-MX8M-PLUS board can be debugged by connecting an external -JLink JTAG debugger to the 14-pin header on the top left side of -the SoM and to the PC. Then the application can be debugged using -the usual way. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: imx8mp_var_som/mimx8ml8/m7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa *** - Hello World! imx8mp_var_som/mimx8ml8/m7 - -References -========== - -- `Variscite Wiki`_ -- `Variscite website`_ -- `i.MX 8M Applications Processor Reference Manual`_ - -.. _Variscite Wiki: - https://variwiki.com/index.php?title=VAR-SOM-MX8M-PLUS - -.. _Variscite website: - https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-mx8m-plus-nxp-i-mx-8m-plus - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som-pinctrl.dtsi b/boards/variscite/imx8mp_var_som/imx8mp_var_som-pinctrl.dtsi deleted file mode 100644 index 20cf2d1bdf409..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som-pinctrl.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright 2022-2024 NXP - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include - -&pinctrl { - uart1_default: uart1_default { - group0 { - pinmux = <&iomuxc_uart1_rxd_uart_rx_uart1_rx>, - <&iomuxc_uart1_txd_uart_tx_uart1_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - - uart3_default: uart3_default { - group0 { - pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, - <&iomuxc_uart3_txd_uart_tx_uart3_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; -}; diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.dts b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.dts deleted file mode 100644 index faa6e233c4f3a..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright 2021-2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_som-pinctrl.dtsi" -#include -#include - -/ { - model = "Variscite VAR-SOM-MX8M-PLUS A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - /* sram node actually locates at DDR DRAM */ - zephyr,sram = &dram; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - - cpu@1 { - status = "disabled"; - }; - - cpu@2 { - status = "disabled"; - }; - }; - - dram: memory@40480000 { - reg = <0x40480000 DT_SIZE_M(1)>; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.yaml b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.yaml deleted file mode 100644 index aa76c5ab71f91..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_som/mimx8ml8/a53 -name: Variscite VAR-SOM-MX8M-PLUS A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - uart - - net -testing: - ignore_tags: - - bluetooth diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53_defconfig b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53_defconfig deleted file mode 100644 index 75fd5682c6033..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_a53_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright 2025 Variscite Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_KERNEL_DIRECT_MAP=y - -# Serial Drivers -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.dts b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.dts deleted file mode 100644 index 009ff61298b02..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_som-pinctrl.dtsi" -#include -#include - -/ { - model = "Variscite VAR-SOM-MX8M-PLUS M7"; - compatible = "nxp,imx8mp_var_som"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.yaml b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.yaml deleted file mode 100644 index 8f8435be13822..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_som/mimx8ml8/m7 -name: Variscite VAR-SOM-MX8M-PLUS M7 -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb -supported: - - uart diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.dts b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.dts deleted file mode 100644 index c530902691fac..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2025 Variscite Ltd. - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "imx8mp_var_som-pinctrl.dtsi" -#include -#include - -/delete-node/ &ddr_code; -/delete-node/ &ddr_sys; - -/ { - model = "Variscite VAR-SOM-MX8M-PLUS M7 (DDR)"; - compatible = "nxp,imx8mp_var_som"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; - - soc { - ddr_code: code@7b000000 { - device_type = "memory"; - compatible = "nxp,imx-code-bus"; - reg = <0x7b000000 DT_SIZE_M(2)>; - }; - - ddr_sys: memory@7b200000 { - device_type = "memory"; - compatible = "nxp,imx-sys-bus"; - reg = <0x7b200000 DT_SIZE_M(2)>; - }; - }; - - aliases { - led0 = &blinky0; - sw0 = &button0; - }; - - leds { - compatible = "gpio-leds"; - - blinky0: blinky_0 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button0: btn_0 { - label = "BTN0"; - gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; - -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.yaml b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.yaml deleted file mode 100644 index cb0ce35a1059a..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: imx8mp_var_som/mimx8ml8/m7/ddr -name: Variscite VAR-SOM-MX8M-PLUS M7 (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb -supported: - - uart diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr_defconfig b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr_defconfig deleted file mode 100644 index cce273e97fdff..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_ddr_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_FLASH_BASE_ADDRESS=0x7b000000 -CONFIG_FLASH_SIZE=2048 diff --git a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_defconfig b/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_defconfig deleted file mode 100644 index 6c7e489b8b5cb..0000000000000 --- a/boards/variscite/imx8mp_var_som/imx8mp_var_som_mimx8ml8_m7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2025 Variscite Ltd. -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y diff --git a/boards/variscite/index.rst b/boards/variscite/index.rst deleted file mode 100644 index 9985dab18c8b6..0000000000000 --- a/boards/variscite/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-variscite: - -Variscite -######### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts index 4562d3435f09d..926f1f564544d 100644 --- a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts @@ -103,7 +103,6 @@ &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; cd-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/waveshare/esp32s3_matrix/Kconfig b/boards/waveshare/esp32s3_matrix/Kconfig deleted file mode 100644 index 9da4605ab555e..0000000000000 --- a/boards/waveshare/esp32s3_matrix/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# Copyright (c) 2025 Chen Xingyu -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32S3_MATRIX_ESP32S3_PROCPU - default 256 if BOARD_ESP32S3_MATRIX_ESP32S3_APPCPU diff --git a/boards/waveshare/esp32s3_matrix/Kconfig.esp32s3_matrix b/boards/waveshare/esp32s3_matrix/Kconfig.esp32s3_matrix deleted file mode 100644 index d85b46fe240e1..0000000000000 --- a/boards/waveshare/esp32s3_matrix/Kconfig.esp32s3_matrix +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# Copyright (c) 2025 Chen Xingyu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S3_MATRIX - select SOC_ESP32S3_R2 - select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_MATRIX_ESP32S3_PROCPU - select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_MATRIX_ESP32S3_APPCPU diff --git a/boards/waveshare/esp32s3_matrix/Kconfig.sysbuild b/boards/waveshare/esp32s3_matrix/Kconfig.sysbuild deleted file mode 100644 index 8d3acb9e11d7c..0000000000000 --- a/boards/waveshare/esp32s3_matrix/Kconfig.sysbuild +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice BOOTLOADER - default BOOTLOADER_MCUBOOT -endchoice - -choice BOOT_SIGNATURE_TYPE - default BOOT_SIGNATURE_TYPE_NONE -endchoice diff --git a/boards/waveshare/esp32s3_matrix/board.cmake b/boards/waveshare/esp32s3_matrix/board.cmake deleted file mode 100644 index b822d4b08332d..0000000000000 --- a/boards/waveshare/esp32s3_matrix/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# SPDX-License-Identifier: Apache-2.0 - -if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") - set(OPENOCD OPENOCD-NOTFOUND) -endif() -find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) - -include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/waveshare/esp32s3_matrix/board.yml b/boards/waveshare/esp32s3_matrix/board.yml deleted file mode 100644 index a2a740f8abd9f..0000000000000 --- a/boards/waveshare/esp32s3_matrix/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32s3_matrix - full_name: ESP32-S3-Matrix - vendor: waveshare - socs: - - name: esp32s3 diff --git a/boards/waveshare/esp32s3_matrix/doc/img/esp32s3_matrix.webp b/boards/waveshare/esp32s3_matrix/doc/img/esp32s3_matrix.webp deleted file mode 100644 index 6f44538e4cd3f..0000000000000 Binary files a/boards/waveshare/esp32s3_matrix/doc/img/esp32s3_matrix.webp and /dev/null differ diff --git a/boards/waveshare/esp32s3_matrix/doc/index.rst b/boards/waveshare/esp32s3_matrix/doc/index.rst deleted file mode 100644 index 4090485a84d66..0000000000000 --- a/boards/waveshare/esp32s3_matrix/doc/index.rst +++ /dev/null @@ -1,229 +0,0 @@ -.. zephyr:board:: esp32s3_matrix - -Overview -******** - -The ESP32-S3-Matrix is an ESP32S3 development board from Waveshare with a 8x8 -RGB LED matrix. This board integrates complete Wi-Fi and Bluetooth Low Energy -functions, an accelerometer and gyroscope, a battery charger and GPIO extension -port. - -Hardware -******** - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -ESP32-S3-Matrix includes the following features: - -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz -- Additional vector instructions support for AI acceleration -- 512KB of SRAM -- 2MB of PSRAM -- 4MB of FLASH -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate -- 8x8 RGB LED matrix -- Accelerometer/gyroscope - -Digital interfaces: - -- 15 programmable GPIOs - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-S3 allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core -architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. - -For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference -manual at `ESP32-S3 Technical Reference Manual`_. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -.. zephyr:board-supported-runners:: - -Simple boot -=========== - -The board could be loaded using the single binary image, without 2nd stage bootloader. -It is the default option when building the application without additional configuration. - -.. note:: - - Simple boot does not provide any security features nor OTA updates. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be built (and flashed) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - - .. code:: cfg - - CONFIG_BOOTLOADER_MCUBOOT=y - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32-S3 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/hello_world - :board: esp32s3_matrix/esp32s3/procpu - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be built one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_matrix/esp32s3/procpu - :goals: build - -The usual ``flash`` target will work with the ``esp32s3_matrix`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_matrix/esp32s3/procpu - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s3_matrix - -Debugging -********* - -ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. - -Here is an example for building the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_matrix/esp32s3/procpu - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_matrix/esp32s3/procpu - :goals: debug - -References -********** - -.. target-notes:: - -.. _ESP32-S3-Matrix Waveshare Wiki: https://www.waveshare.com/wiki/ESP32-S3-Matrix -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf -.. _ESP32-S3 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix-pinctrl.dtsi b/boards/waveshare/esp32s3_matrix/esp32s3_matrix-pinctrl.dtsi deleted file mode 100644 index 574a8cfcbbfaa..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix-pinctrl.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2024 Joel Guittet - * Copyright (c) 2025 Chen Xingyu - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -&pinctrl { - spim2_ws2812_led: spim2_ws2812_led { - group1 { - pinmux = ; - output-low; - }; - }; -}; diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.dts b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.dts deleted file mode 100644 index a327b2edbdf08..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2024 Joel Guittet - * Copyright (c) 2025 Chen Xingyu - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include - -/ { - model = "ESP32-S3-Matrix APPCPU"; - compatible = "waveshare,esp32-s3-matrix"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&flash0 { - reg = <0x0 DT_SIZE_M(4)>; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.yaml b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.yaml deleted file mode 100644 index 11ab49ad2b705..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32s3_matrix/esp32s3/appcpu -name: ESP32-S3-Matrix APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: waveshare diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu_defconfig b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu_defconfig deleted file mode 100644 index 6a13f9c9e3928..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_appcpu_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.dts b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.dts deleted file mode 100644 index a4d998cd8542e..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2024 Joel Guittet - * Copyright (c) 2025 Chen Xingyu - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "esp32s3_matrix-pinctrl.dtsi" - -/ { - model = "ESP32-S3-Matrix PROCPU"; - compatible = "waveshare,esp32-s3-matrix"; - - aliases { - sw0 = &button0; - watchdog0 = &wdt0; - led-strip = &led_strip; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &rgb_matrix; - zephyr,bt-hci = &esp32_bt_hci; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - rgb_matrix: rgb-matrix { - compatible = "led-strip-matrix"; - status = "okay"; - width = <8>; - height = <8>; - circulative; - led-strips = <&led_strip>; - }; -}; - -&flash0 { - reg = <0x0 DT_SIZE_M(4)>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi2 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&spim2_ws2812_led>; - pinctrl-names = "default"; - line-idle-low; - - led_strip: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - reg = <0>; - spi-max-frequency = ; - chain-length = <64>; - color-mapping = , - , - ; - spi-one-frame = ; - spi-zero-frame = ; - }; -}; - -&usb_serial { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&esp32_bt_hci { - status = "okay"; -}; diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.yaml b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.yaml deleted file mode 100644 index 8c4a14b4b0869..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: esp32s3_matrix/esp32s3/procpu -name: ESP32-S3-Matrix PROCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - spi - - watchdog - - pinmux - - nvs - - display -vendor: waveshare diff --git a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu_defconfig b/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu_defconfig deleted file mode 100644 index d01cb68ee6f67..0000000000000 --- a/boards/waveshare/esp32s3_matrix/esp32s3_matrix_esp32s3_procpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# Copyright (c) 2025 Chen Xingyu -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_GPIO=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/waveshare/esp32s3_matrix/support/openocd.cfg b/boards/waveshare/esp32s3_matrix/support/openocd.cfg deleted file mode 100644 index 625341a5aa87b..0000000000000 --- a/boards/waveshare/esp32s3_matrix/support/openocd.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Joel Guittet -# SPDX-License-Identifier: Apache-2.0 - -set ESP_RTOS none -set ESP32_ONLYCPU 1 - -# Source the JTAG interface configuration file -source [find interface/esp_usb_jtag.cfg] -# Source the ESP32-S3 configuration file -source [find target/esp32s3.cfg] diff --git a/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi index 045aebcb93ef4..db0d39f0ac1aa 100644 --- a/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi +++ b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi @@ -13,7 +13,6 @@ drive-push-pull; slew-rate = "max-speed-10mhz"; }; - group2 { pinmux = ; bias-pull-up; @@ -27,13 +26,4 @@ drive-open-drain; }; }; - - red_pwm_pinctrl: red_pwm_pinctrl { - group1 { - pinmux = ; - output-high; - drive-push-pull; - slew-rate = "max-speed-10mhz"; - }; - }; }; diff --git a/boards/wch/ch32v003evt/ch32v003evt.dts b/boards/wch/ch32v003evt/ch32v003evt.dts index c81a00fd30b39..fef72bcbd376e 100644 --- a/boards/wch/ch32v003evt/ch32v003evt.dts +++ b/boards/wch/ch32v003evt/ch32v003evt.dts @@ -7,7 +7,6 @@ #include #include "ch32v003evt-pinctrl.dtsi" -#include #include #include @@ -38,19 +37,8 @@ }; }; - pwmleds: pwmleds { - compatible = "pwm-leds"; - status = "disabled"; - - red_pwm: red_pwm0 { - pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - label = "Red LED"; - }; - }; - aliases { led0 = &red_led; - pwm-led0 = &red_pwm; }; }; diff --git a/boards/wch/ch32v006evt/Kconfig.ch32v006evt b/boards/wch/ch32v006evt/Kconfig.ch32v006evt deleted file mode 100644 index 5a75559928e75..0000000000000 --- a/boards/wch/ch32v006evt/Kconfig.ch32v006evt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 Michael Hope -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CH32V006EVT - select SOC_CH32V006 diff --git a/boards/wch/ch32v006evt/board.cmake b/boards/wch/ch32v006evt/board.cmake deleted file mode 100644 index 34bdc4d10d58c..0000000000000 --- a/boards/wch/ch32v006evt/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2025 Michael Hope -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(minichlink) -include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) - -board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/wch/ch32v006evt/board.yml b/boards/wch/ch32v006evt/board.yml deleted file mode 100644 index 2e63a7442f94f..0000000000000 --- a/boards/wch/ch32v006evt/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: ch32v006evt - full_name: WCH CH32V006EVT - vendor: wch - socs: - - name: ch32v006 diff --git a/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi b/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi deleted file mode 100644 index b01c11f9d1a17..0000000000000 --- a/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2025 Michael Hope - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - usart1_default: usart1_default { - group1 { - pinmux = ; - output-high; - drive-push-pull; - }; - - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - usart2_default: usart2_default { - group1 { - pinmux = ; - output-high; - drive-push-pull; - }; - - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , ; - output-high; - drive-open-drain; - }; - }; - - blue_pwm_pinctrl: blue_pwm_pinctrl { - group1 { - pinmux = ; - output-high; - drive-push-pull; - }; - }; -}; diff --git a/boards/wch/ch32v006evt/ch32v006evt.dts b/boards/wch/ch32v006evt/ch32v006evt.dts deleted file mode 100644 index 2cd0e20abeb0a..0000000000000 --- a/boards/wch/ch32v006evt/ch32v006evt.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2025 Michael Hope - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "ch32v006evt-pinctrl.dtsi" - -#include -#include -#include - -/ { - model = "ch32v006evt"; - compatible = "wch,ch32v006"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; - }; - - leds { - compatible = "gpio-leds"; - - /* - * Please connect the unconnected LED1 on the WCH CH32V006EVT - * board to PD0 and then change this status to "okay". - */ - status = "disabled"; - - blue_led1: led1 { - gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; - }; - - blue_led2: led2 { - gpios = <&gpioc 0 GPIO_ACTIVE_LOW>; - }; - }; - - pwmleds: pwmleds { - compatible = "pwm-leds"; - status = "disabled"; - - /* LED1 is on PD0 which does not have a PWM channel */ - - blue_pwm2: blue_pwm2 { - pwms = <&pwm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - label = "Blue LED 2"; - }; - }; - - aliases { - led0 = &blue_led1; - led1 = &blue_led2; - pwm-led0 = &blue_pwm2; - }; -}; - -&clk_hse { - clock-frequency = ; - status = "okay"; -}; - -&pll { - clocks = <&clk_hse>; - status = "okay"; -}; - -&rcc { - clocks = <&pll>; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&usart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&usart1_default>; - pinctrl-names = "default"; -}; diff --git a/boards/wch/ch32v006evt/ch32v006evt.yaml b/boards/wch/ch32v006evt/ch32v006evt.yaml deleted file mode 100644 index 493e236e5d2f7..0000000000000 --- a/boards/wch/ch32v006evt/ch32v006evt.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: ch32v006evt -name: WCH CH32V006 Evaluation Board -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -ram: 8 -flash: 62 -supported: - - gpio - - i2c - - pwm - - watchdog -vendor: wch diff --git a/boards/wch/ch32v006evt/ch32v006evt_defconfig b/boards/wch/ch32v006evt/ch32v006evt_defconfig deleted file mode 100644 index ab5b6c8458f34..0000000000000 --- a/boards/wch/ch32v006evt/ch32v006evt_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2025 Michael Hope -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp b/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp deleted file mode 100644 index 92e92f477ad0c..0000000000000 Binary files a/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp and /dev/null differ diff --git a/boards/wch/ch32v006evt/doc/index.rst b/boards/wch/ch32v006evt/doc/index.rst deleted file mode 100644 index eb0a2e944ec54..0000000000000 --- a/boards/wch/ch32v006evt/doc/index.rst +++ /dev/null @@ -1,87 +0,0 @@ -.. zephyr:board:: ch32v006evt - -Overview -******** - -The `WCH`_ CH32V006EVT is an evaluation board for the RISC-V based CH32V006K8U6 -SOC. - -The board is equipped with a power LED, reset button, USB port for power, and -two user LEDs. The `WCH webpage on CH32V006`_ contains the processor's -information and the datasheet. - -Hardware -******** - -The QingKe 32-bit RISC-V2C processor of the WCH CH32V006EVT is clocked by an -external crystal and runs at 48 MHz. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Connections and IOs -=================== - -LED ---- - -* LED1 = Unconnected. Connect to an I/O pin (PD0). -* LED2 = Unconnected. Connect to an I/O pin (PC0). - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``ch32v006evt`` board can be built and flashed -in the usual way (see :ref:`build_an_application` and :ref:`application_run` -for more details); however, an external programmer is required since the board -does not have any built-in debug support. - -Connect the programmer to the following pins on the PCB: - -* VCC = VCC (do not power the board from the USB port at the same time) -* GND = GND -* SWIO = PD1 - -Flashing -======== - -You can use minichlink_ to flash the board. Once ``minichlink`` has been set -up, build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ch32v006evt - :goals: build flash - -Debugging -========= - -This board can be debugged via OpenOCD or ``minichlink``. - -Testing the LED on the WCH CH32V006EVT -************************************** - -The ``blinky`` sample can be used to test that the LEDs on the board are working -properly with Zephyr: - -* :zephyr:code-sample:`blinky` - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/wch/ch32v006evt/ch32v006evt.dts`. - -References -********** - -.. target-notes:: - -.. _WCH: http://www.wch-ic.com -.. _WCH webpage on CH32V006: https://www.wch-ic.com/downloads/CH32V006DS0_PDF.html -.. _minichlink: https://github.com/cnlohr/ch32fun/tree/master/minichlink diff --git a/boards/wch/ch32v006evt/support/openocd.cfg b/boards/wch/ch32v006evt/support/openocd.cfg deleted file mode 100644 index 0d24d16ca2025..0000000000000 --- a/boards/wch/ch32v006evt/support/openocd.cfg +++ /dev/null @@ -1,15 +0,0 @@ -#interface wlink -adapter driver wlink -wlink_set -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 -set _FLASHNAME $_CHIPNAME.flash - -flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 - -echo "Ready for Remote Connections" diff --git a/boards/wch/linkw/linkw-pinctrl.dtsi b/boards/wch/linkw/linkw-pinctrl.dtsi index daef46d7c02b0..3cbd4ba16457b 100644 --- a/boards/wch/linkw/linkw-pinctrl.dtsi +++ b/boards/wch/linkw/linkw-pinctrl.dtsi @@ -13,7 +13,6 @@ drive-push-pull; slew-rate = "max-speed-10mhz"; }; - group2 { pinmux = ; bias-pull-up; diff --git a/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 b/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 deleted file mode 100644 index 66780c65f0a8a..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLUEPILLPLUS_CH32V203 - select SOC_CH32V203 diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi deleted file mode 100644 index f30b18d1fc16b..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - usart3_default: usart3_default { - group1 { - pinmux = ; - output-high; - drive-push-pull; - slew-rate = "max-speed-10mhz"; - }; - - group2 { - pinmux = ; - bias-pull-up; - }; - }; -}; diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts deleted file mode 100644 index 217896b541a87..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include -#include "bluepillplus_ch32v203-pinctrl.dtsi" - -/ { - model = "bluepillplus_ch32v203"; - compatible = "wch,ch32v203"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &usart3; - zephyr,shell-uart = &usart3; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - blue_led: led0 { - gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; - }; - }; - - buttons { - compatible = "gpio-keys"; - - mode: sw0 { - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - zephyr,code = ; - }; - }; - - aliases { - led0 = &blue_led; - sw0 = &mode; - }; -}; - -&clk_hse { - clock-frequency = ; - status = "okay"; -}; - -&pll { - clocks = <&clk_hse>; - status = "okay"; -}; - -&rcc { - clocks = <&pll>; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&usart3 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&usart3_default>; - pinctrl-names = "default"; -}; diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml deleted file mode 100644 index e1a2745db9896..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: bluepillplus_ch32v203 -name: WeActStudio BluePill Plus CH32V203 -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -ram: 20 -flash: 224 -supported: - - gpio diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig deleted file mode 100644 index f635cc36f4ce8..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_GPIO=y - -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/weact/bluepillplus_ch32v203/board.cmake b/boards/weact/bluepillplus_ch32v203/board.cmake deleted file mode 100644 index e8573f4798c84..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(minichlink) -include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) - -board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/weact/bluepillplus_ch32v203/board.yml b/boards/weact/bluepillplus_ch32v203/board.yml deleted file mode 100644 index bde9d0cedd434..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: bluepillplus_ch32v203 - full_name: BluePill Plus CH32V203 - vendor: weact - socs: - - name: ch32v203 diff --git a/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp b/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp deleted file mode 100644 index 726d6eeeba3c6..0000000000000 Binary files a/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp and /dev/null differ diff --git a/boards/weact/bluepillplus_ch32v203/doc/index.rst b/boards/weact/bluepillplus_ch32v203/doc/index.rst deleted file mode 100644 index 03ab74f86204d..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/doc/index.rst +++ /dev/null @@ -1,87 +0,0 @@ -.. zephyr:board:: bluepillplus_ch32v203 - -Overview -******** - -The `WeActStudio`_ BluePill Plus CH32V203 hardware provides support for QingKe 32-bit RISC-V4B -processor and the following devices: - -* CLOCK -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`UART (Universal Asynchronous Receiver-Transmitter)` - -The board is equipped with two LEDs and three Buttons. -User can use one of the LEDs and one of the buttons. -The `WCH webpage on CH32V203`_ contains the processor's manuals. -The `WeActStudio webpage on BPP`_ contains the BluePill's schematic. - -Hardware -******** - -The QingKe V4B 32-bit RISC-V processor of the BluePill Plus CH32V203 is clocked by an external -8 MHz crystal or the internal 8 MHz oscillator and runs up to 144 MHz. -The CH32V203 SoC Features 2-4 USART, 4 GPIO ports, 1-2 SPI, 0-2 I2C, 9-16 ADC, RTC, -CAN, USB Device, USB Host, OPA, and several timers. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Connections and IOs -=================== - -LED ---- - -* LED0 = Blue User LED - -Button ------- - -* SW0 = User Button - -Programming and Debugging -************************* - -Applications for the ``bluepillplus_ch32v203`` board can be built and flashed -in the usual way (see :ref:`build_an_application` and :ref:`application_run` -for more details); however, an external programmer is required since the board -does not have any built-in debug support. - -The following pins of the external programmer must be connected to the -following pins on the PCB: - -* VCC = VCC -* GND = GND -* SWIO = PA13 -* SWCLK = PA14 - -Flashing -======== - -You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set -up, build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: bluepillplus_ch32v203 - :goals: build flash - -Debugging -========= - -This board can be debugged via OpenOCD or ``minichlink``. - -References -********** - -.. target-notes:: - -.. _WeActStudio: https://github.com/WeActStudio -.. _WCH webpage on CH32V203: https://www.wch-ic.com/products/CH32V203.html -.. _WeActStudio webpage on BPP: https://github.com/WeActStudio/WeActStudio.BluePill-Plus-CH32 diff --git a/boards/weact/bluepillplus_ch32v203/support/openocd.cfg b/boards/weact/bluepillplus_ch32v203/support/openocd.cfg deleted file mode 100644 index 65a43f18a1697..0000000000000 --- a/boards/weact/bluepillplus_ch32v203/support/openocd.cfg +++ /dev/null @@ -1,20 +0,0 @@ -# Tested with WCH openOCD liberated fork (https://github.com/jnk0le/openocd-wch) -# Copyright (c) 2024 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 -adapter driver wlinke -adapter speed 6000 -transport select sdi - -wlink_set_address 0x00000000 -set _CHIPNAME wch_riscv -sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 -set _FLASHNAME $_CHIPNAME.flash - -flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 - -echo "Ready for Remote Connections" diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.dts b/boards/weact/mini_stm32h743/mini_stm32h743.dts index 28957875b044d..abec39683d407 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743.dts +++ b/boards/weact/mini_stm32h743/mini_stm32h743.dts @@ -146,7 +146,6 @@ &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpiod 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts index f5de87d704e8d..cce16f72fc30f 100644 --- a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts +++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts @@ -123,7 +123,6 @@ &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpiod 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core.dts b/boards/weact/stm32f405_core/weact_stm32f405_core.dts index 0906fcc01c25a..ba9090bf35496 100644 --- a/boards/weact/stm32f405_core/weact_stm32f405_core.dts +++ b/boards/weact/stm32f405_core/weact_stm32f405_core.dts @@ -112,7 +112,6 @@ &sdio_ck_pc12 &sdio_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; - disk-name = "SD"; }; &rtc { diff --git a/boards/weact/stm32h5_core/weact_stm32h5_core.dts b/boards/weact/stm32h5_core/weact_stm32h5_core.dts index 7c38a553f535c..1d39eea4c2018 100644 --- a/boards/weact/stm32h5_core/weact_stm32h5_core.dts +++ b/boards/weact/stm32h5_core/weact_stm32h5_core.dts @@ -54,7 +54,6 @@ cd-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; - disk-name = "SD"; status = "okay"; }; diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts index a6b9bf85b7f49..0453b7ab568f1 100644 --- a/boards/witte/linum/linum.dts +++ b/boards/witte/linum/linum.dts @@ -345,7 +345,6 @@ zephyr_udc0: &usbotg_fs { &sdmmc1_cmd_pd2>; pinctrl-names = "default"; cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>; - disk-name = "SD"; status = "okay"; disk { diff --git a/boards/wiznet/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst index 5fc3ee271f9ec..c05edf5a81895 100644 --- a/boards/wiznet/w5500_evb_pico/doc/index.rst +++ b/boards/wiznet/w5500_evb_pico/doc/index.rst @@ -76,16 +76,152 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. -See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. +Flashing +======== -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. +Using SEGGER JLink +------------------ + +You can Flash the w5500_evb_pico with a SEGGER JLink debug probe as described in +:ref:`Building, Flashing and Debugging `. + +Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: w5500_evb_pico + :goals: build + +.. code-block:: bash + + west flash --runner jlink + +Using OpenOCD +------------- + +To use PicoProbe, You must configure **udev**. + +Create a file in /etc/udev.rules.d with any name, and write the line below. + +.. code-block:: bash + + ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" + +This example is valid for the case that the user joins to ``plugdev`` groups. + +The Raspberry Pi Pico, and thus the W55500 Evaluation Board, has an SWD +interface that can be used to program and debug the on board RP2040. This +interface can be utilized by OpenOCD. To use it with the RP2040, OpenOCD +version 0.12.0 or later is needed. + +If you are using a Debian based system (including Raspberry Pi OS, Ubuntu, and +more), using the `pico_setup.sh`_ script is a convenient way to set up the +forked version of OpenOCD. + +Depending on the interface used (such as JLink), you might need to +checkout to a branch that supports this interface, before proceeding. +Build and install OpenOCD as described in the README. + +Here is an example of building and flashing the :zephyr:code-sample:`blinky` +application. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky :board: w5500_evb_pico :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=picoprobe + +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` and +**OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should +work with the OpenOCD that was installed with the default configuration. This +configuration also works with an environment that is set up by the +`pico_setup.sh`_ script. + +**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. + +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``picoprobe`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and +``blackmagicprobe``. How to connect ``picoprobe`` and ``raspberrypi-swd`` is +described in `Getting Started with Raspberry Pi Pico`_. Any other SWD debug +adapter maybe also work with this configuration. + +The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from +``west flash`` and ``west debug`` if it was previously set while running +``west build``. + +**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as +``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, +**RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug +adapter. + +You can also flash the board with the following +command that directly calls OpenOCD (assuming a SEGGER JLink adapter is used): + +.. code-block:: console + + $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' -c 'program path/to/zephyr.elf verify reset exit' + +Using UF2 +--------- + +If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with +a UF2 file. By default, building an app for this board will generate a +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` +button pressed, it will appear on the host as a mass storage device. The +UF2 file should be drag-and-dropped to the device, which will flash the Pico. + +Debugging +========= + +The SWD interface can also be used to debug the board. To achieve this, you can +either use SEGGER JLink or OpenOCD. + +Using SEGGER JLink +------------------ + +Use a SEGGER JLink debug probe and follow the instruction in +:ref:`Building, Flashing and Debugging`. + + +Using OpenOCD +------------- + +Install OpenOCD as described for flashing the board. + +Here is an example for debugging the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: w5500_evb_pico + :maybe-skip-config: + :goals: debug + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd + +As with flashing, you can specify the debug adapter by specifying +**RPI_PICO_DEBUG_ADAPTER** at ``west build`` time. No needs to specify it at +``west debug`` time. + +You can also debug with OpenOCD and gdb launching from command-line. +Run the following command: + +.. code-block:: console + + $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' + +On another terminal, run: + +.. code-block:: console + + $ gdb-multiarch + +Inside gdb, run: + +.. code-block:: console + + (gdb) tar ext :3333 + (gdb) file path/to/zephyr.elf + +You can then start debugging the board. .. target-notes:: diff --git a/boards/wiznet/w5500_evb_pico2/doc/index.rst b/boards/wiznet/w5500_evb_pico2/doc/index.rst index 4e728fddc4d43..4ddcdd8d7f66e 100644 --- a/boards/wiznet/w5500_evb_pico2/doc/index.rst +++ b/boards/wiznet/w5500_evb_pico2/doc/index.rst @@ -77,16 +77,54 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. -See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. +Flashing +======== -Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. +Using OpenOCD +------------- + +The overall explanation regarding flashing and debugging is the same as or +``rpi_pico``. +See :ref:`rpi_pico_flashing_using_openocd`. in ``rpi_pico`` documentation. + +A typical build command for w5500_evb_pico2 is as follows. +This assumes a CMSIS-DAP adapter such as the Raspberry Pi Debug Probe, +but if you are using something else, specify ``RPI_PICO_DEBUG_ADAPTER``. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: w5500_evb_pico2/rp2350a/m33 + :board: w5500_evb_pico2 :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd + :gen-args: -DOPENOCD=/usr/local/bin/openocd + +Using UF2 +--------- + +If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with +a UF2 file. By default, building an app for this board will generate a +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` +button pressed, it will appear on the host as a mass storage device. The +UF2 file should be drag-and-dropped to the device, which will flash the Pico. + +Debugging +========= + +The SWD interface can also be used to debug the board. To achieve this, you can +either use SEGGER JLink or OpenOCD. + +Using OpenOCD +------------- + +Install OpenOCD as described for flashing the board. + +Here is an example for debugging the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: w5500_evb_pico2 + :maybe-skip-config: + :goals: debug + :gen-args: -DOPENOCD=/usr/local/bin/openocd .. target-notes:: diff --git a/cmake/bintools/gnu/target_bintools.cmake b/cmake/bintools/gnu/target_bintools.cmake index 2abe7d321ab96..6bbe8f8a3cf05 100644 --- a/cmake/bintools/gnu/target_bintools.cmake +++ b/cmake/bintools/gnu/target_bintools.cmake @@ -27,8 +27,8 @@ set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_OBJCOPY}) # List of format the tool supports for converting, for example, -# GNU tools uses objectcopy, which supports the following: ihex, srec, binary, mot -set_property(TARGET bintools PROPERTY elfconvert_formats ihex srec binary mot) +# GNU tools uses objectcopy, which supports the following: ihex, srec, binary +set_property(TARGET bintools PROPERTY elfconvert_formats ihex srec binary) set_property(TARGET bintools PROPERTY elfconvert_flag "") set_property(TARGET bintools PROPERTY elfconvert_flag_final "") diff --git a/cmake/compiler/gcc/compiler_flags.cmake b/cmake/compiler/gcc/compiler_flags.cmake index 53b42823717f5..48afd244ac72a 100644 --- a/cmake/compiler/gcc/compiler_flags.cmake +++ b/cmake/compiler/gcc/compiler_flags.cmake @@ -197,10 +197,6 @@ if(NOT CONFIG_NO_OPTIMIZATIONS) set_compiler_property(PROPERTY security_fortify_run_time _FORTIFY_SOURCE=2) endif() -check_set_compiler_property(PROPERTY sanitizer_undefined -fsanitize=undefined) -check_set_compiler_property(PROPERTY sanitizer_undefined_trap -fsanitize-undefined-trap-on-error) -check_set_compiler_property(PROPERTY sanitizer_undefined_library) - # gcc flag for a hosted (no-freestanding) application check_set_compiler_property(APPEND PROPERTY hosted -fno-freestanding) diff --git a/cmake/compiler/gcc/target.cmake b/cmake/compiler/gcc/target.cmake index 65e37d4bc5ec4..2e90f00f659de 100644 --- a/cmake/compiler/gcc/target.cmake +++ b/cmake/compiler/gcc/target.cmake @@ -78,8 +78,6 @@ elseif("${ARCH}" STREQUAL "mips") include(${CMAKE_CURRENT_LIST_DIR}/target_mips.cmake) elseif("${ARCH}" STREQUAL "xtensa") include(${CMAKE_CURRENT_LIST_DIR}/target_xtensa.cmake) -elseif("${ARCH}" STREQUAL "rx") - include(${CMAKE_CURRENT_LIST_DIR}/target_rx.cmake) endif() if(SYSROOT_DIR) diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake index 95ef3f63c9fbf..81ed0cafedf55 100644 --- a/cmake/compiler/gcc/target_riscv.cmake +++ b/cmake/compiler/gcc/target_riscv.cmake @@ -81,11 +81,6 @@ if(CONFIG_RISCV_ISA_EXT_ZBS) string(CONCAT riscv_march ${riscv_march} "_zbs") endif() -if(CONFIG_RISCV_ISA_EXT_ZMMUL AND - "${GCC_COMPILER_VERSION}" VERSION_GREATER_EQUAL 13.0.0) - string(CONCAT riscv_march ${riscv_march} "_zmmul") -endif() - list(APPEND TOOLCHAIN_C_FLAGS -mabi=${riscv_mabi} -march=${riscv_march}) list(APPEND TOOLCHAIN_LD_FLAGS NO_SPLIT -mabi=${riscv_mabi} -march=${riscv_march}) diff --git a/cmake/compiler/gcc/target_rx.cmake b/cmake/compiler/gcc/target_rx.cmake deleted file mode 100644 index 6911b0cda7256..0000000000000 --- a/cmake/compiler/gcc/target_rx.cmake +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -list(APPEND TOOLCHAIN_C_FLAGS) -list(APPEND TOOLCHAIN_C_FLAGS -mlittle-endian-data -ffunction-sections -fdata-sections) - -list(APPEND TOOLCHAIN_LD_FLAGS) -list(APPEND TOOLCHAIN_LD_FLAGS -mlittle-endian-data) - -if(NOT CONFIG_PICOLIBC) - list(APPEND TOOLCHAIN_LD_FLAGS -lm) -endif() - -if(NOT CONFIG_FPU) - list(APPEND TOOLCHAIN_C_FLAGS -nofpu) -endif() - -if("cross-compile" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) - if(CONFIG_CPU_RXV1) - list(APPEND TOOLCHAIN_C_FLAGS -misa=v1) - list(APPEND TOOLCHAIN_LD_FLAGS -misa=v1) - elseif(CONFIG_CPU_RXV2) - list(APPEND TOOLCHAIN_C_FLAGS -misa=v2) - list(APPEND TOOLCHAIN_LD_FLAGS -misa=v2) - else() - list(APPEND TOOLCHAIN_C_FLAGS -misa=v3) - list(APPEND TOOLCHAIN_LD_FLAGS -misa=v3) - endif() -elseif("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) - if(CONFIG_SOC_SERIES_RX130) - list(APPEND TOOLCHAIN_C_FLAGS -mcpu=rx100) - list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=rx100) - elseif(CONFIG_SOC_SERIES_RX62N) - list(APPEND TOOLCHAIN_C_FLAGS -mcpu=rx600) - list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=rx600) - endif() -endif() diff --git a/cmake/compiler/gcc/target_x86.cmake b/cmake/compiler/gcc/target_x86.cmake index a2c9f8290009e..8dac67a006863 100644 --- a/cmake/compiler/gcc/target_x86.cmake +++ b/cmake/compiler/gcc/target_x86.cmake @@ -15,28 +15,6 @@ else() endif() endif() -# Flags not supported by llext linker -# (regexps are supported and match whole word) -set(LLEXT_REMOVE_FLAGS - -fno-pic - -fno-pie - -ffunction-sections - -fdata-sections - -g.* - -Os -) - -# Force compiler and linker match -if(CONFIG_X86_64) - set(LLEXT_APPEND_FLAGS - -m64 - ) -else() - set(LLEXT_APPEND_FLAGS - -m32 - ) -endif() - # GNU Assembler, by default on non-Linux targets, treats slashes as # start of comments on i386. # (https://sourceware.org/binutils/docs-2.33.1/as/i386_002dChars.html#i386_002dChars) diff --git a/cmake/emu/armfvp.cmake b/cmake/emu/armfvp.cmake index 1b0307d58ead3..354cc43cbcf10 100644 --- a/cmake/emu/armfvp.cmake +++ b/cmake/emu/armfvp.cmake @@ -1,4 +1,4 @@ -# Copyright (c) 2021-2022, 2025 Arm Limited (or its affiliates). All rights reserved. +# Copyright (c) 2021-2022 Arm Limited (or its affiliates). All rights reserved. # SPDX-License-Identifier: Apache-2.0 find_program( @@ -53,7 +53,7 @@ elseif(CONFIG_ARMV8_A_NS) --data cluster0.cpu0="${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME}"@0x88000000 ) else() - string(FIND "${ARMFVP_FLAGS}" "-a;" ARMFVP_APPARG_POS) + string(FIND "${ARMFVP_FLAGS}" " -a " ARMFVP_APPARG_POS) if(${ARMFVP_APPARG_POS} EQUAL -1) set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} diff --git a/cmake/emu/qemu.cmake b/cmake/emu/qemu.cmake index 25acaf02fdc4f..11dead318fbb5 100644 --- a/cmake/emu/qemu.cmake +++ b/cmake/emu/qemu.cmake @@ -282,7 +282,7 @@ elseif(QEMU_NET_STACK) endif() endif(QEMU_PIPE_STACK) -if(CONFIG_CAN AND NOT (CONFIG_SOC_LEON3)) +if(CONFIG_CAN AND NOT (CONFIG_NIOS2 OR CONFIG_SOC_LEON3)) # Add CAN bus 0 list(APPEND QEMU_FLAGS -object can-bus,id=canbus0) diff --git a/cmake/emu/simics.cmake b/cmake/emu/simics.cmake index 5c5c7b8269453..1c5cc3f96ea1e 100644 --- a/cmake/emu/simics.cmake +++ b/cmake/emu/simics.cmake @@ -24,8 +24,6 @@ else() get_property(SIMICS_ARGS GLOBAL PROPERTY "BOARD_EMU_ARGS_simics") - file(REAL_PATH $ENV{SIMICS_PROJECT} simics_project_dir_real) - add_custom_target(run_simics COMMAND ${SIMICS} @@ -36,7 +34,7 @@ else() ${SIMICS_ARGS} $ENV{SIMICS_EXTRA_ARGS} -e run - WORKING_DIRECTORY ${simics_project_dir_real} + WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} DEPENDS ${logical_target_for_zephyr_elf} USES_TERMINAL ) diff --git a/cmake/flash/CMakeLists.txt b/cmake/flash/CMakeLists.txt index 8b2f17aff954d..d1f0d17da6e8d 100644 --- a/cmake/flash/CMakeLists.txt +++ b/cmake/flash/CMakeLists.txt @@ -60,10 +60,6 @@ function(runners_yaml_append_config) get_runners_prop(uf2_file uf2 "${KERNEL_UF2_NAME}") runners_yaml_append(" uf2_file: ${uf2}") endif() - if(CONFIG_BUILD_OUTPUT_MOT) - get_runners_prop(mot_file mot "${KERNEL_MOT_NAME}") - runners_yaml_append(" mot_file: ${mot}") - endif() zephyr_get(OPENOCD) zephyr_get(OPENOCD_DEFAULT_PATH) diff --git a/cmake/kobj.cmake b/cmake/kobj.cmake index 6ccb85245fc5c..22fa36ae44af4 100644 --- a/cmake/kobj.cmake +++ b/cmake/kobj.cmake @@ -1,66 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -find_program(GEN_KOBJECT_LIST NAMES gen_kobject_list gen_kobject_list.py PATHS ${ZEPHYR_BASE}/scripts/build) -message(STATUS "Found gen_kobject_list: ${GEN_KOBJECT_LIST}") -if(GEN_KOBJECT_LIST MATCHES "\.py$") - set(GEN_KOBJECT_LIST_INTERPRETER ${PYTHON_EXECUTABLE}) -endif() - -# Invokes gen_kobject_list.py with the given SCRIPT_ARGS, creating a TARGET that depends on the -# script's OUTPUTS -function(gen_kobject_list) - cmake_parse_arguments(PARSE_ARGV 0 arg - "" - "TARGET" - "OUTPUTS;SCRIPT_ARGS;INCLUDES;DEPENDS" - ) - foreach(include ${arg_INCLUDES}) - list(APPEND arg_SCRIPT_ARGS --include-subsystem-list ${include}) - endforeach() - add_custom_command( - OUTPUT ${arg_OUTPUTS} - COMMAND - ${GEN_KOBJECT_LIST_INTERPRETER} - ${GEN_KOBJECT_LIST} - ${arg_SCRIPT_ARGS} - $<$:--verbose> - DEPENDS - ${arg_DEPENDS} - ${GEN_KOBJECT_LIST} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - add_custom_target(${arg_TARGET} DEPENDS ${arg_OUTPUTS}) -endfunction() - -# Generates a gperf header file named OUTPUT using the symbols found in the KERNEL_TARGET's output -# binary. INCLUDES is a list of JSON files defining kernel subsystems and sockets. -function(gen_kobject_list_gperf) - cmake_parse_arguments(PARSE_ARGV 0 arg - "" - "TARGET;OUTPUT;KERNEL_TARGET" - "INCLUDES;DEPENDS" - ) - gen_kobject_list( - TARGET ${arg_TARGET} - OUTPUTS ${arg_OUTPUT} - SCRIPT_ARGS - --kernel $ - --gperf-output ${arg_OUTPUT} - INCLUDES ${arg_INCLUDES} - DEPENDS - ${arg_DEPENDS} - ${arg_KERNEL_TARGET} - ) -endfunction() - -# Generates header files describing the kernel subsystems defined by the JSON files in INCLUDES. The -# variable named by GEN_DIR_OUT_VAR is set to the directory containing the header files. -function(gen_kobject_list_headers) - cmake_parse_arguments(PARSE_ARGV 0 arg - "" - "GEN_DIR_OUT_VAR" - "INCLUDES;DEPENDS" - ) +function(gen_kobj gen_dir_out) if (PROJECT_BINARY_DIR) set(gen_dir ${PROJECT_BINARY_DIR}/include/generated/zephyr) else () @@ -73,21 +13,24 @@ function(gen_kobject_list_headers) file(MAKE_DIRECTORY ${gen_dir}) - gen_kobject_list( - TARGET ${KOBJ_TYPES_H_TARGET} - OUTPUTS ${KOBJ_TYPES} ${KOBJ_OTYPE} ${KOBJ_SIZE} - SCRIPT_ARGS - --kobj-types-output ${KOBJ_TYPES} - --kobj-otype-output ${KOBJ_OTYPE} - --kobj-size-output ${KOBJ_SIZE} - INCLUDES ${arg_INCLUDES} + add_custom_command( + OUTPUT ${KOBJ_TYPES} ${KOBJ_OTYPE} ${KOBJ_SIZE} + COMMAND + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py + --kobj-types-output ${KOBJ_TYPES} + --kobj-otype-output ${KOBJ_OTYPE} + --kobj-size-output ${KOBJ_SIZE} + ${gen_kobject_list_include_args} + $<$:--verbose> DEPENDS - ${arg_DEPENDS} - ${arg_KERNEL_TARGET} - ) + ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py + ${PARSE_SYSCALLS_TARGET} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + add_custom_target(${KOBJ_TYPES_H_TARGET} DEPENDS ${KOBJ_TYPES} ${KOBJ_OTYPE}) + + cmake_path(GET gen_dir PARENT_PATH gen_dir) + set(${gen_dir_out} ${gen_dir} PARENT_SCOPE) - if(arg_GEN_DIR_OUT_VAR) - cmake_path(GET gen_dir PARENT_PATH gen_dir) - set(${arg_GEN_DIR_OUT_VAR} ${gen_dir} PARENT_SCOPE) - endif() endfunction () diff --git a/cmake/linker/iar/config_file_script.cmake b/cmake/linker/iar/config_file_script.cmake index 1c9db88bc3565..9d430d5b219fe 100644 --- a/cmake/linker/iar/config_file_script.cmake +++ b/cmake/linker/iar/config_file_script.cmake @@ -333,7 +333,7 @@ function(group_to_string) endif() set(${STRING_STRING} "${${STRING_STRING}}\"${name}\": place in ${ILINK_CURRENT_NAME} { block ${name_clean} };\n") - if(CONFIG_IAR_ZEPHYR_INIT AND DEFINED vma AND DEFINED lma AND NOT ${noinit}) + if(DEFINED vma AND DEFINED lma AND NOT ${noinit}) set(${STRING_STRING} "${${STRING_STRING}}\"${name}_init\": place in ${lma} { block ${name_clean}_init };\n") endif() @@ -792,51 +792,32 @@ function(section_to_string) list(JOIN current_sections ", " SELECTORS) set(TEMP "${TEMP}\ndo not initialize {\n${SELECTORS}\n};") else() - + # Generate the _init block and the initialize manually statement. + # Note that we need to have the X_init block defined even if we have + # no sections, since there will come a "place in XXX" statement later. + + # "${TEMP}" is there too keep the ';' else it will be a list + string(REGEX REPLACE "(block[ \t\r\n]+)([^ \t\r\n]+)" "\\1\\2_init" INIT_TEMP "${TEMP}") + string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)([^ \t\r\n,]+)" "\\1\\2\\3\\4_init" INIT_TEMP "${INIT_TEMP}") + string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)" "ro\\2\\3" INIT_TEMP "${INIT_TEMP}") + string(REGEX REPLACE "alphabetical order, " "" INIT_TEMP "${INIT_TEMP}") + string(REGEX REPLACE "{ readwrite }" "{ }" INIT_TEMP "${INIT_TEMP}") + + # If any content is marked as keep, is has to be applied to the init block + # too, esp. for blocks that are not referenced (e.g. empty blocks wiht min_size) + if(to_be_kept) + list(APPEND to_be_kept "block ${name_clean}_init") + endif() + set(TEMP "${TEMP}\n${INIT_TEMP}\n") if(DEFINED current_sections) - if(CONFIG_IAR_DATA_INIT) - set(TEMP "${TEMP}\ninitialize by copy\n") - set(TEMP "${TEMP}{\n") - foreach(section ${current_sections}) - set(TEMP "${TEMP} ${section},\n") - endforeach() - set(TEMP "${TEMP}};") - - set(TEMP "${TEMP}\n\"${name}_init\": place in ${group_parent_lma} {\n") - foreach(section ${current_sections}) - set(TEMP "${TEMP} ${section}_init,\n") - endforeach() - set(TEMP "${TEMP}};") - elseif(CONFIG_IAR_ZEPHYR_INIT) - # Generate the _init block and the initialize manually statement. - # Note that we need to have the X_init block defined even if we have - # no sections, since there will come a "place in XXX" statement later. - - # "${TEMP}" is there too keep the ';' else it will be a list - string(REGEX REPLACE "(block[ \t\r\n]+)([^ \t\r\n]+)" "\\1\\2_init" INIT_TEMP "${TEMP}") - string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)([^ \t\r\n,]+)" "\\1\\2\\3\\4_init" INIT_TEMP "${INIT_TEMP}") - string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)" "ro\\2\\3" INIT_TEMP "${INIT_TEMP}") - string(REGEX REPLACE "alphabetical order, " "" INIT_TEMP "${INIT_TEMP}") - string(REGEX REPLACE "{ readwrite }" "{ }" INIT_TEMP "${INIT_TEMP}") - - # If any content is marked as keep, is has to be applied to the init block - # too, esp. for blocks that are not referenced (e.g. empty blocks wiht min_size) - if(to_be_kept) - list(APPEND to_be_kept "block ${name_clean}_init") - endif() - set(TEMP "${TEMP}\n${INIT_TEMP}\n") - set(TEMP "${TEMP}\ninitialize manually with copy friendly\n") - set(TEMP "${TEMP}{\n") - foreach(section ${current_sections}) - set(TEMP "${TEMP} ${section},\n") - endforeach() - set(TEMP "${TEMP}};") - set(current_sections) - endif() + set(TEMP "${TEMP}\ninitialize manually with copy friendly\n") + set(TEMP "${TEMP}{\n") + foreach(section ${current_sections}) + set(TEMP "${TEMP} ${section},\n") + endforeach() + set(TEMP "${TEMP}};") + set(current_sections) endif() - - set(current_sections) - endif() endif() diff --git a/cmake/linker/iar/linker_flags.cmake b/cmake/linker/iar/linker_flags.cmake index 96710e4cc90d5..f65925ff8a894 100644 --- a/cmake/linker/iar/linker_flags.cmake +++ b/cmake/linker/iar/linker_flags.cmake @@ -4,11 +4,8 @@ # Override the default CMake's IAR ILINK linker signature -string(APPEND CMAKE_C_LINK_FLAGS --no-wrap-diagnostics) +string(APPEND CMAKE_C_LINK_FLAGS --no-wrap-diagnostics ) -if(CONFIG_IAR_DATA_INIT) - string(APPEND CMAKE_C_LINK_FLAGS " --redirect z_data_copy=__iar_data_init3") -endif() foreach(lang C CXX ASM) set(commands "--log modules,libraries,initialization,redirects,sections") set(CMAKE_${lang}_LINK_EXECUTABLE diff --git a/cmake/linker/iar/target.cmake b/cmake/linker/iar/target.cmake index 3553b1f196c57..f2326b60491aa 100644 --- a/cmake/linker/iar/target.cmake +++ b/cmake/linker/iar/target.cmake @@ -10,10 +10,6 @@ find_program(CMAKE_LINKER NO_DEFAULT_PATH ) -if(CONFIG_IAR_DATA_INIT) - zephyr_linker_section(NAME .iar.init_table KVMA RAM_REGION GROUP RODATA_REGION) -endif() - add_custom_target(${IAR_LINKER}) set(ILINK_THUMB_CALLS_WARNING_SUPPRESSED) set(IAR_LIB_USED) @@ -65,8 +61,6 @@ macro(configure_linker_script linker_script_gen linker_pass_define) ${STEERING_FILE_ARG} -DCONFIG_LINKER_LAST_SECTION_ID=${CONFIG_LINKER_LAST_SECTION_ID} -DCONFIG_LINKER_LAST_SECTION_ID_PATTERN=${CONFIG_LINKER_LAST_SECTION_ID_PATTERN} - -DCONFIG_IAR_DATA_INIT=${CONFIG_IAR_DATA_INIT} - -DCONFIG_IAR_ZEPHYR_INIT=${CONFIG_IAR_ZEPHYR_INIT} -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen} ${IAR_LIB_USED} -P ${ZEPHYR_BASE}/cmake/linker/iar/config_file_script.cmake diff --git a/cmake/linker/ld/linker_flags.cmake b/cmake/linker/ld/linker_flags.cmake index 885a1844cc5d6..0e0e8b6b0a107 100644 --- a/cmake/linker/ld/linker_flags.cmake +++ b/cmake/linker/ld/linker_flags.cmake @@ -24,10 +24,6 @@ check_set_linker_property(TARGET linker PROPERTY orphan_error check_set_linker_property(TARGET linker PROPERTY memusage "${LINKERFLAGPREFIX},--print-memory-usage") -check_set_linker_property(TARGET linker PROPERTY sanitizer_undefined -fsanitize=undefined) -check_set_linker_property(TARGET linker PROPERTY sanitizer_undefined_trap -fsanitize-undefined-trap-on-error) -check_set_linker_property(TARGET linker PROPERTY sanitizer_undefined_library) - # -no-pie is not supported until binutils 2.37. # If -no-pie is passed to old binutils <= 2.36, it is parsed # as separate arguments -n and -o, which results in output file diff --git a/cmake/linker_script/common/kobject-text.cmake b/cmake/linker_script/common/kobject-text.cmake index 10d33e21a01cf..9fdf08b478f51 100644 --- a/cmake/linker_script/common/kobject-text.cmake +++ b/cmake/linker_script/common/kobject-text.cmake @@ -24,4 +24,25 @@ if(CONFIG_USERSPACE) EXPR "(@_kobject_text_area_end@ - @_kobject_text_area_start@)" ) -endif() + + if(CONFIG_DYNAMIC_OBJECTS) + zephyr_linker_section_configure( + SECTION + _kobject_text_area + SYMBOLS + z_object_gperf_find + z_object_gperf_wordlist_foreach + PASS NOT LINKER_ZEPHYR_FINAL + ) + else() + zephyr_linker_section_configure( + SECTION + _kobject_text_area + SYMBOLS + k_object_find + k_object_wordlist_foreach + PASS NOT LINKER_ZEPHYR_FINAL + ) + endif() + +endif() \ No newline at end of file diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index bd14a678ef573..41e79dd733792 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -290,21 +290,11 @@ set_property(DIRECTORY APPEND PROPERTY # Run GEN_EDT_SCRIPT. # -if(WEST_TOPDIR) - set(GEN_EDT_WORKSPACE_DIR ${WEST_TOPDIR}) -else() - # If West is not available, define the parent directory of ZEPHYR_BASE as - # the workspace. This will create comments that reference the files in the - # Zephyr tree with a 'zephyr/' prefix. - set(GEN_EDT_WORKSPACE_DIR ${ZEPHYR_BASE}/..) -endif() - string(REPLACE ";" " " EXTRA_DTC_FLAGS_RAW "${EXTRA_DTC_FLAGS}") set(CMD_GEN_EDT ${PYTHON_EXECUTABLE} ${GEN_EDT_SCRIPT} --dts ${DTS_POST_CPP} --dtc-flags '${EXTRA_DTC_FLAGS_RAW}' --bindings-dirs ${DTS_ROOT_BINDINGS} ---workspace-dir ${GEN_EDT_WORKSPACE_DIR} --dts-out ${ZEPHYR_DTS}.new # for debugging and dtc --edt-pickle-out ${EDT_PICKLE}.new ${EXTRA_GEN_EDT_ARGS} diff --git a/cmake/modules/kconfig.cmake b/cmake/modules/kconfig.cmake index 65b3bbb0382c7..d4d22508d0b79 100644 --- a/cmake/modules/kconfig.cmake +++ b/cmake/modules/kconfig.cmake @@ -66,14 +66,6 @@ if(DEFINED BOARD_REVISION) message(DEPRECATION "Use of '${board_rev_file}.conf' is deprecated, please switch to '${board_rev_file}_defconfig'") set_ifndef(BOARD_REVISION_CONFIG ${BOARD_DIR}/${board_rev_file}.conf) endif() - - # Generate boolean board revision kconfig option - zephyr_string(SANITIZE TOUPPER BOARD_REVISION_GEN_CONFIG_VAR "BOARD_REVISION_${BOARD_REVISION}") - - file(APPEND ${KCONFIG_BOARD_DIR}/Kconfig - "config ${BOARD_REVISION_GEN_CONFIG_VAR}\n" - "\tdef_bool y\n" - ) endif() set(DOTCONFIG ${PROJECT_BINARY_DIR}/.config) diff --git a/cmake/modules/kernel.cmake b/cmake/modules/kernel.cmake index c6319611c8c35..b6192b1ba78e9 100644 --- a/cmake/modules/kernel.cmake +++ b/cmake/modules/kernel.cmake @@ -78,7 +78,6 @@ add_custom_target(code_data_relocation_target) # bin_file "zephyr.bin" file for flashing # hex_file "zephyr.hex" file for flashing # elf_file "zephyr.elf" file for flashing or debugging -# mot_file "zephyr.mot" file for flashing # yaml_contents generated contents of runners.yaml # # Note: there are quotes around "zephyr.bin" etc. because the actual @@ -171,7 +170,6 @@ set(KERNEL_EXE_NAME ${KERNEL_NAME}.exe) set(KERNEL_STAT_NAME ${KERNEL_NAME}.stat) set(KERNEL_STRIP_NAME ${KERNEL_NAME}.strip) set(KERNEL_META_NAME ${KERNEL_NAME}.meta) -set(KERNEL_MOT_NAME ${KERNEL_NAME}.mot) set(KERNEL_SYMBOLS_NAME ${KERNEL_NAME}.symbols) # Enable dynamic library support when required by LLEXT. diff --git a/cmake/modules/shields.cmake b/cmake/modules/shields.cmake index 04aaec57ac7bd..145f559b2922d 100644 --- a/cmake/modules/shields.cmake +++ b/cmake/modules/shields.cmake @@ -93,8 +93,6 @@ if(DEFINED SHIELD) ${SHIELD_DIR_${s}} ) - include(${SHIELD_DIR_${s}}/pre_dt_shield.cmake OPTIONAL) - # Search for shield/shield.conf file if(EXISTS ${SHIELD_DIR_${s}}/${s}.conf) list(APPEND diff --git a/cmake/modules/unittest.cmake b/cmake/modules/unittest.cmake index 97b0d099f6e50..4c80283aa0ebc 100644 --- a/cmake/modules/unittest.cmake +++ b/cmake/modules/unittest.cmake @@ -55,7 +55,7 @@ target_link_libraries(testbinary PRIVATE test_interface) set(KOBJ_TYPES_H_TARGET kobj_types_h_target) include(${ZEPHYR_BASE}/cmake/kobj.cmake) add_dependencies(test_interface ${KOBJ_TYPES_H_TARGET}) -gen_kobject_list_headers(GEN_DIR_OUT_VAR KOBJ_GEN_DIR) +gen_kobj(KOBJ_GEN_DIR) # Generates empty header files to build set(INCL_GENERATED_DIR ${APPLICATION_BINARY_DIR}/zephyr/include/generated/zephyr) diff --git a/cmake/modules/yaml.cmake b/cmake/modules/yaml.cmake index 166f23c3d1ac0..17afcd0ef0bdf 100644 --- a/cmake/modules/yaml.cmake +++ b/cmake/modules/yaml.cmake @@ -526,7 +526,7 @@ function(yaml_save) cmake_path(SET yaml_path "${yaml_file}") cmake_path(GET yaml_path STEM yaml_file_no_ext) - set(expanded_file ${CMAKE_CURRENT_BINARY_DIR}/${yaml_file_no_ext}_${genex_save_count}.yaml) + set(expanded_file ${yaml_file_no_ext}_${genex_save_count}.yaml) set_property(TARGET ${save_target} PROPERTY expanded_file ${expanded_file}) # comment this to keep the temporary files diff --git a/cmake/sca/coverity/sca.cmake b/cmake/sca/coverity/sca.cmake deleted file mode 100644 index e80d6c73c18dc..0000000000000 --- a/cmake/sca/coverity/sca.cmake +++ /dev/null @@ -1,21 +0,0 @@ - -find_program(COVERITY_BUILD NAMES cov-build REQUIRED) -find_program(COVERITY_CONFIGURE NAMES cov-configure REQUIRED) -message(STATUS "Found SCA: Coverity (${COVERITY_BUILD})") - - -zephyr_get(COVERITY_OUTPUT_DIR) - -if(NOT COVERITY_OUTPUT_DIR) - set(output_dir ${CMAKE_BINARY_DIR}/sca/coverity) -else() - set(output_dir ${COVERITY_OUTPUT_DIR}) -endif() - -file(MAKE_DIRECTORY ${output_dir}) - -set(output_arg --dir=${output_dir}) - - -set(CMAKE_C_COMPILER_LAUNCHER ${COVERITY_BUILD} ${output_arg} CACHE INTERNAL "") -set(CMAKE_CXX_COMPILER_LAUNCHER ${COVERITY_BUILD} ${output_arg} CACHE INTERNAL "") diff --git a/cmake/sca/eclair/ECL/toolchain.ecl b/cmake/sca/eclair/ECL/toolchain.ecl index 312768d4061a8..9b8393e30a3ae 100644 --- a/cmake/sca/eclair/ECL/toolchain.ecl +++ b/cmake/sca/eclair/ECL/toolchain.ecl @@ -50,8 +50,8 @@ Variables\"; -config=STD.emptinit,behavior={c18,GCC,specified} -doc_end -doc_begin="See Chapter \"6.19 Structures with No Members\" of "GCC_MANUAL"." --config=STD.anonstct,behavior={c99,GCC,specified} --config=STD.anonstct,behavior={c18,GCC,specified} +-config=STD.emptrecd,behavior={c99,GCC,specified} +-config=STD.emptrecd,behavior={c18,GCC,specified} -doc_end -doc="See Chapter \"6.18 Arrays of Length Zero\" of "GCC_MANUAL"." -config=STD.arayzero,behavior={c99,GCC,specified} diff --git a/cmake/toolchain/iar/Kconfig b/cmake/toolchain/iar/Kconfig index 4e994e6fc38a3..056fa5d499f4d 100644 --- a/cmake/toolchain/iar/Kconfig +++ b/cmake/toolchain/iar/Kconfig @@ -9,30 +9,7 @@ choice LINKER_SCRIPT default CMAKE_LINKER_GENERATOR endchoice -menu "IAR options" - -choice IAR_INIT - bool "Static initialization method" - depends on XIP - default IAR_ZEPHYR_INIT - -config IAR_DATA_INIT - bool "IAR" - select SKIP_BSS_CLEAR # IAR handles zeroing. - help - IAR handles initialization of static variables. - Instead of `z_prep_c` calling Zephyrs `z_data_copy` - we call IARs own proprietary initialization method - which can save time and space. - -config IAR_ZEPHYR_INIT - bool "Zephyr" - help - Zephyr handles initialization of static variables. - This is the regular `z_data_copy`. - -endchoice - +menu "IAR library options" config IAR_SEMIHOSTING bool "Use the IAR semihosting implementation." diff --git a/cmake/toolchain/xcc/common.cmake b/cmake/toolchain/xcc/common.cmake index 973b3bad97fcd..06127567a30f1 100644 --- a/cmake/toolchain/xcc/common.cmake +++ b/cmake/toolchain/xcc/common.cmake @@ -23,7 +23,6 @@ zephyr_get(XTENSA_CORE_${NORMALIZED_BOARD_TARGET}) if(DEFINED XTENSA_CORE_${NORMALIZED_BOARD_TARGET}) set(XTENSA_CORE_LOCAL_C_FLAG "--xtensa-core=${XTENSA_CORE_${NORMALIZED_BOARD_TARGET}}") list(APPEND TOOLCHAIN_C_FLAGS "--xtensa-core=${XTENSA_CORE_${NORMALIZED_BOARD_TARGET}}") - list(APPEND TOOLCHAIN_LD_FLAGS "--xtensa-core=${XTENSA_CORE_${NORMALIZED_BOARD_TARGET}}") else() # Not having XTENSA_CORE is not necessarily fatal as # the toolchain can have a default core configuration to use. diff --git a/doc/CMakeLists.txt b/doc/CMakeLists.txt index d43b0c7c96703..cb54555824dfb 100644 --- a/doc/CMakeLists.txt +++ b/doc/CMakeLists.txt @@ -17,7 +17,6 @@ set(SPHINXOPTS_EXTRA "" CACHE STRING "Extra Sphinx Options (added to defaults)") set(LATEXMKOPTS "-halt-on-error -no-shell-escape" CACHE STRING "Default latexmk options") set(DT_TURBO_MODE OFF CACHE BOOL "Enable DT turbo mode") set(HW_FEATURES_TURBO_MODE OFF CACHE BOOL "Enable HW features turbo mode") -set(HW_FEATURES_VENDOR_FILTER "" CACHE STRING "Vendor filter for HW features") set(DOC_TAG "development" CACHE STRING "Documentation tag") set(DTS_ROOTS "${ZEPHYR_BASE}" CACHE STRING "DT bindings root folders") @@ -161,11 +160,6 @@ foreach(tag ${SPHINX_TAGS}) list(APPEND SPHINX_TAGS_ARGS "-t" "${tag}") endforeach() -if(HW_FEATURES_VENDOR_FILTER) - list(JOIN HW_FEATURES_VENDOR_FILTER "," vendor_filter) - list(APPEND SPHINXOPTS "-D" "zephyr_hw_features_vendor_filter=${vendor_filter}") -endif() - add_doc_target( html COMMAND ${CMAKE_COMMAND} -E env ${SPHINX_ENV} OUTPUT_DIR=${DOCS_HTML_DIR} diff --git a/doc/Makefile b/doc/Makefile index 12b3ca371b02f..4ce22f280f439 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -9,7 +9,6 @@ SPHINXOPTS_EXTRA ?= LATEXMKOPTS ?= -halt-on-error -no-shell-escape DT_TURBO_MODE ?= 0 HW_FEATURES_TURBO_MODE ?= 0 -HW_FEATURES_VENDOR_FILTER ?= # ------------------------------------------------------------------------------ # Documentation targets @@ -35,8 +34,7 @@ configure: -DSPHINXOPTS_EXTRA="${SPHINXOPTS_EXTRA}" \ -DLATEXMKOPTS="${LATEXMKOPTS}" \ -DDT_TURBO_MODE=${DT_TURBO_MODE} \ - -DHW_FEATURES_TURBO_MODE=${HW_FEATURES_TURBO_MODE} \ - -DHW_FEATURES_VENDOR_FILTER=${HW_FEATURES_VENDOR_FILTER} + -DHW_FEATURES_TURBO_MODE=${HW_FEATURES_TURBO_MODE} clean: cmake --build ${BUILDDIR} --target clean diff --git a/doc/_extensions/zephyr/domain/__init__.py b/doc/_extensions/zephyr/domain/__init__.py index 3df05b29573c2..462b56527639b 100644 --- a/doc/_extensions/zephyr/domain/__init__.py +++ b/doc/_extensions/zephyr/domain/__init__.py @@ -74,17 +74,15 @@ # Load and parse binding types from text file BINDINGS_TXT_PATH = ZEPHYR_BASE / "dts" / "bindings" / "binding-types.txt" ACRONYM_PATTERN = re.compile(r'([a-zA-Z0-9-]+)\s*\((.*?)\)') -ACRONYM_PATTERN_UPPERCASE_ONLY = re.compile(r'(\b[A-Z0-9-]+)\s*\((.*?)\)') BINDING_TYPE_TO_DOCUTILS_NODE = {} -def parse_text_with_acronyms(text, uppercase_only=False): +def parse_text_with_acronyms(text): """Parse text that may contain acronyms into a list of nodes.""" result = nodes.inline() last_end = 0 - pattern = ACRONYM_PATTERN_UPPERCASE_ONLY if uppercase_only else ACRONYM_PATTERN - for match in pattern.finditer(text): + for match in ACRONYM_PATTERN.finditer(text): # Add any text before the acronym if match.start() > last_end: result += nodes.Text(text[last_end : match.start()]) @@ -939,10 +937,7 @@ def feature_sort_key(feature): # DESCRIPTION column desc_entry = nodes.entry(classes=["description"]) desc_para = nodes.paragraph(classes=["status"]) - if value["title"]: - desc_para += parse_text_with_acronyms(value["title"], uppercase_only=True) - else: - desc_para += nodes.Text(value["description"]) + desc_para += nodes.Text(value["description"]) # Add count indicators for okay and not-okay instances okay_nodes = value.get("okay_nodes", []) @@ -998,12 +993,6 @@ def create_count_indicator(nodes_list, class_type, role_function=role_fn): tbody += row - # Declare the dts and binding files as dependencies of the board doc page, - # ensuring that the page is rerendered if the files change. - for node in okay_nodes + disabled_nodes: - env.note_dependency(node["dts_path"]) - env.note_dependency(node["binding_path"]) - tgroup += tbody table += tgroup tables_container += table @@ -1377,8 +1366,7 @@ def load_board_catalog_into_domain(app: Sphinx) -> None: board_catalog = get_catalog( generate_hw_features=( app.builder.format == "html" and app.config.zephyr_generate_hw_features - ), - hw_features_vendor_filter=app.config.zephyr_hw_features_vendor_filter, + ) ) app.env.domaindata["zephyr"]["boards"] = board_catalog["boards"] app.env.domaindata["zephyr"]["vendors"] = board_catalog["vendors"] @@ -1389,7 +1377,6 @@ def load_board_catalog_into_domain(app: Sphinx) -> None: def setup(app): app.add_config_value("zephyr_breathe_insert_related_samples", False, "env") app.add_config_value("zephyr_generate_hw_features", False, "env") - app.add_config_value("zephyr_hw_features_vendor_filter", [], "env", types=[list[str]]) app.add_domain(ZephyrDomain) diff --git a/doc/_extensions/zephyr/domain/static/css/board-catalog.css b/doc/_extensions/zephyr/domain/static/css/board-catalog.css index 8062ac8fe18ce..36768a1be4ef8 100644 --- a/doc/_extensions/zephyr/domain/static/css/board-catalog.css +++ b/doc/_extensions/zephyr/domain/static/css/board-catalog.css @@ -176,8 +176,10 @@ .board-card .vendor { font-size: 12px; - color: var(--body-color); + color: var(--admonition-note-color); + font-weight: 900; margin-bottom: 18px; + opacity: 0.5; } .board-card img { diff --git a/doc/_extensions/zephyr/domain/templates/board-catalog.html b/doc/_extensions/zephyr/domain/templates/board-catalog.html index 959d28950ad13..4436d3ae09129 100644 --- a/doc/_extensions/zephyr/domain/templates/board-catalog.html +++ b/doc/_extensions/zephyr/domain/templates/board-catalog.html @@ -17,6 +17,7 @@
- get_info :Get CSIS info + get_sirk :Get the currently used SIRK sirk_rsp :Set the response used in SIRK requests @@ -55,14 +55,10 @@ This command can get the currently used SIRK. .. code-block:: console - uart:~$ cap_acceptor get_info - Info for 0x2003b0c8 - SIRK - 00000000: 20 37 0a 00 95 c4 04 20 00 00 00 00 f1 79 09 00 | 7..... .....y..| - Set size: 2 - Rank: 1 - Lockable: true - Locked: false + uart:~$ cap_acceptor get_sirk + SIRK + 36 04 9a dc 66 3a a1 a1 |6...f:.. + 1d 9a 2f 41 01 73 3e 01 |../A.s>. CAP Initiator ************* diff --git a/doc/connectivity/networking/api/coap_server.rst b/doc/connectivity/networking/api/coap_server.rst index a2d0d1b77c1f2..9fb29a7ffda44 100644 --- a/doc/connectivity/networking/api/coap_server.rst +++ b/doc/connectivity/networking/api/coap_server.rst @@ -100,7 +100,7 @@ The following is an example of a CoAP resource registered with our service: /* Append payload */ coap_packet_append_payload_marker(&response); - coap_packet_append_payload(&response, (uint8_t *)msg, strlen(msg)); + coap_packet_append_payload(&response, (uint8_t *)msg, sizeof(msg)); /* Send to response back to the client */ return coap_resource_send(resource, &response, addr, addr_len, NULL); diff --git a/doc/connectivity/networking/api/thread.rst b/doc/connectivity/networking/api/thread.rst index 5cfd392a8b5e5..35b5aa07d04a5 100644 --- a/doc/connectivity/networking/api/thread.rst +++ b/doc/connectivity/networking/api/thread.rst @@ -64,69 +64,4 @@ Zephyr's OpenThread L2 platform adaptation layer glues the external OpenThread stack together with Zephyr's IEEE 802.15.4 protocol agnostic driver API. This API is of interest to OpenThread L2 **subsystem contributors** only. -OpenThread Platform API -======================= - -The OpenThread platform API is defined by the OpenThread stack and implemented in Zephyr as an -OpenThread module. Applications can use this implementation directly, or access it through the -OpenThread L2 adaptation layer. - -Using the OpenThread L2 Adaptation Layer API --------------------------------------------- - -To use the OpenThread platform API via the OpenThread L2 adaptation layer, enable both the -:kconfig:option:`CONFIG_NET_L2_OPENTHREAD` and :kconfig:option:`CONFIG_NETWORKING` Kconfig options -by setting them to ``y``. The adaptation layer will use the OpenThread radio API implementation -found in :file:`modules/openthread/platform/radio.c`. In this setup, the OpenThread stack is -initialized and managed by the adaptation layer. - -Using the OpenThread Platform API Directly ------------------------------------------- - -You can also use the OpenThread platform API directly, bypassing the OpenThread L2 adaptation -layer. However, this approach requires you to provide your own implementation of the OpenThread -radio API that is compatible with your specific radio driver. - -To use the OpenThread platform API directly, set the :kconfig:option:`CONFIG_OPENTHREAD` Kconfig -option to ``y``, and do **not** set :kconfig:option:`CONFIG_NET_L2_OPENTHREAD`. In this case, you -must implement the following functions from the `OpenThread radio API -`_ using your own radio driver: - -* ``otPlatRadioGetPromiscuous`` -* ``otPlatRadioGetCcaEnergyDetectThreshold`` -* ``otPlatRadioGetTransmitPower`` -* ``otPlatRadioGetIeeeEui64`` -* ``otPlatRadioSetPromiscuous`` -* ``otPlatRadioGetCaps`` -* ``otPlatRadioGetTransmitBuffer`` -* ``otPlatRadioSetPanId`` -* ``otPlatRadioEnable`` -* ``otPlatRadioDisable`` -* ``otPlatRadioReceive`` -* ``otPlatRadioGetRssi`` -* ``otPlatRadioGetReceiveSensitivity`` -* ``otPlatRadioEnergyScan`` -* ``otPlatRadioSetExtendedAddress`` -* ``otPlatRadioSetShortAddress`` -* ``otPlatRadioAddSrcMatchExtEntry`` -* ``otPlatRadioTransmit`` -* ``otPlatRadioClearSrcMatchShortEntries`` -* ``otPlatRadioClearSrcMatchExtEntries`` -* ``otPlatRadioEnableSrcMatch`` -* ``otPlatRadioAddSrcMatchShortEntry`` -* ``otPlatRadioClearSrcMatchShortEntry`` -* ``otPlatRadioClearSrcMatchExtEntry`` - -Additionally, you must implement the following functions from the OpenThread radio API (see -:zephyr_file:`include/zephyr/net/openthread.h`) to handle radio initialization and event processing: - -* :c:func:`platformRadioInit` -* :c:func:`platformRadioProcess` - -To initialize the OpenThread stack in this approach, either call the :c:func:`ot_platform_init` -function in your application, or enable the :kconfig:option:`CONFIG_OPENTHREAD_SYS_INIT` Kconfig -option to automatically initialize OpenThread during system startup. You can set the -initialization priority using the :kconfig:option:`CONFIG_OPENTHREAD_SYS_INIT_PRIORITY` Kconfig -option. - .. doxygengroup:: openthread diff --git a/doc/connectivity/networking/api/zperf.rst b/doc/connectivity/networking/api/zperf.rst index 3e68decb25f7e..5ffc7699e4f63 100644 --- a/doc/connectivity/networking/api/zperf.rst +++ b/doc/connectivity/networking/api/zperf.rst @@ -13,7 +13,7 @@ Overview zperf is a shell utility which allows to generate network traffic in Zephyr. The tool may be used to evaluate network bandwidth. -zperf is compatible with iPerf 2.0.10 and newer. For compatibility with older versions, +zperf is compatible with iPerf 2.0.10 and newer. For compatability with older versions, enable :kconfig:option:`CONFIG_NET_ZPERF_LEGACY_HEADER_COMPAT`. zperf can be enabled in any application, a dedicated sample is also present diff --git a/doc/contribute/documentation/generation.rst b/doc/contribute/documentation/generation.rst index 33f34dc4095be..cad9201b113c6 100644 --- a/doc/contribute/documentation/generation.rst +++ b/doc/contribute/documentation/generation.rst @@ -268,19 +268,6 @@ without either of the aforementioned features:: # and supported features index make html-fast -When working with documentation for boards from a specific vendor, it is also -possible to limit generation of the list of supported features to subset of board -vendors. This can be done by setting the following option when invoking cmake:: - - -DHW_FEATURES_VENDOR_FILTER=vendor1,vendor2 - -This option can also be used with the :command:`make` wrapper:: - - cd ~/zephyrproject/zephyr/doc - - # To generate HTML output with supported features limited to a subset of vendors - make html HW_FEATURES_VENDOR_FILTER=vendor1,vendor2 - Viewing generated documentation locally *************************************** diff --git a/doc/contribute/documentation/guidelines.rst b/doc/contribute/documentation/guidelines.rst index c94d6fc0162ee..6c6b37a12f941 100644 --- a/doc/contribute/documentation/guidelines.rst +++ b/doc/contribute/documentation/guidelines.rst @@ -54,8 +54,6 @@ the first non-white space in the preceding line. For example:: Refer to the Zephyr :ref:`coding_style` for additional requirements. -.. _headings: - Headings ======== @@ -1283,11 +1281,6 @@ Boards (``zephyr_generate_hw_features`` config option set to ``True``). If disabled, a warning message will be shown instead of the hardware features tables. - It is possible to limit the hardware features generation to boards from a specific list of vendors - to speed up documentation builds without completely disabling the hardware features table. Set the - config option ``zephyr_hw_features_vendor_filter`` to the list of vendors to generate features for. - If the option is empty, hardware features are generated for all boards from all vendors. - .. rst:directive:: .. zephyr:board-supported-runners:: This directive is used to show the supported runners for the board documented in the current @@ -1303,99 +1296,6 @@ Boards produce a complete table. If disabled, a warning message will be shown instead of the runners tables. -Accessibilty Guidelines -*********************** - -Accessibility is an important aspect of documentation, ensuring that all users, including those with -disabilities, can access and understand the content. - -When writing and maintaining Zephyr Project documentation, please follow these guidelines to improve -accessibility for everyone. - -Images and Figures -================== - -All images and figures must include appropriate alternative text (alt text) to convey the meaning of -the visual content to users who rely on screen readers or cannot view images. - -* Use the ``:alt:`` attribute when including images using the :rst:dir:`image` directive. Example: - - .. code-block:: rst - :emphasize-lines: 2 - - .. image:: image/doc-gen-flow.png - :alt: Documentation generation process overview - -* If the image contains text, ensure that the alt text includes this text verbatim. - -* When using the :rst:dir:`figure` directive, which allows for a caption, the ``:alt:`` text is - still important. The alt text should describe the image itself, while the caption provides - additional context or interpretation. Example: - - .. code-block:: rst - :emphasize-lines: 4 - - .. figure:: ../../images/arch-diagram.png - :alt: High-level overview of Zephyr OS architecture showing layers and components. - - High-level overview of Zephyr OS architecture. - -- Avoid using images as the sole method of conveying information that can be explained - clearly with text. - -.. admonition:: Best Practices for writing alt text - :class: tip - - * **Be Accurate and Equivalent**: Present the same essential information as the image. - * **Be Succinct**: Convey the core message of the image concisely. - * **Avoid Redundancy**: Do not use phrases like "Image of..." or "Picture of..." as screen readers - typically announce the element as an image. - * **Describe, Don't Interpret**: Stick to describing what is visually present on the image. - * **Complex Images**: For charts, diagrams, or other complex visuals, provide a summary in the alt - text. If a full understanding requires more detail, consider providing a more detailed - description in the surrounding text or as part of the figure caption. Using text-based diagram - tools like :ref:`Graphviz ` can also improve accessibility. - - -Headings and Structure -====================== - -Use :ref:`headings ` to structure your document logically. This allows users of assistive -technologies to understand the document's organization and navigate it efficiently. - -Tables -====== - -Tables should be used only for tabular data and must be accessible to screen readers. - -* Always define headers for rows and columns. - -* Use the :rst:dir:`list-table` directive when possible for better responsiveness and accessibility. - -* Include a caption for tables where context is not immediately obvious. Example: - - .. code-block:: rst - :emphasize-lines: 1 - - .. list-table:: GPIO Pin Configuration Options - :widths: 15 30 - :header-rows: 1 - - * - Field - - Description - * - GPIO_INPUT - - Configures pin as input - * - GPIO_OUTPUT - - Configures pin as output - -Additional Resources -==================== - -For more general guidance on web accessibility you may refer to W3C's -`Web Content Accessibility Guidelines (WCAG)`_ - -.. _`Web Content Accessibility Guidelines (WCAG)`: https://www.w3.org/WAI/standards-guidelines/wcag/ - References ********** diff --git a/doc/contribute/guidelines.rst b/doc/contribute/guidelines.rst index 977c094de94c7..e02db855e5d15 100644 --- a/doc/contribute/guidelines.rst +++ b/doc/contribute/guidelines.rst @@ -588,7 +588,7 @@ for example: .. code-block:: bash - west twister -p native_sim -s tests/drivers/build_all/sensor/drivers.sensor.generic_test + west twister -p native_sim -s tests/drivers/build_all/sensor/sensors.generic_test .. _static_analysis: diff --git a/doc/develop/flash_debug/host-tools.rst b/doc/develop/flash_debug/host-tools.rst index 3ccc61f1aa5cf..dfe0462694638 100644 --- a/doc/develop/flash_debug/host-tools.rst +++ b/doc/develop/flash_debug/host-tools.rst @@ -12,19 +12,6 @@ hardware supports them and your Zephyr board directory's :file:`board.cmake` file declares that support properly. See :ref:`west-build-flash-debug` for more information on these commands. -.. _runner_blackmagicprobe: - -Black Magic Probe -***************** - -Black Magic Probe (BMP) is an open-source debugging hardware incorporating GDB debug -server functionality into the firmware. -There is no need for a GDB server program, so there is no program equivalent -to host-tool. - -For more details, including usage instructions and supported targets, -see :ref:`black-magic-probe`. - .. _atmel_sam_ba_bootloader: .. _runner_bossac: @@ -574,28 +561,6 @@ It can be used through the ``west flash`` command to flash Zephyr applications. For advanced usage via the GUI or CLI, check out the `STM32CubeProgrammer User Manual`_. -.. _runner_uf2: - -UF2 Uploader -************ - -The uf2 runner supports flashing some boards using the UF2 (USB Flashing Format). -UF2 is a user-friendly file format designed for drag-and-drop programming via a USB mass storage device. - -It relies on the target device entering a special bootloader mode where it appears to the host -as a USB mass storage device. -Once in this mode, the application image can be uploaded by copying a ``.uf2`` file to the -mounted volume. - -.. code-block:: console - - west flash --runner uf2 - -If the UF2 volume is not automatically detected, you may need to manually specify the mount point -using the ``--device`` option: - -For more about the UF2 format and its tooling, see `USB Flashing Format (UF2)`_. - .. _J-Link Software and Documentation Pack: https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack @@ -667,6 +632,3 @@ For more about the UF2 format and its tooling, see `USB Flashing Format (UF2)`_. .. _STLINK-V3PWR: https://www.st.com/en/development-tools/stlink-v3pwr.html - -.. _USB Flashing Format (UF2): - https://github.com/microsoft/uf2 diff --git a/doc/develop/flash_debug/probes.rst b/doc/develop/flash_debug/probes.rst index 587df342fe6bd..9f7470db580c0 100644 --- a/doc/develop/flash_debug/probes.rst +++ b/doc/develop/flash_debug/probes.rst @@ -488,19 +488,6 @@ NXP S32 Debug Probe is designed to work in conjunction with NXP S32 Design Studi host tools as in indicated in :ref:`nxp-s32-debug-host-tools` before you program the firmware. -.. _black-magic-probe: - -Black Magic Probe -***************** - -The Black Magic Probe is an open-source hardware for debugging that is designed -to be used with `Black Magic Debug`_ firmware. -The firmware incorporates GDB Server so that you can connect directly from ``gdb`` -to the target device. - -Some of the STM32F103-based boards can run the `Black Magic Debug`_ firmware. -See `Black Magic Debug supported hardware`_. - .. _LPCScrypt: https://www.nxp.com/lpcscrypt @@ -539,9 +526,3 @@ See `Black Magic Debug supported hardware`_. .. _DAPLink Bootloader Update: https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _Black Magic Debug: - https://black-magic.org/index.html - -.. _Black Magic Debug supported hardware: - https://black-magic.org/hardware.html diff --git a/doc/develop/getting_started/installation_linux.rst b/doc/develop/getting_started/installation_linux.rst index 23bc8bd9465fa..6ef50b6d45a70 100644 --- a/doc/develop/getting_started/installation_linux.rst +++ b/doc/develop/getting_started/installation_linux.rst @@ -219,6 +219,7 @@ The Zephyr SDK supports the following target architectures: * ARC (32-bit and 64-bit; ARCv1, ARCv2, ARCv3) * ARM (32-bit and 64-bit; ARMv6, ARMv7, ARMv8; A/R/M Profiles) * MIPS (32-bit and 64-bit) +* Nios II * RISC-V (32-bit and 64-bit; RV32I, RV32E, RV64I) * x86 (32-bit and 64-bit) * Xtensa diff --git a/doc/develop/manifest/external/emlearn.rst b/doc/develop/manifest/external/emlearn.rst deleted file mode 100644 index 480d49171f803..0000000000000 --- a/doc/develop/manifest/external/emlearn.rst +++ /dev/null @@ -1,52 +0,0 @@ -.. _external_module_emlearn: - -emlearn -####### - -Introduction -************ - -`emlearn`_ is an open source library for deploying machine learning models on micro-controllers -and embedded systems. It provides portable C code generation from models trained with -scikit-learn or Keras. - -A Python library allows converting complex machine learning models to a minimal C code -representation, which enables running ML inference on resource-constrained embedded devices. - -emlearn is licensed under the MIT license. - -Usage with Zephyr -***************** - -The emlearn repository is a Zephyr :ref:`module ` which provides TinyML capabilities to -Zephyr applications, allowing machine learning models to be run directly on Zephyr-powered devices. - -To pull in emlearn as a Zephyr module, either add it as a West project in the ``west.yaml`` -file or pull it in by adding a submanifest (e.g. ``zephyr/submanifests/emlearn.yaml``) file -with the following content and run ``west update``: - -.. code-block:: yaml - - manifest: - projects: - - name: emlearn - url: https://github.com/emlearn/emlearn.git - revision: master - path: modules/lib/emlearn # adjust the path as needed - -For more detailed instructions and API documentation, refer to the `emlearn documentation`_, and in -particular the `Getting Started on Zephyr RTOS`_ section. - -References -********** - -.. target-notes:: - -.. _emlearn: - https://github.com/emlearn/emlearn - -.. _emlearn documentation: - https://emlearn.readthedocs.io/en/latest/ - -.. _Getting Started on Zephyr RTOS: - https://emlearn.readthedocs.io/en/latest/getting_started_zephyr.html diff --git a/doc/develop/sca/coverity.rst b/doc/develop/sca/coverity.rst deleted file mode 100644 index 28d921d87a2b7..0000000000000 --- a/doc/develop/sca/coverity.rst +++ /dev/null @@ -1,33 +0,0 @@ -.. _coverity: - -Coverity -######### - -Coverity Scan is a service by which Black Duck provides the results of analysis -on open source coding projects to open source code developers that have -registered their products with Coverity Scan. - -This integration was only tested with scan.coverity.com and the tool -distribution available through this service. - -Generating Build Data Files -*************************** - -To use this integration, coverity tool distribution must be found in your :envvar:`PATH` environment and -:ref:`west build ` should be called with a ``-DZEPHYR_SCA_VARIANT=coverity`` -parameter, e.g. - -.. code-block:: shell - - west build -b qemu_cortex_m3 samples/hello_world -- -DZEPHYR_SCA_VARIANT=coverity - - -Results of the scan will be generated as :file:`build/sca/coverity`. - -You can also set :envvar:`COVERITY_OUTPUT_DIR` as the destination for multiple -and incremental scan results. - -Result Analysis -**************** - -Follow the instructions on http://scan.coverity.com for uploading results. diff --git a/doc/develop/sca/index.rst b/doc/develop/sca/index.rst index c14d1d2df56ce..8269b0be4835c 100644 --- a/doc/develop/sca/index.rst +++ b/doc/develop/sca/index.rst @@ -67,4 +67,3 @@ The following is a list of SCA tools natively supported by Zephyr build system. cpptest eclair polyspace - coverity diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index 64aa90f79b9b6..948a487439ae4 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -561,7 +561,6 @@ harness: - robot - ctest - shell - - power See :ref:`twister_harnesses` for more information. @@ -604,18 +603,6 @@ harness_config: Only one fixture can be defined per test scenario and the fixture name has to be unique across all tests in the test suite. - ztest_suite_repeat: (default 1) - This parameter specifies the number of times the entire test suite should be repeated. - - ztest_test_repeat: (default 1) - This parameter specifies the number of times each individual test within the test suite - should be repeated. - - ztest_test_shuffle: (default False) - This parameter indicates whether the order of the tests within the test suite should - be shuffled. When set to ``true``, the tests will be executed in a random order. - - The following is an example yaml file with robot harness_config options. @@ -985,44 +972,6 @@ robot_testsuite: (default empty) robot_option: (default empty) One or more options to be send to robotframework. -Power -===== -The ``power`` harness is used to measure and validate the current consumption. -It integrates with 'pytest' to perform automated data collection and analysis using a hardware power monitor. - -The harness executes the following steps: - -1. Initializes a power monitoring device (e.g., ``stm_powershield``) via the ``PowerMonitor`` abstract interface. -#. Starts current measurement for a defined ``measurement_duration``. -#. Collects raw current waveform data. -#. Uses a peak detection algorithm to segment data into defined execution phases based on power transitions. -#. Computes RMS current values for each phase using a utility function. -#. Compares the computed values with user-defined expected RMS values. - -.. code-block:: yaml - - harness: power - harness_config: - fixture: pm_probe - power_measurements: - element_to_trim: 100 - min_peak_distance: 40 - min_peak_height: 0.008 - peak_padding: 40 - measurement_duration: 6 - num_of_transitions: 4 - expected_rms_values: [56.0, 4.0, 1.2, 0.26, 140] - tolerance_percentage: 20 - -- **elements_to_trim** – Number of samples to discard at the start of measurement to eliminate noise. -- **min_peak_distance** – Minimum distance between detected current peaks (helps detect distinct transitions). -- **min_peak_height** – Minimum current threshold to qualify as a peak (in amps). -- **peak_padding** – Number of samples to extend around each detected peak. -- **measurement_duration** – Total time (in seconds) to record current data. -- **num_of_transitions** – Expected number of power state transitions in the DUT during test execution. -- **expected_rms_values** – Target RMS values for each identified execution phase (in milliamps). -- **tolerance_percentage** – Allowed deviation percentage from the expected RMS values. - Bsim ==== diff --git a/doc/develop/toolchains/arm_compiler_6.rst b/doc/develop/toolchains/arm_compiler.rst similarity index 100% rename from doc/develop/toolchains/arm_compiler_6.rst rename to doc/develop/toolchains/arm_compiler.rst diff --git a/doc/develop/toolchains/arm_toolchain_for_embedded.rst b/doc/develop/toolchains/arm_toolchain_for_embedded.rst deleted file mode 100644 index f5a0d40f7b3a4..0000000000000 --- a/doc/develop/toolchains/arm_toolchain_for_embedded.rst +++ /dev/null @@ -1,86 +0,0 @@ -.. _toolchain_atfe: - -Arm Toolchain for Embedded (ATfE) -################################# - -#. LLVM toolchain by ARM - - #. Arm Toolchain for Embedded (ATfE) is a C and C++ toolchain from Arm based - on the free and open-source LLVM Compiler Infrastructure and the Picolib C - library for baremetal targets. - - #. ATfE is fined-tuned with a particular focus on performance for newer - ARM products (post 2024) like 64-bit Arm Architectures (AArch64), - or the M-Profile Vector Extension (MVE, a 32-bit Armv8.1-M extension). - -#. Installation - - #. Download and install a `Arm toolchain for embedded`_ build for your operating system - and extract it on your file system. - - #. :ref:`Set these environment variables `: - - - Set :envvar:`ZEPHYR_TOOLCHAIN_VARIANT` to ``llvm``. - - Set :envvar:`LLVM_TOOLCHAIN_PATH` to the toolchain installation directory. - - #. To check that you have set these variables correctly in your current - environment, follow these example shell sessions (the - :envvar:`LLVM_TOOLCHAIN_PATH` values may be different on your system): - - .. tabs:: - - .. group-tab:: Ubuntu - - .. code-block:: bash - - echo $ZEPHYR_TOOLCHAIN_VARIANT - llvm - echo $LLVM_TOOLCHAIN_PATH - /home/you/Downloads/ATfE - - .. group-tab:: macOS - - .. code-block:: bash - - echo $ZEPHYR_TOOLCHAIN_VARIANT - llvm - echo $LLVM_TOOLCHAIN_PATH - /home/you/Downloads/ATfE - - .. group-tab:: Windows - - .. code-block:: powershell - - > echo %ZEPHYR_TOOLCHAIN_VARIANT% - llvm - > echo %LLVM_TOOLCHAIN_PATH% - C:\ATfE - - .. _toolchain_env_var: - - #. You can also set ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``LLVM_TOOLCHAIN_PATH`` as CMake - variables when generating a build system for a Zephyr application, like so: - - .. code-block:: console - - west build ... -- -DZEPHYR_TOOLCHAIN_VARIANT=llvm -DLLVM_TOOLCHAIN_PATH=... - -#. Toolchain settings - - #. Because LLVM is widely compatible with GNU tools, When builiding with any - LLVM toolchain, you have to specify some settings to let the compiler - know what tools to use: - - #. Linker: - Set :envvar:`CONFIG_LLVM_USE_LLD=y` to use LLVM linker. - set :envvar:`CONFIG_LLVM_USE_LD=y` to use the GNU LD linker. - - #. Runtime library: - Set :envvar:`CONFIG_COMPILER_RT_RTLIB=y` to use LLVM runtime library. - Set :envvar:`CONFIG_LIBGCC_RTLIB=y` to use LibGCC runtime library. - - .. code-block:: console - - west build ... -- -DZEPHYR_TOOLCHAIN_VARIANT=llvm -DLLVM_TOOLCHAIN_PATH=... -DCONFIG_LLVM_USE_LLD=y -DCONFIG_COMPILER_RT_RTLIB=y - -.. _Arm Toolchain for Embedded: https://developer.arm.com/Tools%20and%20Software/Arm%20Toolchain%20for%20Embedded diff --git a/doc/develop/toolchains/index.rst b/doc/develop/toolchains/index.rst index a1710314e512a..e085a1fbe1c3c 100644 --- a/doc/develop/toolchains/index.rst +++ b/doc/develop/toolchains/index.rst @@ -10,8 +10,7 @@ Guides on how to set up toolchains for Zephyr development. zephyr_sdk.rst - arm_compiler_6.rst - arm_toolchain_for_embedded.rst + arm_compiler.rst cadence_xcc.rst designware_arc_mwdt.rst gnu_arm_embedded.rst diff --git a/doc/develop/toolchains/zephyr_sdk.rst b/doc/develop/toolchains/zephyr_sdk.rst index f9cb99fac79c8..3663dd7b85b15 100644 --- a/doc/develop/toolchains/zephyr_sdk.rst +++ b/doc/develop/toolchains/zephyr_sdk.rst @@ -18,6 +18,7 @@ The Zephyr SDK supports the following target architectures: * ARC (32-bit and 64-bit; ARCv1, ARCv2, ARCv3) * ARM (32-bit and 64-bit; ARMv6, ARMv7, ARMv8; A/R/M Profiles) * MIPS (32-bit and 64-bit) +* Nios II * RISC-V (32-bit and 64-bit; RV32I, RV32E, RV64I) * x86 (32-bit and 64-bit) * Xtensa diff --git a/doc/develop/tools/clion.rst b/doc/develop/tools/clion.rst index c661634b545a2..a9e7104526f11 100644 --- a/doc/develop/tools/clion.rst +++ b/doc/develop/tools/clion.rst @@ -209,7 +209,7 @@ Start debugging Refer to `CLion web help`_ for detailed description of the IDE debug capabilities. -.. _native Zephyr West integration: https://jb.gg/cl_zephyr_doc +.. _native Zephyr West integration: https://www.jetbrains.com/help/clion/zephyr.html .. _CLion: https://www.jetbrains.com/clion/ .. _Download CLion: https://www.jetbrains.com/clion/download .. _Project security: https://www.jetbrains.com/help/clion/project-security.html#projects_security diff --git a/doc/develop/west/install.rst b/doc/develop/west/install.rst index cb207bf3789ff..5ac0f6efaa474 100644 --- a/doc/develop/west/install.rst +++ b/doc/develop/west/install.rst @@ -53,7 +53,6 @@ West currently supports shell completion in the following shells: * bash * zsh * fish -* powershell (board qualifiers only) In order to enable shell completion, you will need to obtain the corresponding completion script and have it sourced. @@ -103,22 +102,5 @@ Using the completion scripts: west completion fish > $HOME/.config/fish/completions/west.fish - .. group-tab:: powershell - - *One-time setup*: - - .. code-block:: powershell - - west completion powershell | Out-String | Invoke-Expression - - *Permanent setup*: - - .. code-block:: powershell - - Set-ExecutionPolicy RemoteSigned -Scope CurrentUser - New-item -type file -force $PROFILE - west completion powershell > $HOME/west-completion.ps1 - (Add-Content -Path $PROFILE -Value ". '{$HOME/west-completion.ps1}'") - .. _PyPI: https://pypi.org/project/west/ diff --git a/doc/develop/west/zephyr-cmds.rst b/doc/develop/west/zephyr-cmds.rst index e40093c3dd16d..b4ef9532cff6a 100644 --- a/doc/develop/west/zephyr-cmds.rst +++ b/doc/develop/west/zephyr-cmds.rst @@ -40,7 +40,6 @@ It currently supports the following shells: - bash - zsh - fish -- powershell (board qualifiers only) Additional instructions are available in the command's help:: @@ -105,18 +104,6 @@ To use this command: west spdx -d BUILD_DIR -.. note:: - - When building with :ref:`sysbuild`, make sure you target the actual application - which you want to generate the SBOM for. For example, if the application is - named ``hello_world``: - - .. code-block:: bash - - west spdx --init -d BUILD_DIR/hello_world - west build -d BUILD_DIR/hello_world - west spdx -d BUILD_DIR/hello_world - This generates the following SPDX bill-of-materials (BOM) documents in :file:`BUILD_DIR/spdx/`: @@ -281,123 +268,3 @@ Additional tips: separate ``west global`` command since ``global`` already searches for the ``GTAGS`` file starting from your current working directory. This is why you need to run ``global`` from inside the workspace. - -.. _west-patch: - -Working with patches: ``west patch`` -************************************ - -The ``patch`` command allows users to apply patches to Zephyr or Zephyr modules -in a controlled manner that makes automation and tracking easier for external applications that -use the :ref:`T2 star topology `. The :ref:`patches.yml ` file stores -metadata about patch files and fills-in the gaps between official Zephyr releases, so that users -can easily see the status of any upstreaming efforts, and determine which patches to drop before -upgrading to the next Zephyr release. - -There are several sub-commands available to manage patches for Zephyr or other modules in the -workspace: - -* ``apply``: apply patches listed in ``patches.yml`` -* ``clean``: remove all patches that have been applied, and reset to the manifest checkout state -* ``list``: list all patches in ``patches.yml`` -* ``gh-fetch``: fetch patches from a GitHub pull request - -.. code-block:: none - - west-workspace/ - └── application/ - ... - ├── west.yml - └── zephyr - ├── module.yml - ├── patches - │ ├── bootloader - │ │ └── mcuboot - │ │ └── my-tweak-for-mcuboot.patch - │ └── zephyr - │ └── my-zephyr-change.patch - └── patches.yml - -In this example, the :ref:`west manifest ` file, ``west.yml``, would pin to a -specific Zephyr revision (e.g. ``v4.1.0``) and apply patches against that revision of Zephyr and -the specific revisions of other modules used in the application. However, this application needs -two changes in order to meet requirements; one for Zephyr and another for MCUBoot. - -.. _patches-yml: - -.. code-block:: yaml - - patches: - - path: zephyr/my-zephyr-change.patch - sha256sum: c676cd376a4d19dc95ac4e44e179c253853d422b758688a583bb55c3c9137035 - module: zephyr - author: Obi-Wan Kenobi - email: obiwan@jedi.org - date: 2025-05-04 - upstreamable: false - comments: | - An application-specific change we need for Zephyr. - - path: bootloader/mcuboot/my-tweak-for-mcuboot.patch - sha256sum: e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 - module: mcuboot - author: Darth Sidious - email: sidious@sith.org - date: 2025-05-04 - merge-pr: https://github.com/zephyrproject-rtos/zephyr/pull/ - issue: https://github.com/zephyrproject-rtos/zephyr/issues/ - merge-status: true - merge-commit: 1234567890abcdef1234567890abcdef12345678 - merge-date: 2025-05-06 - apply-command: git apply - comments: | - A change to mcuboot that has been merged already. We can remove this - patch when we are ready to upgrade to the next Zephyr release. - -Patches can easily be applied in an automated manner. For example: - -.. code-block:: bash - - west init -m - cd - west update - west patch apply - -When it is time to update to a newer version of Zephyr, the ``west.yml`` file can be updated to -point at the next Zephyr release, e.g. ``v4.2.0``. Patches that are no longer needed, like -``my-tweak-for-mcuboot.patch`` in the example above, can be removed from ``patches.yml`` and from -the external application repository, and then the following commands can be run. - -.. code-block:: bash - - west patch clean - west update - west patch apply --roll-back # roll-back all patches if one does not apply cleanly - -If a patch needs to be reworked, remember to update the ``patches.yml`` file with the new SHA256 -checksum. - -.. code-block:: bash - - sha256sum zephyr/patches/zephyr/my-zephyr-change.patch - 7d57ca78d5214f422172cc47fed9d0faa6d97a0796c02485bff0bf29455765e9 - -It is also possible to use ``west patch gh-fetch`` to fetch patches from a GitHub pull request and -automatically create or update the ``patches.yml`` file. This can be useful when the author already -has a number of changes captured in existing upstream pull requests. - -.. code-block:: bash - - west patch gh-fetch --owner zephyrproject-rtos --repo zephyr --pull-request \ - --module zephyr --split-commits - -The above command will create the directory and file structure below, which includes patches for -each individual commit associated with the given pull request. - -.. code-block:: none - - zephyr - ├── patches - │ ├── first-commit-from-pr.patch - │ ├── second-commit-from-pr.patch - │ └── third-commit-from-pr.patch - └── patches.yml diff --git a/doc/hardware/porting/shields.rst b/doc/hardware/porting/shields.rst index d93a43540630f..6f3dff1be5fb8 100644 --- a/doc/hardware/porting/shields.rst +++ b/doc/hardware/porting/shields.rst @@ -19,8 +19,7 @@ under :zephyr_file:`boards/shields`: boards/shields/ ├── .overlay ├── Kconfig.shield - ├── Kconfig.defconfig - └── pre_dt_shield.cmake + └── Kconfig.defconfig These files provides shield configuration as follows: @@ -38,9 +37,6 @@ These files provides shield configuration as follows: shield configuration should be done by keeping in mind that features activation is application responsibility. -* **pre_dt_shield.cmake**: This optional file can be used to pass additional - arguments to the devicetree compiler ``dtc``. - Besides, in order to avoid name conflicts with devices that may be defined at board level, it is advised, specifically for shields devicetree descriptions, to provide a device nodelabel is the form _, for instance: diff --git a/doc/kernel/drivers/index.rst b/doc/kernel/drivers/index.rst index 458da5a87f7e2..762ddb94b28a9 100644 --- a/doc/kernel/drivers/index.rst +++ b/doc/kernel/drivers/index.rst @@ -590,7 +590,7 @@ would be in the driver config struct: Drivers that do not use Zephyr Device Model =========================================== -Some drivers or driver-like code may not use Zephyr's device model, +Some drivers or driver-like code may not user Zephyr's device model, and alternative storage must be arranged for the MMIO data. An example of this are timer drivers, or interrupt controller code. diff --git a/doc/kernel/services/interrupts.rst b/doc/kernel/services/interrupts.rst index ad6cf4b5a5343..0053b019618a4 100644 --- a/doc/kernel/services/interrupts.rst +++ b/doc/kernel/services/interrupts.rst @@ -548,9 +548,10 @@ for IRQ line n, and the function pointers are: spurious IRQ handler will be placed here. The spurious IRQ handler causes a system fatal error if encountered. -Some architectures have a common entry point for all interrupts and do not -support a vector table, in which case the -:kconfig:option:`CONFIG_GEN_IRQ_VECTOR_TABLE` option should be disabled. +Some architectures (such as the Nios II internal interrupt controller) have a +common entry point for all interrupts and do not support a vector table, in +which case the :kconfig:option:`CONFIG_GEN_IRQ_VECTOR_TABLE` option should be +disabled. Some architectures may reserve some initial vectors for system exceptions and declare this in a table elsewhere, in which case diff --git a/doc/kernel/services/polling.rst b/doc/kernel/services/polling.rst index c54054913fb47..875b0f77abcaa 100644 --- a/doc/kernel/services/polling.rst +++ b/doc/kernel/services/polling.rst @@ -296,7 +296,7 @@ been signaled. // weird error } - k_poll_signal_reset(&signal); + k_poll_signal_reset(signal); events[0].state = K_POLL_STATE_NOT_READY; } } diff --git a/doc/kernel/services/scheduling/index.rst b/doc/kernel/services/scheduling/index.rst index 46aa83c6fb735..28319539582c0 100644 --- a/doc/kernel/services/scheduling/index.rst +++ b/doc/kernel/services/scheduling/index.rst @@ -257,14 +257,6 @@ for a kernel object, such as a mutex. Use preemptive threads to give priority to time-sensitive processing over less time-sensitive processing. - -Configuration Options -********************** - -* :kconfig:option:`CONFIG_TIMESLICING` -* :kconfig:option:`CONFIG_TIMESLICE_SIZE` -* :kconfig:option:`CONFIG_TIMESLICE_PRIORITY` - .. _cpu_idle: CPU Idling diff --git a/doc/releases/migration-guide-4.2.rst b/doc/releases/migration-guide-4.2.rst index de27e6b0d3a29..7468848941346 100644 --- a/doc/releases/migration-guide-4.2.rst +++ b/doc/releases/migration-guide-4.2.rst @@ -79,10 +79,6 @@ Boards * Espressif boards ``esp32_devkitc_wroom`` and ``esp32_devkitc_wrover`` shared almost identical features. The differences are covered by the Kconfig options so both boards were merged into ``esp32_devkitc``. -* STM32 boards should now add OpenOCD programming support by including ``openocd-stm32.board.cmake`` - instead of ``openocd.board.cmake``. The ``openocd-stm32.board.cmake`` file extends the default - OpenOCD runner with manufacturer-specific configuration like STM32 mass erase commands. - Device Drivers and Devicetree ***************************** @@ -93,10 +89,6 @@ Devicetree to more specific locations. Therefore, any dts files which ``#include `` a file from in the zephyr tree will need to be changed to just ``#include ``. -* Silicon Labs SoC-level dts files for Series 2 have been reorganized in subdirectories per device - superfamily. Therefore, any dts files for boards that use Series 2 SoCs will need to change their - include from ``#include `` to ``#include ``. - DAI === @@ -223,24 +215,6 @@ Sensors and :dtcompatible:`meas,ms5837-02ba`. In order to use one of the two variants, the status property needs to be used as well. -* The :dtcompatible:`we,wsen-itds` driver has been renamed to - :dtcompatible:`we,wsen-itds-2533020201601`. - The Device Tree can be configured as follows: - - .. code-block:: devicetree - - &i2c0 { - itds:itds-2533020201601@19 { - compatible = "we,wsen-itds-2533020201601"; - reg = <0x19>; - odr = "400"; - op-mode = "high-perf"; - power-mode = "normal"; - events-interrupt-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - drdy-interrupt-gpios = < &gpio1 2 GPIO_ACTIVE_HIGH >; - }; - }; - Serial ======= @@ -274,25 +248,6 @@ Modem * Removed Kconfig option :kconfig:option:`CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE` in favor of :kconfig:option:`CONFIG_MODEM_CMUX_WORK_BUFFER_SIZE` and :kconfig:option:`CONFIG_MODEM_CMUX_MTU`. -Flash -===== - -* Renamed the file from ``flash_hp_ra.h`` to ``soc_flash_renesas_ra_hp.h``. -* Renamed the file from ``flash_hp_ra.c`` to ``soc_flash_renesas_ra_hp.c``. -* Renamed the file from ``flash_hp_ra_ex_op.c`` to ``soc_flash_renesas_ra_hp_ex_op.c``. - -* The Flash HP Renesas RA dual bank mode Kconfig symbol :kconfig:option:`CONFIG_DUAL_BANK_MODE` - has been removed. -* The Flash HP Renesas RA Kconfig symbol :kconfig:option:`CONFIG_RA_FLASH_HP` - has been renamed to :kconfig:option:`CONFIG_SOC_FLASH_RENESAS_RA_HP`. -* The Flash HP Renesas RA write protect Kconfig symbol :kconfig:option:`CONFIG_FLASH_RA_WRITE_PROTECT` - has been renamed to :kconfig:option:`CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT`. - -* Separate the file ``renesas,ra-nv-flash.yaml`` into 2 files ``renesas,ra-nv-code-flash.yaml`` - and ``renesas,ra-nv-data-flash.yaml``. -* Separate the ``compatible`` from ``renesas,ra-nv-flash`` to :dtcompatible:`renesas,ra-nv-code-flash.yaml` - and :dtcompatible:`renesas,ra-nv-data-flash.yaml`. - Stepper ======= @@ -320,12 +275,6 @@ Bluetooth Audio * ``CONFIG_BT_CSIP_SET_MEMBER_NOTIFIABLE`` has been renamed to :kconfig:option:`CONFIG_BT_CSIP_SET_MEMBER_SIRK_NOTIFIABLE``. (:github:`86763``) -* ``bt_csip_set_member_get_sirk`` has been removed. Use :c:func:`bt_csip_set_member_get_info` to get - the SIRK (and other information). (:github:`86996`) - -* ``BT_AUDIO_CONTEXT_TYPE_PROHIBITED`` has been renamed to - :c:enumerator:`BT_AUDIO_CONTEXT_TYPE_NONE`. (:github:`89506`) - Bluetooth HCI ============= @@ -356,9 +305,6 @@ Bluetooth Host * The macro ``BT_GATT_CCC_INITIALIZER`` in :zephyr_file:`include/zephyr/bluetooth/gatt.h` has been renamed to :c:macro:`BT_GATT_CCC_MANAGED_USER_DATA_INIT`. (:github:`88652`) -* The ``CONFIG_BT_ISO_TX_FRAG_COUNT`` Kconfig option was removed as it was completely unused. - Any uses of it can simply be removed. (:github:`89836`) - Bluetooth Classic ================= @@ -404,121 +350,9 @@ Networking the server commands, enable :kconfig:option:`NET_ZPERF_SERVER`. If server support is not needed, :kconfig:option:`ZVFS_POLL_MAX` can possibly be reduced. -* The L2 Wi-Fi shell now supports interface option for most commands, to accommodate this - change some of the existing options have been renamed. The following table - summarizes the changes: - - +------------------------+---------------------+--------------------+ - | Command(s) | Old option | New option | - +------------------------+---------------------+--------------------+ - | ``wifi connect`` | ``-i`` | ``-g`` | - | ``wifi ap enable`` | | | - +------------------------+---------------------+--------------------+ - | ``wifi twt setup`` | ``-i`` | ``-p`` | - +------------------------+---------------------+--------------------+ - | ``wifi ap config`` | ``-i`` | ``-t`` | - +------------------------+---------------------+--------------------+ - | ``wifi mode`` | ``--if-index`` | ``--iface`` | - | ``wifi channel`` | | | - | ``wifi packet_filter`` | | | - +------------------------+---------------------+--------------------+ - -OpenThread -========== - -* The OpenThread stack integration in Zephyr has undergone a major refactor. - The implementation has been moved from the Zephyr networking layer (``subsys/net/l2/openthread/``) - to a dedicated module (``modules/openthread/``). - -* OpenThread is now a standalone module in Zephyr. - It can be used independently of Zephyr's networking stack (L2 and IEEE802.15.4 shim layers). - This enables new use cases, such as applications that use OpenThread directly with their - own IEEE802.15.4 driver, or that do not need the full Zephyr networking stack. - -* Most functions in the :zephyr_file:`include/zephyr/net/openthread.h` file have been deprecated. - These deprecated APIs are still available for backward compatibility, but new applications should - use the new APIs provided by the OpenThread module. The following list summarizes the changes: - - * Mutex handling: - - * Previously: - - * ``openthread_api_mutex_lock`` - * ``openthread_api_mutex_try_lock`` - * ``openthread_api_mutex_unlock`` - - * Now use: - - * :c:func:`openthread_mutex_lock` - * :c:func:`openthread_mutex_try_lock` - * :c:func:`openthread_mutex_unlock` - - * OpenThread starting: - - * Previously: ``openthread_start`` - * Now use: :c:func:`openthread_run` - - * Callback registration: - - * Previously: - - * ``openthread_state_changed_cb_register`` - * ``openthread_state_changed_cb_unregister`` - - * Now use: - - * :c:func:`openthread_state_changed_callback_register` - * :c:func:`openthread_state_changed_callback_unregister` - - * Callback structure: - - * Previously: ``openthread_state_changed_cb`` - * Now use: :c:struct:`openthread_state_changed_callback` - - * The following :c:struct:`openthread_context` struct fields are deprecated and shall not be used - in new code anymore: - - * ``instance`` - * ``api_lock`` - * ``work_q`` - * ``api_work`` - * ``state_change_cbs`` - - * The new functions that were not present before: - - * :c:func:`openthread_init` to initialize the OpenThread stack. - * :c:func:`openthread_stop` to stop and disable the OpenThread stack. - * :c:func:`openthread_set_receive_cb` to set the receive callback for the OpenThread stack. - -* The OpenThread-related Kconfig options from ``subsys/net/l2/openthread/Kconfig`` - have been moved to :zephyr_file:`modules/openthread/Kconfig`. All Kconfig options remain the same. - You can still use them in the same way as before, but to modify them, use the new path in the - menuconfig or guiconfig. - -* If the :kconfig:option:`CONFIG_NET_L2_OPENTHREAD` Kconfig option is enabled, Zephyr's L2 layer - will use the new OpenThread module API as its backend. The L2 layer no longer implements - OpenThread itself, but delegates the implementation to the module. - -* For existing applications using OpenThread through Zephyr's networking stack: - - * Your application should continue to work, as the old APIs are still available for compatibility. - However, you are encouraged to migrate to the new APIs for future-proofing and use the new - modular structure. - * Update any references to OpenThread Kconfig options to use the new path - (``modules/openthread/Kconfig``) in your configuration tools. - -* For applications using :c:struct:`openthread_context` or other deprecated APIs: - - * Begin migrating to the new APIs. The deprecated APIs will be removed in a future release. - * Avoid direct use of :c:struct:`openthread_context` and related fields; use the new - initialization and callback registration functions instead. - -* For new applications or those using OpenThread without Zephyr L2: - - * Use the new initialization (:c:func:`openthread_init`), run (:c:func:`openthread_run`), - and callback registration APIs (:c:func:`openthread_state_change_callback_register`). - * You can now use OpenThread directly, without enabling Zephyr's L2 or IEEE802.15.4 layers, if - your use case allows. +* The OpenThread-related Kconfig options from ``subsys/net/l2/openthread/Kconfig`` have been moved to + ``modules/openthread/Kconfig``. All the Kconfig options remain the same. You can still use them in the + same way as before, but to modify them, use the new path in the menuconfig or guiconfig. SPI === @@ -526,47 +360,16 @@ SPI * Renamed the device tree property ``port_sel`` to ``port-sel``. * Renamed the device tree property ``chip_select`` to ``chip-select``. -xSPI -==== - -* On STM32 devices, external memories device tree descriptions for size and address are now split - in two separate properties to comply with specification recommendations. - - For instance, following external flash description ``reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits /`` - is changed to ``reg = <0>;`` ``size = ; / 512 Mbits */``. - - Note that the property gives the actual size of the memory device in bits. - Previous mapping address information is now described in xspi node at SoC dtsi level. - -Video -===== - -* 8 bit RAW Bayer formats BGGR8 / GBRG8 / GRBG8 / RGGB8 have been renamed by adding - a S prefix in front: - - ``VIDEO_PIX_FMT_BGGR8`` becomes ``VIDEO_PIX_FMT_SBGGR8`` - ``VIDEO_PIX_FMT_GBRG8`` becomes ``VIDEO_PIX_FMT_SGBRG8`` - ``VIDEO_PIX_FMT_GRBG8`` becomes ``VIDEO_PIX_FMT_SGRBG8`` - ``VIDEO_PIX_FMT_RGGB8`` becomes ``VIDEO_PIX_FMT_SRGGB8`` - -* On STM32 devices, the DCMI driver (:dtcompatible:`st,stm32-dcmi`) now relies on endpoint based - video-interfaces.yaml bindings for sensor interface properties (such as bus width and - synchronization signals). - Also the ``capture-rate`` property has been replaced by the usage of the frame interval API - :c:func:`video_set_frmival`. - See (:github:`89627`). - -* video_endpoint_id enum has been dropped. It is no longer a parameter in any video API. - -* video_buf_type enum has been added. It is a required parameter in the following video APIs: - - ``set_stream`` - ``video_stream_start`` - ``video_stream_stop`` - Other subsystems **************** +ZBus +==== + +* The function :c:func:`zbus_chan_add_obs` now requires a :c:struct:`zbus_observer_node` as an argument, + which was previously allocated through :c:func:`k_malloc` internally. The structure must remain valid + in memory until :c:func:`zbus_chan_rem_obs` is called. + Modules ******* diff --git a/doc/releases/release-notes-4.2.rst b/doc/releases/release-notes-4.2.rst index c4ae586ba5152..dae220ba47e2a 100644 --- a/doc/releases/release-notes-4.2.rst +++ b/doc/releases/release-notes-4.2.rst @@ -103,16 +103,11 @@ Deprecated APIs and options deprecated, because support for anonymous authentication had been removed from the hawkBit server in version 0.8.0. -* The :kconfig:option:`CONFIG_BT_CONN_TX_MAX` Kconfig option has been deprecated. The number of - pending TX buffers is now aligned with the :kconfig:option:`CONFIG_BT_BUF_ACL_TX_COUNT` Kconfig - option. - New APIs and options ==================== * Architectures - * NIOS2 Architecture was removed from Zephyr. * :kconfig:option:`ARCH_HAS_VECTOR_TABLE_RELOCATION` * :kconfig:option:`CONFIG_SRAM_VECTOR_TABLE` moved from ``zephyr/Kconfig.zephyr`` to ``zephyr/arch/Kconfig`` and added dependencies to it. @@ -180,12 +175,7 @@ New APIs and options * OpenThread - * Moved OpenThread-related Kconfig options from :zephyr_file:`subsys/net/l2/openthread/Kconfig` - to :zephyr_file:`modules/openthread/Kconfig`. - * Refactored OpenThread networking API, see the OpenThread section of the - :ref:`migration guide `. - * :kconfig:option:`CONFIG_OPENTHREAD_SYS_INIT` - * :kconfig:option:`CONFIG_OPENTHREAD_SYS_INIT_PRIORITY` + * Moved OpenThread-related Kconfig options from ``subsys/net/l2/openthread/Kconfig`` to ``modules/openthread/Kconfig``. * zperf @@ -227,31 +217,10 @@ New APIs and options * :kconfig:option:`CONFIG_NVME_PRP_PAGE_SIZE` -* Debug - - * Core Dump - - * :kconfig:option:`CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP`, enabled by default for ARM Cortex M when :kconfig:option:`CONFIG_DEBUG_COREDUMP_MEMORY_DUMP_MIN` is selected. - * :kconfig:option:`CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY` - * :kconfig:option:`CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY_SIZE` - * Other * :kconfig:option:`CONFIG_LV_Z_COLOR_MONO_HW_INVERSION` -* ZBus - - * Runtime observers can work without heap. Now it is possible to choose between static, dynamic, - and none allocation for the runtime observers nodes. - * Runtime observers using :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_NONE` must use - the new function :c:func:`zbus_chan_add_obs_with_node`. - - * :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_DYNAMIC` - * :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_STATIC` - * :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_NONE` - * :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_POOL_SIZE` - - New Boards ********** @@ -273,43 +242,10 @@ New Boards * :zephyr:board:`versalnet_rpu` (``versalnet_rpu``) -* Aesc Silicon - - * :zephyr:board:`elemrv` (``elemrv``) - -* aithinker - - * :zephyr:board:`ai_wb2_12f` (``ai_wb2_12f``) - -* Ambiq Micro, Inc. - - * :zephyr:board:`apollo510_evb` (``apollo510_evb``) - -* Analog Devices, Inc. - - * :zephyr:board:`max32657evkit` (``max32657evkit``) - -* BeagleBoard.org Foundation - - * :zephyr:board:`pocketbeagle_2` (``pocketbeagle_2``) - * Blues Wireless * :zephyr:board:`cygnet` (``cygnet``) -* Bouffalo Lab (Nanjing) Co., Ltd. - - * :zephyr:board:`bl604e_iot_dvk` (``bl604e_iot_dvk``) - -* Espressif Systems - - * :zephyr:board:`esp32_devkitc` (``esp32_devkitc``) - -* Ezurio - - * :zephyr:board:`bl54l15_dvk` (``bl54l15_dvk``) - * :zephyr:board:`bl54l15u_dvk` (``bl54l15u_dvk``) - * FANKE Technology Co., Ltd. * :zephyr:board:`fk743m5_xih6` (``fk743m5_xih6``) @@ -338,20 +274,14 @@ New Boards * :zephyr:board:`ttgo_toiplus` (``ttgo_toiplus``) * :zephyr:board:`twatch_s3` (``twatch_s3``) -* Microchip Technology Inc. - - * :zephyr:board:`mec_assy6941` (``mec_assy6941``) - * Nuvoton Technology Corporation * :zephyr:board:`numaker_m55m1` (``numaker_m55m1``) * NXP Semiconductors - * :zephyr:board:`frdm_mcxa153` (``frdm_mcxa153``) * :zephyr:board:`frdm_mcxa166` (``frdm_mcxa166``) * :zephyr:board:`frdm_mcxa276` (``frdm_mcxa276``) - * :zephyr:board:`mcx_n9xx_evk` (``mcx_n9xx_evk``) * Octavo Systems LLC @@ -366,17 +296,10 @@ New Boards * :zephyr:board:`pico_plus2` (``pico_plus2``) -* QEMU - - * :zephyr:board:`qemu_rx` (``qemu_rx``) - * Renesas Electronics Corporation - * :zephyr:board:`rsk_rx130` (``rsk_rx130``) - * :zephyr:board:`rza2m_evk` (``rza2m_evk``) * :zephyr:board:`rza3ul_smarc` (``rza3ul_smarc``) * :zephyr:board:`rzg2l_smarc` (``rzg2l_smarc``) - * :zephyr:board:`rzg2lc_smarc` (``rzg2lc_smarc``) * :zephyr:board:`rzn2l_rsk` (``rzn2l_rsk``) * :zephyr:board:`rzt2l_rsk` (``rzt2l_rsk``) * :zephyr:board:`rzt2m_rsk` (``rzt2m_rsk``) @@ -391,10 +314,6 @@ New Boards * :zephyr:board:`ganymed_sk` (``ganymed_sk``) -* Shanghai Ruiside Electronic Technology Co., Ltd. - - * :zephyr:board:`art_pi2` (``art_pi2``) - * Silicon Laboratories * :zephyr:board:`slwrb4180b` (``slwrb4180b``) @@ -402,19 +321,13 @@ New Boards * STMicroelectronics * :zephyr:board:`nucleo_f439zi` (``nucleo_f439zi``) - * :zephyr:board:`nucleo_wba65ri` (``nucleo_wba65ri``) * :zephyr:board:`stm32h757i_eval` (``stm32h757i_eval``) * :zephyr:board:`stm32mp135f_dk` (``stm32mp135f_dk``) - * :zephyr:board:`stm32u5g9j_dk2` (``stm32u5g9j_dk2``) * Texas Instruments * :zephyr:board:`sk_am64` (``sk_am64``) -* Variscite Ltd. - - * :zephyr:board:`imx8mp_var_som` (``imx8mp_var_som``) - * WinChipHead * :zephyr:board:`ch32v003f4p6_dev_board` (``ch32v003f4p6_dev_board``) @@ -440,8 +353,6 @@ New Drivers * :dtcompatible:`adi,ad4050-adc` * :dtcompatible:`adi,ad4052-adc` * :dtcompatible:`adi,ad4130-adc` - * :dtcompatible:`ite,it51xxx-adc` - * :dtcompatible:`realtek,rts5912-adc` * :dtcompatible:`renesas,rz-adc` * Audio @@ -451,17 +362,11 @@ New Drivers * Charger * :dtcompatible:`ti,bq25713` - * :dtcompatible:`x-powers,axp2101-charger` * Clock control * :dtcompatible:`ite,it51xxx-ecpm` * :dtcompatible:`nordic,nrfs-audiopll` - * :dtcompatible:`renesas,rx-cgc-pclk` - * :dtcompatible:`renesas,rx-cgc-pclk-block` - * :dtcompatible:`renesas,rx-cgc-pll` - * :dtcompatible:`renesas,rx-cgc-root-clock` - * :dtcompatible:`renesas,rza2m-cpg` * :dtcompatible:`st,stm32mp13-cpu-clock-mux` * :dtcompatible:`st,stm32mp13-pll-clock` * :dtcompatible:`wch,ch32v20x_30x-pll-clock` @@ -474,16 +379,11 @@ New Drivers * Counter * :dtcompatible:`ite,it8xxx2-counter` - * :dtcompatible:`neorv32,gptmr` - * :dtcompatible:`realtek,rts5912-timer` - * :dtcompatible:`wch,gptm` * :dtcompatible:`zephyr,native-sim-counter` * CPU * :dtcompatible:`intel,bartlett-lake` - * :dtcompatible:`openhwgroup,cva6` - * :dtcompatible:`renesas,rx` * :dtcompatible:`wch,qingke-v4c` * :dtcompatible:`zephyr,native-sim-cpu` @@ -497,11 +397,8 @@ New Drivers * Display - * :dtcompatible:`sinowealth,sh1122` - * :dtcompatible:`sitronix,st75256` * :dtcompatible:`sitronix,st7567` * :dtcompatible:`sitronix,st7701` - * :dtcompatible:`solomon,ssd1320` * :abbr:`DMA (Direct Memory Access)` @@ -516,14 +413,8 @@ New Drivers * :dtcompatible:`ti,dp83867` * :dtcompatible:`xlnx,axi-ethernet-1.00.a` -* Firmware - - * :dtcompatible:`nordic,ironside-call` - * :dtcompatible:`nxp,scmi-cpu` - * Flash controller - * :dtcompatible:`renesas,rx-flash` * :dtcompatible:`silabs,series2-flash-controller` * File system @@ -535,51 +426,30 @@ New Drivers * :dtcompatible:`adi,max14915-gpio` * :dtcompatible:`adi,max14917-gpio` * :dtcompatible:`adi,max22199-gpio` - * :dtcompatible:`bflb,gpio` - * :dtcompatible:`espressif,esp32-lpgpio` * :dtcompatible:`ite,it51xxx-gpio` * :dtcompatible:`nxp,lcd-pmod` * :dtcompatible:`raspberrypi,pico-gpio-port` * :dtcompatible:`renesas,ra-parallel-graphics-header` - * :dtcompatible:`renesas,rx-gpio` - * :dtcompatible:`renesas,rza2m-gpio` - * :dtcompatible:`renesas,rza2m-gpio-int` * :abbr:`I2C (Inter-Integrated Circuit)` * :dtcompatible:`cdns,i2c` - * :dtcompatible:`ite,it51xxx-i2c` * :dtcompatible:`litex,litei2c` * :dtcompatible:`renesas,ra-i2c-sci-b` * :dtcompatible:`renesas,rz-riic` * :dtcompatible:`sensry,sy1xx-i2c` - * :dtcompatible:`wch,i2c` - -* :abbr:`I3C (Improved Inter-Integrated Circuit)` - - * :dtcompatible:`ite,it51xxx-i3cm` - * :dtcompatible:`ite,it51xxx-i3cs` * Input - * :dtcompatible:`ite,it51xxx-kbd` * :dtcompatible:`realtek,rts5912-kbd` * :dtcompatible:`st,stm32-tsc` * :dtcompatible:`tsc-keys` - * :dtcompatible:`vishay,vs1838b` * Interrupt controller * :dtcompatible:`ite,it51xxx-intc` * :dtcompatible:`ite,it51xxx-wuc` * :dtcompatible:`ite,it51xxx-wuc-map` - * :dtcompatible:`renesas,rx-icu` - -* :abbr:`LED (Light Emitting Diode)` - - * :dtcompatible:`dac-leds` - * :dtcompatible:`x-powers,axp192-led` - * :dtcompatible:`x-powers,axp2101-led` * Mailbox @@ -592,7 +462,6 @@ New Drivers * Memory controller - * :dtcompatible:`adi,max32-hpb` * :dtcompatible:`realtek,rts5912-bbram` * :dtcompatible:`st,stm32-xspi-psram` @@ -602,15 +471,10 @@ New Drivers * :dtcompatible:`ambiq,iom` * :dtcompatible:`x-powers,axp2101` -* :abbr:`MIPI DBI (Mobile Industry Processor Interface Display Bus Interface)` - - * :dtcompatible:`nxp,mipi-dbi-dcnano-lcdif` - * Miscellaneous * :dtcompatible:`nordic,nrf-mpc` * :dtcompatible:`renesas,ra-ulpt` - * :dtcompatible:`renesas,rx-sci` * :dtcompatible:`renesas,rz-sci` * Multi-bit SPI @@ -619,11 +483,7 @@ New Drivers * :abbr:`MTD (Memory Technology Device)` - * :dtcompatible:`fixed-subpartitions` * :dtcompatible:`jedec,mspi-nor` - * :dtcompatible:`renesas,ra-nv-code-flash` - * :dtcompatible:`renesas,ra-nv-data-flash` - * :dtcompatible:`renesas,rx-nv-flash` * Networking @@ -631,31 +491,19 @@ New Drivers * Pin control - * :dtcompatible:`ambiq,apollo5-pinctrl` * :dtcompatible:`arm,mps2-pinctrl` * :dtcompatible:`arm,mps3-pinctrl` * :dtcompatible:`arm,v2m_beetle-pinctrl` - * :dtcompatible:`bflb,pinctrl` - * :dtcompatible:`renesas,rx-pinctrl` - * :dtcompatible:`renesas,rx-pinmux` * :dtcompatible:`renesas,rza-pinctrl` - * :dtcompatible:`renesas,rza2m-pinctrl` * :dtcompatible:`renesas,rzn-pinctrl` * :dtcompatible:`renesas,rzt-pinctrl` * :dtcompatible:`renesas,rzv-pinctrl` * :dtcompatible:`wch,20x_30x-afio` -* Power management - - * :dtcompatible:`realtek,rts5912-ulpm` - * :abbr:`PWM (Pulse Width Modulation)` * :dtcompatible:`arduino-header-pwm` - * :dtcompatible:`neorv32,pwm` - * :dtcompatible:`realtek,rts5912-pwm` * :dtcompatible:`silabs,siwx91x-pwm` - * :dtcompatible:`wch,gptm-pwm` * Regulator @@ -675,10 +523,9 @@ New Drivers * :dtcompatible:`nxp,pcf2123` * :dtcompatible:`realtek,rts5912-rtc` -* :abbr:`SDHC (Secure Digital Host Controller)` +* SDHC * :dtcompatible:`ambiq,sdio` - * :dtcompatible:`xlnx,versal-8.9a` * Sensors @@ -690,58 +537,34 @@ New Drivers * :dtcompatible:`meas,ms5837-02ba` * :dtcompatible:`meas,ms5837-30ba` * :dtcompatible:`pixart,paa3905` - * :dtcompatible:`pixart,paj7620` * :dtcompatible:`pixart,pat9136` * :dtcompatible:`st,lsm6dsv32x` * :dtcompatible:`vishay,veml6031` - * :dtcompatible:`we,wsen-itds-2533020201601` * Serial controller - * :dtcompatible:`bflb,uart` - * :dtcompatible:`espressif,esp32-lpuart` * :dtcompatible:`ite,it51xxx-uart` - * :dtcompatible:`renesas,rx-uart-sci` - * :dtcompatible:`renesas,rx-uart-sci-qemu` * :dtcompatible:`renesas,rz-sci-uart` - * :dtcompatible:`renesas,rza2m-scif-uart` * :dtcompatible:`zephyr,native-pty-uart` * :abbr:`SPI (Serial Peripheral Interface)` * :dtcompatible:`cdns,spi` - * :dtcompatible:`silabs,gspi` - * :dtcompatible:`ti,cc23x0-spi` - -* Stepper - - * :dtcompatible:`adi,tmc51xx` - -* Tachometer - - * :dtcompatible:`ite,it51xxx-tach` - * :dtcompatible:`realtek,rts5912-tach` * Timer * :dtcompatible:`ite,it51xxx-timer` * :dtcompatible:`renesas,ra-ulpt-timer` - * :dtcompatible:`renesas,rx-timer-cmt` - * :dtcompatible:`renesas,rx-timer-cmt-start-control` - * :dtcompatible:`renesas,rza2m-ostm` * USB * :dtcompatible:`adi,max32-usbhs` - * :dtcompatible:`st,stm32n6-otghs` * Watchdog - * :dtcompatible:`ite,it51xxx-watchdog` * :dtcompatible:`realtek,rts5912-watchdog` * :dtcompatible:`renesas,ra-wdt` * :dtcompatible:`silabs,siwx91x-wdt` - * :dtcompatible:`wch,iwdg` New Samples *********** @@ -754,16 +577,12 @@ New Samples * :zephyr:code-sample:`debug-ulp` * :zephyr:code-sample:`echo-ulp` * :zephyr:code-sample:`fatfs-fstab` -* :zephyr:code-sample:`net-pkt-filter` -* :zephyr:code-sample:`paj7620_gesture` * :zephyr:code-sample:`pressure_interrupt` * :zephyr:code-sample:`pressure_polling` * :zephyr:code-sample:`renesas_comparator` * :zephyr:code-sample:`rz-openamp-linux-zephyr` * :zephyr:code-sample:`spis-wakeup` * :zephyr:code-sample:`stepper` -* :zephyr:code-sample:`uart_async` -* :zephyr:code-sample:`uuid` * :zephyr:code-sample:`veml6031` Other notable changes diff --git a/doc/services/dsp/index.rst b/doc/services/dsp/index.rst index 9b0b6a9e8a157..38d4ee32d6779 100644 --- a/doc/services/dsp/index.rst +++ b/doc/services/dsp/index.rst @@ -18,6 +18,7 @@ ARC Optimized ARM Optimized ARM64 Optimized MIPS Unoptimized +NIOS2 Unoptimized POSIX Unoptimized RISCV Unoptimized RISCV64 Unoptimized diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 473982e4dbd01..542ef326303e2 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -678,21 +678,6 @@ Enable this option group with :kconfig:option:`CONFIG_XSI_REALTIME`. When this option group is enabled, the ``_XOPEN_REALTIME`` feature test macro will be defined to a value other than -1. -.. _posix_option_group_xsi_single_process: - -XSI_SINGLE_PROCESS -++++++++++++++++++ - -Enable this option group with :kconfig:option:`CONFIG_XSI_SINGLE_PROCESS`. - -.. csv-table:: XSI_SINGLE_PROCESS - :header: API, Supported - :widths: 50,10 - - gethostid(),yes - gettimeofday(),yes - putenv(),yes - .. _posix_option_group_xsi_system_logging: XSI_SYSTEM_LOGGING diff --git a/doc/services/storage/settings/index.rst b/doc/services/storage/settings/index.rst index d5a244b04fb88..4f8831e3a11ee 100644 --- a/doc/services/storage/settings/index.rst +++ b/doc/services/storage/settings/index.rst @@ -78,14 +78,6 @@ backend. This gets called when loading values from persistent storage using :c:func:`settings_load()`. -**csi_load_one** - This gets called when loading only one item from persistent storage using - :c:func:`settings_load_one()`. - -**csi_get_val_len** - This gets called when getting a value's length from persistent storage using - :c:func:`settings_get_val_len()`. - **csi_save** This gets called when saving a single setting to persistent storage using :c:func:`settings_save_one()`. @@ -156,14 +148,6 @@ After all data is loaded, the ``h_commit`` handler is issued, signalling the application that the settings were successfully retrieved. -Alternatively, a call to :c:func:`settings_load_one()` will load only one -Settings entry and store it in the provided buffer. - -Optionally, to get only the value's length associated with the Settings entry, -a call to :c:func:`settings_get_val_len()` can be performed. -This is used for example by applications that allocates dynamically the data -buffer and needs to get the data size before reading it by settings_load_one(). - Technically FCB and file backends may store some history of the entities. This means that the newest data entity is stored after any older existing data entities. diff --git a/doc/services/zbus/index.rst b/doc/services/zbus/index.rst index 3ed574835b909..a7d6b7c55c4bb 100644 --- a/doc/services/zbus/index.rst +++ b/doc/services/zbus/index.rst @@ -848,36 +848,29 @@ The following code has the exact behavior of the code in :ref:`reading from a ch Runtime observer registration ----------------------------- -It is possible to add observers to channels in runtime. Set the -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` to enable the feature. This feature uses the heap to -allocate the nodes dynamically, a memory slab to allocate the nodes statically, or user-provided -nodes. It depends on the :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC`, which can be -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_DYNAMIC`, -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_STATIC`, and -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_NONE`. The dynamic is the default. When -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_STATIC` is enabled, you need to set the -number of runtime observers you are going to use by setting the -:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_POOL_SIZE` configuration. The following example -illustrates the runtime registration usage. +It is possible to add observers to channels at runtime if +:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` is enabled. In addition to the channel and observer +references, :c:func:`zbus_chan_add_obs` also requires a :c:struct:`zbus_observer_node` to link the two +together, which must remain valid in memory for the duration that the observer is attached to the +channel. The simplest way to achieve this is to make the structure ``static``. .. code-block:: c ZBUS_LISTENER_DEFINE(my_listener, callback); // ... void thread_entry(void) { + static struct zbus_observer_node obs_node; // ... /* Adding the observer to channel chan1 */ - zbus_chan_add_obs(&chan1, &my_listener, K_NO_WAIT); + zbus_chan_add_obs(&chan1, &my_listener, &obs_node, K_NO_WAIT); /* Removing the observer from channel chan1 */ zbus_chan_rm_obs(&chan1, &my_listener, K_NO_WAIT); - .. warning:: - The :c:struct:`zbus_observer_node` can only be re-used in :c:func:`zbus_chan_add_obs_with_node` after removing + The :c:struct:`zbus_observer_node` can only be re-used in :c:func:`zbus_chan_add_obs` after removing the channel observer it was first associated with through :c:func:`zbus_chan_rm_obs`. - Samples ******* @@ -943,15 +936,7 @@ Related configuration options: a pool for the message subscriber for a set of channels; * :kconfig:option:`CONFIG_ZBUS_MSG_SUBSCRIBER_NET_BUF_STATIC_DATA_SIZE` the biggest message of zbus channels to be transported into a message buffer; -* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` enables the runtime observer registration; -* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_DYNAMIC` allocate the runtime observers - dynamically using the heap; -* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_STATIC` allocate the runtime observers - statically using a memory slab; -* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_POOL_SIZE` the amount of enabled runtime - observers to statically allocate. -* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS_NODE_ALLOC_NONE` use user-provided runtime - observers nodes; +* :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` enables the runtime observer registration. API Reference ************* diff --git a/drivers/adc/adc_ambiq.c b/drivers/adc/adc_ambiq.c index ac8f7793f078c..5af7b1301b14e 100644 --- a/drivers/adc/adc_ambiq.c +++ b/drivers/adc/adc_ambiq.c @@ -52,7 +52,7 @@ static int adc_ambiq_set_resolution(am_hal_adc_slot_prec_e *prec, uint8_t adc_re case 12: *prec = AM_HAL_ADC_SLOT_12BIT; break; -#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#if !defined(CONFIG_SOC_SERIES_APOLLO4X) case 14: *prec = AM_HAL_ADC_SLOT_14BIT; break; @@ -80,7 +80,7 @@ static int adc_ambiq_slot_config(const struct device *dev, const struct adc_sequ ADCSlotConfig.eChannel = channel; ADCSlotConfig.bWindowCompare = false; ADCSlotConfig.bEnabled = true; -#if !defined(CONFIG_SOC_SERIES_APOLLO3X) +#if defined(CONFIG_SOC_SERIES_APOLLO4X) ADCSlotConfig.ui32TrkCyc = AM_HAL_ADC_MIN_TRKCYC; #endif if (AM_HAL_STATUS_SUCCESS != @@ -101,6 +101,8 @@ static void adc_ambiq_isr(const struct device *dev) /* Read the interrupt status. */ am_hal_adc_interrupt_status(data->adcHandle, &ui32IntMask, true); + /* Clear the ADC interrupt.*/ + am_hal_adc_interrupt_clear(data->adcHandle, ui32IntMask); /* * If we got a conversion completion interrupt (which should be our only @@ -117,8 +119,6 @@ static void adc_ambiq_isr(const struct device *dev) am_hal_adc_disable(data->adcHandle); adc_context_on_sampling_done(&data->ctx, dev); } - /* Clear the ADC interrupt.*/ - am_hal_adc_interrupt_clear(data->adcHandle, ui32IntMask); } static int adc_ambiq_check_buffer_size(const struct adc_sequence *sequence, uint8_t active_channels) @@ -280,9 +280,9 @@ static int adc_ambiq_init(const struct device *dev) /* Initialize the ADC and get the handle*/ if (AM_HAL_STATUS_SUCCESS != - am_hal_adc_initialize(0, &data->adcHandle)) { + am_hal_adc_initialize((cfg->base - ADC_BASE) / (cfg->size * 4), &data->adcHandle)) { ret = -ENODEV; - LOG_ERR("Failed to initialize ADC, code:%d", ret); + LOG_ERR("Faile to initialize ADC, code:%d", ret); return ret; } @@ -292,7 +292,7 @@ static int adc_ambiq_init(const struct device *dev) /* Set up the ADC configuration parameters. These settings are reasonable * for accurate measurements at a low sample rate. */ -#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#if !defined(CONFIG_SOC_SERIES_APOLLO4X) ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC; ADCConfig.eReference = AM_HAL_ADC_REFSEL_INT_1P5; #else diff --git a/drivers/adc/adc_nrfx_saadc.c b/drivers/adc/adc_nrfx_saadc.c index 8d8c6a01ad308..22a839a5f3543 100644 --- a/drivers/adc/adc_nrfx_saadc.c +++ b/drivers/adc/adc_nrfx_saadc.c @@ -40,7 +40,7 @@ static const uint32_t saadc_psels[NRF_SAADC_AIN13 + 1] = { [NRF_SAADC_AIN12] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 9), [NRF_SAADC_AIN13] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 9), }; -#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) +#elif defined(CONFIG_SOC_COMPATIBLE_NRF54LX) static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = { [NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), [NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), @@ -54,20 +54,6 @@ static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = { [NRF_SAADC_AVDD] = NRF_SAADC_INPUT_AVDD, [NRF_SAADC_DVDD] = NRF_SAADC_INPUT_DVDD, }; -#elif defined(CONFIG_SOC_COMPATIBLE_NRF54LX) -static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = { - [NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), - [NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), - [NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(30U, 1), - [NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(29U, 1), - [NRF_SAADC_AIN4] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), - [NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), - [NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), - [NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1), - [NRF_SAADC_VDD] = NRF_SAADC_INPUT_VDD, - [NRF_SAADC_AVDD] = NRF_SAADC_INPUT_AVDD, - [NRF_SAADC_DVDD] = NRF_SAADC_INPUT_DVDD, -}; #endif #else @@ -332,13 +318,8 @@ static int adc_nrfx_channel_setup(const struct device *dev, } if (config.mode == NRF_SAADC_MODE_DIFFERENTIAL) { -#if defined(CONFIG_NRF_PLATFORM_HALTIUM) - if ((input_negative > NRF_SAADC_AIN7) != - (channel_cfg->input_positive > NRF_SAADC_AIN7)) { -#else if (input_negative > NRF_SAADC_AIN7 || input_negative < NRF_SAADC_AIN0) { -#endif return -EINVAL; } @@ -738,27 +719,6 @@ static DEVICE_API(adc, adc_nrfx_driver_api) = { #endif }; -#if defined(CONFIG_NRF_PLATFORM_HALTIUM) -/* AIN8-AIN14 inputs are on 3v3 GPIO port and they cannot be mixed with other - * analog inputs (from 1v8 ports) in differential mode. - */ -#define CH_IS_3V3(val) (val >= NRF_SAADC_AIN8) - -#define MIXED_3V3_1V8_INPUTS(node) \ - (DT_NODE_HAS_PROP(node, zephyr_input_negative) && \ - (CH_IS_3V3(DT_PROP_OR(node, zephyr_input_negative, 0)) != \ - CH_IS_3V3(DT_PROP_OR(node, zephyr_input_positive, 0)))) -#else -#define MIXED_3V3_1V8_INPUTS(node) false -#endif - -#define VALIDATE_CHANNEL_CONFIG(node) \ - BUILD_ASSERT(MIXED_3V3_1V8_INPUTS(node) == false, \ - "1v8 inputs cannot be mixed with 3v3 inputs"); - -/* Validate configuration of all channels. */ -#define VALIDATE_CHANNELS_CONFIG(inst) DT_FOREACH_CHILD(DT_DRV_INST(inst), VALIDATE_CHANNEL_CONFIG) - /* * There is only one instance on supported SoCs, so inst is guaranteed * to be 0 if any instance is okay. (We use adc_0 above, so the driver @@ -771,7 +731,6 @@ static DEVICE_API(adc, adc_nrfx_driver_api) = { #define SAADC_INIT(inst) \ BUILD_ASSERT((inst) == 0, \ "multiple instances not supported"); \ - VALIDATE_CHANNELS_CONFIG(inst) \ PM_DEVICE_DT_INST_DEFINE(0, saadc_pm_hook, 1); \ DEVICE_DT_INST_DEFINE(0, \ init_saadc, \ diff --git a/drivers/adc/adc_realtek_rts5912.c b/drivers/adc/adc_realtek_rts5912.c index 373a54b5a8608..5f517209a7b7b 100644 --- a/drivers/adc/adc_realtek_rts5912.c +++ b/drivers/adc/adc_realtek_rts5912.c @@ -260,7 +260,6 @@ static int adc_rts5912_init(const struct device *dev) regs->ctrl = ADC_CTRL_RST; - NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_rts5912_single_isr, DEVICE_DT_INST_GET(0), 0); irq_enable(DT_INST_IRQN(0)); diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 34d871509ba83..fd8008234706d 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -819,9 +819,6 @@ static void dma_callback(const struct device *dev, void *user_data, LL_ADC_REG_StopConversion(adc); #endif dma_stop(data->dma.dma_dev, data->dma.channel); - if (data->ctx.options.interval_us != 0U) { - adc_context_disable_timer(&data->ctx); - } adc_context_complete(&data->ctx, status); } } diff --git a/drivers/audio/CMakeLists.txt b/drivers/audio/CMakeLists.txt index ca2d3230d9c8c..9fb0dfe912ae9 100644 --- a/drivers/audio/CMakeLists.txt +++ b/drivers/audio/CMakeLists.txt @@ -11,5 +11,4 @@ zephyr_library_sources_ifdef(CONFIG_AUDIO_TAS6422DAC tas6422dac.c) zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_SHELL codec_shell.c) zephyr_library_sources_ifdef(CONFIG_AUDIO_DMIC_MCUX dmic_mcux.c) zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_WM8904 wm8904.c) -zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_WM8962 wm8962.c) zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_CS43L22 cs43l22.c) diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig index d6399c14c2ec3..ffd29112492d7 100644 --- a/drivers/audio/Kconfig +++ b/drivers/audio/Kconfig @@ -40,7 +40,6 @@ source "drivers/audio/Kconfig.tas6422dac" source "drivers/audio/Kconfig.tlv320aic3110" source "drivers/audio/Kconfig.tlv320dac" source "drivers/audio/Kconfig.wm8904" -source "drivers/audio/Kconfig.wm8962" endif # AUDIO_CODEC diff --git a/drivers/audio/Kconfig.wm8962 b/drivers/audio/Kconfig.wm8962 deleted file mode 100644 index 824b08f9bffdb..0000000000000 --- a/drivers/audio/Kconfig.wm8962 +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2025 NXP -# SPDX-License-Identifier: Apache-2.0 - -config AUDIO_CODEC_WM8962 - bool "Wolfson WM8962 codec support" - default y - select I2C - depends on DT_HAS_WOLFSON_WM8962_ENABLED - help - Enable support for the Wolfson WM8962 codec diff --git a/drivers/audio/dmic_nrfx_pdm.c b/drivers/audio/dmic_nrfx_pdm.c index 2e8d71b0a93ce..ea78330deb5bc 100644 --- a/drivers/audio/dmic_nrfx_pdm.c +++ b/drivers/audio/dmic_nrfx_pdm.c @@ -18,21 +18,14 @@ LOG_MODULE_REGISTER(dmic_nrfx_pdm, CONFIG_AUDIO_DMIC_LOG_LEVEL); #if CONFIG_SOC_SERIES_NRF54HX #define DMIC_NRFX_CLOCK_FREQ MHZ(16) #define DMIC_NRFX_CLOCK_FACTOR 8192 -#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(DT_NODELABEL(audiopll), frequency, 0) #else #define DMIC_NRFX_CLOCK_FREQ MHZ(32) #define DMIC_NRFX_CLOCK_FACTOR 4096 -#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(DT_NODELABEL(aclk), clock_frequency, \ - DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0)) #endif struct dmic_nrfx_pdm_drv_data { const nrfx_pdm_t *pdm; -#if CONFIG_CLOCK_CONTROL_NRF struct onoff_manager *clk_mgr; -#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL - const struct device *audiopll_dev; -#endif struct onoff_client clk_cli; struct k_mem_slab *mem_slab; uint32_t block_size; @@ -68,35 +61,6 @@ static void stop_pdm(struct dmic_nrfx_pdm_drv_data *drv_data) nrfx_pdm_stop(drv_data->pdm); } -static int request_clock(struct dmic_nrfx_pdm_drv_data *drv_data) -{ - if (!drv_data->request_clock) { - return 0; - } -#if CONFIG_CLOCK_CONTROL_NRF - return onoff_request(drv_data->clk_mgr, &drv_data->clk_cli); -#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL - return nrf_clock_control_request(drv_data->audiopll_dev, NULL, &drv_data->clk_cli); -#else - return -ENOTSUP; -#endif -} - -static int release_clock(struct dmic_nrfx_pdm_drv_data *drv_data) -{ - if (!drv_data->request_clock) { - return 0; - } - -#if CONFIG_CLOCK_CONTROL_NRF - return onoff_release(drv_data->clk_mgr); -#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL - return nrf_clock_control_release(drv_data->audiopll_dev, NULL); -#else - return -ENOTSUP; -#endif -} - static void event_handler(const struct device *dev, const nrfx_pdm_evt_t *evt) { struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; @@ -155,10 +119,8 @@ static void event_handler(const struct device *dev, const nrfx_pdm_evt_t *evt) if (drv_data->active) { drv_data->active = false; - ret = release_clock(drv_data); - if (ret < 0) { - LOG_ERR("Failed to release clock: %d", ret); - return; + if (drv_data->request_clock) { + (void)onoff_release(drv_data->clk_mgr); } } } else if (evt->buffer_released) { @@ -229,11 +191,9 @@ static bool check_pdm_frequencies(const struct dmic_nrfx_pdm_drv_cfg *drv_cfg, { uint32_t req_rate = pdm_cfg->streams[0].pcm_rate; bool better_found = false; - const uint32_t src_freq = - (NRF_PDM_HAS_SELECTABLE_CLOCK && drv_cfg->clk_src == ACLK) - ? DMIC_NRFX_AUDIO_CLOCK_FREQ - : DMIC_NRFX_CLOCK_FREQ; + #if NRF_PDM_HAS_PRESCALER + uint32_t src_freq = 32 * 1000 * 1000UL; uint32_t req_freq = req_rate * ratio; uint32_t prescaler = src_freq / req_freq; uint32_t act_freq = src_freq / prescaler; @@ -264,6 +224,24 @@ static bool check_pdm_frequencies(const struct dmic_nrfx_pdm_drv_cfg *drv_cfg, } #else if (IS_ENABLED(CONFIG_SOC_SERIES_NRF53X) || IS_ENABLED(CONFIG_SOC_SERIES_NRF54HX)) { + const uint32_t src_freq = + (NRF_PDM_HAS_MCLKCONFIG && drv_cfg->clk_src == ACLK) + /* The DMIC_NRFX_PDM_DEVICE() macro contains build + * assertions that make sure that the ACLK clock + * source is only used when it is available and only + * with the "hfclkaudio-frequency" property defined, + * but the default value of 0 here needs to be used + * to prevent compilation errors when the property is + * not defined (this expression will be eventually + * optimized away then). + */ + /* TODO : PS does not provide correct formula for nRF54H20 PDM_CLK. + * Assume that master clock source frequency is 8 MHz. Remove once + * correct formula is found. + */ + ? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, + 0) + : DMIC_NRFX_CLOCK_FREQ; uint32_t req_freq = req_rate * ratio; /* As specified in the nRF5340 PS: * @@ -483,7 +461,7 @@ static int dmic_nrfx_pdm_configure(const struct device *dev, nrfx_cfg.edge = NRF_PDM_EDGE_LEFTRISING; channel->act_chan_map_lo = alt_map; } -#if NRF_PDM_HAS_SELECTABLE_CLOCK +#if NRF_PDM_HAS_MCLKCONFIG nrfx_cfg.mclksrc = drv_cfg->clk_src == ACLK ? NRF_PDM_MCLKSRC_ACLK : NRF_PDM_MCLKSRC_PCLK32M; @@ -511,10 +489,8 @@ static int dmic_nrfx_pdm_configure(const struct device *dev, * (which is always available without any additional actions), * it is required to request the proper clock to be running * before starting the transfer itself. - * Targets using CLKSELECT register to select clock source - * do not need to request audio clock. */ - drv_data->request_clock = (drv_cfg->clk_src != PCLK32M && !NRF_PDM_HAS_CLKSELECT); + drv_data->request_clock = (drv_cfg->clk_src != PCLK32M); drv_data->configured = true; return 0; } @@ -532,10 +508,8 @@ static int start_transfer(struct dmic_nrfx_pdm_drv_data *drv_data) LOG_ERR("Failed to start PDM: 0x%08x", err); ret = -EIO; - ret = release_clock(drv_data); - if (ret < 0) { - LOG_ERR("Failed to release clock: %d", ret); - return ret; + if (drv_data->request_clock) { + (void)onoff_release(drv_data->clk_mgr); } drv_data->active = false; @@ -555,12 +529,7 @@ static void clock_started_callback(struct onoff_manager *mgr, * the actual transfer in such case. */ if (!drv_data->active) { - int ret = release_clock(drv_data); - - if (ret < 0) { - LOG_ERR("Failed to release clock: %d", ret); - return; - } + (void)onoff_release(drv_data->clk_mgr); } else { (void)start_transfer(drv_data); } @@ -579,7 +548,7 @@ static int trigger_start(const struct device *dev) if (drv_data->request_clock) { sys_notify_init_callback(&drv_data->clk_cli.notify, clock_started_callback); - ret = request_clock(drv_data); + ret = onoff_request(drv_data->clk_mgr, &drv_data->clk_cli); if (ret < 0) { drv_data->active = false; @@ -655,11 +624,12 @@ static int dmic_nrfx_pdm_read(const struct device *dev, return ret; } +#if CONFIG_CLOCK_CONTROL_NRF static void init_clock_manager(const struct device *dev) { -#if CONFIG_CLOCK_CONTROL_NRF - clock_control_subsys_t subsys; struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; + clock_control_subsys_t subsys; + #if NRF_CLOCK_HAS_HFCLKAUDIO const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; @@ -673,12 +643,8 @@ static void init_clock_manager(const struct device *dev) drv_data->clk_mgr = z_nrf_clock_control_get_onoff(subsys); __ASSERT_NO_MSG(drv_data->clk_mgr != NULL); -#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL - struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; - - drv_data->audiopll_dev = DEVICE_DT_GET(DT_NODELABEL(audiopll)); -#endif } +#endif static const struct _dmic_ops dmic_ops = { .configure = dmic_nrfx_pdm_configure, @@ -711,7 +677,8 @@ static const struct _dmic_ops dmic_ops = { k_msgq_init(&dmic_nrfx_pdm_data##idx.mem_slab_queue, \ (char *)mem_slab_msgs##idx, sizeof(void *), \ ARRAY_SIZE(mem_slab_msgs##idx)); \ - init_clock_manager(dev); \ + IF_ENABLED(CONFIG_CLOCK_CONTROL_NRF, \ + (init_clock_manager(dev);)) \ return 0; \ } \ static void event_handler##idx(const nrfx_pdm_evt_t *evt) \ @@ -728,20 +695,13 @@ static const struct _dmic_ops dmic_ops = { .clk_src = PDM_CLK_SRC(idx), \ .mem_reg = DMM_DEV_TO_REG(PDM(idx)), \ }; \ - BUILD_ASSERT(PDM_CLK_SRC(idx) != ACLK || \ - NRF_PDM_HAS_SELECTABLE_CLOCK, \ + BUILD_ASSERT(PDM_CLK_SRC(idx) != ACLK || NRF_PDM_HAS_MCLKCONFIG, \ "Clock source ACLK is not available."); \ BUILD_ASSERT(PDM_CLK_SRC(idx) != ACLK || \ DT_NODE_HAS_PROP(DT_NODELABEL(clock), \ - hfclkaudio_frequency) || \ - DT_NODE_HAS_PROP(DT_NODELABEL(aclk), \ - clock_frequency) || \ - DT_NODE_HAS_PROP(DT_NODELABEL(audiopll), \ - frequency), \ + hfclkaudio_frequency), \ "Clock source ACLK requires the hfclkaudio-frequency " \ - "property to be defined in the nordic,nrf-clock node " \ - "or clock-frequency property to be defined in aclk node" \ - "or frequency property to be defined in audiopll node"); \ + "property to be defined in the nordic,nrf-clock node."); \ DEVICE_DT_DEFINE(PDM(idx), pdm_nrfx_init##idx, NULL, \ &dmic_nrfx_pdm_data##idx, &dmic_nrfx_pdm_cfg##idx, \ POST_KERNEL, CONFIG_AUDIO_DMIC_INIT_PRIORITY, \ diff --git a/drivers/audio/wm8962.c b/drivers/audio/wm8962.c deleted file mode 100644 index 406f81f5e7d11..0000000000000 --- a/drivers/audio/wm8962.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include - -#include -#include -#include -#include -#include - -#include - -LOG_MODULE_REGISTER(wolfson_wm8962, CONFIG_AUDIO_CODEC_LOG_LEVEL); - -#include "wm8962.h" - -#define DT_DRV_COMPAT wolfson_wm8962 - -struct wm8962_driver_config { - struct i2c_dt_spec i2c; - int clock_source; - const struct device *mclk_dev; - clock_control_subsys_t mclk_name; -}; - -#define DEV_CFG(dev) ((const struct wm8962_driver_config *const)dev->config) - -static void wm8962_write_reg(const struct device *dev, uint16_t reg, uint16_t val); -static void wm8962_read_reg(const struct device *dev, uint16_t reg, uint16_t *val); -static void wm8962_update_reg(const struct device *dev, uint16_t reg, uint16_t mask, uint16_t val); -static void wm8962_soft_reset(const struct device *dev); -#if DEBUG_WM8962_REGISTER -static void WM8962_read_all_reg(const struct device *dev, uint16_t endAddress); -#endif - -static void wm8962_configure_output(const struct device *dev); - -static void wm8962_configure_input(const struct device *dev); - -static int wm8962_apply_properties(const struct device *dev); - -static int wm8962_start_sequence(const struct device *dev, wm8962_sequence_id_t id) -{ - uint32_t delayUs = 93000U; - uint16_t sequenceStat = 0U; - - switch (id) { - case kWM8962_SequenceDACToHeadphonePowerUp: - delayUs = 93000U; - break; - case kWM8962_SequenceAnalogueInputPowerUp: - delayUs = 75000U; - break; - case kWM8962_SequenceChipPowerDown: - delayUs = 32000U; - break; - case kWM8962_SequenceSpeakerSleep: - delayUs = 2000U; - break; - case kWM8962_SequenceSpeakerWake: - delayUs = 2000U; - break; - default: - delayUs = 93000U; - break; - } - - wm8962_write_reg(dev, WM8962_REG_WRITE_SEQ_CTRL_1, WM8962_WSEQ_ENA); - wm8962_write_reg(dev, WM8962_REG_WRITE_SEQ_CTRL_2, (uint16_t)id); - while (delayUs != 0U) { - wm8962_read_reg(dev, WM8962_REG_WRITE_SEQ_CTRL_3, &sequenceStat); - if ((sequenceStat & 1U) == 0U) { - break; - } - k_msleep(1U); - delayUs -= 1000U; - } - - return (sequenceStat & 1U) == 0U ? 0 : -EBUSY; -} - -static int wm8962_get_clock_divider(uint32_t inputClock, uint32_t maxClock, uint16_t *divider) -{ - if ((inputClock >> 2U) > maxClock) { - return -EINVAL; - } - - /* fll reference clock divider */ - if (inputClock > maxClock) { - if ((inputClock >> 1U) > maxClock) { - *divider = 2U; - } else { - *divider = 1U; - } - } else { - *divider = 0U; - } - - return 0; -} - -static int wm8962_protocol_config(const struct device *dev, audio_dai_type_t dai_type) -{ - wm8962_protocol_t proto; - - switch (dai_type) { - case AUDIO_DAI_TYPE_I2S: - proto = kWM8962_BusI2S; - break; - case AUDIO_DAI_TYPE_LEFT_JUSTIFIED: - proto = kWM8962_BusLeftJustified; - break; - case AUDIO_DAI_TYPE_RIGHT_JUSTIFIED: - proto = kWM8962_BusRightJustified; - break; - case AUDIO_DAI_TYPE_PCMA: - proto = kWM8962_BusPCMA - 1; - break; - case AUDIO_DAI_TYPE_PCMB: - proto = kWM8962_BusPCMB | 0x10U; - break; - default: - return -EINVAL; - } - - wm8962_update_reg(dev, WM8962_REG_IFACE0, WM8962_IFACE0_FORMAT_MASK, (uint16_t)proto); - - LOG_DBG("Codec protocol: %#x", proto); - return 0; -} - -static int wm8962_audio_fmt_config(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t mclk) -{ - uint32_t val; - uint16_t word_size = cfg->i2s.word_size; - uint32_t ratio = mclk / cfg->i2s.frame_clk_freq; - - switch (word_size) { - case 16: - val = WM8962_IFACE0_WL_16BITS; - break; - case 20: - val = WM8962_IFACE0_WL_20BITS; - break; - case 24: - val = WM8962_IFACE0_WL_24BITS; - break; - case 32: - val = WM8962_IFACE0_WL_32BITS; - break; - default: - LOG_WRN("Invalid codec bit width: %d", cfg->i2s.word_size); - return -EINVAL; - } - - wm8962_update_reg(dev, WM8962_REG_IFACE0, WM8962_IFACE0_WL_MASK, WM8962_IFACE0_WL(val)); - - switch (cfg->i2s.frame_clk_freq) { - case kWM8962_AudioSampleRate8kHz: - val = 0x15U; - break; - case kWM8962_AudioSampleRate11025Hz: - val = 0x04U; - break; - case kWM8962_AudioSampleRate12kHz: - val = 0x14U; - break; - case kWM8962_AudioSampleRate16kHz: - val = 0x13U; - break; - case kWM8962_AudioSampleRate22050Hz: - val = 0x02U; - break; - case kWM8962_AudioSampleRate24kHz: - val = 0x12U; - break; - case kWM8962_AudioSampleRate32kHz: - val = 0x11U; - break; - case kWM8962_AudioSampleRate44100Hz: - val = 0x00U; - break; - case kWM8962_AudioSampleRate48kHz: - val = 0x10U; - break; - case kWM8962_AudioSampleRate88200Hz: - val = 0x06U; - break; - case kWM8962_AudioSampleRate96kHz: - val = 0x16U; - break; - default: - LOG_WRN("Invalid codec sample rate: %d", cfg->i2s.frame_clk_freq); - return -EINVAL; - } - - wm8962_write_reg(dev, WM8962_REG_ADDCTL3, val); - - switch (ratio) { - case 64: - val = 0x00U; - break; - case 128: - val = 0x02U; - break; - case 192: - val = 0x04U; - break; - case 256: - val = 0x06U; - break; - case 384: - val = 0x08U; - break; - case 512: - val = 0x0AU; - break; - case 768: - val = 0x0CU; - break; - case 1024: - val = 0x0EU; - break; - case 1536: - val = 0x12U; - break; - case 3072: - val = 0x14U; - break; - case 6144: - val = 0x16U; - break; - default: - LOG_WRN("Invalid codec ratio: %d", ratio); - return -EINVAL; - } - - wm8962_write_reg(dev, WM8962_REG_CLK4, val); - - return 0; -} - -static int wm8962_out_update(const struct device *dev, audio_channel_t channel, uint16_t val, - uint16_t mask) -{ - switch (channel) { - case AUDIO_CHANNEL_FRONT_LEFT: - wm8962_update_reg(dev, WM8962_REG_LOUT2, mask, val); - return 0; - - case AUDIO_CHANNEL_FRONT_RIGHT: - wm8962_update_reg(dev, WM8962_REG_ROUT2, mask, val); - return 0; - - case AUDIO_CHANNEL_HEADPHONE_LEFT: - wm8962_update_reg(dev, WM8962_REG_LOUT1, mask, val); - return 0; - - case AUDIO_CHANNEL_HEADPHONE_RIGHT: - wm8962_update_reg(dev, WM8962_REG_ROUT1, mask, val); - return 0; - - case AUDIO_CHANNEL_ALL: - wm8962_update_reg(dev, WM8962_REG_LOUT1, mask, val); - wm8962_update_reg(dev, WM8962_REG_ROUT1, mask, val); - wm8962_update_reg(dev, WM8962_REG_LOUT2, mask, val); - wm8962_update_reg(dev, WM8962_REG_ROUT2, mask, val); - return 0; - - default: - return -EINVAL; - } -} - -static int wm8962_out_volume_config(const struct device *dev, audio_channel_t channel, int volume) -{ - /* Set volume values with VU = 0 */ - const uint16_t val = WM8962_REGVAL_OUT_VOL(1, 0, volume); - const uint16_t mask = - WM8962_REGMASK_OUT_VU | WM8962_REGMASK_OUT_ZC | WM8962_REGMASK_OUT_VOL; - - return wm8962_out_update(dev, channel, val, mask); -} - -static int wm8962_out_mute_config(const struct device *dev, audio_channel_t channel, bool mute) -{ - uint8_t val = 0U; - - switch (channel) { - case AUDIO_CHANNEL_FRONT_LEFT: - val = mute ? 2U : 0U; - wm8962_update_reg(dev, WM8962_REG_CLASSD1, WM8962_L_CH_MUTE_MASK, val); - return 0; - - case AUDIO_CHANNEL_FRONT_RIGHT: - val = mute ? 1U : 0U; - wm8962_update_reg(dev, WM8962_REG_CLASSD1, WM8962_R_CH_MUTE_MASK, val); - return 0; - - case AUDIO_CHANNEL_HEADPHONE_LEFT: - val = mute ? 2U : 0U; - wm8962_update_reg(dev, WM8962_REG_POWER2, WM8962_L_CH_MUTE_MASK, val); - return 0; - - case AUDIO_CHANNEL_HEADPHONE_RIGHT: - val = mute ? 1U : 0U; - wm8962_update_reg(dev, WM8962_REG_POWER2, WM8962_R_CH_MUTE_MASK, val); - return 0; - - case AUDIO_CHANNEL_ALL: - val = mute ? 3U : 0U; - wm8962_update_reg(dev, WM8962_REG_CLASSD1, - (WM8962_L_CH_MUTE_MASK | WM8962_R_CH_MUTE_MASK), val); - wm8962_update_reg(dev, WM8962_REG_POWER2, - (WM8962_L_CH_MUTE_MASK | WM8962_R_CH_MUTE_MASK), val); - return 0; - - default: - return -EINVAL; - } -} - -static int wm8962_in_update(const struct device *dev, audio_channel_t channel, uint16_t mask, - uint16_t val) -{ - switch (channel) { - case AUDIO_CHANNEL_FRONT_LEFT: - wm8962_update_reg(dev, WM8962_REG_LINVOL, mask, val); - return 0; - - case AUDIO_CHANNEL_FRONT_RIGHT: - wm8962_update_reg(dev, WM8962_REG_RINVOL, mask, val); - return 0; - - case AUDIO_CHANNEL_ALL: - wm8962_update_reg(dev, WM8962_REG_LINVOL, mask, val); - wm8962_update_reg(dev, WM8962_REG_RINVOL, mask, val); - return 0; - - default: - return -EINVAL; - } -} - -static int wm8962_in_volume_config(const struct device *dev, audio_channel_t channel, int volume) -{ - const uint16_t val = WM8962_REGVAL_IN_VOL(1, 0, 0, volume); - const uint16_t mask = WM8962_REGMASK_IN_MUTE; - - return wm8962_in_update(dev, channel, mask, val); -} - -static int wm8962_in_mute_config(const struct device *dev, audio_channel_t channel, bool mute) -{ - const uint16_t val = WM8962_REGVAL_IN_VOL(1, mute, 0, 0); - const uint16_t mask = WM8962_REGMASK_IN_MUTE; - - return wm8962_in_update(dev, channel, mask, val); -} - -static int wm8962_route_input(const struct device *dev, audio_channel_t channel, uint32_t input) -{ - uint8_t reg; - - switch (channel) { - case AUDIO_CHANNEL_FRONT_LEFT: - reg = WM8962_REG_LEFT_INPUT_PGA; - break; - - case AUDIO_CHANNEL_FRONT_RIGHT: - reg = WM8962_REG_RIGHT_INPUT_PGA; - break; - - default: - return -EINVAL; - } - - /* Input PGA source */ - wm8962_write_reg(dev, reg, input); - return 0; -} - -static int wm8962_route_output(const struct device *dev, audio_channel_t channel, uint32_t output) -{ - /* Output MIXER */ - switch (channel) { - case AUDIO_CHANNEL_HEADPHONE_LEFT: - wm8962_write_reg(dev, WM8962_REG_LEFT_HEADPHONE_MIXER, output); - break; - case AUDIO_CHANNEL_HEADPHONE_RIGHT: - wm8962_write_reg(dev, WM8962_REG_RIGHT_HEADPHONE_MIXER, output); - break; - case AUDIO_CHANNEL_FRONT_LEFT: - case AUDIO_CHANNEL_REAR_LEFT: - case AUDIO_CHANNEL_SIDE_LEFT: - wm8962_write_reg(dev, WM8962_REG_LEFT_SPEAKER_MIXER, output); - break; - case AUDIO_CHANNEL_FRONT_RIGHT: - case AUDIO_CHANNEL_REAR_RIGHT: - case AUDIO_CHANNEL_SIDE_RIGHT: - wm8962_write_reg(dev, WM8962_REG_RIGHT_SPEAKER_MIXER, output); - break; - default: - break; - } - - return 0; -} - -static void wm8962_set_master_clock(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t sysclk) -{ - uint32_t sampleRate = cfg->i2s.frame_clk_freq; - uint32_t bitWidth = cfg->i2s.word_size; - uint32_t bclkDiv = 0U; - uint16_t regClkDiv = 0U, sysClkDiv = 0U; - int ret = 0; - - wm8962_get_clock_divider(sysclk, WM8962_MAX_DSP_CLOCK, &sysClkDiv); - sysclk /= 1 << sysClkDiv; - - bclkDiv = sysclk / (sampleRate * bitWidth * 2U); - - switch (bclkDiv) { - case 1: - regClkDiv = 0U; - break; - case 2: - regClkDiv = 2U; - break; - case 3: - regClkDiv = 3U; - break; - case 4: - regClkDiv = 4U; - break; - case 6: - regClkDiv = 6U; - break; - case 8: - regClkDiv = 7U; - break; - case 12: - regClkDiv = 9U; - break; - case 16: - regClkDiv = 10U; - break; - case 24: - regClkDiv = 11U; - break; - case 32: - regClkDiv = 13U; - break; - - default: - ret = -1; - break; - } - if (ret == 0) { - wm8962_update_reg(dev, WM8962_REG_CLOCK2, WM8962_CLOCK2_BCLK_DIV_MASK, - (uint16_t)regClkDiv); - wm8962_write_reg(dev, WM8962_REG_IFACE2, (uint16_t)(bitWidth * 2U)); - } else { - LOG_ERR("Unsupported divider."); - } -} - -static int wm8962_configure(const struct device *dev, struct audio_codec_cfg *cfg) -{ - uint32_t sysClk = 0; - uint16_t clockDiv = 0U; - - const struct wm8962_driver_config *const dev_cfg = DEV_CFG(dev); - - if (cfg->dai_type >= AUDIO_DAI_TYPE_INVALID) { - LOG_ERR("dai_type not supported"); - return -EINVAL; - } - - if (dev_cfg->clock_source == 0) { - int err = clock_control_on(dev_cfg->mclk_dev, dev_cfg->mclk_name); - - if (err < 0) { - LOG_ERR("MCLK clock source enable fail: %d", err); - } - - err = clock_control_get_rate(dev_cfg->mclk_dev, dev_cfg->mclk_name, - &cfg->mclk_freq); - if (err < 0) { - LOG_ERR("MCLK clock source freq acquire fail: %d", err); - } - } - - wm8962_soft_reset(dev); - if (cfg->dai_route == AUDIO_ROUTE_BYPASS) { - return 0; - } - - /* disable internal osc/FLL2/FLL3/FLL*/ - wm8962_write_reg(dev, WM8962_REG_PLL2, 0); - wm8962_update_reg(dev, WM8962_REG_FLL_CTRL_1, 1U, 0U); - wm8962_write_reg(dev, WM8962_REG_CLOCK2, 0x9E4); - wm8962_write_reg(dev, WM8962_REG_POWER1, 0x1FE); - wm8962_write_reg(dev, WM8962_REG_POWER2, 0x1E0); - - if ((cfg->dai_cfg.i2s.options & I2S_OPT_FRAME_CLK_SLAVE) == I2S_OPT_FRAME_CLK_SLAVE) { - wm8962_set_master_clock(dev, &cfg->dai_cfg, cfg->mclk_freq); - wm8962_update_reg(dev, WM8962_REG_IFACE0, 1U << 6U, 1U << 6U); - } - - wm8962_start_sequence(dev, kWM8962_SequenceDACToHeadphonePowerUp); - wm8962_start_sequence(dev, kWM8962_SequenceAnalogueInputPowerUp); - wm8962_start_sequence(dev, kWM8962_SequenceSpeakerWake); - - /* enable system clock */ - wm8962_update_reg(dev, WM8962_REG_CLOCK2, 0x20U, 0x20U); - - /* sysclk clock divider, maximum 12.288MHZ */ - wm8962_read_reg(dev, WM8962_REG_CLOCK1, &clockDiv); - sysClk = cfg->mclk_freq / (1UL << (clockDiv & 3U)); - - /* set data protocol */ - wm8962_protocol_config(dev, cfg->dai_type); - /* - * ADC volume, 0dB - */ - wm8962_write_reg(dev, WM8962_REG_LADC, WM8962_ADC_DEFAULT_VOLUME_VALUE); - wm8962_write_reg(dev, WM8962_REG_RADC, WM8962_ADC_DEFAULT_VOLUME_VALUE); - /* - * Digital DAC volume, -15.5dB - */ - wm8962_write_reg(dev, WM8962_REG_LDAC, WM8962_DAC_DEFAULT_VOLUME_VALUE); - wm8962_write_reg(dev, WM8962_REG_RDAC, WM8962_DAC_DEFAULT_VOLUME_VALUE); - /* speaker volume 6dB */ - wm8962_write_reg(dev, WM8962_REG_LOUT2, WM8962_SPEAKER_DEFAULT_VOLUME_VALUE); - wm8962_write_reg(dev, WM8962_REG_ROUT2, WM8962_SPEAKER_DEFAULT_VOLUME_VALUE); - /* input PGA volume */ - wm8962_write_reg(dev, WM8962_REG_LINVOL, WM8962_LINEIN_DEFAULT_VOLUME_VALUE); - wm8962_write_reg(dev, WM8962_REG_RINVOL, WM8962_LINEIN_DEFAULT_VOLUME_VALUE); - /* Headphone volume */ - wm8962_write_reg(dev, WM8962_REG_LOUT1, WM8962_HEADPHONE_DEFAULT_VOLUME_VALUE); - wm8962_write_reg(dev, WM8962_REG_ROUT1, WM8962_HEADPHONE_DEFAULT_VOLUME_VALUE); - wm8962_audio_fmt_config(dev, &cfg->dai_cfg, sysClk); - - switch (cfg->dai_route) { - case AUDIO_ROUTE_BYPASS: - - break; - case AUDIO_ROUTE_PLAYBACK: - wm8962_configure_output(dev); - break; - - case AUDIO_ROUTE_CAPTURE: - wm8962_configure_input(dev); - break; - - case AUDIO_ROUTE_PLAYBACK_CAPTURE: - wm8962_configure_output(dev); - wm8962_configure_input(dev); - break; - - default: - break; - } - - return 0; -} - -static void wm8962_start_output(const struct device *dev) -{ - /* Not supported */ -} - -static void wm8962_stop_output(const struct device *dev) -{ - /* Not supported */ -} - -static int wm8962_set_property(const struct device *dev, audio_property_t property, - audio_channel_t channel, audio_property_value_t val) -{ - switch (property) { - case AUDIO_PROPERTY_OUTPUT_VOLUME: - return wm8962_out_volume_config(dev, channel, val.vol); - - case AUDIO_PROPERTY_OUTPUT_MUTE: - return wm8962_out_mute_config(dev, channel, val.mute); - - case AUDIO_PROPERTY_INPUT_VOLUME: - return wm8962_in_volume_config(dev, channel, val.vol); - - case AUDIO_PROPERTY_INPUT_MUTE: - return wm8962_in_mute_config(dev, channel, val.mute); - default: - break; - } - - return -EINVAL; -} - -static int wm8962_apply_properties(const struct device *dev) -{ - /** - * Set VU = 1 for all input and output channels, VU takes effect for the whole - * channel pair. - */ - wm8962_update_reg(dev, WM8962_REG_LOUT1, WM8962_REGVAL_OUT_VOL(1, 0, 0), - WM8962_REGMASK_OUT_VU); - wm8962_update_reg(dev, WM8962_REG_LINVOL, WM8962_REGVAL_IN_VOL(1, 0, 0, 0), - WM8962_REGMASK_IN_VU); - - return 0; -} - -static void wm8962_write_reg(const struct device *dev, uint16_t reg, uint16_t val) -{ - const struct wm8962_driver_config *const dev_cfg = DEV_CFG(dev); - uint8_t data[4]; - int ret; - - /* data is reversed */ - data[0] = (reg >> 8) & 0xff; - data[1] = reg & 0xff; - data[2] = (val >> 8) & 0xff; - data[3] = val & 0xff; - - ret = i2c_write(dev_cfg->i2c.bus, data, 4, dev_cfg->i2c.addr); - - if (ret != 0) { - LOG_ERR("i2c write to codec error %d", ret); - } - - LOG_DBG("REG:%#02x VAL:%#02x", reg, val); -} - -static void wm8962_read_reg(const struct device *dev, uint16_t reg, uint16_t *val) -{ - const struct wm8962_driver_config *const dev_cfg = DEV_CFG(dev); - uint16_t value; - int ret; - - reg = WM8962_SWAP_UINT16_BYTE_SEQUENCE(reg); - - ret = i2c_write_read(dev_cfg->i2c.bus, dev_cfg->i2c.addr, ®, sizeof(reg), &value, - sizeof(value)); - if (ret == 0) { - *val = (value >> 8) & 0xff; - *val += ((value & 0xff) << 8); - /* update cache*/ - LOG_DBG("REG:%#02x VAL:%#02x", WM8962_SWAP_UINT16_BYTE_SEQUENCE(reg), *val); - } -} - -static void wm8962_update_reg(const struct device *dev, uint16_t reg, uint16_t mask, uint16_t val) -{ - uint16_t reg_val = 0; - uint16_t new_value = 0; - - wm8962_read_reg(dev, reg, ®_val); - LOG_DBG("read %#x = %x", reg, reg_val); - new_value = (reg_val & ~mask) | (val & mask); - LOG_DBG("write %#x = %x", reg, new_value); - wm8962_write_reg(dev, reg, new_value); -} - -static void wm8962_soft_reset(const struct device *dev) -{ - wm8962_write_reg(dev, WM8962_REG_RESET, 0x6243U); -} - -static void wm8962_configure_output(const struct device *dev) -{ - wm8962_out_volume_config(dev, AUDIO_CHANNEL_ALL, WM8962_HEADPHONE_DEFAULT_VOLUME_VALUE); - wm8962_out_mute_config(dev, AUDIO_CHANNEL_ALL, false); - - wm8962_apply_properties(dev); -} - -static void wm8962_configure_input(const struct device *dev) -{ - wm8962_route_input(dev, AUDIO_CHANNEL_FRONT_LEFT, kWM8962_InputPGASourceInput1); - wm8962_route_input(dev, AUDIO_CHANNEL_FRONT_RIGHT, kWM8962_InputPGASourceInput3); - - /* Input MIXER source */ - wm8962_write_reg(dev, WM8962_REG_INPUTMIX, - (((kWM8962_InputMixerSourceInputPGA & 7U) << 3U) | - (kWM8962_InputMixerSourceInputPGA & 7U))); - /* Input MIXER enable */ - wm8962_write_reg(dev, WM8962_REG_INPUT_MIXER_1, 3U); - - wm8962_in_volume_config(dev, AUDIO_CHANNEL_ALL, WM8962_LINEIN_DEFAULT_VOLUME_VALUE); - wm8962_in_mute_config(dev, AUDIO_CHANNEL_ALL, false); -} - -#if DEBUG_WM8962_REGISTER -static void WM8962_read_all_reg(const struct device *dev, uint16_t endAddress) -{ - uint16_t readValue = 0U, i = 0U; - - for (i = 0U; i < endAddress; i++) { - wm8962_read_reg(dev, i, &readValue); - } -} -#endif - -static const struct audio_codec_api wm8962_driver_api = {.configure = wm8962_configure, - .start_output = wm8962_start_output, - .stop_output = wm8962_stop_output, - .set_property = wm8962_set_property, - .apply_properties = - wm8962_apply_properties, - .route_input = wm8962_route_input, - .route_output = wm8962_route_output}; - -#define wm8962_INIT(n) \ - static const struct wm8962_driver_config wm8962_device_config_##n = { \ - .i2c = I2C_DT_SPEC_INST_GET(n), \ - .clock_source = DT_INST_PROP_OR(n, clk_source, 0), \ - .mclk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, mclk)), \ - .mclk_name = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, name)}; \ - \ - DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, &wm8962_device_config_##n, POST_KERNEL, \ - CONFIG_AUDIO_CODEC_INIT_PRIORITY, &wm8962_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(wm8962_INIT) diff --git a/drivers/audio/wm8962.h b/drivers/audio/wm8962.h deleted file mode 100644 index edc0fce9b82a9..0000000000000 --- a/drivers/audio/wm8962.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_AUDIO_WM8962_H_ -#define ZEPHYR_DRIVERS_AUDIO_WM8962_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define WM8962_SWAP_UINT16_BYTE_SEQUENCE(x) ((((x) & 0x00ffU) << 8U) | (((x) & 0xff00U) >> 8U)) -/*! @brief WM8962 max clock */ -#define WM8962_MAX_DSP_CLOCK (24576000U) -#define WM8962_MAX_SYS_CLOCK (12288000U) -/*! @brief WM8962 f2 better performance range */ -#define WM8962_FLL_VCO_MIN_FREQ 90000000U -#define WM8962_FLL_VCO_MAX_FREQ 100000000U -#define WM8962_FLL_LOCK_TIMEOUT 10000000U -/*! @brief WM8962 FLLN range */ -#define WM8962_FLL_N_MIN_VALUE 6U -#define WM8962_FLL_N_MAX_VALUE 12U -#define WM8962_FLL_MAX_REFERENCE_CLOCK (13500000U) - -/*! @brief Define the register address of WM8962. */ -#define WM8962_REG_LINVOL 0x0U -#define WM8962_REG_RINVOL 0x1U -#define WM8962_REG_LOUT1 0x2U -#define WM8962_REG_ROUT1 0x3U -#define WM8962_REG_CLOCK1 0x4U -#define WM8962_REG_DACCTL1 0x5U -#define WM8962_REG_DACCTL2 0x6U -#define WM8962_REG_IFACE0 0x7U -#define WM8962_REG_IFACE1 0x9U -#define WM8962_REG_CLOCK2 0x8U -#define WM8962_REG_IFACE2 0xEU -#define WM8962_REG_LDAC 0xaU -#define WM8962_REG_RDAC 0xbU - -#define WM8962_REG_RESET 0xfU -#define WM8962_REG_3D 0x10U -#define WM8962_REG_ALC1 0x11U -#define WM8962_REG_ALC2 0x12U -#define WM8962_REG_ALC3 0x13U -#define WM8962_REG_NOISEG 0x14U -#define WM8962_REG_LADC 0x15U -#define WM8962_REG_RADC 0x16U -#define WM8962_REG_ADDCTL1 0x17U -#define WM8962_REG_ADDCTL2 0x18U -#define WM8962_REG_POWER1 0x19U -#define WM8962_REG_POWER2 0x1aU -#define WM8962_REG_ADDCTL3 0x1bU -#define WM8962_REG_APOP1 0x1cU -#define WM8962_REG_APOP2 0x1dU -#define WM8962_REG_INPUT_MIXER_1 0x1FU - -#define WM8962_REG_LINPATH 0x20U -#define WM8962_REG_RINPATH 0x21U -#define WM8962_REG_INPUTMIX 0x22U - -#define WM8962_REG_LEFT_INPUT_PGA 0x25U -#define WM8962_REG_RIGHT_INPUT_PGA 0x26U -#define WM8962_REG_MONOMIX2 0x27U -#define WM8962_REG_LOUT2 0x28U -#define WM8962_REG_ROUT2 0x29U -#define WM8962_REG_TEMP 0x2FU -#define WM8962_REG_ADDCTL4 0x30U -#define WM8962_REG_CLASSD1 0x31U - -#define WM8962_REG_CLASSD3 0x33U -#define WM8962_REG_CLK4 0x38U -#define WM8962_REG_DC_SERVO_0 0x3CU -#define WM8962_REG_DC_SERVO_1 0x3DU -#define WM8962_REG_ANALOG_HP_0 0x45U -#define WM8962_REG_CHARGE_PUMP_1 0x48U - -#define WM8962_REG_WRITE_SEQ_CTRL_1 0x57U -#define WM8962_REG_WRITE_SEQ_CTRL_2 0x5AU -#define WM8962_REG_WRITE_SEQ_CTRL_3 0x5DU - -#define WM8962_WSEQ_ENA 0x20U - -#define WM8962_REG_LEFT_HEADPHONE_MIXER 0x64U -#define WM8962_REG_RIGHT_HEADPHONE_MIXER 0x65U -#define WM8962_REG_LEFT_HEADPHONE_MIXER_VOLUME 0x66U -#define WM8962_REG_RIGHT_HEADPHONE_MIXER_VOLUME 0x67U - -#define WM8962_REG_LEFT_SPEAKER_MIXER 0x69U -#define WM8962_REG_RIGHT_SPEAKER_MIXER 0x6AU -#define WM8962_REG_LEFT_SPEAKER_MIXER_VOLUME 0x6BU -#define WM8962_REG_RIGHT_SPEAKER_MIXER_VOLUME 0x6CU - -#define WM8962_REG_PLL2 0x81U - -#define WM8962_REG_FLL_CTRL_1 0x9BU -#define WM8962_REG_FLL_CTRL_2 0x9CU -#define WM8962_REG_FLL_CTRL_3 0x9DU -#define WM8962_REG_FLL_CTRL_6 0xA0U -#define WM8962_REG_FLL_CTRL_7 0xA1U -#define WM8962_REG_FLL_CTRL_8 0xA2U -#define WM8962_REG_INT_STATUS_2 0x231U - -#define WSEQ_DONE_EINT_MASK 0x80U - -#define WM8962_L_CH_MUTE_MASK 2U -#define WM8962_R_CH_MUTE_MASK 1U - -/*! @brief WM8962 CLOCK2 bits */ -#define WM8962_CLOCK2_BCLK_DIV_MASK 0xFU - -/*! @brief WM8962_IFACE0 FORMAT bits */ -#define WM8962_IFACE0_FORMAT_MASK 0x13U -#define WM8962_IFACE0_FORMAT_SHIFT 0x00U -#define WM8962_IFACE0_FORMAT_RJ 0x00U -#define WM8962_IFACE0_FORMAT_LJ 0x01U -#define WM8962_IFACE0_FORMAT_I2S 0x02U -#define WM8962_IFACE0_FORMAT_DSP 0x03U -#define WM8962_IFACE0_FORMAT(x) (((x) << WM8962_IFACE1_FORMAT_SHIFT) & WM8962_IFACE1_FORMAT_MASK) - -/*! @brief WM8962_IFACE0 WL bits */ -#define WM8962_IFACE0_WL_MASK 0x0CU -#define WM8962_IFACE0_WL_SHIFT 0x02U -#define WM8962_IFACE0_WL_16BITS 0x00U -#define WM8962_IFACE0_WL_20BITS 0x01U -#define WM8962_IFACE0_WL_24BITS 0x02U -#define WM8962_IFACE0_WL_32BITS 0x03U -#define WM8962_IFACE0_WL(x) (((x) << WM8962_IFACE0_WL_SHIFT) & WM8962_IFACE0_WL_MASK) - -/*! @brief WM8962_IFACE1 LRP bit */ -#define WM8962_IFACE1_LRP_MASK 0x10U -#define WM8962_IFACE1_LRP_SHIFT 0x04U -#define WM8962_IFACE1_LRCLK_NORMAL_POL 0x00U -#define WM8962_IFACE1_LRCLK_INVERT_POL 0x01U -#define WM8962_IFACE1_DSP_MODEA 0x00U -#define WM8962_IFACE1_DSP_MODEB 0x01U -#define WM8962_IFACE1_LRP(x) (((x) << WM8962_IFACE1_LRP_SHIFT) & WM8962_IFACE1_LRP_MASK) - -/*! @brief WM8962_IFACE1 DLRSWAP bit */ -#define WM8962_IFACE1_DLRSWAP_MASK 0x20U -#define WM8962_IFACE1_DLRSWAP_SHIFT 0x05U -#define WM8962_IFACE1_DACCH_NORMAL 0x00U -#define WM8962_IFACE1_DACCH_SWAP 0x01U - -#define WM8962_IFACE1_DLRSWAP(x) (((x) << WM8962_IFACE1_DLRSWAP_SHIFT) & WM8962_IFACE1_DLRSWAP_MASK) - -/*! @brief WM8962_IFACE1 MS bit */ -#define WM8962_IFACE1_MS_MASK 0x40U -#define WM8962_IFACE1_MS_SHIFT 0x06U -#define WM8962_IFACE1_SLAVE 0x00U -#define WM8962_IFACE1_MASTER 0x01U -#define WM8962_IFACE1_MS(x) (((x) << WM8962_IFACE1_MS_SHIFT) & WM8962_IFACE1_MS_MASK) - -/*! @brief WM8962_IFACE1 BCLKINV bit */ -#define WM8962_IFACE1_BCLKINV_MASK 0x80U -#define WM8962_IFACE1_BCLKINV_SHIFT 0x07U -#define WM8962_IFACE1_BCLK_NONINVERT 0x00U -#define WM8962_IFACE1_BCLK_INVERT 0x01U - -#define WM8962_IFACE1_BCLKINV(x) (((x) << WM8962_IFACE1_BCLKINV_SHIFT) & WM8962_IFACE1_BCLKINV_MASK) - -/*! @brief WM8962_IFACE1 ALRSWAP bit */ -#define WM8962_IFACE1_ALRSWAP_MASK 0x100U -#define WM8962_IFACE1_ALRSWAP_SHIFT 0x08U -#define WM8962_IFACE1_ADCCH_NORMAL 0x00U -#define WM8962_IFACE1_ADCCH_SWAP 0x01U - -#define WM8962_IFACE1_ALRSWAP(x) (((x) << WM8962_IFACE1_ALRSWAP_SHIFT) & WM8962_IFACE1_ALRSWAP_MASK) - -/*! @brief WM8962_POWER1 */ -#define WM8962_POWER1_VREF_MASK 0x40U -#define WM8962_POWER1_VREF_SHIFT 0x06U - -#define WM8962_POWER1_AINL_MASK 0x20U -#define WM8962_POWER1_AINL_SHIFT 0x05U - -#define WM8962_POWER1_AINR_MASK 0x10U -#define WM8962_POWER1_AINR_SHIFT 0x04U - -#define WM8962_POWER1_ADCL_MASK 0x08U -#define WM8962_POWER1_ADCL_SHIFT 0x03U - -#define WM8962_POWER1_ADCR_MASK 0x4U -#define WM8962_POWER1_ADCR_SHIFT 0x02U - -#define WM8962_POWER1_MICB_MASK 0x02U -#define WM8962_POWER1_MICB_SHIFT 0x01U - -#define WM8962_POWER1_DIGENB_MASK 0x01U -#define WM8962_POWER1_DIGENB_SHIFT 0x00U - -/*! @brief WM8962_POWER2 */ -#define WM8962_POWER2_DACL_MASK 0x100U -#define WM8962_POWER2_DACL_SHIFT 0x08U - -#define WM8962_POWER2_DACR_MASK 0x80U -#define WM8962_POWER2_DACR_SHIFT 0x07U - -#define WM8962_POWER2_LOUT1_MASK 0x40U -#define WM8962_POWER2_LOUT1_SHIFT 0x06U - -#define WM8962_POWER2_ROUT1_MASK 0x20U -#define WM8962_POWER2_ROUT1_SHIFT 0x05U - -#define WM8962_POWER2_SPKL_MASK 0x10U -#define WM8962_POWER2_SPKL_SHIFT 0x04U - -#define WM8962_POWER2_SPKR_MASK 0x08U -#define WM8962_POWER2_SPKR_SHIFT 0x03U - -#define WM8962_POWER3_LMIC_MASK 0x20U -#define WM8962_POWER3_LMIC_SHIFT 0x05U -#define WM8962_POWER3_RMIC_MASK 0x10U -#define WM8962_POWER3_RMIC_SHIFT 0x04U -#define WM8962_POWER3_LOMIX_MASK 0x08U -#define WM8962_POWER3_LOMIX_SHIFT 0x03U -#define WM8962_POWER3_ROMIX_MASK 0x04U -#define WM8962_POWER3_ROMIX_SHIFT 0x02U -/*! @brief WM8962 I2C address. */ -#define WM8962_I2C_ADDR (0x34 >> 1U) -/*! @brief WM8962 I2C baudrate */ -#define WM8962_I2C_BAUDRATE (100000U) -/*! @brief WM8962 maximum volume value */ -#define WM8962_ADC_MAX_VOLUME_VALUE 0xFFU -#define WM8962_DAC_MAX_VOLUME_VALUE 0xFFU -#define WM8962_HEADPHONE_MAX_VOLUME_VALUE 0x7FU -#define WM8962_HEADPHONE_MIN_VOLUME_VALUE 0x2FU -#define WM8962_LINEIN_MAX_VOLUME_VALUE 0x3FU -#define WM8962_SPEAKER_MAX_VOLUME_VALUE 0x7FU -#define WM8962_SPEAKER_MIN_VOLUME_VALUE 0x2FU - -#define WM8962_ADC_DEFAULT_VOLUME_VALUE 0x1C0U -#define WM8962_DAC_DEFAULT_VOLUME_VALUE 0x1C0U -#define WM8962_HEADPHONE_DEFAULT_VOLUME_VALUE 0x179U -#define WM8962_LINEIN_DEFAULT_VOLUME_VALUE 0x12DU -#define WM8962_SPEAKER_DEFAULT_VOLUME_VALUE 0x179U - -/** - * WM8962_REG_LOUT1, WM8962_REG_ROUT1 (headphone outs), - * WM8962_REG_LOUT2, WM8962_REG_ROUT2 (line outs): - * [8] - VU: Volume update, works for entire channel pair - * [7] - ZC: Zero-crossing enable - * [6:0] - VOL: 7-bit volume value - */ -#define WM8962_REGVAL_OUT_VOL(vu, zc, vol) \ - (((vu & 0b1) << 8) | (zc & 0b1) << 7 | (vol & 0b001111111)) -#define WM8962_REGMASK_OUT_VU 0b100000000 -#define WM8962_REGMASK_OUT_ZC 0b010000000 -#define WM8962_REGMASK_OUT_VOL 0b001111111 - -#define WM8962_OUT_MUTE(x) ((x << 8U) & (1U << 8U)) - -/** - * WM8962_REG_LINVOL, WM8962_REG_RINVOL: - * [8] - VU: Volume update, works for entire channel pair - * [7] - MUTE: Input mute - * [6] - ZC: Zero-crossing enable - * [5:0] - VOL: 6-bit volume value - */ -#define WM8962_REGVAL_IN_VOL(vu, mute, zc, vol) \ - ((vu & 0b1) << 8 | (mute & 0b1) << 7 | (zc & 0b1) << 6 | (vol & 0b000111111)) -#define WM8962_REGMASK_IN_VU 0b100000000 -#define WM8962_REGMASK_IN_MUTE 0b010000000 -#define WM8962_REGMASK_IN_ZC 0b001000000 -#define WM8962_REGMASK_IN_VOLUME 0b000111111 - -/*! @brief wm8962 input mixer source. - * @anchor wm8962_input_mixer_source_t - */ -typedef enum _wm8962_input_mixer_source { - kWM8962_InputMixerSourceInput2 = 4U, /*!< input mixer source input 2 */ - kWM8962_InputMixerSourceInput3 = 2U, /*!< input mixer source input 3 */ - kWM8962_InputMixerSourceInputPGA = 1U, /*!< input mixer source input PGA */ -} wm8962_input_mixer_source_t; - -/*! @brief wm8962 output mixer source. - * @anchor wm8962_output_mixer_source_t - */ -typedef enum _wm8962_output_mixer_source { - kWM8962_OutputMixerDisabled = 0U, /*!< output mixer disabled */ - kWM8962_OutputMixerSourceInput4Right = 1U, /*!< output mixer source input 4 left */ - kWM8962_OutputMixerSourceInput4Left = 2U, /*!< output mixer source input 4 right */ - kWM8962_OutputMixerSourceRightInputMixer = 4U, /*!< output mixer source left input mixer */ - kWM8962_OutputMixerSourceLeftInputMixer = 8U, /*!< output mixer source right input mixer*/ - kWM8962_OutputMixerSourceRightDAC = 0x10U, /*!< output mixer source left DAC */ - kWM8962_OutputMixerSourceLeftDAC = 0x20U, /*!< output mixer source Right DAC */ -} wm8962_output_mixer_source_t; - -/*! @brief Modules in WM8962 board. */ -typedef enum _wm8962_module { - kWM8962_ModuleADC = 0, /*!< ADC module in WM8962 */ - kWM8962_ModuleDAC = 1, /*!< DAC module in WM8962 */ - kWM8962_ModuleMICB = 4, /*!< Mic bias */ - kWM8962_ModuleMIC = 5, /*!< Input Mic */ - kWM8962_ModuleLineIn = 6, /*!< Analog in PGA */ - kWM8962_ModuleHeadphone = 7, /*!< Line out module */ - kWM8962_ModuleSpeaker = 8, /*!< Speaker module */ - kWM8962_ModuleHeaphoneMixer = 9, /*!< Output mixer */ - kWM8962_ModuleSpeakerMixer = 10, /*!< Output mixer */ -} wm8962_module_t; - -/*! @brief wm8962 play channel - * @anchor _wm8962_play_channel - */ -typedef enum _wm8962_play_channel { - kWM8962_HeadphoneLeft = 1, /*!< wm8962 headphone left channel */ - kWM8962_HeadphoneRight = 2, /*!< wm8962 headphone right channel */ - kWM8962_SpeakerLeft = 4, /*!< wm8962 speaker left channel */ - kWM8962_SpeakerRight = 8, /*!< wm8962 speaker right channel */ -} wm8962_play_channel_t; - -/*! - * @brief The audio data transfer protocol choice. - * WM8962 only supports I2S format and PCM format. - */ -typedef enum _wm8962_protocol { - kWM8962_BusPCMA = 4, /*!< PCMA mode */ - kWM8962_BusPCMB = 3, /*!< PCMB mode */ - kWM8962_BusI2S = 2, /*!< I2S type */ - kWM8962_BusLeftJustified = 1, /*!< Left justified mode */ - kWM8962_BusRightJustified = 0, /*!< Right justified mode */ -} wm8962_protocol_t; - -/*! @brief wm8962 input source */ -typedef enum _wm8962_input_pga_source { - kWM8962_InputPGASourceInput1 = 8, /*!< Input PGA source input1 */ - kWM8962_InputPGASourceInput2 = 4, /*!< Input PGA source input2 */ - kWM8962_InputPGASourceInput3 = 2, /*!< Input PGA source input3 */ - kWM8962_InputPGASourceInput4 = 1, /*!< Input PGA source input4 */ -} wm8962_input_pga_source_t; - -/*! @brief wm8962 input source */ -typedef enum _wm8962_output_pga_source { - kWM8962_OutputPGASourceMixer = 0, /*!< Output PGA source mixer */ - kWM8962_OutputPGASourceDAC = 1, /*!< Output PGA source DAC */ -} wm8962_output_pga_source_t; - -/*! @brief audio sample rate definition - * @anchor _wm8962_sample_rate - */ -typedef enum _wm8962_sample_rate { - kWM8962_AudioSampleRate8kHz = 8000U, /*!< Sample rate 8000 Hz */ - kWM8962_AudioSampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ - kWM8962_AudioSampleRate12kHz = 12000U, /*!< Sample rate 12000 Hz */ - kWM8962_AudioSampleRate16kHz = 16000U, /*!< Sample rate 16000 Hz */ - kWM8962_AudioSampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ - kWM8962_AudioSampleRate24kHz = 24000U, /*!< Sample rate 24000 Hz */ - kWM8962_AudioSampleRate32kHz = 32000U, /*!< Sample rate 32000 Hz */ - kWM8962_AudioSampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ - kWM8962_AudioSampleRate48kHz = 48000U, /*!< Sample rate 48000 Hz */ - kWM8962_AudioSampleRate88200Hz = 88200U, /*!< Sample rate 88200 Hz */ - kWM8962_AudioSampleRate96kHz = 96000U, /*!< Sample rate 96000 Hz */ -} wm8962_sample_rate_t; - -/*! @brief audio bit width - * @anchor _wm8962_audio_bit_width - */ -typedef enum _wm8962_audio_bit_width { - kWM8962_AudioBitWidth16bit = 16U, /*!< audio bit width 16 */ - kWM8962_AudioBitWidth20bit = 20U, /*!< audio bit width 20 */ - kWM8962_AudioBitWidth24bit = 24U, /*!< audio bit width 24 */ - kWM8962_AudioBitWidth32bit = 32U, /*!< audio bit width 32 */ -} wm8962_audio_bit_width_t; - -/*! @brief wm8962 fll clock source */ -typedef enum _wm8962_fllclk_source { - kWM8962_FLLClkSourceMCLK = 0U, /*!< FLL clock source from MCLK */ - kWM8962_FLLClkSourceBCLK = 1U, /*!< FLL clock source from BCLK */ -} wm8962_fllclk_source_t; - -/*! @brief wm8962 sysclk source */ -typedef enum _wm8962_sysclk_source { - kWM8962_SysClkSourceMclk = 0U, /*!< sysclk source from external MCLK */ - kWM8962_SysClkSourceFLL = 1U, /*!< sysclk source from internal FLL */ -} wm8962_sysclk_source_t; - -/*! @brief WM8962 default sequence */ -typedef enum _wm8962_sequence_id { - kWM8962_SequenceDACToHeadphonePowerUp = 0x80U, /*!< dac to headphone power up sequence */ - kWM8962_SequenceAnalogueInputPowerUp = 0x92U, /*!< Analogue input power up sequence */ - kWM8962_SequenceChipPowerDown = 0x9BU, /*!< Chip power down sequence */ - kWM8962_SequenceSpeakerSleep = 0xE4U, /*!< Speaker sleep sequence */ - kWM8962_SequenceSpeakerWake = 0xE8U, /*!< speaker wake sequence */ -} wm8962_sequence_id_t; - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_DRIVERS_AUDIO_WM8962_H_ */ diff --git a/drivers/auxdisplay/CMakeLists.txt b/drivers/auxdisplay/CMakeLists.txt index 676836534de2b..ce53a06713bfd 100644 --- a/drivers/auxdisplay/CMakeLists.txt +++ b/drivers/auxdisplay/CMakeLists.txt @@ -4,7 +4,6 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/auxdisplay.h) zephyr_library() zephyr_library_sources_ifdef(CONFIG_USERSPACE auxdisplay_handlers.c) -zephyr_library_sources_ifdef(CONFIG_AUXDISPLAY_GPIO_7SEG auxdisplay_gpio_7seg.c) zephyr_library_sources_ifdef(CONFIG_AUXDISPLAY_HD44780 auxdisplay_hd44780.c) zephyr_library_sources_ifdef(CONFIG_AUXDISPLAY_ITRON auxdisplay_itron.c) zephyr_library_sources_ifdef(CONFIG_AUXDISPLAY_JHD1313 auxdisplay_jhd1313.c) diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig index a9c616642182e..908ceab179684 100644 --- a/drivers/auxdisplay/Kconfig +++ b/drivers/auxdisplay/Kconfig @@ -20,7 +20,6 @@ module = AUXDISPLAY module-str = auxdisplay source "subsys/logging/Kconfig.template.log_config" -source "drivers/auxdisplay/Kconfig.gpio" source "drivers/auxdisplay/Kconfig.hd44780" source "drivers/auxdisplay/Kconfig.itron" source "drivers/auxdisplay/Kconfig.jhd1313" diff --git a/drivers/auxdisplay/Kconfig.gpio b/drivers/auxdisplay/Kconfig.gpio deleted file mode 100644 index f9ac2ddcb581e..0000000000000 --- a/drivers/auxdisplay/Kconfig.gpio +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024-2025 Chen Xingyu -# SPDX-License-Identifier: Apache-2.0 - -config AUXDISPLAY_GPIO_7SEG - bool "Common GPIO-driven 7-Segment Display" - default y - depends on DT_HAS_GPIO_7_SEGMENT_ENABLED - select GPIO diff --git a/drivers/auxdisplay/auxdisplay_gpio_7seg.c b/drivers/auxdisplay/auxdisplay_gpio_7seg.c deleted file mode 100644 index cfe6e925a8356..0000000000000 --- a/drivers/auxdisplay/auxdisplay_gpio_7seg.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2024-2025 Chen Xingyu - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT gpio_7_segment - -#include -#include -#include -#include - -#include -LOG_MODULE_REGISTER(auxdisplay_gpio_7seg, CONFIG_AUXDISPLAY_LOG_LEVEL); - -static const uint8_t DIGITS[] = { - [0] = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5), - [1] = BIT(1) | BIT(2), - [2] = BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6), - [3] = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(6), - [4] = BIT(1) | BIT(2) | BIT(5) | BIT(6), - [5] = BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6), - [6] = BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), - [7] = BIT(0) | BIT(1) | BIT(2), - [8] = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), - [9] = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | BIT(6), -}; - -#define DP (BIT(7)) -#define BLANK (0x00) - -struct auxdisplay_gpio_7seg_data { - struct k_timer timer; - uint32_t refresh_pos; - int16_t cursor_x; - int16_t cursor_y; -}; - -struct auxdisplay_gpio_7seg_config { - struct auxdisplay_capabilities capabilities; - const struct gpio_dt_spec *segment_gpios; - const struct gpio_dt_spec *digit_gpios; - uint32_t segment_count; - uint32_t digit_count; - uint32_t refresh_period_ms; - uint8_t *buffer; -}; - -static int auxdisplay_gpio_7seg_display_on(const struct device *dev) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - - data->refresh_pos = 0; - k_timer_start(&data->timer, K_NO_WAIT, K_MSEC(cfg->refresh_period_ms)); - - return 0; -} - -static int auxdisplay_gpio_7seg_display_off(const struct device *dev) -{ - struct auxdisplay_gpio_7seg_data *data = dev->data; - - k_timer_stop(&data->timer); - - return 0; -} - -static int auxdisplay_gpio_7seg_cursor_position_set(const struct device *dev, - enum auxdisplay_position type, int16_t x, - int16_t y) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - - if (type == AUXDISPLAY_POSITION_RELATIVE) { - x += data->cursor_x; - y += data->cursor_y; - } else if (type == AUXDISPLAY_POSITION_RELATIVE_DIRECTION) { - return -EINVAL; - } - - if (x < 0 || y < 0) { - return -EINVAL; - } else if (x >= cfg->capabilities.columns || y >= cfg->capabilities.rows) { - return -EINVAL; - } - - data->cursor_x = x; - data->cursor_y = y; - - return 0; -} - -static int auxdisplay_gpio_7seg_cursor_position_get(const struct device *dev, int16_t *x, - int16_t *y) -{ - struct auxdisplay_gpio_7seg_data *data = dev->data; - - *x = data->cursor_x; - *y = data->cursor_y; - - return 0; -} - -static int auxdisplay_gpio_7seg_capabilities_get(const struct device *dev, - struct auxdisplay_capabilities *capabilities) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - - memcpy(capabilities, &cfg->capabilities, sizeof(struct auxdisplay_capabilities)); - - return 0; -} - -static int auxdisplay_gpio_7seg_clear(const struct device *dev) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - - memset(cfg->buffer, 0, cfg->digit_count); - data->refresh_pos = 0; - data->cursor_x = 0; - data->cursor_y = 0; - - return 0; -} - -static int auxdisplay_gpio_7seg_write(const struct device *dev, const uint8_t *ch, uint16_t len) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - uint32_t i, cursor; - - for (i = 0; i < len; i++) { - cursor = data->cursor_y * cfg->capabilities.columns + data->cursor_x; - - /* - * Special case where the decimal point should be added to the - * previous digit - */ - if (ch[i] == '.' && cursor > 0) { - cfg->buffer[cursor - 1] |= DP; - continue; - } - - if (cursor >= cfg->digit_count) { - break; - } - - if (ch[i] >= '0' && ch[i] <= '9') { - cfg->buffer[cursor] = DIGITS[ch[i] - '0']; - } else if (ch[i] == '.') { - /* Leading dot, leave the digit blank */ - cfg->buffer[cursor] = DP; - } else { - cfg->buffer[cursor] = BLANK; - } - - /* Move the cursor */ - if (data->cursor_x < cfg->capabilities.columns - 1) { - data->cursor_x++; - } else if (data->cursor_y < cfg->capabilities.rows - 1) { - data->cursor_x = 0; - data->cursor_y++; - } - } - - /* Reset the refresh position */ - data->refresh_pos = 0; - - return 0; -} - -static void auxdisplay_gpio_7seg_timer_expiry_fn(struct k_timer *timer) -{ - const struct device *dev = k_timer_user_data_get(timer); - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - - /* Turn off the current digit and move to the next one */ - gpio_pin_set_dt(&cfg->digit_gpios[data->refresh_pos], 0); - data->refresh_pos = (data->refresh_pos + 1) % cfg->digit_count; - - /* Set the segments for the new digit */ - for (uint32_t i = 0; i < cfg->segment_count; i++) { - gpio_pin_set_dt(&cfg->segment_gpios[i], cfg->buffer[data->refresh_pos] & BIT(i)); - } - - /* Turn on the new digit */ - gpio_pin_set_dt(&cfg->digit_gpios[data->refresh_pos], 1); -} - -static void auxdisplay_gpio_7seg_timer_stop_fn(struct k_timer *timer) -{ - const struct device *dev = k_timer_user_data_get(timer); - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - - /* Turn off all digits */ - for (uint32_t i = 0; i < cfg->digit_count; i++) { - gpio_pin_set_dt(&cfg->digit_gpios[i], 0); - } -} - -static int auxdisplay_gpio_7seg_init(const struct device *dev) -{ - const struct auxdisplay_gpio_7seg_config *cfg = dev->config; - struct auxdisplay_gpio_7seg_data *data = dev->data; - - for (uint32_t i = 0; i < cfg->segment_count; i++) { - gpio_pin_configure_dt(&cfg->segment_gpios[i], GPIO_OUTPUT_INACTIVE); - } - - for (uint32_t i = 0; i < cfg->digit_count; i++) { - gpio_pin_configure_dt(&cfg->digit_gpios[i], GPIO_OUTPUT_INACTIVE); - } - - k_timer_init(&data->timer, auxdisplay_gpio_7seg_timer_expiry_fn, - auxdisplay_gpio_7seg_timer_stop_fn); - k_timer_user_data_set(&data->timer, (void *)dev); - - auxdisplay_gpio_7seg_display_on(dev); - - return 0; -} - -static DEVICE_API(auxdisplay, auxdisplay_gpio_7seg_api) = { - .display_on = auxdisplay_gpio_7seg_display_on, - .display_off = auxdisplay_gpio_7seg_display_off, - .cursor_position_set = auxdisplay_gpio_7seg_cursor_position_set, - .cursor_position_get = auxdisplay_gpio_7seg_cursor_position_get, - .capabilities_get = auxdisplay_gpio_7seg_capabilities_get, - .clear = auxdisplay_gpio_7seg_clear, - .write = auxdisplay_gpio_7seg_write, -}; - -#define AUXDISPLAY_GPIO_7SEG_INST(n) \ - static struct auxdisplay_gpio_7seg_data auxdisplay_gpio_7seg_data_##n; \ - \ - static const struct gpio_dt_spec auxdisplay_gpio_7seg_segment_gpios_##n[] = { \ - DT_INST_FOREACH_PROP_ELEM_SEP(n, segment_gpios, GPIO_DT_SPEC_GET_BY_IDX, (,))}; \ - \ - static const struct gpio_dt_spec auxdisplay_gpio_7seg_digit_gpios_##n[] = { \ - DT_INST_FOREACH_PROP_ELEM_SEP(n, digit_gpios, GPIO_DT_SPEC_GET_BY_IDX, (,))}; \ - \ - static uint8_t auxdisplay_gpio_7seg_buffer_##n[DT_INST_PROP_LEN(n, digit_gpios)]; \ - \ - static const struct auxdisplay_gpio_7seg_config auxdisplay_gpio_7seg_config_##n = { \ - .capabilities = \ - { \ - .columns = DT_INST_PROP(n, columns), \ - .rows = DT_INST_PROP(n, rows), \ - }, \ - .segment_gpios = auxdisplay_gpio_7seg_segment_gpios_##n, \ - .segment_count = DT_INST_PROP_LEN(n, segment_gpios), \ - .digit_gpios = auxdisplay_gpio_7seg_digit_gpios_##n, \ - .digit_count = DT_INST_PROP_LEN(n, digit_gpios), \ - .refresh_period_ms = DT_INST_PROP(n, refresh_period_ms), \ - .buffer = auxdisplay_gpio_7seg_buffer_##n, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, auxdisplay_gpio_7seg_init, NULL, &auxdisplay_gpio_7seg_data_##n, \ - &auxdisplay_gpio_7seg_config_##n, POST_KERNEL, \ - CONFIG_AUXDISPLAY_INIT_PRIORITY, &auxdisplay_gpio_7seg_api); - -DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_GPIO_7SEG_INST) diff --git a/drivers/auxdisplay/auxdisplay_jhd1313.c b/drivers/auxdisplay/auxdisplay_jhd1313.c index 7016572849ba6..112b114ecfaa4 100644 --- a/drivers/auxdisplay/auxdisplay_jhd1313.c +++ b/drivers/auxdisplay/auxdisplay_jhd1313.c @@ -19,45 +19,47 @@ LOG_MODULE_REGISTER(auxdisplay_jhd1313, CONFIG_AUXDISPLAY_LOG_LEVEL); +#define JHD1313_BACKLIGHT_ADDR (0x62) + /* Defines for the JHD1313_CMD_CURSOR_SHIFT */ -#define JHD1313_CS_DISPLAY_SHIFT (1 << 3) -#define JHD1313_CS_RIGHT_SHIFT (1 << 2) +#define JHD1313_CS_DISPLAY_SHIFT (1 << 3) +#define JHD1313_CS_RIGHT_SHIFT (1 << 2) /* Defines for the JHD1313_CMD_INPUT_SET to change text direction */ -#define JHD1313_IS_INCREMENT (1 << 1) -#define JHD1313_IS_DECREMENT (0 << 1) -#define JHD1313_IS_SHIFT (1 << 0) +#define JHD1313_IS_INCREMENT (1 << 1) +#define JHD1313_IS_DECREMENT (0 << 1) +#define JHD1313_IS_SHIFT (1 << 0) /* Defines for the JHD1313_CMD_FUNCTION_SET */ -#define JHD1313_FS_8BIT_MODE (1 << 4) -#define JHD1313_FS_ROWS_2 (1 << 3) -#define JHD1313_FS_ROWS_1 (0 << 3) -#define JHD1313_FS_DOT_SIZE_BIG (1 << 2) -#define JHD1313_FS_DOT_SIZE_LITTLE (0 << 2) +#define JHD1313_FS_8BIT_MODE (1 << 4) +#define JHD1313_FS_ROWS_2 (1 << 3) +#define JHD1313_FS_ROWS_1 (0 << 3) +#define JHD1313_FS_DOT_SIZE_BIG (1 << 2) +#define JHD1313_FS_DOT_SIZE_LITTLE (0 << 2) /* LCD Display Commands */ -#define JHD1313_CMD_SCREEN_CLEAR (1 << 0) -#define JHD1313_CMD_CURSOR_RETURN (1 << 1) -#define JHD1313_CMD_INPUT_SET (1 << 2) -#define JHD1313_CMD_DISPLAY_SWITCH (1 << 3) -#define JHD1313_CMD_CURSOR_SHIFT (1 << 4) -#define JHD1313_CMD_FUNCTION_SET (1 << 5) -#define JHD1313_CMD_SET_CGRAM_ADDR (1 << 6) -#define JHD1313_CMD_SET_DDRAM_ADDR (1 << 7) +#define JHD1313_CMD_SCREEN_CLEAR (1 << 0) +#define JHD1313_CMD_CURSOR_RETURN (1 << 1) +#define JHD1313_CMD_INPUT_SET (1 << 2) +#define JHD1313_CMD_DISPLAY_SWITCH (1 << 3) +#define JHD1313_CMD_CURSOR_SHIFT (1 << 4) +#define JHD1313_CMD_FUNCTION_SET (1 << 5) +#define JHD1313_CMD_SET_CGRAM_ADDR (1 << 6) +#define JHD1313_CMD_SET_DDRAM_ADDR (1 << 7) -#define JHD1313_DS_DISPLAY_ON (1 << 2) -#define JHD1313_DS_CURSOR_ON (1 << 1) -#define JHD1313_DS_BLINK_ON (1 << 0) +#define JHD1313_DS_DISPLAY_ON (1 << 2) +#define JHD1313_DS_CURSOR_ON (1 << 1) +#define JHD1313_DS_BLINK_ON (1 << 0) -#define JHD1313_LED_REG_R 0x04 -#define JHD1313_LED_REG_G 0x03 -#define JHD1313_LED_REG_B 0x02 +#define JHD1313_LED_REG_R 0x04 +#define JHD1313_LED_REG_G 0x03 +#define JHD1313_LED_REG_B 0x02 -#define JHD1313_LINE_FIRST 0x80 -#define JHD1313_LINE_SECOND 0xC0 +#define JHD1313_LINE_FIRST 0x80 +#define JHD1313_LINE_SECOND 0xC0 -#define CLEAR_DELAY_MS 20 -#define UPDATE_DELAY_MS 5 +#define CLEAR_DELAY_MS 20 +#define UPDATE_DELAY_MS 5 struct auxdisplay_jhd1313_data { uint8_t input_set; @@ -71,30 +73,27 @@ struct auxdisplay_jhd1313_data { struct auxdisplay_jhd1313_config { struct auxdisplay_capabilities capabilities; struct i2c_dt_spec bus; - uint8_t backlight_addr; }; static const uint8_t colour_define[][4] = { - {0, 0, 0}, /* Off */ - {255, 255, 255}, /* White */ - {255, 0, 0}, /* Red */ - {0, 255, 0}, /* Green */ - {0, 0, 255}, /* Blue */ + { 0, 0, 0 }, /* Off */ + { 255, 255, 255 }, /* White */ + { 255, 0, 0 }, /* Red */ + { 0, 255, 0 }, /* Green */ + { 0, 0, 255 }, /* Blue */ }; -static void auxdisplay_jhd1313_reg_set(const struct device *dev, uint8_t addr, uint8_t data) +static void auxdisplay_jhd1313_reg_set(const struct device *i2c, uint8_t addr, uint8_t data) { - const struct auxdisplay_jhd1313_config *config = dev->config; - const struct device *i2c = config->bus.bus; - uint8_t command[2] = {addr, data}; + uint8_t command[2] = { addr, data }; - i2c_write(i2c, command, sizeof(command), config->backlight_addr); + i2c_write(i2c, command, sizeof(command), JHD1313_BACKLIGHT_ADDR); } static int auxdisplay_jhd1313_print(const struct device *dev, const uint8_t *data, uint16_t size) { const struct auxdisplay_jhd1313_config *config = dev->config; - uint8_t buf[] = {JHD1313_CMD_SET_CGRAM_ADDR, 0}; + uint8_t buf[] = { JHD1313_CMD_SET_CGRAM_ADDR, 0 }; int rc = 0; int16_t i; @@ -133,7 +132,7 @@ static int auxdisplay_jhd1313_clear(const struct device *dev) { int rc; const struct auxdisplay_jhd1313_config *config = dev->config; - uint8_t clear[] = {0, JHD1313_CMD_SCREEN_CLEAR}; + uint8_t clear[] = { 0, JHD1313_CMD_SCREEN_CLEAR }; rc = i2c_write_dt(&config->bus, clear, sizeof(clear)); LOG_DBG("Clear, delay 20 ms"); @@ -143,11 +142,12 @@ static int auxdisplay_jhd1313_clear(const struct device *dev) return rc; } -static int auxdisplay_jhd1313_update_display_state(const struct auxdisplay_jhd1313_config *config, - struct auxdisplay_jhd1313_data *data) +static int auxdisplay_jhd1313_update_display_state( + const struct auxdisplay_jhd1313_config *config, + struct auxdisplay_jhd1313_data *data) { int rc; - uint8_t buf[] = {0, JHD1313_CMD_DISPLAY_SWITCH}; + uint8_t buf[] = { 0, JHD1313_CMD_DISPLAY_SWITCH }; if (data->power) { buf[1] |= JHD1313_DS_DISPLAY_ON; @@ -191,7 +191,7 @@ static void auxdisplay_jhd1313_input_state_set(const struct device *dev, uint8_t { const struct auxdisplay_jhd1313_config *config = dev->config; struct auxdisplay_jhd1313_data *data = dev->data; - uint8_t buf[] = {0, 0}; + uint8_t buf[] = { 0, 0 }; data->input_set = opt; buf[1] = (opt | JHD1313_CMD_INPUT_SET); @@ -202,6 +202,7 @@ static void auxdisplay_jhd1313_input_state_set(const struct device *dev, uint8_t static int auxdisplay_jhd1313_backlight_set(const struct device *dev, uint8_t colour) { + const struct auxdisplay_jhd1313_config *config = dev->config; struct auxdisplay_jhd1313_data *data = dev->data; if (colour >= ARRAY_SIZE(colour_define)) { @@ -211,9 +212,9 @@ static int auxdisplay_jhd1313_backlight_set(const struct device *dev, uint8_t co data->backlight = colour; - auxdisplay_jhd1313_reg_set(dev, JHD1313_LED_REG_R, colour_define[colour][0]); - auxdisplay_jhd1313_reg_set(dev, JHD1313_LED_REG_G, colour_define[colour][1]); - auxdisplay_jhd1313_reg_set(dev, JHD1313_LED_REG_B, colour_define[colour][2]); + auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_R, colour_define[colour][0]); + auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_G, colour_define[colour][1]); + auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_B, colour_define[colour][2]); return 0; } @@ -231,7 +232,7 @@ static void auxdisplay_jhd1313_function_set(const struct device *dev, uint8_t op { const struct auxdisplay_jhd1313_config *config = dev->config; struct auxdisplay_jhd1313_data *data = dev->data; - uint8_t buf[] = {0, 0}; + uint8_t buf[] = { 0, 0 }; data->function = opt; buf[1] = (opt | JHD1313_CMD_FUNCTION_SET); @@ -295,9 +296,9 @@ static int auxdisplay_jhd1313_initialize(const struct device *dev) /* Now power on the background RGB control */ LOG_INF("Configuring the RGB background"); - auxdisplay_jhd1313_reg_set(dev, 0x00, 0x00); - auxdisplay_jhd1313_reg_set(dev, 0x01, 0x05); - auxdisplay_jhd1313_reg_set(dev, 0x08, 0xAA); + auxdisplay_jhd1313_reg_set(config->bus.bus, 0x00, 0x00); + auxdisplay_jhd1313_reg_set(config->bus.bus, 0x01, 0x05); + auxdisplay_jhd1313_reg_set(config->bus.bus, 0x08, 0xAA); /* Now set the background colour to black */ LOG_DBG("Background set to off"); @@ -347,30 +348,32 @@ static DEVICE_API(auxdisplay, auxdisplay_jhd1313_auxdisplay_api) = { .write = auxdisplay_jhd1313_print, }; -#define AUXDISPLAY_JHD1313_DEVICE(inst) \ - static const struct auxdisplay_jhd1313_config auxdisplay_jhd1313_config_##inst = { \ - .capabilities = \ - { \ - .columns = 16, \ - .rows = 2, \ - .mode = 0, \ - .brightness.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \ - .brightness.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \ - .backlight.minimum = 0, \ - .backlight.maximum = ARRAY_SIZE(colour_define), \ - .custom_characters = 0, \ - }, \ - .bus = I2C_DT_SPEC_INST_GET(inst), \ - .backlight_addr = DT_INST_PROP(inst, backlight_addr), \ - }; \ - static struct auxdisplay_jhd1313_data auxdisplay_jhd1313_data_##inst = { \ - .power = true, \ - .cursor = false, \ - .blinking = false, \ - }; \ - DEVICE_DT_INST_DEFINE(inst, &auxdisplay_jhd1313_initialize, NULL, \ - &auxdisplay_jhd1313_data_##inst, &auxdisplay_jhd1313_config_##inst, \ - POST_KERNEL, CONFIG_AUXDISPLAY_INIT_PRIORITY, \ - &auxdisplay_jhd1313_auxdisplay_api); +#define AUXDISPLAY_JHD1313_DEVICE(inst) \ + static const struct auxdisplay_jhd1313_config auxdisplay_jhd1313_config_##inst = { \ + .capabilities = { \ + .columns = 16, \ + .rows = 2, \ + .mode = 0, \ + .brightness.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \ + .brightness.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \ + .backlight.minimum = 0, \ + .backlight.maximum = ARRAY_SIZE(colour_define), \ + .custom_characters = 0, \ + }, \ + .bus = I2C_DT_SPEC_INST_GET(inst), \ + }; \ + static struct auxdisplay_jhd1313_data auxdisplay_jhd1313_data_##inst = { \ + .power = true, \ + .cursor = false, \ + .blinking = false, \ + }; \ + DEVICE_DT_INST_DEFINE(inst, \ + &auxdisplay_jhd1313_initialize, \ + NULL, \ + &auxdisplay_jhd1313_data_##inst, \ + &auxdisplay_jhd1313_config_##inst, \ + POST_KERNEL, \ + CONFIG_AUXDISPLAY_INIT_PRIORITY, \ + &auxdisplay_jhd1313_auxdisplay_api); DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_JHD1313_DEVICE) diff --git a/drivers/bluetooth/hci/hci_ifx_cyw208xx.c b/drivers/bluetooth/hci/hci_ifx_cyw208xx.c index 1fee53436a6ef..db218fc7e599b 100644 --- a/drivers/bluetooth/hci/hci_ifx_cyw208xx.c +++ b/drivers/bluetooth/hci/hci_ifx_cyw208xx.c @@ -5,46 +5,46 @@ * SPDX-License-Identifier: Apache-2.0 */ -/** - * @brief Zephyr CYW20829 driver. - * - * This driver uses btstack-integration asset as hosts platform adaptation layer - * (porting layer) for CYW20829. btstack-integration layer implements/ - * invokes the interfaces defined by BTSTACK to enable communication - * with the BT controller by using IPC_BTSS (IPC Bluetooth sub-system interface). - * Zephyr CYW20829 driver implements wiced_bt_**** functions requreds for - * btstack-integration asset and Zephyr Bluetooth driver interface - * (defined in struct bt_hci_driver). - * - * CM33 (application core) - * |=========================================| - * | |-------------------------| | - * | | Zephyr application | | - * | |-------------------------| | - * | | | - * | |------------| | - * | | Zephyr | | - * | | Bluetooth | | - * CM33 (BTSS core) | | Host | | - * |=====================| | |------------| | - * | | | | | - * | |---------------| | | |--------------| | -----------| | - * | | Bluetooth | | IPC_BTSS | | btstack- | | Zephyr | | - * | | Controller FW | | <--------|-> | integration | ---- | CYW20829 | | - * | |---------------| | | | asset | | driver | | - * | | | |--------------| |------------| | - * |=====================| | | - * | |=========================================| - * |====================| - * | CYW20829 | - * | Bluetooth | - * |====================| - * - * NOTE: - * cyw920829 requires fetch binary files of Bluetooth controller firmware. - * To fetch Binary Blobs: west blobs fetch hal_infineon - * - */ + /** + * @brief Zephyr CYW20829 driver. + * + * This driver uses btstack-integration asset as hosts platform adaptation layer + * (porting layer) for CYW20829. btstack-integration layer implements/ + * invokes the interfaces defined by BTSTACK to enable communication + * with the BT controller by using IPC_BTSS (IPC Bluetooth sub-system interface). + * Zephyr CYW20829 driver implements wiced_bt_**** functions requreds for + * btstack-integration asset and Zephyr Bluetooth driver interface + * (defined in struct bt_hci_driver). + * + * CM33 (application core) + * |=========================================| + * | |-------------------------| | + * | | Zephyr application | | + * | |-------------------------| | + * | | | + * | |------------| | + * | | Zephyr | | + * | | Bluetooth | | + * CM33 (BTSS core) | | Host | | + * |=====================| | |------------| | + * | | | | | + * | |---------------| | | |--------------| | -----------| | + * | | Bluetooth | | IPC_BTSS | | btstack- | | Zephyr | | + * | | Controller FW | | <--------|-> | integration | ---- | CYW20829 | | + * | |---------------| | | | asset | | driver | | + * | | | |--------------| |------------| | + * |=====================| | | + * | |=========================================| + * |====================| + * | CYW20829 | + * | Bluetooth | + * |====================| + * + * NOTE: + * cyw920829 requires fetch binary files of Bluetooth controller firmware. + * To fetch Binary Blobs: west blobs fetch hal_infineon + * + */ #include #include @@ -69,9 +69,7 @@ #include #include -#include "cyhal_syspm.h" - -#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL +#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL #include LOG_MODULE_REGISTER(cyw208xx); @@ -93,34 +91,25 @@ enum { extern const uint8_t brcm_patchram_buf[]; extern const int brcm_patch_ram_length; -#define CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED (1) -#define BTM_SET_LOCAL_DEV_ADDR_LENGTH 6 +#define CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED (0) +#define BTM_SET_LOCAL_DEV_ADDR_LENGTH 6 static K_SEM_DEFINE(hci_sem, 1, 1); static K_SEM_DEFINE(cybt_platform_task_init_sem, 0, 1); -cy_en_syspm_status_t cyw208xx_syspm_callback(cy_stc_syspm_callback_params_t *callbackParams, - cy_en_syspm_callback_mode_t mode); - -static cy_stc_syspm_callback_params_t cyw208xx_syspm_callback_param = {NULL, NULL}; -static cy_stc_syspm_callback_t cyw208xx_syspm_callback_cfg = { - .callback = &cyw208xx_syspm_callback, - .type = (cy_en_syspm_callback_type_t)CY_SYSPM_DEEPSLEEP | CY_SYSPM_SLEEP, - .callbackParams = &cyw208xx_syspm_callback_param, - .order = 253u, -}; -/* Extern btstack integration functions */ +/****************************************************************************** + * Function Declarations + ******************************************************************************/ extern void host_stack_platform_interface_init(void); extern void cybt_platform_hci_wait_for_boot_fully_up(bool is_from_isr); extern uint8_t *host_stack_get_acl_to_lower_buffer(wiced_bt_transport_t transport, uint32_t size); -extern wiced_result_t host_stack_send_acl_to_lower(wiced_bt_transport_t transport, uint8_t *data, - uint16_t len); +extern wiced_result_t host_stack_send_acl_to_lower(wiced_bt_transport_t transport, + uint8_t *data, uint16_t len); extern wiced_result_t host_stack_send_cmd_to_lower(uint8_t *cmd, uint16_t cmd_len); extern wiced_result_t host_stack_send_iso_to_lower(uint8_t *data, uint16_t len); extern cybt_result_t cybt_platform_msg_to_bt_task(const uint16_t msg, bool is_from_isr); extern void cybt_bttask_deinit(void); -uint8_t task_queue_utilization(void); static int cyw208xx_bt_firmware_download(const uint8_t *firmware_image, uint32_t size) { @@ -140,16 +129,11 @@ static int cyw208xx_bt_firmware_download(const uint8_t *firmware_image, uint32_t size_t data_length = data[2]; /* data length from firmware image block */ uint16_t op_code = *(uint16_t *)data; - if (op_code == BT_HCI_VND_OP_LAUNCH_RAM) { - /* set hf0 to 48MHz */ - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - /* Allocate buffer for hci_write_ram/hci_launch_ram command. */ buf = bt_hci_cmd_create(op_code, data_length); if (buf == NULL) { LOG_ERR("Unable to allocate command buffer"); - return -ENOBUFS; + return err; } /* Add data part of packet */ @@ -190,20 +174,15 @@ static int cyw208xx_setup(const struct device *dev, const struct bt_hci_setup_pa int err; struct net_buf *buf; - /* Avoid sleep while downloading firmware */ - cyhal_syspm_lock_deepsleep(); - /* Send HCI_RESET */ err = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, NULL); if (err) { - cyhal_syspm_unlock_deepsleep(); return err; } /* BT firmware download */ err = cyw208xx_bt_firmware_download(brcm_patchram_buf, (uint32_t)brcm_patch_ram_length); if (err) { - cyhal_syspm_unlock_deepsleep(); return err; } @@ -214,7 +193,6 @@ static int cyw208xx_setup(const struct device *dev, const struct bt_hci_setup_pa buf = bt_hci_cmd_create(BT_HCI_VND_OP_SET_LOCAL_DEV_ADDR, BTM_SET_LOCAL_DEV_ADDR_LENGTH); if (buf == NULL) { LOG_ERR("Unable to allocate command buffer"); - cyhal_syspm_unlock_deepsleep(); return -ENOMEM; } @@ -237,12 +215,9 @@ static int cyw208xx_setup(const struct device *dev, const struct bt_hci_setup_pa err = bt_hci_cmd_send_sync(BT_HCI_VND_OP_SET_LOCAL_DEV_ADDR, buf, NULL); if (err) { LOG_ERR("Failed to set public address (%d)", err); - cyhal_syspm_unlock_deepsleep(); return err; } - cyhal_syspm_unlock_deepsleep(); - return 0; } @@ -342,30 +317,25 @@ static int cyw208xx_hci_init(const struct device *dev) const cybt_platform_config_t cybsp_bt_platform_cfg = { .hci_config = { .hci_transport = CYBT_HCI_IPC, - }, + }, .controller_config = { .sleep_mode = { - .sleep_mode_enabled = - CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED, - }, - }}; + .sleep_mode_enabled = CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED, + }, + } + }; /* Configure platform specific settings for the BT device */ cybt_platform_config_init(&cybsp_bt_platform_cfg); - if (!Cy_SysPm_RegisterCallback(&cyw208xx_syspm_callback_cfg)) { - LOG_ERR("Syspm Callback registering failed!"); - CY_ASSERT(0); - } return 0; } /* Implements wiced_bt_**** functions requreds for the btstack-integration asset */ -wiced_result_t -wiced_bt_dev_vendor_specific_command(uint16_t opcode, uint8_t param_len, uint8_t *param_buf, - wiced_bt_dev_vendor_specific_command_complete_cback_t cback) +wiced_result_t wiced_bt_dev_vendor_specific_command(uint16_t opcode, uint8_t param_len, + uint8_t *param_buf, wiced_bt_dev_vendor_specific_command_complete_cback_t cback) { /* @@ -426,6 +396,7 @@ void wiced_bt_process_hci(hci_packet_type_t pti, uint8_t *data, uint32_t length) default: return; + } buf_tailroom = net_buf_tailroom(buf); @@ -477,37 +448,10 @@ void wiced_bt_process_timer(void) /* NA for Zephyr */ } -cy_en_syspm_status_t cyw208xx_syspm_callback(cy_stc_syspm_callback_params_t *callbackParams, - cy_en_syspm_callback_mode_t mode) -{ - cy_en_syspm_status_t retVal = CY_SYSPM_FAIL; - - CY_UNUSED_PARAMETER(callbackParams); - - switch (mode) { - case CY_SYSPM_CHECK_READY: - case CY_SYSPM_BEFORE_TRANSITION: { - retVal = (task_queue_utilization() == 0) ? CY_SYSPM_SUCCESS : CY_SYSPM_FAIL; - break; - } - - case CY_SYSPM_CHECK_FAIL: - case CY_SYSPM_AFTER_TRANSITION: { - - retVal = CY_SYSPM_SUCCESS; - break; - } - - default: - break; - } - - return retVal; -} - -#define CYW208XX_DEVICE_INIT(inst) \ - static struct cyw208xx_data cyw208xx_data_##inst = {}; \ - DEVICE_DT_INST_DEFINE(inst, cyw208xx_hci_init, NULL, &cyw208xx_data_##inst, NULL, \ +#define CYW208XX_DEVICE_INIT(inst) \ + static struct cyw208xx_data cyw208xx_data_##inst = { \ + }; \ + DEVICE_DT_INST_DEFINE(inst, cyw208xx_hci_init, NULL, &cyw208xx_data_##inst, NULL, \ POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv) /* Only one instance supported */ diff --git a/drivers/bluetooth/hci/hci_silabs_efr32.c b/drivers/bluetooth/hci/hci_silabs_efr32.c index 229eee82b7a30..d85176af0c324 100644 --- a/drivers/bluetooth/hci/hci_silabs_efr32.c +++ b/drivers/bluetooth/hci/hci_silabs_efr32.c @@ -268,12 +268,10 @@ static int slz_bt_open(const struct device *dev, bt_hci_recv_t recv) k_thread_create(&slz_ll_thread, slz_ll_stack, K_KERNEL_STACK_SIZEOF(slz_ll_stack), slz_ll_thread_func, NULL, NULL, NULL, K_PRIO_COOP(CONFIG_BT_SILABS_EFR32_LL_THREAD_PRIO), 0, K_NO_WAIT); - k_thread_name_set(&slz_ll_thread, "EFR32 LL"); k_thread_create(&slz_rx_thread, slz_rx_stack, K_KERNEL_STACK_SIZEOF(slz_rx_stack), slz_rx_thread_func, (void *)dev, NULL, NULL, K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO), 0, K_NO_WAIT); - k_thread_name_set(&slz_rx_thread, "EFR32 HCI RX"); rail_isr_installer(); sl_rail_util_pa_init(); diff --git a/drivers/can/CMakeLists.txt b/drivers/can/CMakeLists.txt index 22815a28acf38..c84884df8b56f 100644 --- a/drivers/can/CMakeLists.txt +++ b/drivers/can/CMakeLists.txt @@ -27,7 +27,6 @@ zephyr_library_sources_ifdef(CONFIG_CAN_NUMAKER can_numaker.c) zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL can_nxp_s32_canxl.c) zephyr_library_sources_ifdef(CONFIG_CAN_RCAR can_rcar.c) zephyr_library_sources_ifdef(CONFIG_CAN_RENESAS_RA_CANFD can_renesas_ra.c) -zephyr_library_sources_ifdef(CONFIG_CAN_RENESAS_RZ_CANFD can_renesas_rz_canfd.c) zephyr_library_sources_ifdef(CONFIG_CAN_SAM can_sam.c) zephyr_library_sources_ifdef(CONFIG_CAN_SAM0 can_sam0.c) zephyr_library_sources_ifdef(CONFIG_CAN_SJA1000 can_sja1000.c) diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig index 0b600db015da5..c6e89e464aa9b 100644 --- a/drivers/can/Kconfig +++ b/drivers/can/Kconfig @@ -130,7 +130,6 @@ source "drivers/can/Kconfig.mcp251xfd" source "drivers/can/Kconfig.xmc4xxx" source "drivers/can/Kconfig.nrf" source "drivers/can/Kconfig.renesas_ra" -source "drivers/can/Kconfig.renesas_rz" source "drivers/can/transceiver/Kconfig" diff --git a/drivers/can/Kconfig.numaker b/drivers/can/Kconfig.numaker index 21bd9f2efefc7..3e0db28a20048 100644 --- a/drivers/can/Kconfig.numaker +++ b/drivers/can/Kconfig.numaker @@ -9,6 +9,6 @@ config CAN_NUMAKER select CAN_MCAN select PINCTRL depends on DT_HAS_NUVOTON_NUMAKER_CANFD_ENABLED - depends on SOC_SERIES_M46X || SOC_SERIES_M2L31X || SOC_SERIES_M55M1X + depends on SOC_SERIES_M46X || SOC_SERIES_M2L31X help Enables Nuvoton NuMaker CAN FD driver, using Bosch M_CAN diff --git a/drivers/can/Kconfig.renesas_rz b/drivers/can/Kconfig.renesas_rz deleted file mode 100644 index d50a33667c517..0000000000000 --- a/drivers/can/Kconfig.renesas_rz +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2025 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config CAN_RENESAS_RZ_CANFD - bool "Renesas RZ CANFD" - default y - depends on DT_HAS_RENESAS_RZ_CANFD_ENABLED - select USE_RZ_FSP_CANFD - select CLOCK_CONTROL - help - Enable Renesas RZ CANFD driver diff --git a/drivers/can/can_common.c b/drivers/can/can_common.c index 875948b65ca61..91d527793e9a6 100644 --- a/drivers/can/can_common.c +++ b/drivers/can/can_common.c @@ -27,8 +27,6 @@ static void can_tx_default_cb(const struct device *dev, int error, void *user_da { struct can_tx_default_cb_ctx *ctx = user_data; - ARG_UNUSED(dev); - ctx->status = error; k_sem_give(&ctx->done); } @@ -160,8 +158,7 @@ static int update_sample_pnt(uint32_t total_tq, uint32_t sample_pnt, struct can_ uint16_t tseg1_max = max->phase_seg1 + max->prop_seg; uint16_t tseg1_min = min->phase_seg1 + min->prop_seg; uint32_t sample_pnt_res; - uint16_t tseg1; - uint16_t tseg2; + uint16_t tseg1, tseg2; /* Calculate number of time quanta in tseg2 for given sample point */ tseg2 = total_tq - (total_tq * sample_pnt) / 1000; @@ -185,8 +182,6 @@ static int update_sample_pnt(uint32_t total_tq, uint32_t sample_pnt, struct can_ if (tseg2 < min->phase_seg2) { return -ENOTSUP; } - } else { - /* Sample point location within range */ } res->phase_seg2 = tseg2; @@ -203,8 +198,6 @@ static int update_sample_pnt(uint32_t total_tq, uint32_t sample_pnt, struct can_ /* Even tseg1 distribution not possible, increase phase_seg1 */ res->phase_seg1 = min->phase_seg1; res->prop_seg = tseg1 - res->phase_seg1; - } else { - /* No redistribution necessary */ } /* Calculate the resulting sample point */ @@ -263,6 +256,7 @@ static int can_calc_timing_internal(const struct device *dev, struct can_timing struct can_timing tmp_res = { 0 }; int err_min = INT_MAX; uint32_t core_clock; + int prescaler; int err; if (bitrate == 0 || sample_pnt >= 1000) { @@ -278,7 +272,7 @@ static int can_calc_timing_internal(const struct device *dev, struct can_timing sample_pnt = sample_point_for_bitrate(bitrate); } - for (int prescaler = MAX(core_clock / (total_tq * bitrate), min->prescaler); + for (prescaler = MAX(core_clock / (total_tq * bitrate), min->prescaler); prescaler <= max->prescaler; prescaler++) { diff --git a/drivers/can/can_numaker.c b/drivers/can/can_numaker.c index 13e25aff6652f..9fc78ec58d5d0 100644 --- a/drivers/can/can_numaker.c +++ b/drivers/can/can_numaker.c @@ -18,6 +18,12 @@ LOG_MODULE_REGISTER(can_numaker, CONFIG_CAN_LOG_LEVEL); +/* CANFD Clock Source Selection */ +#define NUMAKER_CANFD_CLKSEL_HXT 0 +#define NUMAKER_CANFD_CLKSEL_PLL_DIV2 1 +#define NUMAKER_CANFD_CLKSEL_HCLK 2 +#define NUMAKER_CANFD_CLKSEL_HIRC 3 + /* Implementation notes * 1. Use Bosch M_CAN driver (m_can) as backend * 2. Need to modify can_numaker_get_core_clock() for new SOC support @@ -49,49 +55,18 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate) clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1; switch (clksrc_rate_idx) { -#if defined(CONFIG_SOC_SERIES_M46X) - case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos): + case NUMAKER_CANFD_CLKSEL_HXT: *rate = __HXT / clkdiv_divider; break; - case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos): + case NUMAKER_CANFD_CLKSEL_PLL_DIV2: *rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider; break; - case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos): - *rate = CLK_GetHCLKFreq() / clkdiv_divider; - break; - case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos): - *rate = __HIRC / clkdiv_divider; - break; -#elif defined(CONFIG_SOC_SERIES_M2L31X) - case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos): - *rate = __HXT / clkdiv_divider; - break; - case (CLK_CLKSEL0_CANFD0SEL_HIRC48M >> CLK_CLKSEL0_CANFD0SEL_Pos): - *rate = __HIRC48 / clkdiv_divider; - break; - case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos): + case NUMAKER_CANFD_CLKSEL_HCLK: *rate = CLK_GetHCLKFreq() / clkdiv_divider; break; - case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos): + case NUMAKER_CANFD_CLKSEL_HIRC: *rate = __HIRC / clkdiv_divider; break; -#elif defined(CONFIG_SOC_SERIES_M55M1X) - case (CLK_CANFDSEL_CANFD0SEL_HXT >> CLK_CANFDSEL_CANFD0SEL_Pos): - *rate = __HXT / clkdiv_divider; - break; - case (CLK_CANFDSEL_CANFD0SEL_APLL0_DIV2 >> CLK_CANFDSEL_CANFD0SEL_Pos): - *rate = (CLK_GetAPLL0ClockFreq() / 2) / clkdiv_divider; - break; - case (CLK_CANFDSEL_CANFD0SEL_HCLK0 >> CLK_CANFDSEL_CANFD0SEL_Pos): - *rate = CLK_GetHCLK0Freq() / clkdiv_divider; - break; - case (CLK_CANFDSEL_CANFD0SEL_HIRC >> CLK_CANFDSEL_CANFD0SEL_Pos): - *rate = __HIRC / clkdiv_divider; - break; - case (CLK_CANFDSEL_CANFD0SEL_HIRC48M_DIV4 >> CLK_CANFDSEL_CANFD0SEL_Pos): - *rate = (__HIRC48M / 4) / clkdiv_divider; - break; -#endif default: LOG_ERR("Invalid clock source rate index"); return -EIO; diff --git a/drivers/can/can_renesas_rz_canfd.c b/drivers/can/can_renesas_rz_canfd.c deleted file mode 100644 index 5410b23569517..0000000000000 --- a/drivers/can/can_renesas_rz_canfd.c +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * Copyright (c) 2025 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include "r_can_api.h" -#include "r_canfd.h" -#include - -LOG_MODULE_REGISTER(can_renesas_rz_canfd, CONFIG_CAN_LOG_LEVEL); - -#define DT_DRV_COMPAT renesas_rz_canfd - -#define CAN_RENESAS_RZ_TIMING_MAX \ - { \ - .sjw = 32, \ - .prop_seg = 1, \ - .phase_seg1 = 127, \ - .phase_seg2 = 32, \ - .prescaler = 1024, \ - } - -#define CAN_RENESAS_RZ_TIMING_MIN \ - { \ - .sjw = 1, \ - .prop_seg = 1, \ - .phase_seg1 = 2, \ - .phase_seg2 = 2, \ - .prescaler = 1, \ - } - -#ifdef CONFIG_CAN_FD_MODE -#define CAN_RENESAS_RZ_TIMING_DATA_MAX \ - { \ - .sjw = 16, \ - .prop_seg = 1, \ - .phase_seg1 = 31, \ - .phase_seg2 = 16, \ - .prescaler = 256, \ - } -#define CAN_RENESAS_RZ_TIMING_DATA_MIN \ - { \ - .sjw = 1, \ - .prop_seg = 1, \ - .phase_seg1 = 2, \ - .phase_seg2 = 2, \ - .prescaler = 1, \ - } -#endif - -#define CAN_RENESAS_RZ_CHN0 0 -#define CAN_RENESAS_RZ_CHN1 1 - -/* This frame ID will be reserved. Any filter using this ID may cause undefined behavior. */ -#define CAN_RENESAS_RZ_RESERVED_ID (CAN_EXT_ID_MASK) - -/* - * TX Message Buffer Interrupt Enable Configuration: refer to '30.2.53 TX Message Buffer - * Transmission Interrupt Enable Register n (CFDTMIECn)' - RZ/G3S MCU group HWM - */ -#define CANFD_CFG_TXMB_TXI_ENABLE (BIT(0)) /* Enable TXMB0 interrupt */ - -/* - * Channel Error IRQ configurations: refer to '30.2.2 Channel n Control Register (CFDCnCTR)' - - * RZ/G3S MCU group HWM - */ -#define CANFD_CFG_ERR_IRQ \ - (BIT(R_CANFD_CFDC_CTR_EWIE_Pos) | /* Error Warning Interrupt Enable */ \ - BIT(R_CANFD_CFDC_CTR_EPIE_Pos) | /* Error Passive Interrupt Enable */ \ - BIT(R_CANFD_CFDC_CTR_BOEIE_Pos) | /* Bus-Off Entry Interrupt Enable */ \ - BIT(R_CANFD_CFDC_CTR_BORIE_Pos) | /* Bus-Off Recovery Interrupt Enable */ \ - BIT(R_CANFD_CFDC_CTR_OLIE_Pos)) /* Overload Interrupt Enable */ - -#define RULE_NUM_PER_PAGE (16) - -#define CANFD_CFG_RXFIFO_DEFAULT(x) \ - ((CANFD_CFG_RXFIFO##x##_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | \ - (CANFD_CFG_RXFIFO##x##_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | \ - (CANFD_CFG_RXFIFO##x##_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | \ - (CANFD_CFG_RXFIFO##x##_INT_MODE) | (CANFD_CFG_RXFIFO##x##_ENABLE)) - -/* Default Dataphase bitrate configuration in case classic mode is enabled */ -static const can_bit_timing_cfg_t classic_can_data_timing_default = { - .baud_rate_prescaler = 1, - .time_segment_1 = 3, - .time_segment_2 = 2, - .synchronization_jump_width = 1, -}; - -struct can_renesas_rz_filter { - bool set; - struct can_filter filter; - can_rx_callback_t rx_cb; - void *rx_usr_data; -}; - -struct can_renesas_rz_cfg { - struct can_driver_config common; - const struct pinctrl_dev_config *pin_config; - const struct device *global_dev; - const uint32_t rx_filter_num; - const can_api_t *fsp_api; - const struct device *clock_dev; - clock_control_subsys_t clock_subsys; - uint32_t clock_ext_rate; -}; - -struct can_renesas_rz_data { - struct can_driver_data common; - struct k_mutex inst_mutex; - can_tx_callback_t tx_cb; - struct k_sem tx_sem; - void *tx_usr_data; - struct can_renesas_rz_filter *rx_filter; - can_bit_timing_cfg_t data_timing; - - canfd_instance_ctrl_t *fsp_ctrl; - can_cfg_t *fsp_cfg; -}; - -extern void canfd_error_isr(void); -extern void canfd_rx_fifo_isr(void); -extern void canfd_channel_tx_isr(void); -static inline int can_renesas_rz_apply_default_config(const struct device *dev); - -static inline int set_hw_timing_configuration(const struct device *dev, - can_bit_timing_cfg_t *f_timing, - const struct can_timing *z_timing) -{ - struct can_renesas_rz_data *data = dev->data; - - if (f_timing == NULL || z_timing == NULL) { - return -EINVAL; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - *f_timing = (can_bit_timing_cfg_t){ - .baud_rate_prescaler = z_timing->prescaler, - .time_segment_1 = z_timing->prop_seg + z_timing->phase_seg1, - .time_segment_2 = z_timing->phase_seg2, - .synchronization_jump_width = z_timing->sjw, - }; - - k_mutex_unlock(&data->inst_mutex); - - return 0; -} - -static inline int get_free_filter_id(const struct device *dev) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - int ret = 0; - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) { - if (!data->rx_filter[filter_id].set) { - ret = filter_id; - k_mutex_unlock(&data->inst_mutex); - return ret; - } - } - - /* there are no free filter */ - ret = -ENOSPC; - k_mutex_unlock(&data->inst_mutex); - return ret; -} - -static void set_afl_rule(const struct device *dev, const struct can_filter *filter, - uint32_t afl_offset) -{ - struct can_renesas_rz_data *data = dev->data; - canfd_extended_cfg_t const *p_extend = data->fsp_cfg->p_extend; - uint32_t channel = data->fsp_cfg->channel; - canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset]; - - *afl = (canfd_afl_entry_t){.id = {.id = filter->id, -#ifndef CONFIG_CAN_ACCEPT_RTR - .frame_type = CAN_FRAME_TYPE_DATA, -#endif - .id_mode = ((filter->flags & CAN_FILTER_IDE) != 0) - ? CAN_ID_MODE_EXTENDED - : CAN_ID_MODE_STANDARD}, - .mask = {.mask_id = filter->mask, -#ifdef CONFIG_CAN_ACCEPT_RTR - /* Accept all types of frames */ - .mask_frame_type = 0, -#else - /* Only accept frames with the configured frametype */ - .mask_frame_type = 1, -#endif - .mask_id_mode = ((filter->flags & CAN_FILTER_IDE) != 0) - ? CAN_ID_MODE_EXTENDED - : CAN_ID_MODE_STANDARD}, - .destination = {.fifo_select_flags = CANFD_RX_FIFO_0}}; - - if (data->common.started) { - /* These steps help update AFL rules while CAN module running */ - canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_ctrl; - R_CANFD_Type *reg = p_ctrl->p_reg; - - /* Unlock AFL entry access */ - reg->CFDGAFLECTR_b.AFLDAE = true; - - /** set AFL page number */ - if (channel == CAN_RENESAS_RZ_CHN1) { - reg->CFDGAFLECTR_b.AFLPN = - (CANFD_CFG_AFL_CH0_RULE_NUM + afl_offset) / RULE_NUM_PER_PAGE; - } else { - reg->CFDGAFLECTR_b.AFLPN = afl_offset / RULE_NUM_PER_PAGE; - } - - reg->CFDGAFL[afl_offset % RULE_NUM_PER_PAGE] = *(R_CANFD_CFDGAFL_Type *)afl; - - reg->CFDGAFL[afl_offset % RULE_NUM_PER_PAGE].P0_b.GAFLIFL0 = - channel & CAN_RENESAS_RZ_CHN1; - /* Lock AFL entry access */ - reg->CFDGAFLECTR_b.AFLDAE = false; - } -} - -static void remove_afl_rule(const struct device *dev, uint32_t afl_offset) -{ - struct can_renesas_rz_data *data = dev->data; - uint32_t channel = data->fsp_cfg->channel; - canfd_extended_cfg_t const *p_extend = data->fsp_cfg->p_extend; - canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset]; - - /* Set the AFL ID to reserved ID */ - *afl = (canfd_afl_entry_t){ - .id = {.id = CAN_RENESAS_RZ_RESERVED_ID, .id_mode = CAN_ID_MODE_EXTENDED}, - .mask = {.mask_id = CAN_RENESAS_RZ_RESERVED_ID, - .mask_id_mode = CAN_ID_MODE_EXTENDED}}; - - if (data->common.started) { - /* These steps help update AFL rules while CAN module running */ - canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_ctrl; - R_CANFD_Type *reg = p_ctrl->p_reg; - - /* Unlock AFL entry access */ - reg->CFDGAFLECTR_b.AFLDAE = true; - - /** set AFL page number */ - if (channel == CAN_RENESAS_RZ_CHN1) { - reg->CFDGAFLECTR_b.AFLPN = - (CANFD_CFG_AFL_CH0_RULE_NUM + afl_offset) / RULE_NUM_PER_PAGE; - } else { - reg->CFDGAFLECTR_b.AFLPN = afl_offset / RULE_NUM_PER_PAGE; - } - - /* Change configurations for AFL entry */ - reg->CFDGAFL[afl_offset % RULE_NUM_PER_PAGE] = *(R_CANFD_CFDGAFL_Type *)(afl); - reg->CFDGAFL[afl_offset % RULE_NUM_PER_PAGE].P0_b.GAFLIFL0 = - channel & CAN_RENESAS_RZ_CHN1; - - /* Lock AFL entry access */ - reg->CFDGAFLECTR_b.AFLDAE = false; - } -} - -#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE -static int recover_bus(const struct device *dev, k_timeout_t timeout) -{ - struct can_renesas_rz_data *data = dev->data; - canfd_instance_ctrl_t *p_ctrl = data->fsp_ctrl; - R_CANFD_Type *reg = p_ctrl->p_reg; - uint32_t cfdcnctr = reg->CFDC->CTR; - int ret = 0; - - if (reg->CFDC->ERFL_b.BOEF == 0) { - /* Channel bus-off entry not detected */ - return 0; - } - - reg->CFDC->CTR_b.BOM = 0x00; /* Switch to Normal Bus-Off mode (comply with ISO 11898-1) */ - reg->CFDC->CTR_b.RTBO = 1; /* Force channel state to return from bus-off */ - - int64_t start_ticks = k_uptime_ticks(); - - while (reg->CFDC->ERFL_b.BORF == 0) { - if ((k_uptime_ticks() - start_ticks) > timeout.ticks) { - ret = -EAGAIN; - break; - } - } - reg->CFDC->CTR = cfdcnctr; /* Restore channel configuration */ - - return ret; -} -#endif - -static inline void can_renesas_rz_call_tx_cb(const struct device *dev, int err) -{ - struct can_renesas_rz_data *data = dev->data; - can_tx_callback_t cb = data->tx_cb; - - if (cb != NULL) { - data->tx_cb = NULL; - cb(dev, err, data->tx_usr_data); - k_sem_give(&data->tx_sem); - } -} - -static inline void can_renesas_rz_call_rx_cb(const struct device *dev, can_callback_args_t *p_args) -{ - struct can_renesas_rz_data *data = dev->data; - struct can_renesas_rz_filter *rx_filter = data->rx_filter; - const struct can_renesas_rz_cfg *cfg = dev->config; - struct can_frame frame = { - .dlc = can_bytes_to_dlc(p_args->frame.data_length_code), - .id = p_args->frame.id, - .flags = (((p_args->frame.id_mode == CAN_ID_MODE_EXTENDED) ? CAN_FRAME_IDE : 0UL) | - ((p_args->frame.type == CAN_FRAME_TYPE_REMOTE) ? CAN_FRAME_RTR : 0UL) | - ((p_args->frame.options & CANFD_FRAME_OPTION_FD) != 0 ? CAN_FRAME_FDF - : 0UL) | - ((p_args->frame.options & CANFD_FRAME_OPTION_ERROR) != 0 ? CAN_FRAME_ESI - : 0UL) | - ((p_args->frame.options & CANFD_FRAME_OPTION_BRS) != 0 ? CAN_FRAME_BRS - : 0UL)), - }; - - memcpy(frame.data, p_args->frame.data, p_args->frame.data_length_code); - - for (uint32_t i = 0; i < cfg->rx_filter_num; i++) { - can_rx_callback_t cb = rx_filter->rx_cb; - void *usr_data = rx_filter->rx_usr_data; - - if (cb == NULL) { - rx_filter++; - continue; /* this filter has not set yet */ - } - - if (!can_frame_matches_filter(&frame, &rx_filter->filter)) { - rx_filter++; - continue; /* filter did not match */ - } - - cb(dev, &frame, usr_data); - break; - } -} - -static inline void can_renesas_rz_call_state_change_cb(const struct device *dev, - enum can_state state) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - can_info_t can_info; - - if (FSP_SUCCESS != cfg->fsp_api->infoGet(data->fsp_ctrl, &can_info)) { - LOG_DBG("get state info failed"); - return; - } - - struct can_bus_err_cnt err_cnt = { - .rx_err_cnt = can_info.error_count_receive, - .tx_err_cnt = can_info.error_count_transmit, - }; - - data->common.state_change_cb(dev, state, err_cnt, data->common.state_change_cb_user_data); -} - -static int can_renesas_rz_get_capabilities(const struct device *dev, can_mode_t *cap) -{ - ARG_UNUSED(dev); - *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK; - -#ifdef CONFIG_CAN_FD_MODE - *cap |= CAN_MODE_FD; -#endif - -#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE - *cap |= CAN_MODE_MANUAL_RECOVERY; -#endif - - return 0; -} - -static int can_renesas_rz_start(const struct device *dev) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - - const struct device *transceiver_dev = can_get_transceiver(dev); - int ret = 0; - - if (!device_is_ready(dev)) { - return -EIO; - } - - if (data->common.started) { - return -EALREADY; - } - - if ((transceiver_dev != NULL) && - can_transceiver_enable(transceiver_dev, data->common.mode)) { - LOG_DBG("CAN transceiver enable failed"); - return -EIO; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - canfd_extended_cfg_t *p_extend = (canfd_extended_cfg_t *)data->fsp_cfg->p_extend; - - p_extend->p_data_timing = - (can_bit_timing_cfg_t *)((data->common.mode & CAN_MODE_FD) != 0 - ? &data->data_timing - : &classic_can_data_timing_default); - if (FSP_SUCCESS != cfg->fsp_api->close(data->fsp_ctrl)) { - LOG_DBG("CAN close failed"); - ret = -EIO; - goto end; - } - - if (FSP_SUCCESS != cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg)) { - LOG_DBG("CAN open failed"); - ret = -EIO; - goto end; - } - - if ((data->common.mode & CAN_MODE_LOOPBACK) != 0) { - if (FSP_SUCCESS != cfg->fsp_api->modeTransition(data->fsp_ctrl, - CAN_OPERATION_MODE_NORMAL, - CAN_TEST_MODE_LOOPBACK_INTERNAL)) { - LOG_DBG("CAN mode change failed"); - ret = -EIO; - goto end; - } - } - - data->common.started = true; -end: - k_mutex_unlock(&data->inst_mutex); - return ret; -} - -static int can_renesas_rz_stop(const struct device *dev) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - const struct device *transceiver_dev = can_get_transceiver(dev); - int ret = 0; - - /** START body of stop function */ - if (!data->common.started) { - return -EALREADY; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - if (FSP_SUCCESS != cfg->fsp_api->modeTransition(data->fsp_ctrl, CAN_OPERATION_MODE_HALT, - CAN_TEST_MODE_DISABLED)) { - LOG_DBG("CAN stop failed"); - ret = -EIO; - goto end; - } - - if (((transceiver_dev != NULL) && can_transceiver_disable(transceiver_dev))) { - LOG_DBG("CAN transceiver disable failed"); - ret = -EIO; - goto end; - } - - if (data->tx_cb != NULL) { - data->tx_cb = NULL; - k_sem_give(&data->tx_sem); - } - - data->common.started = false; - -end: - k_mutex_unlock(&data->inst_mutex); - return ret; -} - -static int can_renesas_rz_set_mode(const struct device *dev, can_mode_t mode) -{ - struct can_renesas_rz_data *data = dev->data; - int ret = 0; - - if (data->common.started) { - /* CAN controller should be in stopped state */ - return -EBUSY; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - can_mode_t caps = 0; - - ret = can_renesas_rz_get_capabilities(dev, &caps); - if (ret != 0) { - goto end; - } - - if ((mode & ~caps) != 0) { - ret = -ENOTSUP; - goto end; - } - - data->common.mode = mode; - -end: - k_mutex_unlock(&data->inst_mutex); - return ret; -} - -static int can_renesas_rz_set_timing(const struct device *dev, const struct can_timing *timing) -{ - struct can_renesas_rz_data *data = dev->data; - - if (data->common.started) { - /* Device is not in stopped state */ - return -EBUSY; - } - - return set_hw_timing_configuration(dev, data->fsp_cfg->p_bit_timing, timing); -} - -static int can_renesas_rz_send(const struct device *dev, const struct can_frame *frame, - k_timeout_t timeout, can_tx_callback_t callback, void *user_data) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - - if (!data->common.started) { - return -ENETDOWN; - } - if ((data->common.mode & CAN_MODE_FD) != 0) { - if (frame->dlc > CANFD_MAX_DLC) { - return -EINVAL; - } - if ((frame->flags & CAN_FRAME_ESI) != 0) { - return -ENOTSUP; - } - } else { - if ((frame->flags & CAN_FRAME_FDF) != 0) { - return -ENOTSUP; - } - if (frame->dlc > CAN_MAX_DLC) { - return -EINVAL; - } - } - - if (k_sem_take(&data->tx_sem, timeout) != 0) { - return -EAGAIN; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - int ret = 0; - - data->tx_cb = callback; - data->tx_usr_data = user_data; - - can_frame_t fsp_frame = { - .id = frame->id, - .id_mode = ((frame->flags & CAN_FRAME_IDE) != 0) ? CAN_ID_MODE_EXTENDED - : CAN_ID_MODE_STANDARD, - .type = ((frame->flags & CAN_FRAME_RTR) != 0) ? CAN_FRAME_TYPE_REMOTE - : CAN_FRAME_TYPE_DATA, - .data_length_code = can_dlc_to_bytes(frame->dlc), - .options = - ((((frame->flags & CAN_FRAME_FDF) != 0) ? CANFD_FRAME_OPTION_FD : 0UL) | - (((frame->flags & CAN_FRAME_BRS) != 0) ? CANFD_FRAME_OPTION_BRS : 0UL) | - (((frame->flags & CAN_FRAME_ESI) != 0) ? CANFD_FRAME_OPTION_ERROR : 0UL)), - }; - memcpy(fsp_frame.data, frame->data, fsp_frame.data_length_code); - - if (FSP_SUCCESS != cfg->fsp_api->write(data->fsp_ctrl, CANFD_TX_MB_0, &fsp_frame)) { - LOG_DBG("CAN transmit failed"); - data->tx_cb = NULL; - data->tx_usr_data = NULL; - k_sem_give(&data->tx_sem); - ret = -EIO; - } - - k_mutex_unlock(&data->inst_mutex); - return ret; -} - -static int can_renesas_rz_add_rx_filter(const struct device *dev, can_rx_callback_t callback, - void *user_data, const struct can_filter *filter) -{ - struct can_renesas_rz_data *data = dev->data; - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - int filter_id = get_free_filter_id(dev); - - if (filter_id == -ENOSPC) { - goto end; - } - - set_afl_rule(dev, filter, filter_id); - - memcpy(&data->rx_filter[filter_id].filter, filter, sizeof(struct can_filter)); - data->rx_filter[filter_id].rx_cb = callback; - data->rx_filter[filter_id].rx_usr_data = user_data; - data->rx_filter[filter_id].set = true; - -end: - k_mutex_unlock(&data->inst_mutex); - - return filter_id; -} - -static void can_renesas_rz_remove_rx_filter(const struct device *dev, int filter_id) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - - if ((filter_id < 0) || (filter_id >= cfg->rx_filter_num)) { - return; - } - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - remove_afl_rule(dev, filter_id); - - data->rx_filter[filter_id].rx_cb = NULL; - data->rx_filter[filter_id].rx_usr_data = NULL; - data->rx_filter[filter_id].set = false; - - k_mutex_unlock(&data->inst_mutex); -} - -#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE -static int can_renesas_rz_recover(const struct device *dev, k_timeout_t timeout) -{ - struct can_renesas_rz_data *data = dev->data; - - if (!data->common.started) { - return -ENETDOWN; - } - - if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0) { - return -ENOTSUP; - } - - return recover_bus(dev, timeout); -} -#endif - -static int can_renesas_rz_get_state(const struct device *dev, enum can_state *state, - struct can_bus_err_cnt *err_cnt) -{ - struct can_renesas_rz_data *data = dev->data; - const struct can_renesas_rz_cfg *cfg = dev->config; - - if (!data->common.started) { - if (state != NULL) { - *state = CAN_STATE_STOPPED; - } - } else { - can_info_t fsp_info = {0}; - - if (FSP_SUCCESS != cfg->fsp_api->infoGet(data->fsp_ctrl, &fsp_info)) { - LOG_DBG("CAN get state info failed"); - return -EIO; - } - - if (err_cnt != NULL) { - err_cnt->tx_err_cnt = fsp_info.error_count_transmit; - err_cnt->rx_err_cnt = fsp_info.error_count_receive; - } - - if (state != NULL) { - if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) { - *state = CAN_STATE_BUS_OFF; - } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) { - *state = CAN_STATE_ERROR_PASSIVE; - } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) { - *state = CAN_STATE_ERROR_WARNING; - } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) { - *state = CAN_STATE_ERROR_ACTIVE; - } - } - } - - return 0; -} - -static void can_renesas_rz_set_state_change_callback(const struct device *dev, - can_state_change_callback_t callback, - void *user_data) -{ - struct can_renesas_rz_data *data = dev->data; - canfd_instance_ctrl_t *p_ctrl = data->fsp_ctrl; - int key = irq_lock(); - - k_mutex_lock(&data->inst_mutex, K_FOREVER); - - if (callback != NULL) { - /* Enable state change interrupt */ - p_ctrl->p_reg->CFDC->CTR |= (uint32_t)CANFD_CFG_ERR_IRQ; - } else { - /* Disable state change interrupt */ - p_ctrl->p_reg->CFDC->CTR &= (uint32_t)~CANFD_CFG_ERR_IRQ; - - /* Clear state change interrupt flags */ - p_ctrl->p_reg->CFDC->ERFL &= - ~(BIT(R_CANFD_CFDC_ERFL_BOEF_Pos) | BIT(R_CANFD_CFDC_ERFL_EWF_Pos) | - BIT(R_CANFD_CFDC_ERFL_EPF_Pos) | BIT(R_CANFD_CFDC_ERFL_BOEF_Pos)); - } - - data->common.state_change_cb = callback; - data->common.state_change_cb_user_data = user_data; - - k_mutex_unlock(&data->inst_mutex); - - irq_unlock(key); -} - -static int can_renesas_rz_get_core_clock(const struct device *dev, uint32_t *rate) -{ - const struct can_renesas_rz_cfg *cfg = dev->config; - int ret = 0; - - if (cfg->clock_ext_rate) { - *rate = cfg->clock_ext_rate; - } else { - uint32_t canfd_pclk = 0; - - ret = clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &canfd_pclk); - - if (ret < 0) { - return ret; - } - - *rate = canfd_pclk / 2; - } - - return ret; -} - -static int can_renesas_rz_get_max_filters(const struct device *dev, bool ide) -{ - ARG_UNUSED(ide); - const struct can_renesas_rz_cfg *cfg = dev->config; - - return cfg->rx_filter_num; -} - -#ifdef CONFIG_CAN_FD_MODE -static int can_renesas_rz_set_timing_data(const struct device *dev, - const struct can_timing *timing_data) -{ - struct can_renesas_rz_data *data = dev->data; - - if (data->common.started) { - return -EBUSY; - } - - return set_hw_timing_configuration(dev, &data->data_timing, timing_data); -} -#endif /* CONFIG_CAN_FD_MODE */ - -void can_renesas_rz_fsp_cb(can_callback_args_t *p_args) -{ - const struct device *dev = p_args->p_context; - - switch (p_args->event) { - case CAN_EVENT_RX_COMPLETE: { - can_renesas_rz_call_rx_cb(dev, p_args); - break; - } - - case CAN_EVENT_TX_COMPLETE: { - can_renesas_rz_call_tx_cb(dev, 0); - break; - } - - case CAN_EVENT_ERR_CHANNEL: { - if ((p_args->error & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) { - can_renesas_rz_call_state_change_cb(dev, CAN_STATE_ERROR_ACTIVE); - } - if ((p_args->error & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) { - can_renesas_rz_call_state_change_cb(dev, CAN_STATE_ERROR_WARNING); - } - if ((p_args->error & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) { - can_renesas_rz_call_state_change_cb(dev, CAN_STATE_ERROR_PASSIVE); - } - if ((p_args->error & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) { - can_renesas_rz_call_state_change_cb(dev, CAN_STATE_BUS_OFF); - } - - if ((p_args->error & R_CANFD_CFDC_ERFL_ALF_Msk) != 0) { /* Arbitration Lost Error */ - can_renesas_rz_call_tx_cb(dev, -EBUSY); - } - if ((p_args->error & (R_CANFD_CFDC_ERFL_AERR_Msk | /* ACK Error */ - R_CANFD_CFDC_ERFL_ADERR_Msk | /* ACK Delimiter Error */ - R_CANFD_CFDC_ERFL_B1ERR_Msk | /* Bit 1 Error */ - R_CANFD_CFDC_ERFL_B0ERR_Msk)) /* Bit 0 Error */ - != 0) { - can_renesas_rz_call_tx_cb(dev, -EIO); - } - } - - default: - break; - } -} - -static inline int can_renesas_rz_apply_default_config(const struct device *dev) -{ - struct can_renesas_rz_cfg *cfg = (struct can_renesas_rz_cfg *)dev->config; - int ret; - struct can_timing timing = {0}; - - ret = can_calc_timing(dev, &timing, cfg->common.bitrate, cfg->common.sample_point); - - if (ret < 0) { - return ret; - } - - ret = can_renesas_rz_set_timing(dev, &timing); - if (ret != 0) { - return ret; - } -#ifdef CONFIG_CAN_FD_MODE - can_calc_timing_data(dev, &timing, cfg->common.bitrate_data, cfg->common.sample_point_data); - - ret = can_renesas_rz_set_timing_data(dev, &timing); - if (ret < 0) { - return ret; - } -#endif - for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) { - remove_afl_rule(dev, filter_id); - } - - return 0; -} - -static int can_renesas_rz_init(const struct device *dev) -{ - const struct can_renesas_rz_cfg *cfg = dev->config; - struct can_renesas_rz_data *data = dev->data; - canfd_extended_cfg_t *p_extend = (canfd_extended_cfg_t *)data->fsp_cfg->p_extend; - int ret = 0; - - k_mutex_init(&data->inst_mutex); - k_sem_init(&data->tx_sem, 1, 1); - data->common.started = false; - - /* Check external clock is used */ - if (cfg->clock_ext_rate) { - p_extend->p_global_cfg->global_config |= R_CANFD_CFDGCFG_DCS_Msk; - } - - /* Configure dt provided device signals when available */ - ret = pinctrl_apply_state(cfg->pin_config, PINCTRL_STATE_DEFAULT); - if (ret) { - LOG_ERR("pin function initial failed"); - return ret; - } - - /* Apply config and setting for CAN controller HW */ - ret = can_renesas_rz_apply_default_config(dev); - if (ret) { - LOG_ERR("invalid default configuration"); - return ret; - } - - ret = cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); - if (ret != FSP_SUCCESS) { - LOG_ERR("CAN bus initialize failed"); - return -EIO; - } - - /* Put CAN controller into stopped state */ - ret = cfg->fsp_api->modeTransition(data->fsp_ctrl, CAN_OPERATION_MODE_HALT, - CAN_TEST_MODE_DISABLED); - if (ret != FSP_SUCCESS) { - cfg->fsp_api->close(data->fsp_ctrl); - LOG_ERR("CAN stop failed"); - return -EIO; - } - - return 0; -} - -static DEVICE_API(can, can_renesas_rz_driver_api) = { - .get_capabilities = can_renesas_rz_get_capabilities, - .start = can_renesas_rz_start, - .stop = can_renesas_rz_stop, - .set_mode = can_renesas_rz_set_mode, - .set_timing = can_renesas_rz_set_timing, - .send = can_renesas_rz_send, - .add_rx_filter = can_renesas_rz_add_rx_filter, - .remove_rx_filter = can_renesas_rz_remove_rx_filter, -#if defined(CONFIG_CAN_MANUAL_RECOVERY_MODE) - .recover = can_renesas_rz_recover, -#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ - .get_state = can_renesas_rz_get_state, - .set_state_change_callback = can_renesas_rz_set_state_change_callback, - .get_core_clock = can_renesas_rz_get_core_clock, - .get_max_filters = can_renesas_rz_get_max_filters, - .timing_min = CAN_RENESAS_RZ_TIMING_MIN, - .timing_max = CAN_RENESAS_RZ_TIMING_MAX, -#if defined(CONFIG_CAN_FD_MODE) - .set_timing_data = can_renesas_rz_set_timing_data, - .timing_data_min = CAN_RENESAS_RZ_TIMING_DATA_MIN, - .timing_data_max = CAN_RENESAS_RZ_TIMING_DATA_MAX, -#endif /* CONFIG_CAN_FD_MODE */ -}; - -#define CAN_RENESAS_RZ_GLOBAL_IRQ_INIT() \ - IRQ_CONNECT(DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_err, \ - irq), \ - DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_err, \ - priority), \ - canfd_error_isr, NULL, 0); \ - IRQ_CONNECT(DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_recc, \ - irq), \ - DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_recc, \ - priority), \ - canfd_rx_fifo_isr, NULL, 0); \ - irq_enable(DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_err, \ - irq)); \ - irq_enable(DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_recc, \ - irq)); - -static int can_renesas_rz_global_init(const struct device *dev) -{ - CAN_RENESAS_RZ_GLOBAL_IRQ_INIT(); - - return 0; -} - -DEVICE_DT_DEFINE(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), can_renesas_rz_global_init, - NULL, NULL, NULL, PRE_KERNEL_2, CONFIG_CAN_INIT_PRIORITY, NULL) - -#define CAN_RENESAS_RZ_CHANNEL_IRQ_INIT(index) \ - { \ - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, ch_rec, irq), \ - DT_INST_IRQ_BY_NAME(index, ch_rec, priority), canfd_rx_fifo_isr, NULL, \ - 0); \ - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, ch_trx, irq), \ - DT_INST_IRQ_BY_NAME(index, ch_trx, priority), canfd_channel_tx_isr, \ - NULL, 0); \ - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, ch_err, irq), \ - DT_INST_IRQ_BY_NAME(index, ch_err, priority), canfd_error_isr, NULL, \ - 0); \ - \ - irq_enable(DT_INST_IRQ_BY_NAME(index, ch_rec, irq)); \ - irq_enable(DT_INST_IRQ_BY_NAME(index, ch_trx, irq)); \ - irq_enable(DT_INST_IRQ_BY_NAME(index, ch_err, irq)); \ - } - -#define CAN_RENESAS_RZG_INIT(index) \ - PINCTRL_DT_INST_DEFINE(index); \ - static canfd_global_cfg_t g_canfd_global_cfg = { \ - .global_interrupts = CANFD_CFG_GLOBAL_ERR_SOURCES, \ - .global_config = (CANFD_CFG_TX_PRIORITY | CANFD_CFG_DLC_CHECK | \ - CANFD_CFD_CLOCK_SOURCE | CANFD_CFG_FD_OVERFLOW), \ - .rx_mb_config = (CANFD_CFG_RXMB_NUMBER | \ - (CANFD_CFG_RXMB_SIZE << R_CANFD_CFDRMNB_RMPLS_Pos)), \ - .global_err_ipl = DT_IRQ_BY_NAME( \ - DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_err, priority), \ - .rx_fifo_ipl = DT_IRQ_BY_NAME( \ - DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_canfd_global), g_recc, priority), \ - .rx_fifo_config = \ - { \ - CANFD_CFG_RXFIFO_DEFAULT(0), \ - CANFD_CFG_RXFIFO_DEFAULT(1), \ - CANFD_CFG_RXFIFO_DEFAULT(2), \ - CANFD_CFG_RXFIFO_DEFAULT(3), \ - CANFD_CFG_RXFIFO_DEFAULT(4), \ - CANFD_CFG_RXFIFO_DEFAULT(5), \ - CANFD_CFG_RXFIFO_DEFAULT(6), \ - CANFD_CFG_RXFIFO_DEFAULT(7), \ - }, \ - }; \ - static canfd_afl_entry_t p_canfd_ch##index##_afl[DT_INST_PROP(index, rx_max_filters)]; \ - struct can_renesas_rz_filter \ - can_renesas_rz_rx_filter##index[DT_INST_PROP(index, rx_max_filters)]; \ - static can_bit_timing_cfg_t g_canfd_ch##index##_bit_timing_cfg; \ - uint32_t clock_subsys##index = DT_INST_CLOCKS_CELL(index, clk_id); \ - static const struct can_renesas_rz_cfg can_renesas_rz_cfg##index = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(index, 0, 8000000), \ - .global_dev = DEVICE_DT_GET(DT_INST_PARENT(index)), \ - .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ - .rx_filter_num = DT_INST_PROP(index, rx_max_filters), \ - .fsp_api = &g_canfd_on_canfd, \ - .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)), \ - .clock_subsys = (clock_control_subsys_t)(&clock_subsys##index), \ - .clock_ext_rate = DT_PROP_OR(DT_NODELABEL(can_clk), clock_frequency, 0), \ - }; \ - static canfd_instance_ctrl_t g_canfd_ch##index##_ctrl; \ - static canfd_extended_cfg_t g_canfd_ch##index##_extern_cfg = { \ - .p_afl = p_canfd_ch##index##_afl, \ - .txmb_txi_enable = CANFD_CFG_TXMB_TXI_ENABLE, \ - .error_interrupts = 0U, \ - .p_global_cfg = &g_canfd_global_cfg, \ - }; \ - static can_cfg_t g_canfd_ch##index##cfg = { \ - .channel = DT_INST_PROP(index, channel), \ - .ipl = DT_INST_IRQ_BY_NAME(index, ch_err, priority), \ - .error_irq = DT_INST_IRQ_BY_NAME(index, ch_err, irq), \ - .rx_irq = DT_INST_IRQ_BY_NAME(index, ch_rec, irq), \ - .tx_irq = DT_INST_IRQ_BY_NAME(index, ch_trx, irq), \ - .p_extend = &g_canfd_ch##index##_extern_cfg, \ - .p_bit_timing = &g_canfd_ch##index##_bit_timing_cfg, \ - .p_context = DEVICE_DT_INST_GET(index), \ - .p_callback = can_renesas_rz_fsp_cb, \ - }; \ - static struct can_renesas_rz_data can_renesas_rz_data##index = { \ - .fsp_ctrl = &g_canfd_ch##index##_ctrl, \ - .fsp_cfg = &g_canfd_ch##index##cfg, \ - .rx_filter = can_renesas_rz_rx_filter##index, \ - }; \ - static int can_renesas_rz_init##index(const struct device *dev) \ - { \ - const struct device *global_canfd = DEVICE_DT_GET(DT_INST_PARENT(index)); \ - if (!device_is_ready(global_canfd)) { \ - return -EIO; \ - } \ - CAN_RENESAS_RZ_CHANNEL_IRQ_INIT(index) \ - return can_renesas_rz_init(dev); \ - } \ - CAN_DEVICE_DT_INST_DEFINE(index, can_renesas_rz_init##index, NULL, \ - &can_renesas_rz_data##index, &can_renesas_rz_cfg##index, \ - POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \ - &can_renesas_rz_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(CAN_RENESAS_RZG_INIT) diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 325ed9d281529..bf2312736db05 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -19,7 +19,6 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_control_mcux_scg_k4.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MSPM0 clock_control_mspm0.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c) @@ -36,9 +35,6 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT clock_control_renesas_rx_root_cgc.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL clock_control_renesas_rx_pll_cgc.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK clock_control_renesas_rx_pclk_cgc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_control_renesas_rz_cpg.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index f528aa2dad327..229a45792e8d9 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -50,8 +50,6 @@ source "drivers/clock_control/Kconfig.mcux_sim" source "drivers/clock_control/Kconfig.mcux_syscon" -source "drivers/clock_control/Kconfig.mspm0" - source "drivers/clock_control/Kconfig.npcm" source "drivers/clock_control/Kconfig.npcx" @@ -90,8 +88,6 @@ source "drivers/clock_control/Kconfig.agilex5" source "drivers/clock_control/Kconfig.renesas_ra_cgc" -source "drivers/clock_control/Kconfig.renesas_rx_cgc" - source "drivers/clock_control/Kconfig.renesas_rz_cpg" source "drivers/clock_control/Kconfig.max32" diff --git a/drivers/clock_control/Kconfig.mspm0 b/drivers/clock_control/Kconfig.mspm0 deleted file mode 100644 index e21e3b305a550..0000000000000 --- a/drivers/clock_control/Kconfig.mspm0 +++ /dev/null @@ -1,11 +0,0 @@ -# TI MSPM0 Family - -# Copyright (c) 2025, Texas Instruments Inc. -# SPDX-License-Identifier: Apache-2.0 - -config CLOCK_CONTROL_MSPM0 - bool "TI MSPM0 clock" - default y - depends on SOC_FAMILY_TI_MSPM0 - help - This option enables the TI MSPM0 Clock Control Enabler diff --git a/drivers/clock_control/Kconfig.nrf b/drivers/clock_control/Kconfig.nrf index 67185497d94ee..0a3c7f652fb13 100644 --- a/drivers/clock_control/Kconfig.nrf +++ b/drivers/clock_control/Kconfig.nrf @@ -32,30 +32,25 @@ choice CLOCK_CONTROL_NRF_SOURCE config CLOCK_CONTROL_NRF_K32SRC_RC bool "RC Oscillator" - select NRFX_CLOCK_LF_SRC_RC if !CLOCK_CONTROL_NRF_FORCE_ALT config CLOCK_CONTROL_NRF_K32SRC_XTAL - bool "Crystal Oscillator" - select NRFX_CLOCK_LF_SRC_XTAL if !CLOCK_CONTROL_NRF_FORCE_ALT select NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED if (!SOC_SERIES_BSIM_NRFXX && \ !CLOCK_CONTROL_NRF_FORCE_ALT) + bool "Crystal Oscillator" config CLOCK_CONTROL_NRF_K32SRC_SYNTH - bool "Synthesized from HFCLK" depends on !SOC_SERIES_NRF91X - select NRFX_CLOCK_LF_SRC_SYNTH if !CLOCK_CONTROL_NRF_FORCE_ALT + bool "Synthesized from HFCLK" config CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING - bool "External low swing" depends on SOC_SERIES_NRF52X select NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED if !CLOCK_CONTROL_NRF_FORCE_ALT - select NRFX_CLOCK_LF_SRC_LOW_SWING if !CLOCK_CONTROL_NRF_FORCE_ALT + bool "External low swing" config CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING - bool "External full swing" depends on SOC_SERIES_NRF52X select NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED if !CLOCK_CONTROL_NRF_FORCE_ALT - select NRFX_CLOCK_LF_SRC_FULL_SWING if !CLOCK_CONTROL_NRF_FORCE_ALT + bool "External full swing" endchoice @@ -63,7 +58,6 @@ config CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION bool "LF clock calibration" depends on !SOC_SERIES_NRF91X && CLOCK_CONTROL_NRF_K32SRC_RC default y if !SOC_NRF53_CPUNET_ENABLE - select NRFX_CLOCK_LF_CAL_ENABLED if !CLOCK_CONTROL_NRF_FORCE_ALT help If calibration is disabled when RC is used for low frequency clock then accuracy of the low frequency clock will degrade. Disable on your own @@ -81,9 +75,9 @@ config CLOCK_CONTROL_NRF_DRIVER_CALIBRATION config CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON bool "LF clock is always on" - default y if NRF_RTC_TIMER || NRF_GRTC_TIMER + default y if NRF_RTC_TIMER help - If RTC or GRTC is used as system timer then LF clock is always on and handling + If RTC is used as system timer then LF clock is always on and handling can be simplified. config CLOCK_CONTROL_NRF_CALIBRATION_PERIOD diff --git a/drivers/clock_control/Kconfig.renesas_rx_cgc b/drivers/clock_control/Kconfig.renesas_rx_cgc deleted file mode 100644 index 21ea76e55f211..0000000000000 --- a/drivers/clock_control/Kconfig.renesas_rx_cgc +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config CLOCK_CONTROL_RENESAS_RX_CGC - bool "RX CGC driver" - default y - depends on SOC_FAMILY_RENESAS_RX - help - Enable support for Renesas RX CGC driver. - -if CLOCK_CONTROL_RENESAS_RX_CGC - -config CLOCK_CONTROL_RENESAS_RX_ROOT - bool "Renesas RX root clock source" - default y - help - Enable Renesas RX root clock - -config CLOCK_CONTROL_RENESAS_RX_PLL - bool "Renesas RX root clock source" - default y - help - Enable Renesas RX PLL - -config CLOCK_CONTROL_RENESAS_RX_PCLK - bool "Renesas RX root clock source" - default y - help - Enable Renesas RX PCLK - -endif diff --git a/drivers/clock_control/clock_control_ifx_cat1.c b/drivers/clock_control/clock_control_ifx_cat1.c index 84ecad2ddaf9c..071eb0e9559d5 100644 --- a/drivers/clock_control/clock_control_ifx_cat1.c +++ b/drivers/clock_control/clock_control_ifx_cat1.c @@ -14,7 +14,7 @@ #include #include -#define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(N), 0)) +#define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(N), 0)) /* Enumeration of enabled in device tree Clock, uses for indexing clock info table */ enum { @@ -126,177 +126,133 @@ enum { INFINEON_CAT1_CLOCK_FLL0, #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) - INFINEON_CAT1_CLOCK_PILO, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) - INFINEON_CAT1_CLOCK_WCO, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) - INFINEON_CAT1_CLOCK_ILO, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf)) - INFINEON_CAT1_CLOCK_LF, -#endif /* Count of enabled clock */ INFINEON_CAT1_ENABLED_CLOCK_COUNT }; /* infineon_cat1_clock_info_name_t */ /* Clock info structure */ struct infineon_cat1_clock_info_t { - union clock_obj { - /* For all clock instance which configure via cyhal, - * we should keep cyhal_clock_t object. - */ - cyhal_clock_t cyhal_clock; /* Hal Clock object */ - - /* For all clklf (in sources keep) information about the - * name (cy_en_clklf_in_sources_t). - */ - cy_en_clklf_in_sources_t clklf_in_source; - } obj; - - uint32_t dt_ord; /* Device tree node's dependency ordinal */ + cyhal_clock_t obj; /* Hal Clock object */ + uint32_t dt_ord; /* Device tree node's dependency ordinal */ }; /* Lookup table which presents clock objects (cyhal_clock_t) correspondence to ordinal * number of device tree clock nodes. */ -static struct infineon_cat1_clock_info_t clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = { -/* We always have IMO */ +static struct infineon_cat1_clock_info_t + clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = { + /* We always have IMO */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo)) - [INFINEON_CAT1_CLOCK_IMO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo))}, + [INFINEON_CAT1_CLOCK_IMO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho)) - [INFINEON_CAT1_CLOCK_IHO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_iho))}, + [INFINEON_CAT1_CLOCK_IHO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_iho)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0)) - [INFINEON_CAT1_CLOCK_PATHMUX0] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux0))}, + [INFINEON_CAT1_CLOCK_PATHMUX0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux0)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1)) - [INFINEON_CAT1_CLOCK_PATHMUX1] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux1))}, + [INFINEON_CAT1_CLOCK_PATHMUX1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux1)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2)) - [INFINEON_CAT1_CLOCK_PATHMUX2] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux2))}, + [INFINEON_CAT1_CLOCK_PATHMUX2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux2)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3)) - [INFINEON_CAT1_CLOCK_PATHMUX3] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux3))}, + [INFINEON_CAT1_CLOCK_PATHMUX3] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux3)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4)) - [INFINEON_CAT1_CLOCK_PATHMUX4] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux4))}, + [INFINEON_CAT1_CLOCK_PATHMUX4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux4)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0)) - [INFINEON_CAT1_CLOCK_HF0] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf0))}, + [INFINEON_CAT1_CLOCK_HF0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf0)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1)) - [INFINEON_CAT1_CLOCK_HF1] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf1))}, + [INFINEON_CAT1_CLOCK_HF1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf1)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2)) - [INFINEON_CAT1_CLOCK_HF2] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf2))}, + [INFINEON_CAT1_CLOCK_HF2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf2)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3)) - [INFINEON_CAT1_CLOCK_HF3] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf3))}, + [INFINEON_CAT1_CLOCK_HF3] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf3)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4)) - [INFINEON_CAT1_CLOCK_HF4] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf4))}, + [INFINEON_CAT1_CLOCK_HF4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf4)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5)) - [INFINEON_CAT1_CLOCK_HF5] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf5))}, + [INFINEON_CAT1_CLOCK_HF5] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf5)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6)) - [INFINEON_CAT1_CLOCK_HF6] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf6))}, + [INFINEON_CAT1_CLOCK_HF6] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf6)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7)) - [INFINEON_CAT1_CLOCK_HF7] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf7))}, + [INFINEON_CAT1_CLOCK_HF7] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf7)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8)) - [INFINEON_CAT1_CLOCK_HF8] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf8))}, + [INFINEON_CAT1_CLOCK_HF8] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf8)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9)) - [INFINEON_CAT1_CLOCK_HF9] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf9))}, + [INFINEON_CAT1_CLOCK_HF9] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf9)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10)) - [INFINEON_CAT1_CLOCK_HF10] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf10))}, + [INFINEON_CAT1_CLOCK_HF10] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf10)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11)) - [INFINEON_CAT1_CLOCK_HF11] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf11))}, + [INFINEON_CAT1_CLOCK_HF11] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf11)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12)) - [INFINEON_CAT1_CLOCK_HF12] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf12))}, + [INFINEON_CAT1_CLOCK_HF12] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf12)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13)) - [INFINEON_CAT1_CLOCK_HF13] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf13))}, + [INFINEON_CAT1_CLOCK_HF13] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf13)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast)) - [INFINEON_CAT1_CLOCK_FAST] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_fast))}, + [INFINEON_CAT1_CLOCK_FAST] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_fast)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow)) - [INFINEON_CAT1_CLOCK_SLOW] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_slow))}, + [INFINEON_CAT1_CLOCK_SLOW] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_slow)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri)) - [INFINEON_CAT1_CLOCK_PERI] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_peri))}, + [INFINEON_CAT1_CLOCK_PERI] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_peri)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0)) - [INFINEON_CAT1_CLOCK_PLL0] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(pll0))}, + [INFINEON_CAT1_CLOCK_PLL0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll0)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1)) - [INFINEON_CAT1_CLOCK_PLL1] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(pll1))}, + [INFINEON_CAT1_CLOCK_PLL1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll1)) }, #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0)) - [INFINEON_CAT1_CLOCK_FLL0] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(fll0))}, + [INFINEON_CAT1_CLOCK_FLL0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(fll0)) }, #endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) - [INFINEON_CAT1_CLOCK_PILO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_pilo)), - .obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_PILO}, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) - [INFINEON_CAT1_CLOCK_WCO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_wco)), - .obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_WCO}, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) - [INFINEON_CAT1_CLOCK_ILO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_ilo)), - .obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_ILO}, -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf)) - [INFINEON_CAT1_CLOCK_LF] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_lf))}, -#endif - }; -static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj, cyhal_clock_t *clock_source_obj, +static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj, + cyhal_clock_t *clock_source_obj, const cyhal_clock_t *reserve_obj) { cy_rslt_t rslt; @@ -312,8 +268,10 @@ static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj, cyhal_clock_t *cl return rslt; } -static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj, cyhal_clock_t *clock_source_obj, - const cyhal_clock_t *reserve_obj, uint32_t clock_div) +static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj, + cyhal_clock_t *clock_source_obj, + const cyhal_clock_t *reserve_obj, + uint32_t clock_div) { cy_rslt_t rslt; @@ -361,30 +319,14 @@ static cyhal_clock_t *_get_hal_obj_from_ord(uint32_t dt_ord) for (uint32_t i = 0u; i < INFINEON_CAT1_ENABLED_CLOCK_COUNT; i++) { if (clock_info_table[i].dt_ord == dt_ord) { - ret_obj = &clock_info_table[i].obj.cyhal_clock; + ret_obj = &clock_info_table[i].obj; return ret_obj; } } return ret_obj; } -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf)) -static cy_en_clklf_in_sources_t _get_clklf_source_from_ord(uint32_t dt_ord) -{ - cy_en_clklf_in_sources_t ret_clklf_in_source = CY_SYSCLK_CLKLF_IN_ILO; - - for (uint32_t i = 0u; i < INFINEON_CAT1_ENABLED_CLOCK_COUNT; i++) { - if (clock_info_table[i].dt_ord == dt_ord) { - return clock_info_table[i].obj.clklf_in_source; - } - } - return ret_clklf_in_source; -} -#endif - -#define CY_CFG_SYSCLK_PLL_ERROR 3 -#define CY_CFG_SYSCLK_WCO_ERROR 2 - +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) __WEAK void cycfg_ClockStartupError(uint32_t error) { (void)error; /* Suppress the compiler warning */ @@ -392,9 +334,10 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) } } -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) void Cy_SysClk_Dpll_Hp0_Init(void) { +#define CY_CFG_SYSCLK_PLL_ERROR 3 + static cy_stc_dpll_hp_config_t srss_0_clock_0_pll500m_0_hp_pllConfig = { .pDiv = 0, .nDiv = 15, @@ -434,43 +377,7 @@ void Cy_SysClk_Dpll_Hp0_Init(void) cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); } } -#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) */ - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) -static inline void Cy_SysClk_PiloInit(void) -{ - Cy_SysClk_PiloEnable(); - - if (!Cy_SysClk_PiloOkay()) { - Cy_SysPm_TriggerXRes(); - } -} -#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) */ - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) -#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT5 -#define CY_CFG_SYSCLK_WCO_IN_PIN 0U -#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT5 -#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U - -static inline void Cy_SysClk_WcoInit(void) -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT5, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT5, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) */ - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) -static inline void Cy_SysClk_IloInit(void) -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) */ +#endif static int clock_control_infineon_cat1_init(const struct device *dev) { @@ -484,25 +391,25 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure IMO */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj; if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IMO)) { return -EIO; } #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj; if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IHO)) { return -EIO; } #endif -#if !DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo)) && \ +#if !DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo)) && \ !DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho)) -#error "IMO clock or IHO clock must be enabled" + #error "IMO clock or IHO clock must be enabled" #endif /* Configure the PathMux[0] to source defined in tree device 'path_mux0' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux0)); if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[0])) { @@ -512,7 +419,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the PathMux[1] to source defined in tree device 'path_mux1' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux1)); if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[1])) { @@ -522,7 +429,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the PathMux[2] to source defined in tree device 'path_mux2' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux2)); if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[2])) { @@ -532,7 +439,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the PathMux[3] to source defined in tree device 'path_mux3' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux3)); if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[3])) { @@ -542,7 +449,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the PathMux[4] to source defined in tree device 'path_mux4' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux4)); if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[4])) { @@ -552,7 +459,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure FLL0 */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj; frequency = DT_PROP(DT_NODELABEL(fll0), clock_frequency); rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj, @@ -564,7 +471,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure PLL0 */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj; frequency = DT_PROP(DT_NODELABEL(pll0), clock_frequency); rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj, @@ -577,7 +484,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure PLL1 */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj; frequency = DT_PROP(DT_NODELABEL(pll1), clock_frequency); rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj, @@ -589,7 +496,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[0] to source defined in tree device 'clk_hf0' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf0)); clock_div = DT_PROP(DT_NODELABEL(clk_hf0), clock_div); @@ -600,7 +507,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[1] to source defined in tree device 'clk_hf1' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf1)); clock_div = DT_PROP(DT_NODELABEL(clk_hf1), clock_div); @@ -611,7 +518,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[2] to source defined in tree device 'clk_hf2' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf2)); clock_div = DT_PROP(DT_NODELABEL(clk_hf2), clock_div); @@ -622,11 +529,12 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[3] to source defined in tree device 'clk_hf3' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3)); clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div); -#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && defined(CONFIG_USE_INFINEON_ADC) +#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && \ + defined(CONFIG_USE_INFINEON_ADC) Cy_SysClk_ClkHfSetSource(3, CY_SYSCLK_CLKHF_IN_CLKPATH1); Cy_SysClk_ClkHfSetDivider(3, CY_SYSCLK_CLKHF_DIVIDE_BY_2); Cy_SysClk_ClkHfEnable(3); @@ -639,7 +547,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[4] to source defined in tree device 'clk_hf4' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf4)); clock_div = DT_PROP(DT_NODELABEL(clk_hf4), clock_div); @@ -650,7 +558,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[5] to source defined in tree device 'clk_hf5' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf5)); clock_div = DT_PROP(DT_NODELABEL(clk_hf5), clock_div); @@ -661,7 +569,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[6] to source defined in tree device 'clk_hf6' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf6)); clock_div = DT_PROP(DT_NODELABEL(clk_hf6), clock_div); @@ -672,7 +580,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[7] to source defined in tree device 'clk_hf7' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf7)); clock_div = DT_PROP(DT_NODELABEL(clk_hf7), clock_div); @@ -683,7 +591,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[8] to source defined in tree device 'clk_hf8' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf8)); clock_div = DT_PROP(DT_NODELABEL(clk_hf8), clock_div); @@ -694,7 +602,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[9] to source defined in tree device 'clk_hf9' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf9)); clock_div = DT_PROP(DT_NODELABEL(clk_hf9), clock_div); @@ -705,7 +613,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[10] to source defined in tree device 'clk_hf10' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf10)); clock_div = DT_PROP(DT_NODELABEL(clk_hf10), clock_div); @@ -716,7 +624,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[11] to source defined in tree device 'clk_hf11' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf11)); clock_div = DT_PROP(DT_NODELABEL(clk_hf11), clock_div); @@ -727,7 +635,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[12] to source defined in tree device 'clk_hf12' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf12)); clock_div = DT_PROP(DT_NODELABEL(clk_hf12), clock_div); @@ -738,7 +646,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the HF[13] to source defined in tree device 'clk_hf13' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj; clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf13)); clock_div = DT_PROP(DT_NODELABEL(clk_hf13), clock_div); @@ -749,7 +657,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the clock fast to source defined in tree device 'clk_fast' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj; clock_div = DT_PROP(DT_NODELABEL(clk_fast), clock_div); rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_FAST); @@ -763,7 +671,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the clock peri to source defined in tree device 'clk_peri' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj; clock_div = DT_PROP(DT_NODELABEL(clk_peri), clock_div); rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_PERI); @@ -777,7 +685,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev) /* Configure the clock slow to source defined in tree device 'clk_slow' node */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow)) - clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj.cyhal_clock; + clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj; clock_div = DT_PROP(DT_NODELABEL(clk_slow), clock_div); rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_SLOW); @@ -794,27 +702,11 @@ static int clock_control_infineon_cat1_init(const struct device *dev) SystemCoreClockUpdate(); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) - Cy_SysClk_PiloInit(); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) - Cy_SysClk_WcoInit(); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) - Cy_SysClk_IloInit(); -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf)) - /* set ClkLf source (PILO, ILO, WCO) */ - Cy_SysClk_ClkLfSetSource(_get_clklf_source_from_ord(GET_CLK_SOURCE_ORD(clk_lf))); -#endif - - return (int)rslt; + return (int) rslt; } -static int clock_control_infineon_cat_on_off(const struct device *dev, clock_control_subsys_t sys) +static int clock_control_infineon_cat_on_off(const struct device *dev, + clock_control_subsys_t sys) { ARG_UNUSED(dev); ARG_UNUSED(sys); diff --git a/drivers/clock_control/clock_control_max32.c b/drivers/clock_control/clock_control_max32.c index 32ddebb0c8102..396701834abe6 100644 --- a/drivers/clock_control/clock_control_max32.c +++ b/drivers/clock_control/clock_control_max32.c @@ -85,9 +85,6 @@ static int api_get_rate(const struct device *dev, clock_control_subsys_t clkcfg, case ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8: *rate = ADI_MAX32_CLK_IBRO_FREQ / 8; break; - case ADI_MAX32_PRPH_CLK_SRC_IPLL: - *rate = ADI_MAX32_CLK_IPLL_FREQ; - break; default: *rate = 0U; /* Invalid parameters */ @@ -133,10 +130,6 @@ static void setup_fixed_clocks(void) MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_ERTCO); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ipll)) - MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_IPLL); -#endif - /* Some device does not support external clock */ #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_extclk), fixed_clock, okay) MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_EXTCLK); diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 6cc104d37167f..5ae8d71d979df 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -296,11 +296,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, #ifdef CONFIG_PTP_CLOCK_NXP_ENET case IMX_CCM_ENET_PLL: -#if defined(CONFIG_SOC_SERIES_IMXRT10XX) - *rate = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); -#else *rate = CLOCK_GetPllFreq(kCLOCK_PllEnet); -#endif break; #endif diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index c8182c79a9757..ef0c83d314182 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -525,11 +525,6 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de #endif /* defined(CONFIG_UART_MCUX_LPUART) */ #if (defined(CONFIG_I2C_MCUX_LPI2C) && CONFIG_SOC_SERIES_MCXA) -#if (defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT == 1)) - case MCUX_LPI2C0_CLK: - *rate = CLOCK_GetLpi2cClkFreq(); - break; -#else case MCUX_LPI2C0_CLK: *rate = CLOCK_GetLpi2cClkFreq(0); break; @@ -542,7 +537,6 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de case MCUX_LPI2C3_CLK: *rate = CLOCK_GetLpi2cClkFreq(3); break; -#endif /* defined(FSL_FEATURE_SOC_LPI2C_COUNT) */ #endif /* defined(CONFIG_I2C_MCUX_LPI2C) */ #if defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) diff --git a/drivers/clock_control/clock_control_mspm0.c b/drivers/clock_control/clock_control_mspm0.c deleted file mode 100644 index 9caa2be386f4e..0000000000000 --- a/drivers/clock_control/clock_control_mspm0.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments - * Copyright (c) 2025 Linumiz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include -#include - -#define MSPM0_ULPCLK_DIV COND_CODE_1( \ - DT_NODE_HAS_PROP(DT_NODELABEL(ulpclk), clk_div), \ - (CONCAT(DL_SYSCTL_ULPCLK_DIV_, \ - DT_PROP(DT_NODELABEL(ulpclk), clk_div))), \ - (0)) - -#define MSPM0_MCLK_DIV COND_CODE_1( \ - DT_NODE_HAS_PROP(DT_NODELABEL(mclk), clk_div), \ - (CONCAT(DL_SYSCTL_MCLK_DIVIDER_, \ - DT_PROP(DT_NODELABEL(mclk), clk_div))), \ - (0)) - -#define MSPM0_MFPCLK_DIV COND_CODE_1( \ - DT_NODE_HAS_PROP(DT_NODELABEL(mfpclk), clk_div), \ - (CONCAT(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_, \ - DT_PROP(DT_NODELABEL(mfpclk), clk_div))), \ - (0)) - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(mfpclk), okay) -#define MSPM0_MFPCLK_ENABLED 1 -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) -#define MSPM0_PLL_ENABLED 1 -#endif - -#define DT_MCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(mclk)) -#define DT_LFCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(lfclk)) -#define DT_HSCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(hsclk)) -#define DT_HFCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(hfclk)) -#define DT_MFPCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(mfpclk)) -#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) - -struct mspm0_clk_cfg { - uint32_t clk_div; - uint32_t clk_freq; -}; - -static struct mspm0_clk_cfg mspm0_lfclk_cfg = { - .clk_freq = DT_PROP(DT_NODELABEL(lfclk), clock_frequency), -}; - -static struct mspm0_clk_cfg mspm0_ulpclk_cfg = { - .clk_freq = DT_PROP(DT_NODELABEL(ulpclk), clock_frequency), - .clk_div = MSPM0_ULPCLK_DIV, -}; - -static struct mspm0_clk_cfg mspm0_mclk_cfg = { - .clk_freq = DT_PROP(DT_NODELABEL(mclk), clock_frequency), - .clk_div = MSPM0_MCLK_DIV, -}; - -#if MSPM0_MFPCLK_ENABLED -static struct mspm0_clk_cfg mspm0_mfpclk_cfg = { - .clk_freq = DT_PROP(DT_NODELABEL(mfpclk), clock_frequency), - .clk_div = MSPM0_MFPCLK_DIV, -}; -#endif - -#if MSPM0_PLL_ENABLED -/* basic checks of the devicetree to follow */ -#if (DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div) && \ - DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div)) -#error "Only CLK2X or CLK0 can be enabled at a time on the PLL" -#endif - -static DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll = { - .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ, - .sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X, - .sysPLLRef = DL_SYSCTL_SYSPLL_REF_SYSOSC, - .rDivClk2x = (DT_PROP_OR(DT_NODELABEL(pll), clk2x_div, 1) - 1), - .rDivClk1 = (DT_PROP_OR(DT_NODELABEL(pll), clk1_div, 1) - 1), - .rDivClk0 = (DT_PROP_OR(DT_NODELABEL(pll), clk0_div, 1) - 1), - .qDiv = (DT_PROP(DT_NODELABEL(pll), q_div) - 1), - .pDiv = CONCAT(DL_SYSCTL_SYSPLL_PDIV_, - DT_PROP(DT_NODELABEL(pll), p_div)), - .enableCLK2x = COND_CODE_1( - DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div), - (DL_SYSCTL_SYSPLL_CLK2X_ENABLE), - (DL_SYSCTL_SYSPLL_CLK2X_DISABLE)), - .enableCLK1 = COND_CODE_1( - DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk1_div), - (DL_SYSCTL_SYSPLL_CLK1_ENABLE), - (DL_SYSCTL_SYSPLL_CLK1_DISABLE)), - .enableCLK0 = COND_CODE_1( - DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div), - (DL_SYSCTL_SYSPLL_CLK0_ENABLE), - (DL_SYSCTL_SYSPLL_CLK0_DISABLE)), -}; -#endif - -static int clock_mspm0_on(const struct device *dev, clock_control_subsys_t sys) -{ - return 0; -} - -static int clock_mspm0_off(const struct device *dev, clock_control_subsys_t sys) -{ - return 0; -} - -static int clock_mspm0_get_rate(const struct device *dev, - clock_control_subsys_t sys, - uint32_t *rate) -{ - struct mspm0_sys_clock *sys_clock = (struct mspm0_sys_clock *)sys; - - switch (sys_clock->clk) { - case MSPM0_CLOCK_LFCLK: - *rate = mspm0_lfclk_cfg.clk_freq; - break; - - case MSPM0_CLOCK_ULPCLK: - *rate = mspm0_ulpclk_cfg.clk_freq; - break; - - case MSPM0_CLOCK_MCLK: - *rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; - break; - -#if MSPM0_MFPCLK_ENABLED - case MSPM0_CLOCK_MFPCLK: - *rate = mspm0_mfpclk_cfg.clk_freq; - break; -#endif - - case MSPM0_CLOCK_MFCLK: - case MSPM0_CLOCK_CANCLK: - default: - return -ENOTSUP; - } - - return 0; -} - -static int clock_mspm0_init(const struct device *dev) -{ - /* setup clocks based on specific rates */ - DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); - - DL_SYSCTL_setMCLKDivider(mspm0_mclk_cfg.clk_div); - DL_SYSCTL_setULPCLKDivider(mspm0_ulpclk_cfg.clk_div); - -#if MSPM0_PLL_ENABLED -#if DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll0)) - clock_mspm0_cfg_syspll.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0; -#endif -#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(hfclk)) - clock_mspm0_cfg_syspll.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK; -#endif - DL_SYSCTL_configSYSPLL( - (DL_SYSCTL_SYSPLLConfig *)&clock_mspm0_cfg_syspll); -#endif - -#if DT_SAME_NODE(DT_HFCLK_CLOCKS_CTRL, DT_NODELABEL(hfxt)) - uint32_t hf_range; - uint32_t hfxt_freq = DT_PROP(DT_NODELABEL(hfxt), - clock_frequency) / MHZ(1); - uint32_t xtal_startup_delay = DT_PROP_OR(DT_NODELABEL(hfxt), - ti_xtal_startup_delay_us, 0); - - if (hfxt_freq >= 4 && - hfxt_freq <= 8) { - hf_range = DL_SYSCTL_HFXT_RANGE_4_8_MHZ; - } else if (hfxt_freq > 8 && - hfxt_freq <= 16) { - hf_range = DL_SYSCTL_HFXT_RANGE_8_16_MHZ; - } else if (hfxt_freq > 16 && - hfxt_freq <= 32) { - hf_range = DL_SYSCTL_HFXT_RANGE_16_32_MHZ; - } else if (hfxt_freq > 32 && - hfxt_freq <= 48) { - hf_range = DL_SYSCTL_HFXT_RANGE_32_48_MHZ; - } else { - return -EINVAL; - } - - /* startup time in 64us resolution */ - DL_SYSCTL_setHFCLKSourceHFXTParams(hf_range, - mspm0_hfclk_cfg.xtal_startup_delay / 64, - true); -#else - DL_SYSCTL_setHFCLKSourceHFCLKIN(); -#endif - -#if MSPM0_LFCLK_ENABLED -#if DT_SAME_NODE(DT_LFCLK_CLOCKS_CTRL, DT_NODELABEL(lfxt)) - DL_SYSCTL_LFCLKConfig config = {0}; - - DL_SYSCTL_setLFCLKSourceLFXT(&config); -#elif DT_SAME_NODE(DT_LFCLK_CLOCKS_CTRL, DT_NODELABEL(lfdig_in)) - DL_SYSCTL_setLFCLKSourceEXLF(); -#endif -#endif /* MSPM0_LFCLK_ENABLED */ - -#if DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(hsclk)) -#if DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(hfclk)) - DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, - DL_SYSCTL_HSCLK_SOURCE_HFCLK); -#endif - -#if MSPM0_PLL_ENABLED -#if (DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll0)) || \ - DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll2x))) - DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, - DL_SYSCTL_HSCLK_SOURCE_SYSPLL); -#endif -#endif /* MSPM0_PLL_ENABLED */ - -#elif DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(lfclk)) - DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, false); -#endif /* DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(hsclk)) */ - -#if MSPM0_MFPCLK_ENABLED -#if DT_SAME_NODE(DT_MFPCLK_CLOCKS_CTRL, DT_NODELABEL(hfclk)) - DL_SYSCTL_setHFCLKDividerForMFPCLK(mspm0_mfpclk_cfg.clk_div); - DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_HFCLK); -#else - DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC); -#endif - DL_SYSCTL_enableMFPCLK(); -#endif /* MSPM0_MFPCLK_ENABLED */ - - return 0; -} - -static const struct clock_control_driver_api clock_mspm0_driver_api = { - .on = clock_mspm0_on, - .off = clock_mspm0_off, - .get_rate = clock_mspm0_get_rate, -}; - -DEVICE_DT_DEFINE(DT_NODELABEL(ckm), &clock_mspm0_init, NULL, NULL, NULL, - PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, - &clock_mspm0_driver_api); diff --git a/drivers/clock_control/clock_control_npcm.c b/drivers/clock_control/clock_control_npcm.c index 057f43abf503b..832d7decefb2f 100644 --- a/drivers/clock_control/clock_control_npcm.c +++ b/drivers/clock_control/clock_control_npcm.c @@ -343,8 +343,8 @@ static int npcm_clock_control_init(const struct device *dev) /* Load M and N values into the frequency multiplier */ priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD); /* Wait for stable */ - while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG)) { - } + while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG)) + ; } /* Set all clock prescalers of core and peripherals. */ diff --git a/drivers/clock_control/clock_control_npcx.c b/drivers/clock_control/clock_control_npcx.c index b6ea89a2cf570..e622b7cc9bc19 100644 --- a/drivers/clock_control/clock_control_npcx.c +++ b/drivers/clock_control/clock_control_npcx.c @@ -13,12 +13,6 @@ #include LOG_MODULE_REGISTER(clock_control_npcx, CONFIG_CLOCK_CONTROL_LOG_LEVEL); -#if defined(CONFIG_NPCX_SOC_VARIANT_NPCXN) -#define NPCX_PWDWN_CTL_START_OFFSET NPCX_PWDWN_CTL1 -#elif defined(CONFIG_NPCX_SOC_VARIANT_NPCKN) -#define NPCX_PWDWN_CTL_START_OFFSET NPCX_PWDWN_CTL0 -#endif - /* Driver config */ struct npcx_pcc_config { /* cdcg device base address */ @@ -249,7 +243,7 @@ static int npcx_clock_control_init(const struct device *dev) * power consumption. */ for (int i = 0; i < ARRAY_SIZE(pddwn_ctl_val); i++) { - NPCX_PWDWN_CTL(pmc_base, i + NPCX_PWDWN_CTL_START_OFFSET) = pddwn_ctl_val[i]; + NPCX_PWDWN_CTL(pmc_base, i) = pddwn_ctl_val[i]; } /* Turn off the clock of the eSPI module only if eSPI isn't required */ diff --git a/drivers/clock_control/clock_control_nrf2_common.c b/drivers/clock_control/clock_control_nrf2_common.c index f070d5d7b6988..da3b6b8686350 100644 --- a/drivers/clock_control/clock_control_nrf2_common.c +++ b/drivers/clock_control/clock_control_nrf2_common.c @@ -81,12 +81,6 @@ static void onoff_stop_option(struct onoff_manager *mgr, notify(mgr, 0); } -static void onoff_reset_option(struct onoff_manager *mgr, - onoff_notify_fn notify) -{ - notify(mgr, 0); -} - static inline uint8_t get_index_of_highest_bit(uint32_t value) { return value ? (uint8_t)(31 - __builtin_clz(value)) : 0; @@ -135,8 +129,7 @@ int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_ for (int i = 0; i < onoff_cnt; ++i) { static const struct onoff_transitions transitions = { .start = onoff_start_option, - .stop = onoff_stop_option, - .reset = onoff_reset_option, + .stop = onoff_stop_option }; int rc; @@ -155,22 +148,6 @@ int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_ return 0; } -int clock_config_request(struct onoff_manager *mgr, struct onoff_client *cli) -{ - /* If the on-off service recorded earlier an error, its state must be - * reset before a new request is made, otherwise the request would fail - * immediately. - */ - if (onoff_has_error(mgr)) { - struct onoff_client reset_cli; - - sys_notify_init_spinwait(&reset_cli.notify); - onoff_reset(mgr, &reset_cli); - } - - return onoff_request(mgr, cli); -} - uint8_t clock_config_update_begin(struct k_work *work) { struct clock_config_generic *cfg = diff --git a/drivers/clock_control/clock_control_nrf2_common.h b/drivers/clock_control/clock_control_nrf2_common.h index 7f934fdac5b8a..1f08e5b090f87 100644 --- a/drivers/clock_control/clock_control_nrf2_common.h +++ b/drivers/clock_control/clock_control_nrf2_common.h @@ -59,20 +59,6 @@ int lfosc_get_accuracy(uint16_t *accuracy); */ int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_work_handler); -/** - * @brief Helper function for requesting a clock configuration handled by - * a given on-off manager. - * - * If needed, the function resets the on-off service prior to making the new - * request. - * - * @param mgr pointer to the manager for which the request is to be done. - * @param cli pointer to a client state structure to be used for the request. - * - * @return result returned by onoff_request(). - */ -int clock_config_request(struct onoff_manager *mgr, struct onoff_client *cli); - /** * @brief Starts a clock configuration update. * diff --git a/drivers/clock_control/clock_control_nrf2_fll16m.c b/drivers/clock_control/clock_control_nrf2_fll16m.c index 7bb10263d5b63..cbec791aa77c6 100644 --- a/drivers/clock_control/clock_control_nrf2_fll16m.c +++ b/drivers/clock_control/clock_control_nrf2_fll16m.c @@ -21,18 +21,15 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define FLAG_HFXO_STARTED BIT(FLAGS_COMMON_BITS) #define FLL16M_MODE_OPEN_LOOP 0 -#define FLL16M_MODE_CLOSED_LOOP 1 /* <-- DO NOT IMPLEMENT, CAN CAUSE HARDWARE BUG */ +#define FLL16M_MODE_CLOSED_LOOP 1 #define FLL16M_MODE_BYPASS 2 #define FLL16M_MODE_DEFAULT FLL16M_MODE_OPEN_LOOP -#define FLL16M_MODE_LOOP_MASK BIT(0) - -BUILD_ASSERT(FLL16M_MODE_OPEN_LOOP == NRF_LRCCONF_CLK_SRC_OPEN_LOOP); -BUILD_ASSERT(FLL16M_MODE_CLOSED_LOOP == NRF_LRCCONF_CLK_SRC_CLOSED_LOOP); #define FLL16M_HFXO_NODE DT_INST_PHANDLE_BY_NAME(0, clocks, hfxo) #define FLL16M_HFXO_ACCURACY DT_PROP(FLL16M_HFXO_NODE, accuracy_ppm) #define FLL16M_OPEN_LOOP_ACCURACY DT_INST_PROP(0, open_loop_accuracy_ppm) +#define FLL16M_CLOSED_LOOP_BASE_ACCURACY DT_INST_PROP(0, closed_loop_base_accuracy_ppm) #define FLL16M_MAX_ACCURACY FLL16M_HFXO_ACCURACY #define BICR (NRF_BICR_Type *)DT_REG_ADDR(DT_NODELABEL(bicr)) @@ -46,6 +43,9 @@ static struct clock_options { .accuracy = FLL16M_OPEN_LOOP_ACCURACY, .mode = FLL16M_MODE_OPEN_LOOP, }, + { + .mode = FLL16M_MODE_CLOSED_LOOP, + }, { /* Bypass mode uses HFXO */ .accuracy = FLL16M_HFXO_ACCURACY, @@ -65,13 +65,13 @@ struct fll16m_dev_config { static void activate_fll16m_mode(struct fll16m_dev_data *dev_data, uint8_t mode) { + /* TODO: change to nrf_lrcconf_* function when such is available. */ + if (mode != FLL16M_MODE_DEFAULT) { soc_lrcconf_poweron_request(&dev_data->fll16m_node, NRF_LRCCONF_POWER_MAIN); } - nrf_lrcconf_clock_source_set(NRF_LRCCONF010, 0, - (nrf_lrcconf_clk_src_t)(mode & FLL16M_MODE_LOOP_MASK), - (mode == FLL16M_MODE_BYPASS)); + NRF_LRCCONF010->CLKCTRL[0].SRC = mode; if (mode == FLL16M_MODE_DEFAULT) { soc_lrcconf_poweron_release(&dev_data->fll16m_node, NRF_LRCCONF_POWER_MAIN); @@ -178,7 +178,7 @@ static int api_request_fll16m(const struct device *dev, struct onoff_manager *mgr = fll16m_find_mgr(dev, spec); if (mgr) { - return clock_config_request(mgr, cli); + return onoff_request(mgr, cli); } return -EINVAL; @@ -225,6 +225,27 @@ static int api_get_rate_fll16m(const struct device *dev, static int fll16m_init(const struct device *dev) { struct fll16m_dev_data *dev_data = dev->data; + nrf_bicr_lfosc_mode_t lfosc_mode; + + clock_options[1].accuracy = FLL16M_CLOSED_LOOP_BASE_ACCURACY; + + /* Closed-loop mode uses LFXO as source if present, HFXO otherwise */ + lfosc_mode = nrf_bicr_lfosc_mode_get(BICR); + + if (lfosc_mode != NRF_BICR_LFOSC_MODE_UNCONFIGURED && + lfosc_mode != NRF_BICR_LFOSC_MODE_DISABLED) { + int ret; + uint16_t accuracy; + + ret = lfosc_get_accuracy(&accuracy); + if (ret < 0) { + return ret; + } + + clock_options[1].accuracy += accuracy; + } else { + clock_options[1].accuracy += FLL16M_HFXO_ACCURACY; + } return clock_config_init(&dev_data->clk_cfg, ARRAY_SIZE(dev_data->clk_cfg.onoff), diff --git a/drivers/clock_control/clock_control_nrf2_global_hsfll.c b/drivers/clock_control/clock_control_nrf2_global_hsfll.c index 50f3396429c1a..69053c99ff2f4 100644 --- a/drivers/clock_control/clock_control_nrf2_global_hsfll.c +++ b/drivers/clock_control/clock_control_nrf2_global_hsfll.c @@ -101,7 +101,7 @@ static int api_request_global_hsfll(const struct device *dev, struct onoff_manager *mgr = global_hsfll_find_mgr(dev, spec); if (mgr) { - return clock_config_request(mgr, cli); + return onoff_request(mgr, cli); } return -EINVAL; diff --git a/drivers/clock_control/clock_control_nrf2_hsfll.c b/drivers/clock_control/clock_control_nrf2_hsfll.c index eb2dfde989c73..f67373070f1a4 100644 --- a/drivers/clock_control/clock_control_nrf2_hsfll.c +++ b/drivers/clock_control/clock_control_nrf2_hsfll.c @@ -140,7 +140,7 @@ static int api_request_hsfll(const struct device *dev, struct onoff_manager *mgr = hsfll_find_mgr(dev, spec); if (mgr) { - return clock_config_request(mgr, cli); + return onoff_request(mgr, cli); } return -EINVAL; diff --git a/drivers/clock_control/clock_control_nrf2_lfclk.c b/drivers/clock_control/clock_control_nrf2_lfclk.c index c5f70c1497ba9..2cbef9b8bf094 100644 --- a/drivers/clock_control/clock_control_nrf2_lfclk.c +++ b/drivers/clock_control/clock_control_nrf2_lfclk.c @@ -146,7 +146,7 @@ static int api_request_lfclk(const struct device *dev, struct onoff_manager *mgr = lfclk_find_mgr(dev, spec); if (mgr) { - return clock_config_request(mgr, cli); + return onoff_request(mgr, cli); } return -EINVAL; diff --git a/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c b/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c deleted file mode 100644 index c518fb35a5b7f..0000000000000 --- a/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#define DT_DRV_COMPAT renesas_rx_cgc_pclk - -#include -#include -#include -#include -#include -#include - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pclkblock), okay) -#define MSTP_REGS_ELEM(node_id, prop, idx) \ - [DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \ - (volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx), - -static volatile uint32_t *mstp_regs[] = { - DT_FOREACH_PROP_ELEM(DT_NODELABEL(pclkblock), reg_names, MSTP_REGS_ELEM)}; -#else -static volatile uint32_t *mstp_regs[] = {}; -#endif - -static int clock_control_renesas_rx_on(const struct device *dev, clock_control_subsys_t sys) -{ - struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys; - - if (!dev || !sys) { - return -EINVAL; - } - - renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); - WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false); - renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); - - return 0; -} - -static int clock_control_renesas_rx_off(const struct device *dev, clock_control_subsys_t sys) -{ - struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys; - - if (!dev || !sys) { - return -EINVAL; - } - - renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); - WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true); - renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); - - return 0; -} - -static int clock_control_renesas_rx_get_rate(const struct device *dev, clock_control_subsys_t sys, - uint32_t *rate) -{ - const struct clock_control_rx_pclk_cfg *config = dev->config; - uint32_t clk_src_rate; - uint32_t clk_div_val; - int ret; - - if (!device_is_ready(dev)) { - return -ENODEV; - } - - ret = clock_control_get_rate(config->clock_src_dev, NULL, &clk_src_rate); - if (ret) { - return ret; - } - - clk_div_val = config->clk_div; - *rate = clk_src_rate / clk_div_val; - - return 0; -} - -static DEVICE_API(clock_control, clock_control_renesas_rx_api) = { - .on = clock_control_renesas_rx_on, - .off = clock_control_renesas_rx_off, - .get_rate = clock_control_renesas_rx_get_rate, -}; - -#define RENESAS_RX_CLOCK_SOURCE(node_id) \ - COND_CODE_1(DT_NODE_HAS_PROP(node_id, clocks), (DEVICE_DT_GET(DT_CLOCKS_CTLR(node_id))), \ - DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(node_id)))) - -#define INIT_PCLK(node_id) \ - static const struct clock_control_rx_pclk_cfg clock_control_cfg_##node_id = { \ - .clock_src_dev = RENESAS_RX_CLOCK_SOURCE(node_id), \ - .clk_div = DT_INST_PROP_OR(node_id, div, 1), \ - }; \ - DEVICE_DT_INST_DEFINE(node_id, NULL, NULL, NULL, &clock_control_cfg_##node_id, \ - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ - &clock_control_renesas_rx_api); - -DT_INST_FOREACH_STATUS_OKAY(INIT_PCLK); diff --git a/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c b/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c deleted file mode 100644 index e085800bd447b..0000000000000 --- a/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_rx_cgc_pll - -#include -#include -#include -#include -#include -#include - -static int clock_control_renesas_rx_pll_on(const struct device *dev, clock_control_subsys_t sys) -{ - return -ENOTSUP; -} - -static int clock_control_renesas_rx_pll_off(const struct device *dev, clock_control_subsys_t sys) -{ - return -ENOTSUP; -} - -static enum clock_control_status clock_control_renesas_rx_pll_get_status(const struct device *dev, - clock_control_subsys_t sys) -{ - return CLOCK_CONTROL_STATUS_ON; -} - -static int clock_control_renesas_rx_pll_get_rate(const struct device *dev, - clock_control_subsys_t sys, uint32_t *rate) -{ - const struct clock_control_rx_pll_cfg *config = dev->config; - struct clock_control_rx_pll_data *data = dev->data; - float pll_multiplier; - float pll_divider; - uint32_t pll_clock_freq; - uint32_t clock_dev_freq; - int ret; - - if (!device_is_ready(dev)) { - return -ENODEV; - } - - /* Get the clock frequency of PLL clock device */ - ret = clock_control_get_rate(config->clock_dev, NULL, &clock_dev_freq); - if (ret) { - return ret; - } - - /* Calculate the PLL multiple and divider */ - pll_multiplier = (data->pll_mul + 1) / (2.0); - pll_divider = data->pll_div; - - /* Calculate PLL clock frequency */ - pll_clock_freq = ((clock_dev_freq / pll_divider) * pll_multiplier); - - *rate = pll_clock_freq; - return 0; -} - -static DEVICE_API(clock_control, clock_control_renesas_rx_pll_api) = { - .on = clock_control_renesas_rx_pll_on, - .off = clock_control_renesas_rx_pll_off, - .get_status = clock_control_renesas_rx_pll_get_status, - .get_rate = clock_control_renesas_rx_pll_get_rate, -}; - -#define PLL_CLK_INIT(idx) \ - static struct clock_control_rx_pll_cfg pll_cfg##idx = { \ - .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))), \ - }; \ - static struct clock_control_rx_pll_data pll_data##idx = { \ - .pll_div = DT_INST_PROP(idx, div), \ - .pll_mul = DT_INST_PROP(idx, mul), \ - }; \ - DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &pll_data##idx, &pll_cfg##idx, PRE_KERNEL_1, \ - CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ - &clock_control_renesas_rx_pll_api); - -DT_INST_FOREACH_STATUS_OKAY(PLL_CLK_INIT); diff --git a/drivers/clock_control/clock_control_renesas_rx_root_cgc.c b/drivers/clock_control/clock_control_renesas_rx_root_cgc.c deleted file mode 100644 index 25ed0da71d7a8..0000000000000 --- a/drivers/clock_control/clock_control_renesas_rx_root_cgc.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_rx_cgc_root_clock - -#include -#include -#include -#include -#include - -static int clock_control_renesas_rx_root_on(const struct device *dev, clock_control_subsys_t sys) -{ - return -ENOTSUP; -} - -static int clock_control_renesas_rx_root_off(const struct device *dev, clock_control_subsys_t sys) -{ - return -ENOTSUP; -} - -static int clock_control_renesas_rx_root_get_rate(const struct device *dev, - clock_control_subsys_t sys, uint32_t *rate) -{ - const struct clock_control_rx_root_cfg *config = dev->config; - - ARG_UNUSED(sys); - - if (!device_is_ready(dev)) { - return -ENODEV; - } - - *rate = config->rate; - return 0; -} - -static int clock_control_rx_init(const struct device *dev) -{ - ARG_UNUSED(dev); -#if CONFIG_HAS_RENESAS_RX_RDP - /* Call to HAL layer to initialize system clock and peripheral clock */ - mcu_clock_setup(); -#endif - return 0; -} - -static DEVICE_API(clock_control, clock_control_renesas_rx_root_api) = { - .on = clock_control_renesas_rx_root_on, - .off = clock_control_renesas_rx_root_off, - .get_rate = clock_control_renesas_rx_root_get_rate, -}; - -#define ROOT_CLK_INIT(idx) \ - static const struct clock_control_rx_root_cfg clock_control_rx_root_cfg##idx = { \ - .rate = DT_INST_PROP(idx, clock_frequency), \ - }; \ - DEVICE_DT_INST_DEFINE(idx, &clock_control_rx_init, NULL, NULL, \ - &clock_control_rx_root_cfg##idx, PRE_KERNEL_1, \ - CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ - &clock_control_renesas_rx_root_api); - -DT_INST_FOREACH_STATUS_OKAY(ROOT_CLK_INIT); diff --git a/drivers/clock_control/clock_control_si32_pll.c b/drivers/clock_control/clock_control_si32_pll.c index 1dd29b804d3f2..2229acd0c76a0 100644 --- a/drivers/clock_control/clock_control_si32_pll.c +++ b/drivers/clock_control/clock_control_si32_pll.c @@ -80,8 +80,8 @@ static int clock_control_si32_pll_on(const struct device *dev, clock_control_sub SI32_PLL_A_select_dco_frequency_lock_mode(config->pll); while (!(SI32_PLL_A_is_locked(config->pll) || SI32_PLL_A_is_saturation_low_interrupt_pending(config->pll) || - SI32_PLL_A_is_saturation_high_interrupt_pending(config->pll))) { - } + SI32_PLL_A_is_saturation_high_interrupt_pending(config->pll))) + ; return 0; } diff --git a/drivers/clock_control/clock_control_silabs_siwx91x.c b/drivers/clock_control/clock_control_silabs_siwx91x.c index 477aaebf02cb0..57c703f6936b0 100644 --- a/drivers/clock_control/clock_control_silabs_siwx91x.c +++ b/drivers/clock_control/clock_control_silabs_siwx91x.c @@ -13,13 +13,12 @@ #include "rsi_rom_ulpss_clk.h" #include "rsi_rom_clks.h" #include "rsi_sysrtc.h" -#include "rsi_pll.h" #include "clock_update.h" #include "sl_si91x_clock_manager.h" +#define DT_DRV_COMPAT silabs_siwx91x_clock #define DT_DRV_COMPAT silabs_siwx91x_clock #define LF_FSM_CLOCK_FREQUENCY 32768 -#define XTAL_FREQUENCY 40000000 LOG_MODULE_REGISTER(siwx91x_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); @@ -78,31 +77,6 @@ static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys */ rsi_sysrtc_clk_set(RSI_SYSRTC_CLK_32kHz_Xtal, 0); break; - case SIWX91X_CLK_GSPI: - RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); - RSI_CLK_GspiClkConfig(M4CLK, GSPI_INTF_PLL_CLK); - break; - case SIWX91X_CLK_QSPI: - RSI_CLK_Qspi2ClkConfig(M4CLK, QSPI_ULPREFCLK, 0, 0, 0); - break; - case SIWX91X_CLK_RTC: - /* Already done in sl_calendar_init()*/ - RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCURTC | SLPSS_PWRGATE_ULP_TIMEPERIOD); - break; - case SIWX91X_CLK_I2S0: - RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); - break; - case SIWX91X_CLK_STATIC_I2S0: - MISC_CFG_MISC_CTRL1 |= (1 << 23); - RSI_CLK_PeripheralClkEnable(M4CLK, I2SM_CLK, ENABLE_STATIC_CLK); - break; - case SIWX91X_CLK_ULP_I2S: - RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2S); - break; - case SIWX91X_CLK_STATIC_ULP_I2S: - ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_MASTER_SLAVE_MODE_b = 1; - RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2S_CLK, ENABLE_STATIC_CLK); - break; default: return -EINVAL; } @@ -132,12 +106,6 @@ static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sy case SIWX91X_CLK_DMA0: RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK); break; - case SIWX91X_CLK_STATIC_I2S0: - RSI_CLK_PeripheralClkDisable(M4CLK, I2SM_CLK); - break; - case SIWX91X_CLK_STATIC_ULP_I2S: - RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2S_CLK); - break; case SIWX91X_CLK_ULP_UART: case SIWX91X_CLK_I2C0: case SIWX91X_CLK_I2C1: @@ -173,36 +141,6 @@ static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys case SIWX91X_CLK_WATCHDOG: *rate = LF_FSM_CLOCK_FREQUENCY; return 0; - case SIWX91X_CLK_GSPI: - *rate = RSI_CLK_GetBaseClock(M4_GSPI); - return 0; - default: - /* For now, no other driver need clock rate */ - return -EINVAL; - } -} - -static int siwx91x_clock_set_rate(const struct device *dev, clock_control_subsys_t sys, - clock_control_subsys_rate_t rate) -{ - uintptr_t clockid = (uintptr_t)sys; - ULP_I2S_CLK_SELECT_T ref_clk; - uint32_t freq; - int ret; - - switch (clockid) { - case SIWX91X_CLK_I2S0: - RSI_CLK_SetI2sPllFreq(M4CLK, *((uint32_t *)rate), XTAL_FREQUENCY); - RSI_CLK_I2sClkConfig(M4CLK, I2S_PLLCLK, 0); - return 0; - case SIWX91X_CLK_ULP_I2S: - ref_clk = ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b; - freq = RSI_CLK_GetBaseClock(ULPSS_I2S); - ret = RSI_ULPSS_UlpI2sClkConfig(ULPCLK, ref_clk, freq / (*((uint32_t *)rate) / 2)); - if (ret) { - return -EIO; - } - return 0; default: /* For now, no other driver need clock rate */ return -EINVAL; @@ -256,7 +194,6 @@ static DEVICE_API(clock_control, siwx91x_clock_api) = { .on = siwx91x_clock_on, .off = siwx91x_clock_off, .get_rate = siwx91x_clock_get_rate, - .set_rate = siwx91x_clock_set_rate, .get_status = siwx91x_clock_get_status, }; diff --git a/drivers/clock_control/clock_control_wch_rcc.c b/drivers/clock_control/clock_control_wch_rcc.c index 14722d9ede4cf..9275fd0bc82fe 100644 --- a/drivers/clock_control/clock_control_wch_rcc.c +++ b/drivers/clock_control/clock_control_wch_rcc.c @@ -18,7 +18,6 @@ #define WCH_RCC_CLOCK_ID_OFFSET(id) (((id) >> 5) & 0xFF) #define WCH_RCC_CLOCK_ID_BIT(id) ((id) & 0x1F) -#define WCH_RCC_SYSCLK DT_PROP(DT_NODELABEL(cpu0), clock_frequency) #if DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_pll_clock) || \ DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v20x_30x_pll_clock) @@ -79,33 +78,6 @@ static int clock_control_wch_rcc_get_rate(const struct device *dev, clock_contro return 0; } -static void clock_control_wch_rcc_setup_flash(void) -{ -#if defined(FLASH_ACTLR_LATENCY) - uint32_t latency; - -#if defined(CONFIG_SOC_CH32V003) - if (WCH_RCC_SYSCLK <= 24000000) { - latency = FLASH_ACTLR_LATENCY_0; - } else { - latency = FLASH_ACTLR_LATENCY_1; - } -#elif defined(CONFIG_SOC_SERIES_CH32V00X) - if (WCH_RCC_SYSCLK <= 15000000) { - latency = FLASH_ACTLR_LATENCY_0; - } else if (WCH_RCC_SYSCLK <= 24000000) { - latency = FLASH_ACTLR_LATENCY_1; - } else { - latency = FLASH_ACTLR_LATENCY_2; - } - FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | latency; -#else -#error Unrecognised SOC family -#endif - FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | latency; -#endif -} - static DEVICE_API(clock_control, clock_control_wch_rcc_api) = { .on = clock_control_wch_rcc_on, .get_rate = clock_control_wch_rcc_get_rate, @@ -115,8 +87,6 @@ static int clock_control_wch_rcc_init(const struct device *dev) { const struct clock_control_wch_rcc_config *config = dev->config; - clock_control_wch_rcc_setup_flash(); - if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED) || IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) { /* Disable the PLL before potentially changing the input clocks. */ @@ -175,6 +145,10 @@ static int clock_control_wch_rcc_init(const struct device *dev) RCC->INTR = RCC_CSSC | RCC_PLLRDYC | RCC_HSERDYC | RCC_LSIRDYC; /* HCLK = SYSCLK = APB1 */ RCC->CFGR0 = (RCC->CFGR0 & ~RCC_HPRE) | RCC_HPRE_DIV1; +#if defined(CONFIG_SOC_CH32V003) + /* Set the Flash to 0 wait state */ + FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | FLASH_ACTLR_LATENCY_1; +#endif return 0; } diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 1e6acfd6d8490..5d6bcb72fa998 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -53,29 +53,15 @@ /* This check should only be performed for the M7 core code */ #ifdef CONFIG_CPU_CORTEX_M7 -/* Choose PLL SRC : same source for all the PLL */ -#if defined(STM32_PLL_SRC_HSI) || defined(STM32_PLL2_SRC_HSI) || defined(STM32_PLL3_SRC_HSI) +/* Choose PLL SRC */ +#if defined(STM32_PLL_SRC_HSI) #define PLLSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR)) -#endif - -#if defined(STM32_PLL_SRC_CSI) || defined(STM32_PLL2_SRC_CSI) || defined(STM32_PLL3_SRC_CSI) -#if !defined(PLLSRC_FREQ) +#elif defined(STM32_PLL_SRC_CSI) #define PLLSRC_FREQ STM32_CSI_FREQ -#else -#error "All PLLs must have the same clock source" -#endif -#endif - -#if defined(STM32_PLL_SRC_HSE) || defined(STM32_PLL2_SRC_HSE) || defined(STM32_PLL3_SRC_HSE) -#if !defined(PLLSRC_FREQ) +#elif defined(STM32_PLL_SRC_HSE) #define PLLSRC_FREQ STM32_HSE_FREQ #else -#error "All PLLs must have the same clock source" -#endif -#endif - -#if !defined(PLLSRC_FREQ) -#define PLLSRC_FREQ 0 +#define PLLSRC_FREQ 0 #endif /* Given source clock and dividers, computed the output frequency of PLLP */ @@ -351,16 +337,6 @@ int enabled_clock(uint32_t src_clk) ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) || ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || -#if defined(CONFIG_SOC_SERIES_STM32H7RSX) - (src_clk == STM32_SRC_HCLK1) || - (src_clk == STM32_SRC_HCLK2) || - (src_clk == STM32_SRC_HCLK3) || - (src_clk == STM32_SRC_HCLK4) || - (src_clk == STM32_SRC_HCLK5) || - ((src_clk == STM32_SRC_PLL2_S) && IS_ENABLED(STM32_PLL2_S_ENABLED)) || - ((src_clk == STM32_SRC_PLL2_T) && IS_ENABLED(STM32_PLL2_T_ENABLED)) || - ((src_clk == STM32_SRC_PLL3_S) && IS_ENABLED(STM32_PLL3_S_ENABLED)) || -#endif ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { return 0; } @@ -484,14 +460,6 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB3: case STM32_CLOCK_BUS_AHB4: -#if defined(CONFIG_SOC_SERIES_STM32H7RSX) - /* HCLKn is a possible source clock for some peripherals */ - case STM32_SRC_HCLK1: - case STM32_SRC_HCLK2: - case STM32_SRC_HCLK3: - case STM32_SRC_HCLK4: - case STM32_SRC_HCLK5: -#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ *rate = ahb_clock; break; case STM32_CLOCK_BUS_APB1: @@ -576,7 +544,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_N_MULTIPLIER, STM32_PLL_S_DIVISOR); break; - /* PLL 1 has no T-divider */ + /* PLL 1 has no T-divider */ #endif /* CONFIG_SOC_SERIES_STM32H7RSX */ #endif /* STM32_PLL_ENABLED */ #if defined(STM32_PLL2_ENABLED) @@ -814,19 +782,13 @@ static int set_up_plls(void) /* Configure PLL source */ /* Can be HSE , HSI 64Mhz/HSIDIV, CSI 4MHz*/ - if (IS_ENABLED(STM32_PLL_SRC_HSE) || - IS_ENABLED(STM32_PLL2_SRC_HSE) || - IS_ENABLED(STM32_PLL3_SRC_HSE)) { + if (IS_ENABLED(STM32_PLL_SRC_HSE)) { /* Main PLL configuration and activation */ LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); - } else if (IS_ENABLED(STM32_PLL_SRC_CSI) || - IS_ENABLED(STM32_PLL2_SRC_CSI) || - IS_ENABLED(STM32_PLL3_SRC_CSI)) { + } else if (IS_ENABLED(STM32_PLL_SRC_CSI)) { /* Main PLL configuration and activation */ LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_CSI); - } else if (IS_ENABLED(STM32_PLL_SRC_HSI) || - IS_ENABLED(STM32_PLL2_SRC_HSI) || - IS_ENABLED(STM32_PLL3_SRC_HSI)) { + } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) { /* Main PLL configuration and activation */ LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI); } else { diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c index b543ae195a613..4c880513732b4 100644 --- a/drivers/clock_control/clock_stm32_ll_mp13.c +++ b/drivers/clock_control/clock_stm32_ll_mp13.c @@ -17,29 +17,6 @@ #include #include -/** @brief Verifies clock is part of active clock configuration */ -int enabled_clock(uint32_t src_clk) -{ - if ((src_clk == STM32_SRC_HSE && IS_ENABLED(STM32_HSE_ENABLED)) || - (src_clk == STM32_SRC_HSI && IS_ENABLED(STM32_HSI_ENABLED)) || - (src_clk == STM32_SRC_LSE && IS_ENABLED(STM32_LSE_ENABLED)) || - (src_clk == STM32_SRC_LSI && IS_ENABLED(STM32_LSI_ENABLED)) || - (src_clk == STM32_SRC_PLL1_P && IS_ENABLED(STM32_PLL_P_ENABLED)) || - (src_clk == STM32_SRC_PLL2_P && IS_ENABLED(STM32_PLL2_P_ENABLED)) || - (src_clk == STM32_SRC_PLL2_Q && IS_ENABLED(STM32_PLL2_Q_ENABLED)) || - (src_clk == STM32_SRC_PLL2_R && IS_ENABLED(STM32_PLL2_R_ENABLED)) || - (src_clk == STM32_SRC_PLL3_P && IS_ENABLED(STM32_PLL3_P_ENABLED)) || - (src_clk == STM32_SRC_PLL3_Q && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || - (src_clk == STM32_SRC_PLL3_R && IS_ENABLED(STM32_PLL3_R_ENABLED)) || - (src_clk == STM32_SRC_PLL4_P && IS_ENABLED(STM32_PLL4_P_ENABLED)) || - (src_clk == STM32_SRC_PLL4_Q && IS_ENABLED(STM32_PLL4_Q_ENABLED)) || - (src_clk == STM32_SRC_PLL4_R && IS_ENABLED(STM32_PLL4_R_ENABLED))) { - return 0; - } - - return -ENOTSUP; -} - static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system; @@ -80,32 +57,6 @@ static int stm32_clock_control_off(const struct device *dev, clock_control_subsy return 0; } -static int stm32_clock_control_configure(const struct device *dev, - clock_control_subsys_t sub_system, - void *data) -{ - struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); - int err; - - ARG_UNUSED(dev); - ARG_UNUSED(data); - - err = enabled_clock(pclken->bus); - if (err < 0) { - /* Attempt to configure a src clock not available or not valid */ - return err; - } - - sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), - STM32_DT_CLKSEL_MASK_GET(pclken->enr) << - STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); - sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), - STM32_DT_CLKSEL_VAL_GET(pclken->enr) << - STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); - - return 0; -} - static int stm32_clock_control_get_subsys_rate(const struct device *dev, clock_control_subsys_t sub_system, uint32_t *rate) { @@ -119,25 +70,6 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, case LL_APB1_GRP1_PERIPH_UART4: *rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE); break; - case LL_APB1_GRP1_PERIPH_I2C1: - case LL_APB1_GRP1_PERIPH_I2C2: - *rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_CLKSOURCE); - break; - default: - return -ENOTSUP; - } - break; - case STM32_CLOCK_BUS_APB6: - switch (pclken->enr) { - case LL_APB6_GRP1_PERIPH_I2C3: - *rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C3_CLKSOURCE); - break; - case LL_APB6_GRP1_PERIPH_I2C4: - *rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C4_CLKSOURCE); - break; - case LL_APB6_GRP1_PERIPH_I2C5: - *rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C5_CLKSOURCE); - break; default: return -ENOTSUP; } @@ -148,37 +80,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, return 0; } -static enum clock_control_status stm32_clock_control_get_status(const struct device *dev, - clock_control_subsys_t sub_system) -{ - struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system; - - ARG_UNUSED(dev); - - if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) { - /* Gated clocks */ - if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) - == pclken->enr) { - return CLOCK_CONTROL_STATUS_ON; - } else { - return CLOCK_CONTROL_STATUS_OFF; - } - } else { - /* Domain clock sources */ - if (enabled_clock(pclken->bus) == 0) { - return CLOCK_CONTROL_STATUS_ON; - } else { - return CLOCK_CONTROL_STATUS_OFF; - } - } -} - static DEVICE_API(clock_control, stm32_clock_control_api) = { .on = stm32_clock_control_on, .off = stm32_clock_control_off, .get_rate = stm32_clock_control_get_subsys_rate, - .configure = stm32_clock_control_configure, - .get_status = stm32_clock_control_get_status, }; static void set_up_fixed_clock_sources(void) @@ -249,7 +154,7 @@ static int stm32_clock_control_init(const struct device *dev) uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n); uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m); uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p); - uint32_t pll1_fracn = DT_PROP(DT_NODELABEL(pll1), fracn); + uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v); LL_RCC_PLL1_SetN(pll1_n); while (LL_RCC_PLL1_GetN() != pll1_n) { @@ -260,8 +165,8 @@ static int stm32_clock_control_init(const struct device *dev) LL_RCC_PLL1_SetP(pll1_p); while (LL_RCC_PLL1_GetP() != pll1_p) { } - LL_RCC_PLL1_SetFRACV(pll1_fracn); - while (LL_RCC_PLL1_GetFRACV() != pll1_fracn) { + LL_RCC_PLL1_SetFRACV(pll1_v); + while (LL_RCC_PLL1_GetFRACV() != pll1_v) { } LL_RCC_PLL1_Enable(); diff --git a/drivers/clock_control/clock_stm32_mco.c b/drivers/clock_control/clock_stm32_mco.c index e94c054e02f7f..1a524d74c59b2 100644 --- a/drivers/clock_control/clock_stm32_mco.c +++ b/drivers/clock_control/clock_stm32_mco.c @@ -49,11 +49,6 @@ static int stm32_mco_init(const struct device *dev) STM32_DT_CLKSEL_VAL_GET(pclken->enr) << STM32_DT_CLKSEL_SHIFT_GET(pclken->enr)); -#if defined(MCOX_ON) - sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), - MCOX_ON); -#endif - #if defined(HAS_PRESCALER) /* MCO prescaler */ sys_clear_bits( diff --git a/drivers/comparator/comparator_nrf_common.h b/drivers/comparator/comparator_nrf_common.h deleted file mode 100644 index c45e6676e2d8e..0000000000000 --- a/drivers/comparator/comparator_nrf_common.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_ -#define ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_ - -#include - -#if (NRF_COMP_HAS_AIN_AS_PIN || NRF_LPCOMP_HAS_AIN_AS_PIN) -static const uint32_t shim_nrf_comp_ain_map[] = { -#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) - NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), -#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) - NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), -#elif defined(CONFIG_SOC_COMPATIBLE_NRF54LX) - NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(30U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(29U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), - NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1), -#endif -}; -#endif - -#endif /* ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_ */ diff --git a/drivers/comparator/comparator_nrf_comp.c b/drivers/comparator/comparator_nrf_comp.c index b60aef179873d..33bea15778f98 100644 --- a/drivers/comparator/comparator_nrf_comp.c +++ b/drivers/comparator/comparator_nrf_comp.c @@ -9,7 +9,6 @@ #include #include #include -#include "comparator_nrf_common.h" #define DT_DRV_COMPAT nordic_nrf_comp @@ -68,6 +67,30 @@ struct shim_nrf_comp_data { void *user_data; }; +#if (NRF_COMP_HAS_AIN_AS_PIN) +static const uint32_t shim_nrf_comp_ain_map[] = { +#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) + NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), +#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) + NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), +#endif +}; +#endif + #if SHIM_NRF_COMP_DT_INST_MAIN_MODE_IS_SE(0) BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_DOWN(0) < 64); BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_UP(0) < 64); diff --git a/drivers/comparator/comparator_nrf_lpcomp.c b/drivers/comparator/comparator_nrf_lpcomp.c index a3de2b8069c6d..5b3ff0d4a46a8 100644 --- a/drivers/comparator/comparator_nrf_lpcomp.c +++ b/drivers/comparator/comparator_nrf_lpcomp.c @@ -9,7 +9,6 @@ #include #include #include -#include "comparator_nrf_common.h" #include @@ -39,6 +38,30 @@ struct shim_nrf_lpcomp_data { void *user_data; }; +#if (NRF_LPCOMP_HAS_AIN_AS_PIN) +static const uint32_t shim_nrf_lpcomp_ain_map[] = { +#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) + NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), +#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) + NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), + NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), +#endif +}; +#endif + #if (NRF_LPCOMP_HAS_AIN_AS_PIN) BUILD_ASSERT(COMP_NRF_LPCOMP_PSEL_AIN0 == 0); BUILD_ASSERT(COMP_NRF_LPCOMP_PSEL_AIN7 == 7); @@ -129,11 +152,11 @@ static int shim_nrf_lpcomp_pm_callback(const struct device *dev, enum pm_device_ static int shim_nrf_lpcomp_psel_to_nrf(enum comp_nrf_lpcomp_psel shim, nrf_lpcomp_input_t *nrf) { - if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) { + if (shim >= ARRAY_SIZE(shim_nrf_lpcomp_ain_map)) { return -EINVAL; } - *nrf = shim_nrf_comp_ain_map[(uint32_t)shim]; + *nrf = shim_nrf_lpcomp_ain_map[(uint32_t)shim]; return 0; } #else @@ -185,11 +208,11 @@ static int shim_nrf_lpcomp_psel_to_nrf(enum comp_nrf_lpcomp_psel shim, static int shim_nrf_lpcomp_extrefsel_to_nrf(enum comp_nrf_lpcomp_extrefsel shim, nrf_lpcomp_ext_ref_t *nrf) { - if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) { + if (shim >= ARRAY_SIZE(shim_nrf_lpcomp_ain_map)) { return -EINVAL; } - *nrf = shim_nrf_comp_ain_map[shim]; + *nrf = shim_nrf_lpcomp_ain_map[shim]; return 0; } #else diff --git a/drivers/counter/CMakeLists.txt b/drivers/counter/CMakeLists.txt index 1fd17b77af2c8..b2c6365228068 100644 --- a/drivers/counter/CMakeLists.txt +++ b/drivers/counter/CMakeLists.txt @@ -57,6 +57,3 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_RA_AGT counter_renesas_ zephyr_library_sources_ifdef(CONFIG_COUNTER_RENESAS_RZ_GTM counter_renesas_rz_gtm.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912_SLWTMR counter_realtek_rts5912_slwtmr.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912 counter_realtek_rts5912.c) -zephyr_library_sources_ifdef(CONFIG_COUNTER_NEORV32_GPTMR counter_neorv32_gptmr.c) -zephyr_library_sources_ifdef(CONFIG_COUNTER_WUT_MAX32 counter_max32_wut.c) -zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_RTC counter_cc23x0_rtc.c) diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index ff2a8f2498dee..2cff7c5f51e06 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -112,10 +112,4 @@ source "drivers/counter/Kconfig.rts5912_slwtmr" source "drivers/counter/Kconfig.rts5912" -source "drivers/counter/Kconfig.neorv32" - -source "drivers/counter/Kconfig.max32_wut" - -source "drivers/counter/Kconfig.cc23x0_rtc" - endif # COUNTER diff --git a/drivers/counter/Kconfig.cc23x0_rtc b/drivers/counter/Kconfig.cc23x0_rtc deleted file mode 100644 index 5afcbda2d3e85..0000000000000 --- a/drivers/counter/Kconfig.cc23x0_rtc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config COUNTER_CC23X0_RTC - bool "CC23x0 Counter driver based on the RTC Timer" - default y - depends on DT_HAS_TI_CC23X0_RTC_ENABLED - help - Enable counter driver based on RTC timer for cc23x0 diff --git a/drivers/counter/Kconfig.max32_wut b/drivers/counter/Kconfig.max32_wut deleted file mode 100644 index 654fd5016ec97..0000000000000 --- a/drivers/counter/Kconfig.max32_wut +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2025 Analog Devices, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config COUNTER_WUT_MAX32 - bool "MAX32xxx wake-up timer driver" - default y - depends on DT_HAS_ADI_MAX32_WUT_ENABLED - help - Enable the wake-up timer driver for MAX32 MCUs. diff --git a/drivers/counter/Kconfig.neorv32 b/drivers/counter/Kconfig.neorv32 deleted file mode 100644 index 41c154f602242..0000000000000 --- a/drivers/counter/Kconfig.neorv32 +++ /dev/null @@ -1,12 +0,0 @@ -# NEORV32 General Purpose Timer (GPTMR) -# -# Copyright (c) 2025 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config COUNTER_NEORV32_GPTMR - bool "NEORV32 GPTMR driver" - default y - depends on DT_HAS_NEORV32_GPTMR_ENABLED - depends on SYSCON - help - Enable NEORV32 General Purpose Timer (GPTMR) driver. diff --git a/drivers/counter/counter_cc23x0_rtc.c b/drivers/counter/counter_cc23x0_rtc.c deleted file mode 100644 index d651426bce8aa..0000000000000 --- a/drivers/counter/counter_cc23x0_rtc.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2024 BayLibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ti_cc23x0_rtc - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -LOG_MODULE_REGISTER(cc23x0_counter_rtc, CONFIG_COUNTER_LOG_LEVEL); - -static void counter_cc23x0_isr(const struct device *dev); - -struct counter_cc23x0_config { - struct counter_config_info counter_info; - uint32_t base; -}; - -struct counter_cc23x0_data { - struct counter_alarm_cfg alarm_cfg0; -}; - -static int counter_cc23x0_get_value(const struct device *dev, uint32_t *ticks) -{ - /* Resolution is 8us and max timeout ~9.5h */ - const struct counter_cc23x0_config *config = dev->config; - - *ticks = HWREG(config->base + RTC_O_TIME8U); - - return 0; -} - -static int counter_cc23x0_get_value_64(const struct device *dev, uint64_t *ticks) -{ - const struct counter_cc23x0_config *config = dev->config; - - /* - * RTC counter register is 67 bits, only part of the bits are accessible. - * They are split in two partially overlapping registers: - * TIME524M [50:19] - * TIME8U [34:3] - */ - - uint64_t rtc_time_now = - ((HWREG(config->base + RTC_O_TIME524M) << 16) & 0xFFFFFFF800000000) | - HWREG(config->base + RTC_O_TIME8U); - - *ticks = rtc_time_now; - - return 0; -} - -static void counter_cc23x0_isr(const struct device *dev) -{ - const struct counter_cc23x0_config *config = dev->config; - struct counter_cc23x0_data *data = dev->data; - - /* Clear RTC interrupt regs */ - HWREG(config->base + RTC_O_ICLR) = 0x3; - HWREG(config->base + RTC_O_IMCLR) = 0x3; - - uint32_t now = HWREG(config->base + RTC_O_TIME8U); - - if (data->alarm_cfg0.callback) { - data->alarm_cfg0.callback(dev, 0, now, data->alarm_cfg0.user_data); - } -} - -static int counter_cc23x0_set_alarm(const struct device *dev, uint8_t chan_id, - const struct counter_alarm_cfg *alarm_cfg) -{ - const struct counter_cc23x0_config *config = dev->config; - struct counter_cc23x0_data *data = dev->data; - - /* RTC have resolutiuon of 8us */ - if (counter_ticks_to_us(dev, alarm_cfg->ticks) <= 8) { - return -ENOTSUP; - } - - uint32_t now = HWREG(config->base + RTC_O_TIME8U); - - /* Calculate next alarm relative to current time in us */ - uint32_t next_alarm = now + (counter_ticks_to_us(dev, alarm_cfg->ticks) / 8); - - HWREG(config->base + RTC_O_CH0CC8U) = next_alarm; - HWREG(config->base + RTC_O_IMASK) = 0x1; - HWREG(config->base + RTC_O_ARMSET) = 0x1; - - HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = EVTSVT_CPUIRQ16SEL_PUBID_AON_RTC_COMB; - - IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), counter_cc23x0_isr, - DEVICE_DT_INST_GET(0), 0); - - irq_enable(DT_INST_IRQN(0)); - - data->alarm_cfg0.flags = 0; - data->alarm_cfg0.ticks = alarm_cfg->ticks; - data->alarm_cfg0.callback = alarm_cfg->callback; - data->alarm_cfg0.user_data = alarm_cfg->user_data; - - return 0; -} - -static int counter_cc23x0_cancel_alarm(const struct device *dev, uint8_t chan_id) -{ - const struct counter_cc23x0_config *config = dev->config; - - /* Unset interrupt source */ - HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = 0x0; - - /* Unarm both channels */ - HWREG(config->base + RTC_O_ARMCLR) = 0x3; - - return 0; -} - -static int counter_cc23x0_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) -{ - return -ENOTSUP; -} - -static uint32_t counter_cc23x0_get_pending_int(const struct device *dev) -{ - const struct counter_cc23x0_config *config = dev->config; - struct counter_cc23x0_data *data = dev->data; - - /* Check interrupt and mask */ - if (HWREG(config->base + RTC_O_RIS) & HWREG(config->base + RTC_O_MIS)) { - /* Clear RTC interrupt regs */ - HWREG(config->base + RTC_O_ICLR) = 0x3; - HWREG(config->base + RTC_O_IMCLR) = 0x3; - - uint32_t now = HWREG(config->base + RTC_O_TIME8U); - - if (data->alarm_cfg0.callback) { - data->alarm_cfg0.callback(dev, 0, now, data->alarm_cfg0.user_data); - } - - return 0; - } - - return -ESRCH; -} - -static uint32_t counter_cc23x0_get_top_value(const struct device *dev) -{ - ARG_UNUSED(dev); - - return -ENOTSUP; -} - -static uint32_t counter_cc23x0_get_freq(const struct device *dev) -{ - ARG_UNUSED(dev); - - /* - * From TRM clock for RTC is 24Mhz handled internally - * which is 1/2 from main 48Mhz clock = 24Mhz - * Accessible for user resolution is 8us per bit - * TIME8U [34:3] ~ 9.5h - */ - - return (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) / 2); -} - -static int counter_cc23x0_start(const struct device *dev) -{ - ARG_UNUSED(dev); - - /* RTC timer runs after power-on reset */ - - return -ENOTSUP; -} - -static int counter_cc23x0_stop(const struct device *dev) -{ - ARG_UNUSED(dev); - - /* Any reset/sleep mode, except for POR, will not stop or reset the RTC timer */ - - return -ENOTSUP; -} - -static int counter_cc23x0_init(const struct device *dev) -{ - const struct counter_cc23x0_config *config = dev->config; - - /* Clear interrupt Mask */ - HWREG(config->base + RTC_O_IMCLR) = 0x3; - - /* Clear Interrupt */ - HWREG(config->base + RTC_O_ICLR) = 0x3; - - /* Clear Armed */ - HWREG(config->base + RTC_O_ARMCLR) = 0x3; - - return 0; -} - -static const struct counter_driver_api rtc_cc23x0_api = { - .start = counter_cc23x0_start, - .stop = counter_cc23x0_stop, - .get_value = counter_cc23x0_get_value, - .get_value_64 = counter_cc23x0_get_value_64, - .set_alarm = counter_cc23x0_set_alarm, - .cancel_alarm = counter_cc23x0_cancel_alarm, - .get_top_value = counter_cc23x0_get_top_value, - .set_top_value = counter_cc23x0_set_top_value, - .get_pending_int = counter_cc23x0_get_pending_int, - .get_freq = counter_cc23x0_get_freq, -}; - -#define CC23X0_INIT(inst) \ - static const struct counter_cc23x0_config cc23x0_config_##inst = { \ - .counter_info = \ - { \ - .max_top_value = UINT32_MAX, \ - .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ - .channels = 1, \ - }, \ - .base = DT_INST_REG_ADDR(inst), \ - }; \ - \ - static struct counter_cc23x0_data cc23x0_data_##inst; \ - \ - DEVICE_DT_INST_DEFINE(0, &counter_cc23x0_init, NULL, &cc23x0_data_##inst, \ - &cc23x0_config_##inst, POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \ - &rtc_cc23x0_api); - -DT_INST_FOREACH_STATUS_OKAY(CC23X0_INIT) diff --git a/drivers/counter/counter_gecko_stimer.c b/drivers/counter/counter_gecko_stimer.c index 029ccd2d920e4..2987fcaabe743 100644 --- a/drivers/counter/counter_gecko_stimer.c +++ b/drivers/counter/counter_gecko_stimer.c @@ -15,16 +15,24 @@ #include #include +#include #include #include #include LOG_MODULE_REGISTER(counter_gecko, CONFIG_COUNTER_LOG_LEVEL); -#define DT_RTC DT_COMPAT_GET_ANY_STATUS_OKAY(silabs_gecko_stimer) +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_RTCC +#define STIMER_IRQ_HANDLER RTCC_IRQHandler +#define STIMER_MAX_VALUE _RTCC_CNT_MASK +#elif SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC +#define STIMER_IRQ_HANDLER SYSRTC_APP_IRQHandler +#define STIMER_MAX_VALUE _SYSRTC_CNT_MASK +#else +#error "Unsupported sleep timer peripheral" +#endif #define STIMER_ALARM_NUM 2 -#define STIMER_MAX_VALUE 0xFFFFFFFFUL struct counter_gecko_config { struct counter_config_info info; @@ -243,20 +251,16 @@ static uint32_t counter_gecko_get_pending_int(const struct device *dev) static int counter_gecko_init(const struct device *dev) { -#ifndef CONFIG_SILABS_SLEEPTIMER_TIMER const struct counter_gecko_config *const dev_cfg = (const struct counter_gecko_config *const)(dev)->config; -#endif struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data; - /* Avoid reconfiguring of IRQs */ -#ifndef CONFIG_SILABS_SLEEPTIMER_TIMER - dev_cfg->irq_config(); -#endif - sl_sleeptimer_init(); dev_data->top_data.ticks = STIMER_MAX_VALUE; + /* Configure & enable module interrupts */ + dev_cfg->irq_config(); + LOG_INF("Device %s initialized", (dev)->name); return 0; @@ -277,12 +281,8 @@ BUILD_ASSERT((DT_INST_PROP(0, prescaler) > 0U) && (DT_INST_PROP(0, prescaler) <= static void counter_gecko_0_irq_config(void) { -#ifndef CONFIG_SILABS_SLEEPTIMER_TIMER - IRQ_DIRECT_CONNECT(DT_IRQ(DT_RTC, irq), DT_IRQ(DT_RTC, priority), - CONCAT(DT_STRING_UPPER_TOKEN_BY_IDX(DT_RTC, interrupt_names, 0), - _IRQHandler), 0); + IRQ_DIRECT_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), STIMER_IRQ_HANDLER, 0); irq_enable(DT_INST_IRQN(0)); -#endif } static const struct counter_gecko_config counter_gecko_0_config = { @@ -299,4 +299,4 @@ static const struct counter_gecko_config counter_gecko_0_config = { static struct counter_gecko_data counter_gecko_0_data; DEVICE_DT_INST_DEFINE(0, counter_gecko_init, NULL, &counter_gecko_0_data, &counter_gecko_0_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &counter_gecko_driver_api); + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &counter_gecko_driver_api); diff --git a/drivers/counter/counter_ll_stm32_timer.c b/drivers/counter/counter_ll_stm32_timer.c index 045d2a981c15a..c7a6216ac6642 100644 --- a/drivers/counter/counter_ll_stm32_timer.c +++ b/drivers/counter/counter_ll_stm32_timer.c @@ -155,14 +155,6 @@ static int counter_stm32_get_value(const struct device *dev, uint32_t *ticks) return 0; } -static int counter_stm32_reset(const struct device *dev) -{ - const struct counter_stm32_config *config = dev->config; - - LL_TIM_SetCounter(config->timer, 0); - return 0; -} - static uint32_t counter_stm32_ticks_add(uint32_t val1, uint32_t val2, uint32_t top) { uint32_t to_top; @@ -585,7 +577,6 @@ static DEVICE_API(counter, counter_stm32_driver_api) = { .start = counter_stm32_start, .stop = counter_stm32_stop, .get_value = counter_stm32_get_value, - .reset = counter_stm32_reset, .set_alarm = counter_stm32_set_alarm, .cancel_alarm = counter_stm32_cancel_alarm, .set_top_value = counter_stm32_set_top_value, diff --git a/drivers/counter/counter_max32_wut.c b/drivers/counter/counter_max32_wut.c deleted file mode 100644 index 34730051b4bff..0000000000000 --- a/drivers/counter/counter_max32_wut.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2025 Analog Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT adi_max32_wut - -#include -#include -#include -#include - -#include -#include -#include - -LOG_MODULE_REGISTER(counter_max32_wut, CONFIG_COUNTER_LOG_LEVEL); - -#define MAX32_WUT_COUNTER_FREQ 32768 - -struct max32_wut_alarm_data { - counter_alarm_callback_t callback; - void *user_data; -}; - -struct max32_wut_data { - struct max32_wut_alarm_data alarm; - uint32_t guard_period; -}; - -struct max32_wut_config { - struct counter_config_info info; - mxc_wut_regs_t *regs; - int clock_source; - int prescaler; - void (*irq_config)(const struct device *dev); - uint32_t irq_number; - bool wakeup_source; -}; - -static int counter_max32_wut_start(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - - MXC_WUT_Enable(cfg->regs); - - return 0; -} - -static int counter_max32_wut_stop(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - - MXC_WUT_Disable(cfg->regs); - - return 0; -} - -static int counter_max32_wut_get_value(const struct device *dev, uint32_t *ticks) -{ - const struct max32_wut_config *cfg = dev->config; - - *ticks = MXC_WUT_GetCount(cfg->regs); - - return 0; -} - -static int counter_max32_wut_set_top_value(const struct device *dev, - const struct counter_top_cfg *top_cfg) -{ - ARG_UNUSED(dev); - ARG_UNUSED(top_cfg); - - return -ENOTSUP; -} - -static uint32_t counter_max32_wut_get_pending_int(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - - return MXC_WUT_GetFlags(cfg->regs); -} - -static uint32_t counter_max32_wut_get_top_value(const struct device *dev) -{ - ARG_UNUSED(dev); - - return UINT32_MAX; -} - -static uint32_t counter_max32_wut_get_freq(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - - return cfg->info.freq; -} - -static uint32_t counter_max32_wut_get_guard_period(const struct device *dev, uint32_t flags) -{ - struct max32_wut_data *data = dev->data; - - ARG_UNUSED(flags); - - return data->guard_period; -} - -static int counter_max32_wut_set_guard_period(const struct device *dev, uint32_t ticks, - uint32_t flags) -{ - struct max32_wut_data *data = dev->data; - - ARG_UNUSED(flags); - - if (ticks > counter_max32_wut_get_top_value(dev)) { - return -EINVAL; - } - - data->guard_period = ticks; - - return 0; -} - -static int counter_max32_wut_set_alarm(const struct device *dev, uint8_t chan, - const struct counter_alarm_cfg *alarm_cfg) -{ - const struct max32_wut_config *cfg = dev->config; - struct max32_wut_data *data = dev->data; - uint32_t now_ticks, top_ticks; - uint64_t abs_ticks, min_abs_ticks; - bool irq_on_late = false; - bool absolute = alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE; - - counter_max32_wut_get_value(dev, &now_ticks); - - top_ticks = counter_max32_wut_get_top_value(dev); - if (alarm_cfg->ticks > top_ticks) { - return -EINVAL; - } - - if (data->alarm.callback != NULL) { - return -EBUSY; - } - - MXC_WUT_ClearFlags(cfg->regs); - - data->alarm.callback = alarm_cfg->callback; - data->alarm.user_data = alarm_cfg->user_data; - - if (absolute) { - abs_ticks = alarm_cfg->ticks; - } else { - abs_ticks = (uint64_t)now_ticks + alarm_cfg->ticks; - } - - min_abs_ticks = (uint64_t)now_ticks + data->guard_period; - if ((!absolute && (abs_ticks < now_ticks)) || (abs_ticks > min_abs_ticks)) { - MXC_WUT_SetCompare(cfg->regs, abs_ticks & top_ticks); - MXC_WUT_Enable(cfg->regs); - return 0; - } - - irq_on_late = alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE; - if (irq_on_late || !absolute) { - NVIC_SetPendingIRQ(cfg->irq_number); - } else { - data->alarm.callback = NULL; - data->alarm.user_data = NULL; - } - - return -ETIME; -} - -static int counter_max32_wut_cancel_alarm(const struct device *dev, uint8_t chan) -{ - ARG_UNUSED(chan); - struct max32_wut_data *data = dev->data; - - counter_max32_wut_stop(dev); - - data->alarm.callback = NULL; - data->alarm.user_data = NULL; - - return 0; -} - -static void counter_max32_wut_isr(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - struct max32_wut_data *data = dev->data; - - if (data->alarm.callback) { - counter_alarm_callback_t cb = data->alarm.callback; - - data->alarm.callback = NULL; - cb(dev, 0, MXC_WUT_GetCount(cfg->regs), data->alarm.user_data); - } - - MXC_WUT_ClearFlags(cfg->regs); -} - -static void counter_max32_wut_hw_init(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - - Wrap_MXC_SYS_Select32KClockSource(cfg->clock_source); - - cfg->irq_config(dev); - - if (cfg->wakeup_source) { - MXC_LP_EnableWUTAlarmWakeup(); - } -} - -static int counter_max32_wut_init(const struct device *dev) -{ - const struct max32_wut_config *cfg = dev->config; - uint8_t prescaler_lo, prescaler_hi; - mxc_wut_pres_t pres; - mxc_wut_cfg_t wut_cfg; - - counter_max32_wut_hw_init(dev); - - prescaler_lo = FIELD_GET(GENMASK(2, 0), LOG2(cfg->prescaler)); - prescaler_hi = FIELD_GET(BIT(3), LOG2(cfg->prescaler)); - - pres = (prescaler_hi << MXC_F_WUT_CTRL_PRES3_POS) | - (prescaler_lo << MXC_F_WUT_CTRL_PRES_POS); - - MXC_WUT_Init(cfg->regs, pres); - - wut_cfg.mode = MXC_WUT_MODE_COMPARE; - wut_cfg.cmp_cnt = cfg->info.max_top_value; - MXC_WUT_Config(cfg->regs, &wut_cfg); - - MXC_WUT_SetCount(cfg->regs, 0); - - return 0; -} - -#ifdef CONFIG_PM_DEVICE -static int counter_max32_wut_pm_action(const struct device *dev, enum pm_device_action action) -{ - switch (action) { - case PM_DEVICE_ACTION_RESUME: - counter_max32_wut_hw_init(dev); - break; - case PM_DEVICE_ACTION_SUSPEND: - break; - default: - return -ENOTSUP; - } - - return 0; -} -#endif /* CONFIG_PM_DEVICE */ - -static DEVICE_API(counter, counter_max32_wut_driver_api) = { - .start = counter_max32_wut_start, - .stop = counter_max32_wut_stop, - .get_value = counter_max32_wut_get_value, - .set_top_value = counter_max32_wut_set_top_value, - .get_pending_int = counter_max32_wut_get_pending_int, - .get_top_value = counter_max32_wut_get_top_value, - .get_freq = counter_max32_wut_get_freq, - .set_alarm = counter_max32_wut_set_alarm, - .cancel_alarm = counter_max32_wut_cancel_alarm, - .get_guard_period = counter_max32_wut_get_guard_period, - .set_guard_period = counter_max32_wut_set_guard_period, -}; - -#define TIMER(_num) DT_INST_PARENT(_num) -#define MAX32_TIM(idx) ((mxc_wut_regs_t *)DT_REG_ADDR(TIMER(idx))) - -#define COUNTER_MAX32_WUT_DEFINE(_num) \ - static void max32_wut_irq_init_##_num(const struct device *dev) \ - { \ - IRQ_CONNECT(DT_IRQN(TIMER(_num)), DT_IRQ(TIMER(_num), priority), \ - counter_max32_wut_isr, DEVICE_DT_INST_GET(_num), 0); \ - irq_enable(DT_IRQN(TIMER(_num))); \ - }; \ - static const struct max32_wut_config max32_wut_config_##_num = { \ - .info = \ - { \ - .max_top_value = UINT32_MAX, \ - .freq = MAX32_WUT_COUNTER_FREQ / DT_PROP(TIMER(_num), prescaler), \ - .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ - .channels = 1, \ - }, \ - .regs = (mxc_wut_regs_t *)DT_REG_ADDR(TIMER(_num)), \ - .clock_source = \ - DT_PROP_OR(TIMER(_num), clock_source, ADI_MAX32_PRPH_CLK_SRC_ERTCO), \ - .prescaler = DT_PROP(TIMER(_num), prescaler), \ - .irq_config = max32_wut_irq_init_##_num, \ - .irq_number = DT_IRQN(TIMER(_num)), \ - .wakeup_source = DT_PROP(TIMER(_num), wakeup_source), \ - }; \ - static struct max32_wut_data max32_wut_data##_num; \ - PM_DEVICE_DT_INST_DEFINE(_num, counter_max32_wut_pm_action); \ - DEVICE_DT_INST_DEFINE(_num, &counter_max32_wut_init, PM_DEVICE_DT_INST_GET(_num), \ - &max32_wut_data##_num, &max32_wut_config_##_num, PRE_KERNEL_1, \ - CONFIG_COUNTER_INIT_PRIORITY, &counter_max32_wut_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(COUNTER_MAX32_WUT_DEFINE) diff --git a/drivers/counter/counter_mcux_ctimer.c b/drivers/counter/counter_mcux_ctimer.c index a77b64b969466..3733be0886c02 100644 --- a/drivers/counter/counter_mcux_ctimer.c +++ b/drivers/counter/counter_mcux_ctimer.c @@ -11,7 +11,6 @@ #include #include #include -#include LOG_MODULE_REGISTER(mcux_ctimer, CONFIG_COUNTER_LOG_LEVEL); @@ -249,7 +248,7 @@ static void mcux_lpc_ctimer_isr(const struct device *dev) #endif } -static int mcux_lpc_ctimer_init_common(const struct device *dev) +static int mcux_lpc_ctimer_init(const struct device *dev) { const struct mcux_lpc_ctimer_config *config = dev->config; struct mcux_lpc_ctimer_data *data = dev->data; @@ -278,32 +277,6 @@ static int mcux_lpc_ctimer_init_common(const struct device *dev) return 0; } -static int mcux_lpc_ctimer_pm_action(const struct device *dev, enum pm_device_action action) -{ - switch (action) { - case PM_DEVICE_ACTION_RESUME: - break; - case PM_DEVICE_ACTION_SUSPEND: - break; - case PM_DEVICE_ACTION_TURN_OFF: - break; - case PM_DEVICE_ACTION_TURN_ON: - mcux_lpc_ctimer_init_common(dev); - break; - default: - return -ENOTSUP; - } - return 0; -} - -static int mcux_lpc_ctimer_init(const struct device *dev) -{ - /* Rest of the init is done from the PM_DEVICE_TURN_ON action - * which is invoked by pm_device_driver_init(). - */ - return pm_device_driver_init(dev, mcux_lpc_ctimer_pm_action); -} - static DEVICE_API(counter, mcux_ctimer_driver_api) = { .start = mcux_lpc_ctimer_start, .stop = mcux_lpc_ctimer_stop, @@ -333,10 +306,8 @@ static DEVICE_API(counter, mcux_ctimer_driver_api) = { .prescale = DT_INST_PROP(id, prescale), \ .irq_config_func = mcux_lpc_ctimer_irq_config_##id, \ }; \ - PM_DEVICE_DT_INST_DEFINE(id, mcux_lpc_ctimer_pm_action); \ static struct mcux_lpc_ctimer_data mcux_lpc_ctimer_data_##id; \ - DEVICE_DT_INST_DEFINE(id, &mcux_lpc_ctimer_init, PM_DEVICE_DT_INST_GET(id), \ - &mcux_lpc_ctimer_data_##id, \ + DEVICE_DT_INST_DEFINE(id, &mcux_lpc_ctimer_init, NULL, &mcux_lpc_ctimer_data_##id, \ &mcux_lpc_ctimer_config_##id, POST_KERNEL, \ CONFIG_COUNTER_INIT_PRIORITY, &mcux_ctimer_driver_api); \ static void mcux_lpc_ctimer_irq_config_##id(const struct device *dev) \ diff --git a/drivers/counter/counter_native_sim.c b/drivers/counter/counter_native_sim.c index 8be0f8085b348..c044f8eef3df3 100644 --- a/drivers/counter/counter_native_sim.c +++ b/drivers/counter/counter_native_sim.c @@ -32,7 +32,7 @@ static struct counter_alarm_cfg pending_alarm[DRIVER_CONFIG_INFO_CHANNELS]; static bool is_alarm_pending[DRIVER_CONFIG_INFO_CHANNELS]; static struct counter_top_cfg top; static bool is_top_set; -static const struct device *dev_p; +static const struct device *device; static void schedule_next_isr(void) { @@ -67,14 +67,16 @@ static void counter_isr(const void *arg) if (is_alarm_pending[i] && (current_value == pending_alarm[i].ticks)) { is_alarm_pending[i] = false; if (pending_alarm[i].callback) { - pending_alarm[i].callback(dev_p, i, current_value, + pending_alarm[i].callback(device, i, current_value, pending_alarm[i].user_data); } } } - if (is_top_set && (current_value == top.ticks) && top.callback) { - top.callback(dev_p, top.user_data); + if (is_top_set && (current_value == top.ticks)) { + if (top.callback) { + top.callback(device, top.user_data); + } } schedule_next_isr(); @@ -82,7 +84,7 @@ static void counter_isr(const void *arg) static int ctr_init(const struct device *dev) { - dev_p = dev; + device = dev; memset(is_alarm_pending, 0, sizeof(is_alarm_pending)); is_top_set = false; top.ticks = TOP_VALUE; diff --git a/drivers/counter/counter_neorv32_gptmr.c b/drivers/counter/counter_neorv32_gptmr.c deleted file mode 100644 index 5dcc7583e3b08..0000000000000 --- a/drivers/counter/counter_neorv32_gptmr.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2025 Henrik Brix Andersen - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT neorv32_gptmr - -#include -#include -#include -#include -#include -#include - -#include - -LOG_MODULE_REGISTER(neorv32_gptmr, CONFIG_COUNTER_LOG_LEVEL); - -/* Registers */ -#define NEORV32_GPTMR_CTRL 0x00 -#define NEORV32_GPTMR_CTRL_EN BIT(0) -#define NEORV32_GPTMR_CTRL_PRSC GENMASK(3, 1) -#define NEORV32_GPTMR_CTRL_IRQ_CLR BIT(30) -#define NEORV32_GPTMR_CTRL_IRQ_PND BIT(31) - -#define NEORV32_GPTMR_THRES 0x04 -#define NEORV32_GPTMR_COUNT 0x08 - -struct neorv32_gptmr_config { - struct counter_config_info info; - const struct device *syscon; - mm_reg_t base; - uint8_t prescaler; - void (*irq_config_func)(void); -}; - -struct neorv32_gptmr_data { - struct k_spinlock lock; - counter_top_callback_t top_callback; - void *top_user_data; -}; - -static inline uint32_t neorv32_gptmr_read(const struct device *dev, uint16_t reg) -{ - const struct neorv32_gptmr_config *config = dev->config; - - return sys_read32(config->base + reg); -} - -static inline void neorv32_gptmr_write(const struct device *dev, uint16_t reg, uint32_t val) -{ - const struct neorv32_gptmr_config *config = dev->config; - - sys_write32(val, config->base + reg); -} - -static int neorv32_gptmr_start(const struct device *dev) -{ - struct neorv32_gptmr_data *data = dev->data; - k_spinlock_key_t key; - uint32_t ctrl; - - key = k_spin_lock(&data->lock); - - ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL); - ctrl |= NEORV32_GPTMR_CTRL_EN; - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl); - - k_spin_unlock(&data->lock, key); - - return 0; -} - -static int neorv32_gptmr_stop(const struct device *dev) -{ - struct neorv32_gptmr_data *data = dev->data; - k_spinlock_key_t key; - uint32_t ctrl; - - key = k_spin_lock(&data->lock); - - ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL); - ctrl &= ~NEORV32_GPTMR_CTRL_EN; - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl); - - k_spin_unlock(&data->lock, key); - - return 0; -} - -static int neorv32_gptmr_get_value(const struct device *dev, uint32_t *ticks) -{ - *ticks = neorv32_gptmr_read(dev, NEORV32_GPTMR_COUNT); - - return 0; -} - -static int neorv32_gptmr_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) -{ - struct neorv32_gptmr_data *data = dev->data; - k_spinlock_key_t key; - bool restart = false; - uint32_t count; - uint32_t ctrl; - int err = 0; - - __ASSERT_NO_MSG(cfg != NULL); - - if (cfg->ticks == 0) { - return -EINVAL; - } - - if ((cfg->flags & ~(COUNTER_TOP_CFG_DONT_RESET | COUNTER_TOP_CFG_RESET_WHEN_LATE)) != 0U) { - LOG_ERR("unsupported flags 0x%08x", cfg->flags); - return -ENOTSUP; - } - - key = k_spin_lock(&data->lock); - - data->top_callback = cfg->callback; - data->top_user_data = cfg->user_data; - - ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL); - count = neorv32_gptmr_read(dev, NEORV32_GPTMR_COUNT); - - if ((ctrl & NEORV32_GPTMR_CTRL_EN) != 0U) { - if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) == 0U) { - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl & ~NEORV32_GPTMR_CTRL_EN); - restart = true; - } else if (count >= cfg->ticks) { - if ((cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) != 0U) { - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, - ctrl & ~NEORV32_GPTMR_CTRL_EN); - restart = true; - } - - err = -ETIME; - } - } - - neorv32_gptmr_write(dev, NEORV32_GPTMR_THRES, cfg->ticks); - - if (restart) { - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl); - } - - k_spin_unlock(&data->lock, key); - - return err; -} - -static uint32_t neorv32_gptmr_get_pending_int(const struct device *dev) -{ - uint32_t ctrl; - - ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL); - - return (ctrl & NEORV32_GPTMR_CTRL_IRQ_PND) != 0 ? 1 : 0; -} - -static uint32_t neorv32_gptmr_get_top_value(const struct device *dev) -{ - return neorv32_gptmr_read(dev, NEORV32_GPTMR_THRES); -} - -static uint32_t neorv32_gptmr_get_freq(const struct device *dev) -{ - static const uint16_t prescalers[] = { 2U, 4U, 8U, 64U, 128U, 1024U, 2048U, 4096U }; - const struct neorv32_gptmr_config *config = dev->config; - uint32_t clk; - int err; - - err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_CLK, &clk); - if (err < 0) { - LOG_ERR("failed to determine clock rate (err %d)", err); - return 0U; - } - - return clk / prescalers[config->prescaler]; -} - -static void neorv32_gptmr_isr(const struct device *dev) -{ - struct neorv32_gptmr_data *data = dev->data; - counter_top_callback_t top_callback; - void *top_user_data; - k_spinlock_key_t key; - uint32_t ctrl; - - key = k_spin_lock(&data->lock); - - ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL); - ctrl |= NEORV32_GPTMR_CTRL_IRQ_CLR; - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl); - - top_callback = data->top_callback; - top_user_data = data->top_user_data; - - k_spin_unlock(&data->lock, key); - - if (top_callback != NULL) { - top_callback(dev, top_user_data); - } -} - -static int neorv32_gptmr_init(const struct device *dev) -{ - const struct neorv32_gptmr_config *config = dev->config; - uint32_t features; - uint32_t ctrl; - int err; - - if (!device_is_ready(config->syscon)) { - LOG_ERR("syscon device not ready"); - return -EINVAL; - } - - err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features); - if (err < 0) { - LOG_ERR("failed to determine implemented features (err %d)", err); - return -EIO; - } - - if ((features & NEORV32_SYSINFO_SOC_IO_GPTMR) == 0) { - LOG_ERR("neorv32 gptmr not supported"); - return -ENODEV; - } - - /* Stop timer, set prescaler, clear any pending interrupt */ - ctrl = FIELD_PREP(NEORV32_GPTMR_CTRL_PRSC, config->prescaler) | NEORV32_GPTMR_CTRL_IRQ_CLR; - neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl); - - config->irq_config_func(); - - return 0; -} - -static DEVICE_API(counter, neorv32_gptmr_driver_api) = { - .start = neorv32_gptmr_start, - .stop = neorv32_gptmr_stop, - .get_value = neorv32_gptmr_get_value, - .set_top_value = neorv32_gptmr_set_top_value, - .get_pending_int = neorv32_gptmr_get_pending_int, - .get_top_value = neorv32_gptmr_get_top_value, - .get_freq = neorv32_gptmr_get_freq, -}; - -#define COUNTER_NEORV32_GPTMR_INIT(n) \ - static void neorv32_gptmr_config_func_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), neorv32_gptmr_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - } \ - \ - static struct neorv32_gptmr_data neorv32_gptmr_data_##n; \ - \ - static struct neorv32_gptmr_config neorv32_gptmr_config_##n = { \ - .info = { \ - .max_top_value = UINT32_MAX, \ - .freq = 0U, \ - .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ - .channels = 0, \ - }, \ - .syscon = DEVICE_DT_GET(DT_INST_PHANDLE(n, syscon)), \ - .base = DT_INST_REG_ADDR(n), \ - .prescaler = DT_INST_ENUM_IDX(n, prescaler), \ - .irq_config_func = neorv32_gptmr_config_func_##n, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, &neorv32_gptmr_init, NULL, &neorv32_gptmr_data_##n, \ - &neorv32_gptmr_config_##n, POST_KERNEL, \ - CONFIG_COUNTER_INIT_PRIORITY, &neorv32_gptmr_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(COUNTER_NEORV32_GPTMR_INIT) diff --git a/drivers/counter/counter_nxp_mrt.c b/drivers/counter/counter_nxp_mrt.c index b08a6765fc42c..db4ca47303fb3 100644 --- a/drivers/counter/counter_nxp_mrt.c +++ b/drivers/counter/counter_nxp_mrt.c @@ -22,7 +22,6 @@ #include #include #include -#include #include @@ -209,7 +208,7 @@ uint32_t nxp_mrt_get_freq(const struct device *dev) return freq; } -static int nxp_mrt_init_common(const struct device *dev) +static int nxp_mrt_init(const struct device *dev) { const struct nxp_mrt_config *config = dev->config; MRT_Type *base = config->base; @@ -240,32 +239,6 @@ static int nxp_mrt_init_common(const struct device *dev) return 0; } -static int nxp_mrt_pm_action(const struct device *dev, enum pm_device_action action) -{ - switch (action) { - case PM_DEVICE_ACTION_RESUME: - break; - case PM_DEVICE_ACTION_SUSPEND: - break; - case PM_DEVICE_ACTION_TURN_OFF: - break; - case PM_DEVICE_ACTION_TURN_ON: - nxp_mrt_init_common(dev); - break; - default: - return -ENOTSUP; - } - return 0; -} - -static int nxp_mrt_init(const struct device *dev) -{ - /* Rest of the init is done from the PM_DEVICE_TURN_ON action - * which is invoked by pm_device_driver_init(). - */ - return pm_device_driver_init(dev, nxp_mrt_pm_action); -} - static void nxp_mrt_isr(const struct device *dev) { const struct nxp_mrt_config *config = dev->config; @@ -375,10 +348,8 @@ DEVICE_API(counter, nxp_mrt_api) = { .reset = RESET_DT_SPEC_INST_GET(n), \ }; \ \ - PM_DEVICE_DT_INST_DEFINE(n, nxp_mrt_pm_action); \ - \ /* Init parent device in order to handle ISR and init. */ \ - DEVICE_DT_INST_DEFINE(n, &nxp_mrt_init, PM_DEVICE_DT_INST_GET(n), NULL, \ + DEVICE_DT_INST_DEFINE(n, &nxp_mrt_init, NULL, NULL, \ &nxp_mrt_##n##_config, \ POST_KERNEL, \ CONFIG_COUNTER_INIT_PRIORITY, NULL); diff --git a/drivers/counter/counter_renesas_ra_agt.c b/drivers/counter/counter_renesas_ra_agt.c index b29ae3d8a2902..535e37086c6f5 100644 --- a/drivers/counter/counter_renesas_ra_agt.c +++ b/drivers/counter/counter_renesas_ra_agt.c @@ -73,8 +73,8 @@ static int counter_ra_agt_start(const struct device *dev) reg->AGTCR = AGT_AGTCR_START_TIMER; - while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) { - } + while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) + ; return timeout > 0 ? 0 : -EIO; } @@ -86,8 +86,8 @@ static int counter_ra_agt_stop(const struct device *dev) reg->AGTCR = AGT_AGTCR_STOP_TIMER; - while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) { - } + while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) + ; return timeout > 0 ? 0 : -EIO; } diff --git a/drivers/counter/rtc_mcp7940n.c b/drivers/counter/rtc_mcp7940n.c index 288b8a7fc6b5a..38ffd93463d9a 100644 --- a/drivers/counter/rtc_mcp7940n.c +++ b/drivers/counter/rtc_mcp7940n.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2019-2020 Peter Bigot Consulting, LLC * Copyright (c) 2021 Laird Connectivity - * Copyright (c) 2025 Marcin Lyda * * SPDX-License-Identifier: Apache-2.0 */ @@ -51,7 +50,6 @@ struct mcp7940n_config { struct counter_config_info generic; struct i2c_dt_spec i2c; const struct gpio_dt_spec int_gpios; - bool vbat_enable; }; struct mcp7940n_data { @@ -680,10 +678,6 @@ static int mcp7940n_init(const struct device *dev) goto out; } - /* Configure VBat enable */ - data->registers.rtc_weekday.vbaten = cfg->vbat_enable; - - /* Set day of week and update VBat enable config */ rc = set_day_of_week(dev, &unix_time); if (rc < 0) { goto out; @@ -699,6 +693,7 @@ static int mcp7940n_init(const struct device *dev) /* Configure alarm interrupt gpio */ if (cfg->int_gpios.port != NULL) { + if (!gpio_is_ready_dt(&cfg->int_gpios)) { LOG_ERR("Port device %s is not ready", cfg->int_gpios.port->name); @@ -762,7 +757,6 @@ static DEVICE_API(counter, mcp7940n_api) = { }, \ .i2c = I2C_DT_SPEC_INST_GET(index), \ .int_gpios = GPIO_DT_SPEC_INST_GET_OR(index, int_gpios, {0}), \ - .vbat_enable = DT_INST_PROP(index, vbat_enable) \ }; \ \ DEVICE_DT_INST_DEFINE(index, mcp7940n_init, NULL, \ diff --git a/drivers/crypto/CMakeLists.txt b/drivers/crypto/CMakeLists.txt index a84a191642b30..5094377abb137 100644 --- a/drivers/crypto/CMakeLists.txt +++ b/drivers/crypto/CMakeLists.txt @@ -10,7 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_NRF_ECB crypto_nrf_ecb.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_INTEL_SHA crypto_intel_sha.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_NPCX_SHA crypto_npcx_sha.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCHP_XEC_SYMCR crypto_mchp_xec_symcr.c) -zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT51XXX_SHA crypto_it51xxx_sha.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA crypto_it8xxx2_sha.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA_V2 crypto_it8xxx2_sha_v2.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP crypto_mcux_dcp.c) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 0a609e3fce550..9a7bdb89b54ee 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -80,7 +80,6 @@ source "drivers/crypto/Kconfig.nrf_ecb" source "drivers/crypto/Kconfig.intel" source "drivers/crypto/Kconfig.npcx" source "drivers/crypto/Kconfig.xec" -source "drivers/crypto/Kconfig.it51xxx" source "drivers/crypto/Kconfig.it8xxx2" source "drivers/crypto/Kconfig.mcux_dcp" source "drivers/crypto/Kconfig.si32" diff --git a/drivers/crypto/Kconfig.it51xxx b/drivers/crypto/Kconfig.it51xxx deleted file mode 100644 index 8cda3a7788733..0000000000000 --- a/drivers/crypto/Kconfig.it51xxx +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2025 ITE Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config CRYPTO_IT51XXX_SHA - bool "ITE IT51XXX SHA driver" - default y - depends on DT_HAS_ITE_IT51XXX_SHA_ENABLED - select SOC_IT51XXX_SHA256_HW_ACCELERATE - help - The IT51XXX hardware supports SHA-256 calculation, which is faster than - the firmware implementation. diff --git a/drivers/crypto/crypto_it51xxx_sha.c b/drivers/crypto/crypto_it51xxx_sha.c deleted file mode 100644 index bd20c29b25fac..0000000000000 --- a/drivers/crypto/crypto_it51xxx_sha.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2025 ITE Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ite_it51xxx_sha - -#include -#include -#include -#include -#include - -#include -LOG_MODULE_REGISTER(crypto_it51xxx_sha, CONFIG_CRYPTO_LOG_LEVEL); - -#define IT51XXX_SHA_REGS_BASE DT_REG_ADDR(DT_NODELABEL(sha256)) - -/* 0x00: SHA Control Register (SHACR) */ -#define IT51XXX_SHACR (IT51XXX_SHA_REGS_BASE + 0x00) -#define IT51XXX_SHAWB BIT(2) -#define IT51XXX_SHAINI BIT(1) -#define IT51XXX_SHAEXE BIT(0) -/* 0x01: SHA Status Register (SHASR)*/ -#define IT51XXX_SHASR (IT51XXX_SHA_REGS_BASE + 0x01) -#define IT51XXX_SHAIE BIT(3) -#define IT51XXX_SHAIS BIT(2) -#define IT51XXX_SHABUSY BIT(0) -/* 0x02: SHA Execution Counter Register (SHAECR) */ -#define IT51XXX_SHAECR (IT51XXX_SHA_REGS_BASE + 0x02) -#define IT51XXX_SHAEXEC_64_BYTE 0x00 -#define IT51XXX_SHAEXEC_1K_BYTE 0x0F -/* 0x03: SHA DLM Base Address 0 Register (SHADBA0R) */ -#define IT51XXX_SHADBA0R (IT51XXX_SHA_REGS_BASE + 0x03) -/* 0x04: SHA DLM Base Address 1 Register (SHADBA1R) */ -#define IT51XXX_SHADBA1R (IT51XXX_SHA_REGS_BASE + 0x04) -/* 0x05: SHA Setting Register (SHASETR) */ -#define IT51XXX_SHASETR (IT51XXX_SHA_REGS_BASE + 0x05) -#define IT51XXX_SHA256 0x00 -/* 0x06: SHA DLM Base Address 2 Register (SHADBA2R) */ -#define IT51XXX_SHADBA2R (IT51XXX_SHA_REGS_BASE + 0x06) - -#define SHA_SHA256_HASH_LEN 32 -#define SHA_SHA256_BLOCK_LEN 64 -#define SHA_SHA256_HASH_LEN_WORDS (SHA_SHA256_HASH_LEN / sizeof(uint32_t)) -#define SHA_SHA256_BLOCK_LEN_WORDS (SHA_SHA256_BLOCK_LEN / sizeof(uint32_t)) - -/* - * If the input message is more than 1K bytes, taking 10K bytes for example, - * it should run 10 times SHA hardwired loading and execution, and process 1K bytes each time. - */ -#define SHA_HW_MAX_INPUT_LEN 1024 -#define SHA_HW_MAX_INPUT_LEN_WORDS (SHA_HW_MAX_INPUT_LEN / sizeof(uint32_t)) - -/* - * This struct is used by the hardware and must be stored in RAM first 4k-byte - * and aligned on a 256-byte boundary. - */ -struct chip_sha256_ctx { - union { - /* SHA data buffer */ - uint32_t w_sha[SHA_HW_MAX_INPUT_LEN_WORDS]; - uint8_t w_input[SHA_HW_MAX_INPUT_LEN]; - }; - /* H[0] ~ H[7] */ - uint32_t h[SHA_SHA256_HASH_LEN_WORDS]; - uint32_t sha_init; - uint32_t w_input_index; - uint32_t total_len; -} __aligned(256); - -Z_GENERIC_SECTION(.__sha256_ram_block) struct chip_sha256_ctx chip_ctx; - -static void it51xxx_sha256_init(bool init_k) -{ - chip_ctx.sha_init = init_k; - chip_ctx.total_len = 0; - chip_ctx.w_input_index = 0; - - /* Set DLM address for input data */ - sys_write8(((uint32_t)&chip_ctx) & 0xC0, IT51XXX_SHADBA0R); - sys_write8(((uint32_t)&chip_ctx) >> 8, IT51XXX_SHADBA1R); - sys_write8(((uint32_t)&chip_ctx) >> 16, IT51XXX_SHADBA2R); -} - -static void it51xxx_sha256_module_calculation(void) -{ - uint32_t key; - - /* - * Global interrupt is disabled because the CPU cannot access memory - * via the DLM (Data Local Memory) bus while HW module is computing - * hash. - */ - key = irq_lock(); - - if (chip_ctx.sha_init) { - chip_ctx.sha_init = 0; - sys_write8(IT51XXX_SHAINI | IT51XXX_SHAEXE, IT51XXX_SHACR); - } else { - sys_write8(IT51XXX_SHAEXE, IT51XXX_SHACR); - } - - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - sys_write8(IT51XXX_SHAIS, IT51XXX_SHASR); - - irq_unlock(key); - - chip_ctx.w_input_index = 0; -} - -static int it51xxx_hash_handler(struct hash_ctx *ctx, struct hash_pkt *pkt, bool finish) -{ - uint32_t i; - uint32_t in_buf_idx = 0; - uint32_t key; - uint32_t rem_len = pkt->in_len; - - /* data length >= 1KiB */ - while (rem_len >= SHA_HW_MAX_INPUT_LEN) { - rem_len = rem_len - SHA_HW_MAX_INPUT_LEN; - - for (i = 0; i < SHA_HW_MAX_INPUT_LEN; i++) { - chip_ctx.w_input[chip_ctx.w_input_index++] = pkt->in_buf[in_buf_idx++]; - } - - /* HW automatically load 1KB data from DLM */ - sys_write8(IT51XXX_SHAEXEC_1K_BYTE, IT51XXX_SHAECR); - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - - it51xxx_sha256_module_calculation(); - } - - /* 0 <= data length < 1KiB */ - while (rem_len) { - rem_len--; - chip_ctx.w_input[chip_ctx.w_input_index++] = pkt->in_buf[in_buf_idx++]; - - /* - * If fill full 64byte then execute HW calculation. - * If not, will execute in later finish block. - */ - if (chip_ctx.w_input_index >= SHA_SHA256_BLOCK_LEN) { - /* HW automatically load 64 bytes data from DLM */ - sys_write8(IT51XXX_SHAEXEC_64_BYTE, IT51XXX_SHAECR); - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - - it51xxx_sha256_module_calculation(); - } - } - - chip_ctx.total_len += pkt->in_len; - - if (finish) { - uint32_t *out_buf_ptr = (uint32_t *)pkt->out_buf; - - /* Pre-processing (Padding) */ - chip_ctx.w_input[chip_ctx.w_input_index++] = 0x80; - memset(&chip_ctx.w_input[chip_ctx.w_input_index], 0, - SHA_SHA256_BLOCK_LEN - chip_ctx.w_input_index); - - /* - * Handles the boundary case of rest data: - * Because the last eight bytes are bit length field of SHA256 rule. - * If the data index >= 56, it needs to trigger HW to calculate, - * then fill 0 data and the last eight bytes bit length, and calculate - * again. - */ - if (chip_ctx.w_input_index >= 56) { - /* HW automatically load 64Bytes data from DLM */ - sys_write8(IT51XXX_SHAEXEC_64_BYTE, IT51XXX_SHAECR); - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - - it51xxx_sha256_module_calculation(); - - memset(&chip_ctx.w_input[chip_ctx.w_input_index], 0, - SHA_SHA256_BLOCK_LEN - chip_ctx.w_input_index); - } - - /* - * Since input data (big-endian) are copied 1byte by 1byte to - * it51xxx memory (little-endian), so the bit length needs to - * be transformed into big-endian format and then write to memory. - */ - chip_ctx.w_sha[15] = sys_cpu_to_be32(chip_ctx.total_len * 8); - - /* HW automatically load 64Bytes data from DLM */ - sys_write8(IT51XXX_SHAEXEC_64_BYTE, IT51XXX_SHAECR); - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - - it51xxx_sha256_module_calculation(); - - /* HW write back the hash result to DLM */ - /* Set DLM address for input data */ - sys_write8(((uint32_t)&chip_ctx.h) & 0xC0, IT51XXX_SHADBA0R); - sys_write8(((uint32_t)&chip_ctx.h) >> 8, IT51XXX_SHADBA1R); - - key = irq_lock(); - - sys_write8(IT51XXX_SHAWB, IT51XXX_SHACR); - while (sys_read8(IT51XXX_SHASR) & IT51XXX_SHABUSY) { - }; - - sys_write8(IT51XXX_SHAIS, IT51XXX_SHASR); - - irq_unlock(key); - - for (i = 0; i < SHA_SHA256_HASH_LEN_WORDS; i++) { - out_buf_ptr[i] = chip_ctx.h[i]; - } - - it51xxx_sha256_init(true); - } - - return 0; -} - -static int it51xxx_hash_session_free(const struct device *dev, struct hash_ctx *ctx) -{ - it51xxx_sha256_init(true); - - return 0; -} - -static inline int it51xxx_query_hw_caps(const struct device *dev) -{ - return (CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS); -} - -static int it51xxx_hash_begin_session(const struct device *dev, struct hash_ctx *ctx, - enum hash_algo algo) -{ - if (algo != CRYPTO_HASH_ALGO_SHA256) { - LOG_ERR("Unsupported algorithm"); - return -EINVAL; - } - - if (ctx->flags & ~(it51xxx_query_hw_caps(dev))) { - LOG_ERR("Unsupported flag"); - return -EINVAL; - } - - it51xxx_sha256_init(true); - ctx->hash_hndlr = it51xxx_hash_handler; - - return 0; -} - -static int it51xxx_sha_init(const struct device *dev) -{ - it51xxx_sha256_init(true); - - /* Select SHA-2 Family, SHA-256 */ - sys_write8(IT51XXX_SHA256, IT51XXX_SHASETR); - - /* SHA interrupt disable */ - sys_write8(sys_read8(IT51XXX_SHASR) & ~IT51XXX_SHAIE, IT51XXX_SHASR); - - return 0; -} - -static DEVICE_API(crypto, it51xxx_crypto_api) = { - .hash_begin_session = it51xxx_hash_begin_session, - .hash_free_session = it51xxx_hash_session_free, - .query_hw_caps = it51xxx_query_hw_caps, -}; - -DEVICE_DT_INST_DEFINE(0, &it51xxx_sha_init, NULL, NULL, NULL, POST_KERNEL, - CONFIG_CRYPTO_INIT_PRIORITY, &it51xxx_crypto_api); -BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "support only one sha compatible node"); diff --git a/drivers/dac/CMakeLists.txt b/drivers/dac/CMakeLists.txt index a190bd0885d14..cd719fa718528 100644 --- a/drivers/dac/CMakeLists.txt +++ b/drivers/dac/CMakeLists.txt @@ -6,7 +6,6 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_LPDAC dac_mcux_lpdac.c) zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_DAC dac_mcux_dac.c) -zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_DAC12 dac_mcux_dac12.c) zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_DAC32 dac_mcux_dac32.c) zephyr_library_sources_ifdef(CONFIG_DAC_STM32 dac_stm32.c) zephyr_library_sources_ifdef(CONFIG_DAC_SAM dac_sam.c) diff --git a/drivers/dac/Kconfig.mcux b/drivers/dac/Kconfig.mcux index 1d43d883a0bc7..417e1b9be943a 100644 --- a/drivers/dac/Kconfig.mcux +++ b/drivers/dac/Kconfig.mcux @@ -11,13 +11,6 @@ config DAC_MCUX_DAC help Enable the driver for the NXP Kinetis MCUX DAC. -config DAC_MCUX_DAC12 - bool "NXP MCUX DAC12 driver" - default y - depends on DT_HAS_NXP_DAC12_ENABLED - help - Enable the driver for the NXP MCUX DAC12. - config DAC_MCUX_DAC32 bool "NXP Kinetis MCUX DAC32 driver" default y diff --git a/drivers/dac/dac_mcux_dac12.c b/drivers/dac/dac_mcux_dac12.c deleted file mode 100644 index 08b3c51080cb7..0000000000000 --- a/drivers/dac/dac_mcux_dac12.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2020 Henrik Brix Andersen - * Copyright (c) 2023, NXP - * Copyright (c) 2025 PHYTEC America LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nxp_dac12 - -#include -#include -#include - -#include - -LOG_MODULE_REGISTER(dac_mcux_dac12, CONFIG_DAC_LOG_LEVEL); - -struct mcux_dac12_config { - DAC_Type *base; - dac12_reference_voltage_source_t reference; - bool buffered; -}; - -struct mcux_dac12_data { - bool configured; -}; - -static int mcux_dac12_channel_setup(const struct device *dev, - const struct dac_channel_cfg *channel_cfg) -{ - const struct mcux_dac12_config *config = dev->config; - struct mcux_dac12_data *data = dev->data; - dac12_config_t dac12_config; - - if (channel_cfg->channel_id != 0) { - LOG_ERR("unsupported channel %d", channel_cfg->channel_id); - return -ENOTSUP; - } - - if (channel_cfg->resolution != 12) { - LOG_ERR("unsupported resolution %d", channel_cfg->resolution); - return -ENOTSUP; - } - - if (channel_cfg->internal) { - LOG_ERR("Internal channels not supported"); - return -ENOTSUP; - } - - DAC12_GetDefaultConfig(&dac12_config); - dac12_config.referenceVoltageSource = config->reference; - - DAC12_Init(config->base, &dac12_config); - DAC12_Enable(config->base, true); - - data->configured = true; - - return 0; -} - -static int mcux_dac12_write_value(const struct device *dev, uint8_t channel, uint32_t value) -{ - const struct mcux_dac12_config *config = dev->config; - struct mcux_dac12_data *data = dev->data; - - if (!data->configured) { - LOG_ERR("channel not initialized"); - return -EINVAL; - } - - if (channel != 0) { - LOG_ERR("unsupported channel %d", channel); - return -ENOTSUP; - } - - if (value >= 4096) { - LOG_ERR("value %d out of range", value); - return -EINVAL; - } - - DAC12_SetData(config->base, value); - - return 0; -} - -static const struct dac_driver_api mcux_dac12_driver_api = { - .channel_setup = mcux_dac12_channel_setup, - .write_value = mcux_dac12_write_value, -}; - -#define TO_DAC12_VREF_SRC(val) _DO_CONCAT(kDAC12_ReferenceVoltageSourceAlt, val) - -#define MCUX_DAC12_INIT(n) \ - static struct mcux_dac12_data mcux_dac12_data_##n; \ - \ - static const struct mcux_dac12_config mcux_dac12_config_##n = { \ - .base = (DAC_Type *)DT_INST_REG_ADDR(n), \ - .reference = \ - TO_DAC12_VREF_SRC(DT_INST_PROP(n, voltage_reference)), \ - .buffered = DT_INST_PROP(n, buffered), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, NULL, NULL, \ - &mcux_dac12_data_##n, \ - &mcux_dac12_config_##n, \ - POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \ - &mcux_dac12_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(MCUX_DAC12_INIT) diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index 0a7b48a89378f..5123faeafd085 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -16,15 +16,10 @@ zephyr_library_sources_ifdef(CONFIG_IST3931 display_ist3931.c) zephyr_library_sources_ifdef(CONFIG_LS0XX ls0xx.c) zephyr_library_sources_ifdef(CONFIG_MAX7219 display_max7219.c) zephyr_library_sources_ifdef(CONFIG_OTM8009A display_otm8009a.c) -zephyr_library_sources_ifdef(CONFIG_SH1122 display_sh1122.c) -zephyr_library_sources_ifdef(CONFIG_SSD1320 display_ssd1320.c) zephyr_library_sources_ifdef(CONFIG_SSD1306 ssd1306.c) zephyr_library_sources_ifdef(CONFIG_SSD1327 ssd1327.c) zephyr_library_sources_ifdef(CONFIG_SSD16XX ssd16xx.c) zephyr_library_sources_ifdef(CONFIG_SSD1322 ssd1322.c) -zephyr_library_sources_ifdef(CONFIG_SSD1331 display_ssd1331.c) -zephyr_library_sources_ifdef(CONFIG_SSD1351 display_ssd1351.c) -zephyr_library_sources_ifdef(CONFIG_ST75256 display_st75256.c) zephyr_library_sources_ifdef(CONFIG_ST7567 display_st7567.c) zephyr_library_sources_ifdef(CONFIG_ST7789V display_st7789v.c) zephyr_library_sources_ifdef(CONFIG_ST7735R display_st7735r.c) diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index e51afc012476a..08de8a09ce532 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -26,15 +26,10 @@ source "drivers/display/Kconfig.nrf_led_matrix" source "drivers/display/Kconfig.ili9xxx" source "drivers/display/Kconfig.ist3931" source "drivers/display/Kconfig.sdl" -source "drivers/display/Kconfig.sh1122" source "drivers/display/Kconfig.ssd1306" -source "drivers/display/Kconfig.ssd1320" source "drivers/display/Kconfig.ssd1327" source "drivers/display/Kconfig.ssd16xx" source "drivers/display/Kconfig.ssd1322" -source "drivers/display/Kconfig.ssd1331" -source "drivers/display/Kconfig.ssd1351" -source "drivers/display/Kconfig.st75256" source "drivers/display/Kconfig.st7567" source "drivers/display/Kconfig.st7735r" source "drivers/display/Kconfig.st7789v" diff --git a/drivers/display/Kconfig.led_strip_matrix b/drivers/display/Kconfig.led_strip_matrix index a3dbacca0d9a8..1230a83ce678b 100644 --- a/drivers/display/Kconfig.led_strip_matrix +++ b/drivers/display/Kconfig.led_strip_matrix @@ -5,7 +5,7 @@ config LED_STRIP_MATRIX bool "LED strip matrix display driver" default y depends on DT_HAS_LED_STRIP_MATRIX_ENABLED - select LED_STRIP + depends on LED_STRIP help Enable LED strip matrix display (LED strip arranged in a grid pattern) driver. diff --git a/drivers/display/Kconfig.sh1122 b/drivers/display/Kconfig.sh1122 deleted file mode 100644 index 30b78d07a0219..0000000000000 --- a/drivers/display/Kconfig.sh1122 +++ /dev/null @@ -1,23 +0,0 @@ -# SH1122 display controller configuration options -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -menuconfig SH1122 - bool "SH1122 display controller driver" - default y - depends on DT_HAS_SINOWEALTH_SH1122_ENABLED - select MIPI_DBI if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1122),mipi-dbi) - select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1122),i2c) - help - Enable driver for SH1122 display controller. - -if SH1122 - -config SH1122_DEFAULT_CONTRAST - int "SH1122 default contrast" - default 16 - range 0 255 - help - SH1122 default contrast. - -endif # SH1122 diff --git a/drivers/display/Kconfig.ssd1320 b/drivers/display/Kconfig.ssd1320 deleted file mode 100644 index c6e94ddd4f150..0000000000000 --- a/drivers/display/Kconfig.ssd1320 +++ /dev/null @@ -1,28 +0,0 @@ -# SSD1320 display controller configuration options -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -menuconfig SSD1320 - bool "SSD1320 display controller driver" - default y - depends on DT_HAS_SOLOMON_SSD1320_ENABLED - select MIPI_DBI if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1320),mipi-dbi) - select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1320),i2c) - help - Enable driver for SSD1320 display controller. - -if SSD1320 - -config SSD1320_DEFAULT_CONTRAST - int "SSD1320 default contrast" - default 128 - range 0 255 - help - SSD1320 default contrast. - -config SSD1320_CONV_BUFFER_LINES - int "How many lines can the conversion buffer hold" - default 16 - range 1 160 - -endif # SSD1327 diff --git a/drivers/display/Kconfig.ssd1327 b/drivers/display/Kconfig.ssd1327 index f109d169ecea9..1afd3d3566c5c 100644 --- a/drivers/display/Kconfig.ssd1327 +++ b/drivers/display/Kconfig.ssd1327 @@ -4,11 +4,10 @@ # SPDX-License-Identifier: Apache-2.0 menuconfig SSD1327 - bool "SSD1327 display controller driver" + bool "SSD1327 display driver" default y depends on DT_HAS_SOLOMON_SSD1327FB_ENABLED - select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1327FB),i2c) - select MIPI_DBI if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1327FB),mipi-dbi) + select MIPI_DBI help Enable driver for SSD1327 display. @@ -21,9 +20,4 @@ config SSD1327_DEFAULT_CONTRAST help SSD1327 default contrast. -config SSD1327_CONV_BUFFER_LINES - int "How many lines can the conversion buffer hold" - default 1 - range 1 128 - endif # SSD1327 diff --git a/drivers/display/Kconfig.ssd1331 b/drivers/display/Kconfig.ssd1331 deleted file mode 100644 index d121b84c63fdd..0000000000000 --- a/drivers/display/Kconfig.ssd1331 +++ /dev/null @@ -1,43 +0,0 @@ -# SSD1331 display controller configuration options -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -menuconfig SSD1331 - bool "SSD1331 display controller driver" - default y - depends on DT_HAS_SOLOMON_SSD1331_ENABLED - select MIPI_DBI - help - Enable driver for SSD1331 display controller. - -if SSD1331 - -config SSD1331_DEFAULT_CONTRAST - int "SSD1331 default contrast" - default 100 - range 0 255 - help - SSD1331 default contrast. - -config SSD1331_CONTRASTA - int "SSD1331 contrast multiplier for seg A" - default 145 - range 0 255 - help - Contrast multiplier for seg A - -config SSD1331_CONTRASTB - int "SSD1331 contrast multiplier for seg B" - default 80 - range 0 255 - help - Contrast multiplier for seg B - -config SSD1331_CONTRASTC - int "SSD1331 contrast multiplier for seg C" - default 125 - range 0 255 - help - Contrast multiplier for seg C - -endif # SSD1331 diff --git a/drivers/display/Kconfig.ssd1351 b/drivers/display/Kconfig.ssd1351 deleted file mode 100644 index 97d903329a165..0000000000000 --- a/drivers/display/Kconfig.ssd1351 +++ /dev/null @@ -1,43 +0,0 @@ -# SSD1351 display controller configuration options -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -menuconfig SSD1351 - bool "SSD1351 display controller driver" - default y - depends on DT_HAS_SOLOMON_SSD1351_ENABLED - select MIPI_DBI - help - Enable driver for SSD1351 display controller. - -if SSD1351 - -config SSD1351_DEFAULT_CONTRAST - int "SSD1351 default contrast" - default 100 - range 0 255 - help - SSD1351 default contrast. - -config SSD1351_CONTRASTA - int "SSD1351 contrast multiplier for seg A" - default 145 - range 0 255 - help - Contrast multiplier for seg A - -config SSD1351_CONTRASTB - int "SSD1351 contrast multiplier for seg B" - default 80 - range 0 255 - help - Contrast multiplier for seg B - -config SSD1351_CONTRASTC - int "SSD1351 contrast multiplier for seg C" - default 125 - range 0 255 - help - Contrast multiplier for seg C - -endif # SSD1351 diff --git a/drivers/display/Kconfig.st75256 b/drivers/display/Kconfig.st75256 deleted file mode 100644 index 53b20aa3ad04f..0000000000000 --- a/drivers/display/Kconfig.st75256 +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -menuconfig ST75256 - bool "ST75256 display controller" - default y - depends on DT_HAS_SITRONIX_ST75256_ENABLED - select MIPI_DBI - help - Enable driver for ST75256 display controller. - -if ST75256 - -config ST75256_DEFAULT_CONTRAST - int "ST75256 default contrast" - default 155 - range 0 255 - help - ST75256 default contrast. - -config ST75256_DEFAULT_GREYSCALE - bool "ST75256 default mode is greyscale" - help - Sets greyscale mode as default mode - -config ST75256_CONV_BUFFER_LINES - int "How many lines can the conversion buffer hold" - default 16 - range 1 162 - -endif # ST75256 diff --git a/drivers/display/Kconfig.stm32_ltdc b/drivers/display/Kconfig.stm32_ltdc index eda2bf0cac715..6b74d3d0e794e 100644 --- a/drivers/display/Kconfig.stm32_ltdc +++ b/drivers/display/Kconfig.stm32_ltdc @@ -56,17 +56,6 @@ config STM32_LTDC_FB_NUM config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP bool "Use shared multi heap for the display buffer" -config STM32_LTDC_FB_SMH_ATTRIBUTE - int "Shared multi heap attribute for the display buffer" - depends on STM32_LTDC_FB_USE_SHARED_MULTI_HEAP - default 0 - range 0 2 - help - Shared multi heap attribute for the display buffer: - 0: SMH_REG_ATTR_CACHEABLE - 1: SMH_REG_ATTR_NON_CACHEABLE - 2: SMH_REG_ATTR_EXTERNAL - config STM32_LTDC_DISABLE_FMC_BANK1 bool "Disable FMC bank1 for STM32F7/H7 series" depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32F7X diff --git a/drivers/display/display_mcux_elcdif.c b/drivers/display/display_mcux_elcdif.c index bdde9f59ed90c..8de6fb56ab922 100644 --- a/drivers/display/display_mcux_elcdif.c +++ b/drivers/display/display_mcux_elcdif.c @@ -224,24 +224,24 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u static int mcux_elcdif_display_blanking_off(const struct device *dev) { -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) + #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) const struct mcux_elcdif_config *config = dev->config; if (config->backlight_gpio.port) { return gpio_pin_set_dt(&config->backlight_gpio, 1); } -#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) */ + #endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) */ return -ENOSYS; } static int mcux_elcdif_display_blanking_on(const struct device *dev) { -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) + #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) const struct mcux_elcdif_config *config = dev->config; if (config->backlight_gpio.port) { return gpio_pin_set_dt(&config->backlight_gpio, 0); } -#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) */ + #endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) */ return -ENOSYS; } @@ -338,14 +338,14 @@ static int mcux_elcdif_init(const struct device *dev) return err; } -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) + #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) if (config->backlight_gpio.port) { err = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT_ACTIVE); if (err) { return err; } } -#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpios) */ + #endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */ k_sem_init(&dev_data->sem, 0, 1); #ifdef CONFIG_MCUX_ELCDIF_PXP diff --git a/drivers/display/display_sdl.c b/drivers/display/display_sdl.c index 27944de3212a6..e03232da9054e 100644 --- a/drivers/display/display_sdl.c +++ b/drivers/display/display_sdl.c @@ -47,7 +47,6 @@ struct sdl_display_task { struct sdl_display_config { uint16_t height; uint16_t width; - const char *title; }; struct sdl_display_data { @@ -117,13 +116,14 @@ static void sdl_task_thread(void *p1, void *p2, void *p3) sdl_display_zoom_pct = CONFIG_SDL_DISPLAY_ZOOM_PCT; } - int rc = sdl_display_init_bottom( - config->height, config->width, sdl_display_zoom_pct, use_accelerator, - &disp_data->window, dev, config->title, &disp_data->renderer, &disp_data->mutex, - &disp_data->texture, &disp_data->read_texture, &disp_data->background_texture, - CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_1, - CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_2, - CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_SIZE); + int rc = sdl_display_init_bottom(config->height, config->width, sdl_display_zoom_pct, + use_accelerator, &disp_data->window, dev, + &disp_data->renderer, &disp_data->mutex, + &disp_data->texture, &disp_data->read_texture, + &disp_data->background_texture, + CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_1, + CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_2, + CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_SIZE); k_sem_give(&disp_data->task_sem); @@ -734,30 +734,35 @@ static DEVICE_API(display, sdl_display_api) = { .set_pixel_format = sdl_display_set_pixel_format, }; -#define DISPLAY_SDL_DEFINE(n) \ - static const struct sdl_display_config sdl_config_##n = { \ - .height = DT_INST_PROP(n, height), \ - .width = DT_INST_PROP(n, width), \ - .title = DT_INST_PROP_OR(n, title, "Zephyr Display"), \ - }; \ - \ - static uint8_t sdl_buf_##n[4 * DT_INST_PROP(n, height) * DT_INST_PROP(n, width)]; \ - static uint8_t sdl_read_buf_##n[4 * DT_INST_PROP(n, height) * DT_INST_PROP(n, width)]; \ - K_MSGQ_DEFINE(sdl_task_msgq_##n, sizeof(struct sdl_display_task), 1, 4); \ - static struct sdl_display_data sdl_data_##n = { \ - .buf = sdl_buf_##n, \ - .read_buf = sdl_read_buf_##n, \ - .task_msgq = &sdl_task_msgq_##n, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, &sdl_display_init, NULL, &sdl_data_##n, &sdl_config_##n, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &sdl_display_api); \ - \ - static void sdl_display_cleanup_##n(void) \ - { \ - sdl_display_cleanup(&sdl_data_##n); \ - } \ - \ +#define DISPLAY_SDL_DEFINE(n) \ + static const struct sdl_display_config sdl_config_##n = { \ + .height = DT_INST_PROP(n, height), \ + .width = DT_INST_PROP(n, width), \ + }; \ + \ + static uint8_t sdl_buf_##n[4 * DT_INST_PROP(n, height) \ + * DT_INST_PROP(n, width)]; \ + static uint8_t sdl_read_buf_##n[4 * DT_INST_PROP(n, height) \ + * DT_INST_PROP(n, width)]; \ + K_MSGQ_DEFINE(sdl_task_msgq_##n, sizeof(struct sdl_display_task), 1, 4); \ + static struct sdl_display_data sdl_data_##n = { \ + .buf = sdl_buf_##n, \ + .read_buf = sdl_read_buf_##n, \ + .task_msgq = &sdl_task_msgq_##n, \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &sdl_display_init, NULL, \ + &sdl_data_##n, \ + &sdl_config_##n, \ + POST_KERNEL, \ + CONFIG_DISPLAY_INIT_PRIORITY, \ + &sdl_display_api); \ + \ + static void sdl_display_cleanup_##n(void) \ + { \ + sdl_display_cleanup(&sdl_data_##n); \ + } \ + \ NATIVE_TASK(sdl_display_cleanup_##n, ON_EXIT, 1); DT_INST_FOREACH_STATUS_OKAY(DISPLAY_SDL_DEFINE) diff --git a/drivers/display/display_sdl_bottom.c b/drivers/display/display_sdl_bottom.c index 6ecc2cc446c16..da50ad81c91d8 100644 --- a/drivers/display/display_sdl_bottom.c +++ b/drivers/display/display_sdl_bottom.c @@ -15,18 +15,15 @@ int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct, bool use_accelerator, void **window, const void *window_user_data, - const char *title, void **renderer, void **mutex, void **texture, - void **read_texture, void **background_texture, - uint32_t transparency_grid_color1, uint32_t transparency_grid_color2, - uint16_t transparency_grid_cell_size) + void **renderer, void **mutex, void **texture, void **read_texture, + void **background_texture, uint32_t transparency_grid_color1, + uint32_t transparency_grid_color2, uint16_t transparency_grid_cell_size) { - /* clang-format off */ - *window = SDL_CreateWindow(title, SDL_WINDOWPOS_UNDEFINED, SDL_WINDOWPOS_UNDEFINED, - width * zoom_pct / 100, + *window = SDL_CreateWindow("Zephyr Display", SDL_WINDOWPOS_UNDEFINED, + SDL_WINDOWPOS_UNDEFINED, width * zoom_pct / 100, height * zoom_pct / 100, SDL_WINDOW_SHOWN); - /* clang-format on */ if (*window == NULL) { - nsi_print_warning("Failed to create SDL window %s: %s", title, SDL_GetError()); + nsi_print_warning("Failed to create SDL window: %s", SDL_GetError()); return -1; } SDL_SetWindowData(*window, "zephyr_display", (void *)window_user_data); @@ -157,13 +154,11 @@ int sdl_display_read_bottom(const uint16_t height, const uint16_t width, } SDL_SetRenderTarget(renderer, read_texture); - SDL_SetTextureBlendMode(texture, SDL_BLENDMODE_NONE); SDL_RenderClear(renderer); SDL_RenderCopy(renderer, texture, NULL, NULL); SDL_RenderReadPixels(renderer, &rect, SDL_PIXELFORMAT_ARGB8888, buf, width * 4); - SDL_SetTextureBlendMode(texture, SDL_BLENDMODE_BLEND); SDL_SetRenderTarget(renderer, NULL); SDL_UnlockMutex(mutex); diff --git a/drivers/display/display_sdl_bottom.h b/drivers/display/display_sdl_bottom.h index a77242bf2a146..4ce795f64e309 100644 --- a/drivers/display/display_sdl_bottom.h +++ b/drivers/display/display_sdl_bottom.h @@ -22,9 +22,9 @@ extern "C" { int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct, bool use_accelerator, void **window, const void *window_user_data, - const char *title, void **renderer, void **mutex, void **texture, - void **read_texture, void **background_texture, - uint32_t transparency_grid_color1, uint32_t transparency_grid_color2, + void **renderer, void **mutex, void **texture, void **read_texture, + void **background_texture, uint32_t transparency_grid_color1, + uint32_t transparency_grid_color2, uint16_t transparency_grid_cell_size); void sdl_display_write_bottom(const uint16_t height, const uint16_t width, const uint16_t x, const uint16_t y, void *renderer, void *mutex, void *texture, diff --git a/drivers/display/display_sh1122.c b/drivers/display/display_sh1122.c deleted file mode 100644 index c4ddf5feaef62..0000000000000 --- a/drivers/display/display_sh1122.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -LOG_MODULE_REGISTER(sh1122, CONFIG_DISPLAY_LOG_LEVEL); - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SH1122_CONTROL_ALL_BYTES_CMD 0x0 -#define SH1122_CONTROL_ALL_BYTES_DATA 0x40 - -#define SH1122_SET_PHASE_LENGTH 0xD9 -#define SH1122_SET_OSC_FREQ 0xD5 -#define SH1122_SET_VCOMH 0xDB -#define SH1122_SET_DCDC 0xAD -#define SH1122_SET_DISPLAY_OFFSET 0xD3 -#define SH1122_DISPLAY_ON 0xAF -#define SH1122_DISPLAY_OFF 0xAE -#define SH1122_SET_MULTIPLEX_RATIO 0xA8 -#define SH1122_SET_SEG_ORDER_10 0xA0 -#define SH1122_SET_SEG_ORDER_01 0xA1 -#define SH1122_SET_COM_ORDER_10 0xC0 -#define SH1122_SET_COM_ORDER_01 0xC8 -#define SH1122_SET_CONTRAST_CTRL 0x81 -#define SH1122_SET_VSEGM 0xDC -#define SH1122_SET_DISPLAY_RAM 0xA4 -#define SH1122_SET_DISPLAY_ALL_ON 0xA5 -#define SH1122_SET_NORMAL_DISPLAY 0xA6 -#define SH1122_SET_REVERSE_DISPLAY 0xA7 -#define SH1122_SET_ROW_ADDR 0xB0 - -#define SH1122_SET_COLUMN_ADDR_HIGH(n) (0x10 + ((n) >> 4)) -#define SH1122_SET_COLUMN_ADDR_LOW(n) (0x0 + ((n) & 0xf)) -#define SH1122_SET_DISPLAY_START_LINE(n) (0x40 + ((n) & 0x3f)) -#define SH1122_SET_VSL(n) (0x30 + ((n) & 0xf)) - -#define SH1122_RESET_DELAY 10 -#define SH1122_MAXIMUM_CMD_LENGTH 16 -/* One line since we need to return to column every partial line */ -#define SH1122_CONV_BUFFER_SIZE 128 - -typedef int (*sh1122_write_bus_cmd_fn)(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len); -typedef int (*sh1122_write_pixels_fn)(const struct device *dev, const uint8_t *buf, - const struct display_buffer_descriptor *desc); -typedef int (*sh1122_release_bus_fn)(const struct device *dev); - -struct sh1122_config { - struct i2c_dt_spec i2c; - sh1122_write_bus_cmd_fn write_cmd; - sh1122_write_pixels_fn write_pixels; - sh1122_release_bus_fn release_bus; - const struct device *mipi_dev; - const struct mipi_dbi_config dbi_config; - uint16_t height; - uint16_t width; - uint8_t oscillator_freq; - uint8_t start_line; - uint8_t display_offset; - uint8_t multiplex_ratio; - uint8_t dc_dc; - uint8_t remap_value; - uint8_t phase_length; - uint8_t precharge_voltage; - uint8_t vcomh_voltage; - uint8_t low_voltage; - bool color_inversion; - bool inv_seg; - bool inv_com; - uint8_t *conversion_buf; - size_t conversion_buf_size; -}; - -struct sh1122_data { - uint8_t contrast; - uint8_t scan_mode; -}; - -static inline int sh1122_write_bus_cmd_mipi(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) -{ - const struct sh1122_config *config = dev->config; - int err; - - /* Values given after the memory register must be sent with pin D/C set to 0. */ - /* Data is sent as a command following the mipi_cbi api */ - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, NULL, 0); - if (err) { - return err; - } - for (size_t i = 0; i < len; i++) { - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, data[i], NULL, - 0); - if (err) { - return err; - } - } - - return 0; -} - -static inline int sh1122_write_bus_cmd_i2c(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) -{ - const struct sh1122_config *config = dev->config; - static uint8_t buf[SH1122_MAXIMUM_CMD_LENGTH]; - - if (len > SH1122_MAXIMUM_CMD_LENGTH - 1) { - return -EINVAL; - } - - buf[0] = cmd; - memcpy(&(buf[1]), data, len); - - return i2c_burst_write_dt(&config->i2c, SH1122_CONTROL_ALL_BYTES_CMD, buf, len + 1); -} - -static inline int sh1122_set_hardware_config(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - err = config->write_cmd(dev, SH1122_SET_DISPLAY_START_LINE(config->start_line), NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_DISPLAY_OFFSET, &config->display_offset, 1); - if (err < 0) { - return err; - } - - err = config->write_cmd(dev, SH1122_SET_DISPLAY_RAM, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_NORMAL_DISPLAY, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd( - dev, config->inv_com ? SH1122_SET_COM_ORDER_01 : SH1122_SET_COM_ORDER_10, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd( - dev, config->inv_seg ? SH1122_SET_SEG_ORDER_01 : SH1122_SET_SEG_ORDER_10, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_VSL(config->low_voltage), NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1); - if (err < 0) { - return err; - } - - err = config->write_cmd(dev, SH1122_SET_PHASE_LENGTH, &config->phase_length, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_OSC_FREQ, &config->oscillator_freq, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_VSEGM, &config->precharge_voltage, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SH1122_SET_VCOMH, &config->vcomh_voltage, 1); - if (err < 0) { - return err; - } - return config->write_cmd(dev, SH1122_SET_DCDC, &config->dc_dc, 1); -} - -static int sh1122_resume(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - err = config->write_cmd(dev, SH1122_DISPLAY_ON, NULL, 0); - if (err < 0) { - return err; - } - return config->release_bus(dev); -} - -static int sh1122_suspend(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - err = config->write_cmd(dev, SH1122_DISPLAY_OFF, NULL, 0); - if (err < 0) { - return err; - } - return config->release_bus(dev); -} - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1122, mipi_dbi) -static int sh1122_write_pixels_mipi(const struct device *dev, const uint8_t *buf, - const struct display_buffer_descriptor *desc) -{ - const struct sh1122_config *config = dev->config; - struct display_buffer_descriptor mipi_desc; - - mipi_desc.buf_size = desc->width / 2; - mipi_desc.pitch = desc->pitch; - mipi_desc.width = desc->width; - mipi_desc.height = 1; - - /* This is the wrong format, but it doesn't matter to almost all mipi drivers */ - return mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, config->conversion_buf, - &mipi_desc, PIXEL_FORMAT_L_8); -} - -static int sh1122_release_bus_mipi(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1122, i2c) -static int sh1122_write_pixels_i2c(const struct device *dev, const uint8_t *buf, - const struct display_buffer_descriptor *desc) -{ - const struct sh1122_config *config = dev->config; - - return i2c_burst_write_dt(&config->i2c, SH1122_CONTROL_ALL_BYTES_DATA, - config->conversion_buf, desc->width / 2); -} - -static int sh1122_release_bus_i2c(const struct device *dev) -{ - return 0; -} -#endif - -static int sh1122_write(const struct device *dev, const uint16_t x, const uint16_t y, - const struct display_buffer_descriptor *desc, const void *buf) -{ - const struct sh1122_config *config = dev->config; - int err; - size_t buf_len; - int pixel_count = desc->width * desc->height; - int total = 0; - uint8_t ybuf = y; - - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; - } - - /* Following the datasheet, two segment are split in one register */ - buf_len = MIN(desc->buf_size, desc->height * desc->width / 2); - if (buf == NULL || buf_len == 0U) { - LOG_ERR("Display buffer is not available"); - return -EINVAL; - } - - if ((x & 1) != 0U) { - LOG_ERR("Unsupported origin"); - return -EINVAL; - } - - LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, - desc->width, desc->height, buf_len); - - while (pixel_count > total) { - - err = config->write_cmd(dev, SH1122_SET_COLUMN_ADDR_HIGH(x / 2), NULL, 0); - if (err) { - return err; - } - - err = config->write_cmd(dev, SH1122_SET_COLUMN_ADDR_LOW(x / 2), NULL, 0); - if (err) { - return err; - } - - err = config->write_cmd(dev, SH1122_SET_ROW_ADDR, &ybuf, 1); - if (err) { - return err; - } - - /* Convert one line to pixelx+1 (3:0) and pixelx (7:4) - * SH1122 is 2 pixels per byte. - */ - for (int i = 0; desc->width > i; i += 2) { - config->conversion_buf[i / 2] = (((uint8_t *)buf)[total + i + 1] >> 4) | - ((((uint8_t *)buf)[total + i] >> 4) << 4); - } - - err = config->write_pixels(dev, config->conversion_buf, desc); - if (err) { - return err; - } - total += desc->width; - ybuf++; - } - return config->release_bus(dev); -} - -static int sh1122_set_contrast(const struct device *dev, const uint8_t contrast) -{ - const struct sh1122_config *config = dev->config; - int err; - - err = config->write_cmd(dev, SH1122_SET_CONTRAST_CTRL, &contrast, 1); - if (err < 0) { - return err; - } - return config->release_bus(dev); -} - -static void sh1122_get_capabilities(const struct device *dev, struct display_capabilities *caps) -{ - const struct sh1122_config *config = dev->config; - - memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = config->width; - caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_L_8; - caps->current_pixel_format = PIXEL_FORMAT_L_8; - caps->screen_info = 0; -} - -static int sh1122_set_pixel_format(const struct device *dev, const enum display_pixel_format pf) -{ - if (pf == PIXEL_FORMAT_L_8) { - return 0; - } - LOG_ERR("Unsupported pixel format"); - return -ENOTSUP; -} - -static int sh1122_init_device(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - /* Turn display off */ - err = sh1122_suspend(dev); - if (err < 0) { - return err; - } - - err = sh1122_set_contrast(dev, CONFIG_SH1122_DEFAULT_CONTRAST); - if (err < 0) { - return err; - } - - err = sh1122_set_hardware_config(dev); - if (err < 0) { - return err; - } - - err = config->write_cmd(dev, - config->color_inversion ? SH1122_SET_REVERSE_DISPLAY - : SH1122_SET_NORMAL_DISPLAY, - NULL, 0); - if (err < 0) { - return err; - } - - err = sh1122_resume(dev); - if (err < 0) { - return err; - } - - return config->release_bus(dev); -} - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1122, mipi_dbi) -static int sh1122_init(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!device_is_ready(config->mipi_dev)) { - LOG_ERR("MIPI Device not ready!"); - return -EINVAL; - } - - err = mipi_dbi_reset(config->mipi_dev, SH1122_RESET_DELAY); - if (err < 0) { - LOG_ERR("Failed to reset device!"); - return err; - } - k_msleep(SH1122_RESET_DELAY); - - err = sh1122_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1122, i2c) -static int sh1122_init_i2c(const struct device *dev) -{ - const struct sh1122_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!i2c_is_ready_dt(&config->i2c)) { - LOG_ERR("I2C Device not ready!"); - return -EINVAL; - } - - err = sh1122_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} -#endif - -static DEVICE_API(display, sh1122_driver_api) = { - .blanking_on = sh1122_suspend, - .blanking_off = sh1122_resume, - .write = sh1122_write, - .set_contrast = sh1122_set_contrast, - .get_capabilities = sh1122_get_capabilities, - .set_pixel_format = sh1122_set_pixel_format, -}; - -#define SH1122_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define SH1122_DEFINE_I2C(node_id) \ - static uint8_t conversion_buf##node_id[SH1122_CONV_BUFFER_SIZE]; \ - static struct sh1122_data data##node_id; \ - static const struct sh1122_config config##node_id = { \ - .i2c = I2C_DT_SPEC_GET(node_id), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .dc_dc = DT_PROP(node_id, dc_dc), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .low_voltage = DT_PROP(node_id, low_voltage), \ - .inv_seg = DT_PROP(node_id, inv_seg), \ - .inv_com = DT_PROP(node_id, inv_com), \ - .write_cmd = sh1122_write_bus_cmd_i2c, \ - .write_pixels = sh1122_write_pixels_i2c, \ - .release_bus = sh1122_release_bus_i2c, \ - .conversion_buf = conversion_buf##node_id, \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, sh1122_init_i2c, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &sh1122_driver_api); - -#define SH1122_DEFINE_MIPI(node_id) \ - static uint8_t conversion_buf##node_id[SH1122_CONV_BUFFER_SIZE]; \ - static struct sh1122_data data##node_id; \ - static const struct sh1122_config config##node_id = { \ - .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, SH1122_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .dc_dc = DT_PROP(node_id, dc_dc), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .low_voltage = DT_PROP(node_id, low_voltage), \ - .inv_seg = DT_PROP(node_id, inv_seg), \ - .inv_com = DT_PROP(node_id, inv_com), \ - .write_cmd = sh1122_write_bus_cmd_mipi, \ - .write_pixels = sh1122_write_pixels_mipi, \ - .release_bus = sh1122_release_bus_mipi, \ - .conversion_buf = conversion_buf##node_id, \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, sh1122_init, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &sh1122_driver_api); - -#define SH1122_DEFINE(node_id) \ - COND_CODE_1(DT_ON_BUS(node_id, i2c), \ - (SH1122_DEFINE_I2C(node_id)), (SH1122_DEFINE_MIPI(node_id))) - -DT_FOREACH_STATUS_OKAY(sinowealth_sh1122, SH1122_DEFINE) diff --git a/drivers/display/display_ssd1320.c b/drivers/display/display_ssd1320.c deleted file mode 100644 index abc25b22cca22..0000000000000 --- a/drivers/display/display_ssd1320.c +++ /dev/null @@ -1,554 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -LOG_MODULE_REGISTER(ssd1320, CONFIG_DISPLAY_LOG_LEVEL); - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SSD1320_SET_COMMAND_LOCK 0xFD -#define SSD1320_UNLOCK_COMMAND 0x12 - -#define SSD1320_CONTROL_ALL_BYTES_CMD 0x0 -#define SSD1320_CONTROL_ALL_BYTES_DATA 0x40 - -#define SSD1320_SET_PHASE_LENGTH 0xD9 -#define SSD1320_SET_OSC_FREQ 0xD5 -#define SSD1320_LINEAR_LUT 0xBF -#define SSD1320_SET_PRECHARGE_VOLTAGE 0xBC -#define SSD1320_SET_VCOMH 0xDB -#define SSD1320_SET_INTERNAL_IREF 0xAD -#define SSD1320_SET_DISPLAY_START_LINE 0xA2 -#define SSD1320_SET_DISPLAY_OFFSET 0xD3 -#define SSD1320_SET_DISPLAY_RAM 0xA4 -#define SSD1320_SET_SEGMENT_MAP_REMAPED 0xDA -#define SSD1320_SET_MULTIPLEX_RATIO 0xA8 -#define SSD1320_DISPLAY_ON 0xAF -#define SSD1320_DISPLAY_OFF 0xAE -#define SSD1320_SET_COLUMN_ADDR 0x21 -#define SSD1320_SET_ROW_ADDR 0x22 -#define SSD1320_SET_CONTRAST_CTRL 0x81 -#define SSD1320_SET_NORMAL_DISPLAY 0xA6 -#define SSD1320_SET_REVERSE_DISPLAY 0xA7 -#define SSD1320_SET_COM_ORDER_10 0xC0 -#define SSD1320_SET_COM_ORDER_01 0xC8 -#define SSD1320_SET_SEG_ORDER_10 0xA0 -#define SSD1320_SET_SEG_ORDER_01 0xA1 -#define SSD1320_SET_GREY_ENHANCE 0xD8 -#define SSD1320_SET_GREY_ENHANCE_ON 0xD5 -#define SSD1320_SET_GREY_ENHANCE_OFF 0xF5 - -#define SSD1320_RESET_DELAY 10 -#define SSD1320_MAXIMUM_CMD_LENGTH 16 - -typedef int (*ssd1320_write_bus_cmd_fn)(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len); -typedef int (*ssd1320_write_pixels_fn)(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc); - -struct ssd1320_config { - struct i2c_dt_spec i2c; - ssd1320_write_bus_cmd_fn write_cmd; - ssd1320_write_pixels_fn write_pixels; - const struct device *mipi_dev; - const struct mipi_dbi_config dbi_config; - uint16_t height; - uint16_t width; - uint8_t oscillator_freq; - uint8_t start_line; - uint8_t display_offset; - uint8_t multiplex_ratio; - uint8_t internal_iref; - uint8_t remap_value; - uint8_t phase_length; - uint8_t precharge_voltage; - uint8_t vcomh_voltage; - bool color_inversion; - bool greyscale_enhancement; - bool inv_seg; - bool inv_com; - uint8_t *conversion_buf; - size_t conversion_buf_size; -}; - -struct ssd1320_data { - uint8_t contrast; - uint8_t scan_mode; -}; - -static inline int ssd1320_write_bus_cmd_mipi(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) -{ - const struct ssd1320_config *config = dev->config; - int err; - - /* Values given after the memory register must be sent with pin D/C set to 0. */ - /* Data is sent as a command following the mipi_cbi api */ - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, NULL, 0); - if (err) { - return err; - } - for (size_t i = 0; i < len; i++) { - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, data[i], NULL, - 0); - if (err) { - return err; - } - } - mipi_dbi_release(config->mipi_dev, &config->dbi_config); - - return 0; -} - -static inline int ssd1320_write_bus_cmd_i2c(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) -{ - const struct ssd1320_config *config = dev->config; - static uint8_t buf[SSD1320_MAXIMUM_CMD_LENGTH]; - - if (len > SSD1320_MAXIMUM_CMD_LENGTH - 1) { - return -EINVAL; - } - - buf[0] = cmd; - memcpy(&(buf[1]), data, len); - - return i2c_burst_write_dt(&config->i2c, SSD1320_CONTROL_ALL_BYTES_CMD, buf, len + 1); -} - -static inline int ssd1320_set_hardware_config(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - uint8_t buf; - int err; - - err = config->write_cmd(dev, SSD1320_SET_DISPLAY_START_LINE, &config->start_line, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_DISPLAY_OFFSET, &config->display_offset, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_DISPLAY_RAM, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_NORMAL_DISPLAY, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd( - dev, config->inv_com ? SSD1320_SET_COM_ORDER_01 : SSD1320_SET_COM_ORDER_10, NULL, - 0); - if (err < 0) { - return err; - } - err = config->write_cmd( - dev, config->inv_seg ? SSD1320_SET_SEG_ORDER_01 : SSD1320_SET_SEG_ORDER_10, NULL, - 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1); - if (err < 0) { - return err; - } - if (config->greyscale_enhancement) { - buf = SSD1320_SET_GREY_ENHANCE_ON; - err = config->write_cmd(dev, SSD1320_SET_GREY_ENHANCE, &buf, 1); - if (err < 0) { - return err; - } - - /* Undocumented enhancement provided by datasheet */ - buf = 0x21; - err = config->write_cmd(dev, 0xF0, &buf, 1); - if (err < 0) { - return err; - } - } - err = config->write_cmd(dev, SSD1320_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_PHASE_LENGTH, &config->phase_length, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_OSC_FREQ, &config->oscillator_freq, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_LINEAR_LUT, NULL, 0); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_PRECHARGE_VOLTAGE, &config->precharge_voltage, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_VCOMH, &config->vcomh_voltage, 1); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_INTERNAL_IREF, &config->internal_iref, 1); - if (err < 0) { - return err; - } - buf = SSD1320_UNLOCK_COMMAND; - return config->write_cmd(dev, SSD1320_SET_COMMAND_LOCK, &buf, 1); -} - -static int ssd1320_resume(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - - return config->write_cmd(dev, SSD1320_DISPLAY_ON, NULL, 0); -} - -static int ssd1320_suspend(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - - return config->write_cmd(dev, SSD1320_DISPLAY_OFF, NULL, 0); -} - -static int ssd1320_set_display(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - int err; - uint8_t x_position[] = {0, config->width - 1}; - uint8_t y_position[] = {0, config->height - 1}; - - err = config->write_cmd(dev, SSD1320_SET_COLUMN_ADDR, x_position, sizeof(x_position)); - if (err < 0) { - return err; - } - err = config->write_cmd(dev, SSD1320_SET_ROW_ADDR, y_position, sizeof(y_position)); - if (err < 0) { - return err; - } - return config->write_cmd(dev, SSD1320_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1); -} - -/* Convert what the conversion buffer can hold to pixelx (3:0) and pixelx+1 (7:4) */ -static int ssd1320_convert_L_8(const struct device *dev, const uint8_t *buf, int cur_offset, - uint32_t pixel_count) -{ - const struct ssd1320_config *config = dev->config; - int i = 0; - - for (; i / 2 < config->conversion_buf_size && pixel_count > cur_offset + i; i += 2) { - config->conversion_buf[i / 2] = buf[cur_offset + i] >> 4; - config->conversion_buf[i / 2] |= (buf[cur_offset + i + 1] >> 4) << 4; - } - return i; -} - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1320, mipi_dbi) -static int ssd1320_write_pixels_mipi(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc) -{ - const struct ssd1320_config *config = dev->config; - struct display_buffer_descriptor mipi_desc; - int ret, i; - int total = 0; - - mipi_desc.pitch = desc->pitch; - - while (pixel_count > total) { - i = ssd1320_convert_L_8(dev, buf, total, pixel_count); - - mipi_desc.buf_size = i / 2; - mipi_desc.width = mipi_desc.buf_size / desc->height; - mipi_desc.height = mipi_desc.buf_size / desc->width; - - /* This is the wrong format, but it doesn't matter to almost all mipi drivers */ - ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, - config->conversion_buf, &mipi_desc, PIXEL_FORMAT_L_8); - if (ret < 0) { - return ret; - } - total += i; - } - mipi_dbi_release(config->mipi_dev, &config->dbi_config); - return 0; -} -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1320, i2c) -static int ssd1320_write_pixels_i2c(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc) -{ - const struct ssd1320_config *config = dev->config; - int ret, i; - int total = 0; - - while (pixel_count > total) { - i = ssd1320_convert_L_8(dev, buf, total, pixel_count); - - ret = i2c_burst_write_dt(&config->i2c, SSD1320_CONTROL_ALL_BYTES_DATA, - config->conversion_buf, i / 2); - if (ret < 0) { - return ret; - } - total += i; - } - return 0; -} -#endif - -static int ssd1320_write(const struct device *dev, const uint16_t x, const uint16_t y, - const struct display_buffer_descriptor *desc, const void *buf) -{ - const struct ssd1320_config *config = dev->config; - int err; - size_t buf_len; - int32_t pixel_count = desc->width * desc->height; - uint8_t x_position[] = {x / 2, (x + desc->width - 1) / 2}; - uint8_t y_position[] = {y, y + desc->height - 1}; - - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; - } - - /* Following the datasheet, in the GDDRAM, two segment are split in one register */ - buf_len = MIN(desc->buf_size, desc->height * desc->width / 2); - if (buf == NULL || buf_len == 0U) { - LOG_ERR("Display buffer is not available"); - return -EINVAL; - } - - if ((x & 1) != 0U) { - LOG_ERR("Unsupported origin"); - return -EINVAL; - } - - LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, - desc->width, desc->height, buf_len); - - err = config->write_cmd(dev, SSD1320_SET_COLUMN_ADDR, x_position, sizeof(x_position)); - if (err) { - return err; - } - - err = config->write_cmd(dev, SSD1320_SET_ROW_ADDR, y_position, sizeof(y_position)); - if (err) { - return err; - } - - return config->write_pixels(dev, buf, pixel_count, desc); -} - -static int ssd1320_set_contrast(const struct device *dev, const uint8_t contrast) -{ - const struct ssd1320_config *config = dev->config; - - return config->write_cmd(dev, SSD1320_SET_CONTRAST_CTRL, &contrast, 1); -} - -static void ssd1320_get_capabilities(const struct device *dev, struct display_capabilities *caps) -{ - const struct ssd1320_config *config = dev->config; - - memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = config->width; - caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_L_8; - caps->current_pixel_format = PIXEL_FORMAT_L_8; - caps->screen_info = 0; -} - -static int ssd1320_set_pixel_format(const struct device *dev, const enum display_pixel_format pf) -{ - if (pf == PIXEL_FORMAT_L_8) { - return 0; - } - LOG_ERR("Unsupported pixel format"); - return -ENOTSUP; -} - -static int ssd1320_init_device(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - uint8_t buf; - int err; - - /* Turn display off */ - err = ssd1320_suspend(dev); - if (err < 0) { - return err; - } - - err = ssd1320_set_display(dev); - if (err < 0) { - return err; - } - - err = ssd1320_set_contrast(dev, CONFIG_SSD1320_DEFAULT_CONTRAST); - if (err < 0) { - return err; - } - - err = ssd1320_set_hardware_config(dev); - if (err < 0) { - return err; - } - - buf = (config->color_inversion ? SSD1320_SET_REVERSE_DISPLAY : SSD1320_SET_NORMAL_DISPLAY); - err = config->write_cmd(dev, buf, NULL, 0); - if (err < 0) { - return err; - } - - return ssd1320_resume(dev); -} - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1320, mipi_dbi) -static int ssd1320_init(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!device_is_ready(config->mipi_dev)) { - LOG_ERR("MIPI Device not ready!"); - return -EINVAL; - } - - if (mipi_dbi_reset(config->mipi_dev, SSD1320_RESET_DELAY)) { - LOG_ERR("Failed to reset device!"); - return -EIO; - } - k_msleep(SSD1320_RESET_DELAY); - - err = ssd1320_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1320, i2c) -static int ssd1320_init_i2c(const struct device *dev) -{ - const struct ssd1320_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!i2c_is_ready_dt(&config->i2c)) { - LOG_ERR("I2C Device not ready!"); - return -EINVAL; - } - - err = ssd1320_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} -#endif - -static DEVICE_API(display, ssd1320_driver_api) = { - .blanking_on = ssd1320_suspend, - .blanking_off = ssd1320_resume, - .write = ssd1320_write, - .set_contrast = ssd1320_set_contrast, - .get_capabilities = ssd1320_get_capabilities, - .set_pixel_format = ssd1320_set_pixel_format, -}; - -#define SSD1320_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define SSD1320_CONV_BUFFER_SIZE(node_id) \ - DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_SSD1320_CONV_BUFFER_LINES, 2) - -#define SSD1320_DEFINE_I2C(node_id) \ - static uint8_t conversion_buf##node_id[SSD1320_CONV_BUFFER_SIZE(node_id)]; \ - static struct ssd1320_data data##node_id; \ - static const struct ssd1320_config config##node_id = { \ - .i2c = I2C_DT_SPEC_GET(node_id), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .remap_value = DT_PROP(node_id, remap_value), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .internal_iref = DT_PROP(node_id, internal_iref), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .greyscale_enhancement = DT_PROP(node_id, greyscale_enhancement), \ - .inv_seg = DT_PROP(node_id, inv_seg), \ - .inv_com = DT_PROP(node_id, inv_com), \ - .write_cmd = ssd1320_write_bus_cmd_i2c, \ - .write_pixels = ssd1320_write_pixels_i2c, \ - .conversion_buf = conversion_buf##node_id, \ - .conversion_buf_size = sizeof(conversion_buf##node_id), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, ssd1320_init_i2c, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1320_driver_api); - -#define SSD1320_DEFINE_MIPI(node_id) \ - static uint8_t conversion_buf##node_id[SSD1320_CONV_BUFFER_SIZE(node_id)]; \ - static struct ssd1320_data data##node_id; \ - static const struct ssd1320_config config##node_id = { \ - .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, SSD1320_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .remap_value = DT_PROP(node_id, remap_value), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .internal_iref = DT_PROP(node_id, internal_iref), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .greyscale_enhancement = DT_PROP(node_id, greyscale_enhancement), \ - .inv_seg = DT_PROP(node_id, inv_seg), \ - .inv_com = DT_PROP(node_id, inv_com), \ - .write_cmd = ssd1320_write_bus_cmd_mipi, \ - .write_pixels = ssd1320_write_pixels_mipi, \ - .conversion_buf = conversion_buf##node_id, \ - .conversion_buf_size = sizeof(conversion_buf##node_id), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, ssd1320_init, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1320_driver_api); - -#define SSD1320_DEFINE(node_id) \ - COND_CODE_1(DT_ON_BUS(node_id, i2c), \ - (SSD1320_DEFINE_I2C(node_id)), (SSD1320_DEFINE_MIPI(node_id))) - -DT_FOREACH_STATUS_OKAY(solomon_ssd1320, SSD1320_DEFINE) diff --git a/drivers/display/display_ssd1331.c b/drivers/display/display_ssd1331.c deleted file mode 100644 index d1e9957e0f3e0..0000000000000 --- a/drivers/display/display_ssd1331.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -LOG_MODULE_REGISTER(ssd1331, CONFIG_DISPLAY_LOG_LEVEL); - -#include -#include -#include -#include -#include -#include -#include - -#define SSD1331_DISPLAY_OFF 0xAE -#define SSD1331_DISPLAY_ON 0xAF -#define SSD1331_SET_NORMAL_DISPLAY 0xA4 -#define SSD1331_SET_REVERSE_DISPLAY 0xA7 - -#define SSD1331_SET_COLUMN_ADDR 0x15 -#define SSD1331_SET_ROW_ADDR 0x75 - -#define SSD1331_SET_DISPLAY_START_LINE 0xA1 -#define SSD1331_SET_DISPLAY_OFFSET 0xA2 -#define SSD1331_SET_MULTIPLEX_RATIO 0xA8 -#define SSD1331_SET_PHASE_LENGTH 0xB1 -#define SSD1331_SET_OSC_FREQ 0xB3 -#define SSD1331_SET_PRECHARGE_A 0x8A -#define SSD1331_SET_PRECHARGE_B 0x8B -#define SSD1331_SET_PRECHARGE_C 0x8C -#define SSD1331_SET_PRECHARGE_V 0xBB -#define SSD1331_SET_VCOMH 0xBE -#define SSD1331_SET_CURRENT_ATT 0x87 -#define SSD1331_SET_REMAP 0xA0 -#define SSD1331_DISABLE_SCROLL 0x2E - -#define SSD1331_SET_EXTERNAL_SUPPLY 0xAD -#define SSD1331_EXTERNAL_SUPPLY 0x8E - -#define SSD1331_SET_POWER_SAVE 0xB0 -#define SSD1331_POWER_SAVE 0x1A -#define SSD1331_NOT_POWER_SAVE 0x0B - -#define SSD1331_CONTRASTA 0x81 -#define SSD1331_CONTRASTB 0x82 -#define SSD1331_CONTRASTC 0x83 - -#define SSD1331_RESET_DELAY 10 - -struct ssd1331_config { - const struct device *mipi_dev; - const struct mipi_dbi_config dbi_config; - uint16_t height; - uint16_t width; - uint8_t start_line; - uint8_t display_offset; - uint8_t multiplex_ratio; - uint8_t phase_length; - uint8_t oscillator_freq; - uint8_t precharge_time_a; - uint8_t precharge_time_b; - uint8_t precharge_time_c; - uint8_t precharge_voltage; - uint8_t vcomh_voltage; - uint8_t current_att; - uint8_t remap_value; - bool power_save; - bool color_inversion; -}; - -/* SSD1331 doesn't follow typical DBI behavior with D/C pin so we do this to make it fit in DBI */ -static inline int ssd1331_write_command(const struct device *dev, uint8_t cmd, const uint8_t *buf, - size_t len) -{ - const struct ssd1331_config *config = dev->config; - int err; - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, NULL, 0); - if (err < 0) { - return err; - } - for (int x = 0; x < len; x++) { - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, buf[x], NULL, - 0); - if (err < 0) { - return err; - } - } - - return err; -} - -static inline int ssd1331_set_hardware_config(const struct device *dev) -{ - const struct ssd1331_config *config = dev->config; - int err; - uint8_t tmp; - - err = ssd1331_write_command(dev, SSD1331_SET_REMAP, &config->remap_value, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_DISPLAY_START_LINE, &config->start_line, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_DISPLAY_OFFSET, &config->display_offset, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1); - if (err < 0) { - return err; - } - tmp = SSD1331_EXTERNAL_SUPPLY; - err = ssd1331_write_command(dev, SSD1331_SET_EXTERNAL_SUPPLY, &tmp, 1); - if (err < 0) { - return err; - } - tmp = config->power_save ? SSD1331_POWER_SAVE : SSD1331_NOT_POWER_SAVE; - err = ssd1331_write_command(dev, SSD1331_SET_POWER_SAVE, &tmp, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_PHASE_LENGTH, &config->phase_length, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_OSC_FREQ, &config->oscillator_freq, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_PRECHARGE_A, &config->precharge_time_a, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_PRECHARGE_B, &config->precharge_time_b, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_PRECHARGE_C, &config->precharge_time_c, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_PRECHARGE_V, &config->precharge_voltage, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_VCOMH, &config->vcomh_voltage, 1); - if (err < 0) { - return err; - } - err = ssd1331_write_command(dev, SSD1331_SET_CURRENT_ATT, &config->current_att, 1); - if (err < 0) { - return err; - } - return ssd1331_write_command(dev, SSD1331_DISABLE_SCROLL, NULL, 0); -} - -static int ssd1331_resume(const struct device *dev) -{ - const struct ssd1331_config *config = dev->config; - int err; - - err = ssd1331_write_command(dev, SSD1331_DISPLAY_ON, NULL, 0); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1331_suspend(const struct device *dev) -{ - const struct ssd1331_config *config = dev->config; - int err; - - err = ssd1331_write_command(dev, SSD1331_DISPLAY_OFF, NULL, 0); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1331_write(const struct device *dev, const uint16_t x, const uint16_t y, - const struct display_buffer_descriptor *desc, const void *buf) -{ - const struct ssd1331_config *config = dev->config; - int err; - size_t buf_len; - struct display_buffer_descriptor mipi_desc = *desc; - uint8_t x_position[] = {x, x + desc->width - 1}; - uint8_t y_position[] = {y, y + desc->height - 1}; - - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; - } - - /* Following the datasheet, two segment are split in one register */ - buf_len = MIN(desc->buf_size, desc->height * desc->width * 2); - if (buf == NULL || buf_len == 0U) { - LOG_ERR("Display buffer is not available"); - return -EINVAL; - } - - LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, - desc->width, desc->height, buf_len); - - err = ssd1331_write_command(dev, SSD1331_SET_COLUMN_ADDR, x_position, 2); - if (err < 0) { - return err; - } - - err = ssd1331_write_command(dev, SSD1331_SET_ROW_ADDR, y_position, 2); - if (err < 0) { - return err; - } - - err = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc, - PIXEL_FORMAT_RGB_565); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1331_set_contrast(const struct device *dev, const uint8_t contrast) -{ - int err; - uint8_t tmp; - - tmp = (contrast * CONFIG_SSD1331_CONTRASTA) / 0xFF; - err = ssd1331_write_command(dev, SSD1331_CONTRASTA, &tmp, 1); - if (err < 0) { - return err; - } - tmp = (contrast * CONFIG_SSD1331_CONTRASTB) / 0xFF; - err = ssd1331_write_command(dev, SSD1331_CONTRASTB, &tmp, 1); - if (err < 0) { - return err; - } - tmp = (contrast * CONFIG_SSD1331_CONTRASTC) / 0xFF; - return ssd1331_write_command(dev, SSD1331_CONTRASTC, &tmp, 1); -} - -static void ssd1331_get_capabilities(const struct device *dev, struct display_capabilities *caps) -{ - const struct ssd1331_config *config = dev->config; - - memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = config->width; - caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_RGB_565; - caps->current_pixel_format = PIXEL_FORMAT_RGB_565; - caps->screen_info = 0; -} - -static int ssd1331_set_pixel_format(const struct device *dev, const enum display_pixel_format pf) -{ - if (pf == PIXEL_FORMAT_RGB_565) { - return 0; - } - LOG_ERR("Unsupported pixel format"); - return -ENOTSUP; -} - -static int ssd1331_init_device(const struct device *dev) -{ - const struct ssd1331_config *config = dev->config; - int err; - - /* Turn display off */ - err = ssd1331_suspend(dev); - if (err < 0) { - return err; - } - - err = ssd1331_set_hardware_config(dev); - if (err < 0) { - return err; - } - - err = ssd1331_set_contrast(dev, CONFIG_SSD1331_DEFAULT_CONTRAST); - if (err < 0) { - return err; - } - - err = ssd1331_write_command(dev, - config->color_inversion ? SSD1331_SET_REVERSE_DISPLAY - : SSD1331_SET_NORMAL_DISPLAY, - NULL, 0); - if (err < 0) { - return err; - } - - err = ssd1331_resume(dev); - if (err < 0) { - return err; - } - - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1331_init(const struct device *dev) -{ - const struct ssd1331_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!device_is_ready(config->mipi_dev)) { - LOG_ERR("MIPI Device not ready!"); - return -EINVAL; - } - - err = mipi_dbi_reset(config->mipi_dev, SSD1331_RESET_DELAY); - if (err < 0) { - LOG_ERR("Failed to reset device!"); - return err; - } - - err = ssd1331_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} - -static DEVICE_API(display, ssd1331_driver_api) = { - .blanking_on = ssd1331_suspend, - .blanking_off = ssd1331_resume, - .write = ssd1331_write, - .set_contrast = ssd1331_set_contrast, - .get_capabilities = ssd1331_get_capabilities, - .set_pixel_format = ssd1331_set_pixel_format, -}; - -#define SSD1331_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define SSD1331_DEFINE_MIPI(node_id) \ - static const struct ssd1331_config config##node_id = { \ - .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, SSD1331_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .power_save = DT_PROP(node_id, power_save), \ - .precharge_time_a = DT_PROP(node_id, precharge_time_a), \ - .precharge_time_b = DT_PROP(node_id, precharge_time_b), \ - .precharge_time_c = DT_PROP(node_id, precharge_time_c), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .current_att = DT_PROP(node_id, current_att), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .remap_value = DT_PROP(node_id, remap_value), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, ssd1331_init, NULL, NULL, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1331_driver_api); - -DT_FOREACH_STATUS_OKAY(solomon_ssd1331, SSD1331_DEFINE_MIPI) diff --git a/drivers/display/display_ssd1351.c b/drivers/display/display_ssd1351.c deleted file mode 100644 index 49b4771db682c..0000000000000 --- a/drivers/display/display_ssd1351.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -LOG_MODULE_REGISTER(ssd1351, CONFIG_DISPLAY_LOG_LEVEL); - -#include -#include -#include -#include -#include -#include -#include - -#define SSD1351_DISPLAY_OFF 0xAE -#define SSD1351_DISPLAY_ON 0xAF -#define SSD1351_SET_NORMAL_DISPLAY 0xA6 -#define SSD1351_SET_REVERSE_DISPLAY 0xA7 - -#define SSD1351_SET_COLUMN_ADDR 0x15 -#define SSD1351_SET_ROW_ADDR 0x75 - -#define SSD1351_SET_DISPLAY_START_LINE 0xA1 -#define SSD1351_SET_DISPLAY_OFFSET 0xA2 -#define SSD1351_SET_MULTIPLEX_RATIO 0xCA -#define SSD1351_SET_PHASE_LENGTH 0xB1 -#define SSD1351_SET_OSC_FREQ 0xB3 -#define SSD1351_SET_PRECHARGE_V 0xBB -#define SSD1351_SET_VCOMH 0xBE -#define SSD1351_SET_CURRENT_ATT 0xC7 -#define SSD1351_SET_PRECHARGE_P 0xB6 -#define SSD1351_SET_REMAP 0xA0 -#define SSD1351_STOP_SCROLL 0x9E -#define SSD1351_SET_LINEAR_LUT 0xB9 - -#define SSD1351_CONTRAST 0xC1 - -#define SSD1351_SET_LOCK 0xFD -#define SSD1351_UNLOCK_1 0x12 -#define SSD1351_UNLOCK_2 0xB1 -#define SSD1351_LOCK_1 0x16 -#define SSD1351_LOCK_2 0xB0 - -#define SSD1351_WRITE 0x5C - -#define SSD1351_RESET_DELAY 10 - -struct ssd1351_config { - const struct device *mipi_dev; - const struct mipi_dbi_config dbi_config; - uint16_t height; - uint16_t width; - uint8_t start_line; - uint8_t display_offset; - uint8_t multiplex_ratio; - uint8_t phase_length; - uint8_t oscillator_freq; - uint8_t precharge_voltage; - uint8_t precharge_time; - uint8_t vcomh_voltage; - uint8_t current_att; - uint8_t remap_value; - bool color_inversion; -}; - -static inline int ssd1351_set_hardware_config(const struct device *dev) -{ - const struct ssd1351_config *config = dev->config; - int err; - uint8_t tmp; - - tmp = SSD1351_UNLOCK_1; - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_LOCK, &tmp, - 1); - if (err < 0) { - return err; - } - tmp = SSD1351_UNLOCK_2; - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_LOCK, &tmp, - 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_OSC_FREQ, - &config->oscillator_freq, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, - SSD1351_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, - SSD1351_SET_DISPLAY_OFFSET, &config->display_offset, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_REMAP, - &config->remap_value, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, - SSD1351_SET_DISPLAY_START_LINE, &config->start_line, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, - SSD1351_SET_PHASE_LENGTH, &config->phase_length, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_VCOMH, - &config->vcomh_voltage, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_CURRENT_ATT, - &config->current_att, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_PRECHARGE_V, - &config->precharge_voltage, 1); - if (err < 0) { - return err; - } - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_PRECHARGE_P, - &config->precharge_time, 1); - if (err < 0) { - return err; - } - - return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_STOP_SCROLL, - NULL, 0); -} - -static int ssd1351_resume(const struct device *dev) -{ - const struct ssd1351_config *config = dev->config; - int err; - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_DISPLAY_ON, - NULL, 0); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1351_suspend(const struct device *dev) -{ - const struct ssd1351_config *config = dev->config; - int err; - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_DISPLAY_OFF, - NULL, 0); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1351_write(const struct device *dev, const uint16_t x, const uint16_t y, - const struct display_buffer_descriptor *desc, const void *buf) -{ - const struct ssd1351_config *config = dev->config; - int err; - size_t buf_len; - struct display_buffer_descriptor mipi_desc = *desc; - uint8_t x_position[] = {x, x + desc->width - 1}; - uint8_t y_position[] = {y, y + desc->height - 1}; - - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; - } - - /* Following the datasheet, two segment are split in one register */ - buf_len = MIN(desc->buf_size, desc->height * desc->width * 2); - if (buf == NULL || buf_len == 0U) { - LOG_ERR("Display buffer is not available"); - return -EINVAL; - } - - LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, - desc->width, desc->height, buf_len); - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_COLUMN_ADDR, - x_position, 2); - if (err < 0) { - return err; - } - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_SET_ROW_ADDR, - y_position, 2); - if (err < 0) { - return err; - } - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_WRITE, NULL, 0); - if (err < 0) { - return err; - } - - err = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc, - PIXEL_FORMAT_RGB_565); - if (err < 0) { - return err; - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1351_set_contrast(const struct device *dev, const uint8_t contrast) -{ - const struct ssd1351_config *config = dev->config; - uint8_t tmp[3]; - - tmp[0] = (contrast * CONFIG_SSD1351_CONTRASTA) / 0xFF; - tmp[1] = (contrast * CONFIG_SSD1351_CONTRASTB) / 0xFF; - tmp[2] = (contrast * CONFIG_SSD1351_CONTRASTC) / 0xFF; - return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, SSD1351_CONTRAST, tmp, - 3); -} - -static void ssd1351_get_capabilities(const struct device *dev, struct display_capabilities *caps) -{ - const struct ssd1351_config *config = dev->config; - - memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = config->width; - caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_RGB_565; - caps->current_pixel_format = PIXEL_FORMAT_RGB_565; - caps->screen_info = 0; -} - -static int ssd1351_set_pixel_format(const struct device *dev, const enum display_pixel_format pf) -{ - if (pf == PIXEL_FORMAT_RGB_565) { - return 0; - } - LOG_ERR("Unsupported pixel format"); - return -ENOTSUP; -} - -static int ssd1351_init_device(const struct device *dev) -{ - const struct ssd1351_config *config = dev->config; - int err; - - /* Turn display off */ - err = ssd1351_suspend(dev); - if (err < 0) { - return err; - } - - err = ssd1351_set_hardware_config(dev); - if (err < 0) { - return err; - } - - err = ssd1351_set_contrast(dev, CONFIG_SSD1351_DEFAULT_CONTRAST); - if (err < 0) { - return err; - } - - err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, - config->color_inversion ? SSD1351_SET_REVERSE_DISPLAY - : SSD1351_SET_NORMAL_DISPLAY, - NULL, 0); - if (err < 0) { - return err; - } - - err = ssd1351_resume(dev); - if (err < 0) { - return err; - } - - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -static int ssd1351_init(const struct device *dev) -{ - const struct ssd1351_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!device_is_ready(config->mipi_dev)) { - LOG_ERR("MIPI Device not ready!"); - return -EINVAL; - } - - err = mipi_dbi_reset(config->mipi_dev, SSD1351_RESET_DELAY); - if (err < 0) { - LOG_ERR("Failed to reset device!"); - return err; - } - - err = ssd1351_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} - -static DEVICE_API(display, ssd1351_driver_api) = { - .blanking_on = ssd1351_suspend, - .blanking_off = ssd1351_resume, - .write = ssd1351_write, - .set_contrast = ssd1351_set_contrast, - .get_capabilities = ssd1351_get_capabilities, - .set_pixel_format = ssd1351_set_pixel_format, -}; - -#define SSD1351_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define SSD1351_DEFINE_MIPI(node_id) \ - static const struct ssd1351_config config##node_id = { \ - .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, SSD1351_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .precharge_time = DT_PROP(node_id, precharge_time), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .current_att = DT_PROP(node_id, current_att), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .remap_value = DT_PROP(node_id, remap_value), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, ssd1351_init, NULL, NULL, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1351_driver_api); - -DT_FOREACH_STATUS_OKAY(solomon_ssd1351, SSD1351_DEFINE_MIPI) diff --git a/drivers/display/display_st75256.c b/drivers/display/display_st75256.c deleted file mode 100644 index 7be532ec78b69..0000000000000 --- a/drivers/display/display_st75256.c +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "zephyr/sys/util.h" -#define DT_DRV_COMPAT sitronix_st75256 - -#include -LOG_MODULE_REGISTER(st75256, CONFIG_DISPLAY_LOG_LEVEL); - -#include -#include -#include -#include -#include -#include -#include - -#define ST75256_EXTCOM 0x30 -#define ST75256_EXTCOM_1 ST75256_EXTCOM -#define ST75256_EXTCOM_2 ST75256_EXTCOM + 1 -#define ST75256_EXTCOM_3 ST75256_EXTCOM + 8 -#define ST75256_EXTCOM_4 ST75256_EXTCOM + 9 - -/* EXTCOM_1 Commands */ -#define ST75256_DISPLAY_NORMAL 0xa6 -#define ST75256_DISPLAY_INVERT 0xa7 -#define ST75256_DISPLAY_ON 0xaf -#define ST75256_DISPLAY_OFF 0xae -#define ST75256_ALL_OFF 0x22 -#define ST75256_ALL_ON 0x23 -#define ST75256_SLEEP_IN 0x95 -#define ST75256_SLEEP_OUT 0x94 -#define ST75256_SET_VOP 0x81 -#define ST75256_COL_RANGE 0x15 -#define ST75256_PAGE_RANGE 0x75 -#define ST75256_LSB_BOTTOM 0x8 -#define ST75256_LSB_TOP 0xc -#define ST75256_FLIP_CONFIG 0xbc -#define ST75256_DISP_CONTROL 0xca -#define ST75256_MULTI_MASTER 0x6E -#define ST75256_MULTI_SLAVE 0x6F -#define ST75256_START_WRITE 0x5C - -#define ST75256_COLOR_MODE 0xf0 -#define ST75256_GREYSCALE 0x11 -#define ST75256_MONO 0x10 - -#define ST75256_POWER_CONTROL 0x20 - -/* EXTCOM_2 Commands */ -#define ST75256_AUTOREAD 0xd7 -#define ST75256_AUTOREAD_ENABLE 0x8f -#define ST75256_AUTOREAD_DISABLE 0x9f -#define ST75256_ANALOG_SETTINGS 0x32 -#define ST75256_OTP_READ 0xE3 -#define ST75256_OTP_WRITE 0xE2 -#define ST75256_OTP_OUT 0xE1 -#define ST75256_SET_GREY 0x20 -#define ST75256_POWER_INTERNAL 0x40 -#define ST75256_POWER_EXTERNAL 0x41 - -#define ST75256_OTP_RW 0xE0 -#define ST75256_OTP_RW_READ 0x00 -#define ST75256_OTP_RW_WRITE 0x20 - -#define ST75256_BOOSTER_LEVEL 0x51 -#define ST75256_BOOSTER_LEVEL_10 0xFB -#define ST75256_BOOSTER_LEVEL_8 0xFA - -struct st75256_config { - const struct device *mipi_dev; - struct mipi_dbi_config dbi_config; - uint16_t height; - uint16_t width; - uint8_t booster_frequency; - uint8_t bias_ratio; - bool lsb_invdir; - uint8_t flip_configuration; - uint8_t duty; - uint8_t fi_settings; - uint8_t power_control; - uint8_t light_grey; - uint8_t dark_grey; - bool external_power; - bool inversion_on; - uint8_t *conversion_buf; - size_t conversion_buf_size; -}; - -struct st75256_data { - int current_pixel_format; - int current_screen_info; -}; - -static inline int st75256_write_command(const struct device *dev, uint8_t cmd, const uint8_t *buf, - size_t len) -{ - const struct st75256_config *config = dev->config; - - return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, buf, len); -} - -static int st75256_blanking_on(const struct device *dev) -{ - int err; - - err = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (err < 0) { - return err; - } - err = st75256_write_command(dev, ST75256_DISPLAY_OFF, NULL, 0); - if (err < 0) { - return err; - } - return st75256_write_command(dev, ST75256_SLEEP_IN, NULL, 0); -} - -static int st75256_blanking_off(const struct device *dev) -{ - int err; - - err = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (err < 0) { - return err; - } - err = st75256_write_command(dev, ST75256_SLEEP_OUT, NULL, 0); - if (err < 0) { - return err; - } - /* Wait 10 msec to allow display out of sleep */ - k_msleep(10); - return st75256_write_command(dev, ST75256_DISPLAY_ON, NULL, 0); -} - -static int st75256_set_window(const struct device *dev, int x, int y, int width, int height) -{ - struct st75256_data *data = dev->data; - int ret; - uint8_t x_position[] = {x, x + width - 1}; - uint8_t y_position[2]; - - if (data->current_pixel_format == PIXEL_FORMAT_L_8) { - y_position[0] = y / 4; - y_position[1] = ((y + height) / 4) - 1; - } else { - y_position[0] = y / 8; - y_position[1] = ((y + height) / 8) - 1; - } - - ret = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_PAGE_RANGE, y_position, 2); - if (ret < 0) { - return ret; - } - - return st75256_write_command(dev, ST75256_COL_RANGE, x_position, 2); -} - -static int st75256_start_write(const struct device *dev) -{ - int ret; - - ret = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (ret < 0) { - return ret; - } - - return st75256_write_command(dev, ST75256_START_WRITE, NULL, 0); -} - -static int st75256_write_pixels_MONO01(const struct device *dev, const uint16_t x, const uint16_t y, - const uint8_t *buf, - const struct display_buffer_descriptor *desc) -{ - const struct st75256_config *config = dev->config; - struct display_buffer_descriptor mipi_desc; - int ret; - - for (int i = 0; i < desc->height / 8; i++) { - st75256_set_window(dev, x, y + i * 8, desc->width, desc->height); - st75256_start_write(dev); - mipi_desc.buf_size = desc->width; - mipi_desc.width = desc->width; - mipi_desc.height = 8; - ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc, - PIXEL_FORMAT_MONO01); - if (ret < 0) { - return ret; - } - } - return mipi_dbi_release(config->mipi_dev, &config->dbi_config); -} - -/* ST75256 4-level is greyscale is 4 pixels per byte vtiled. - * It also does not have windowing capability so we do one line per one line. - */ -static int st75256_write_pixels_L_8(const struct device *dev, const uint16_t x, const uint16_t y, - const uint8_t *buf, - const struct display_buffer_descriptor *desc) -{ - const struct st75256_config *config = dev->config; - struct display_buffer_descriptor mipi_desc; - int32_t line_count = desc->height; - int ret, l; - int line_total = 0; - - mipi_desc.pitch = desc->pitch; - - st75256_set_window(dev, x, y, desc->width, desc->height); - st75256_start_write(dev); - while (line_count > line_total) { - l = 0; - - /* Convert what the conversion buffer can hold to - * pixelx[7:6], pixelx+pitch[5:4], pixelx+2pitch[3:2], pixelx+3pitch[1:0] - */ - for (; l * desc->width / 4 < config->conversion_buf_size && - line_count > line_total + l; - l += 4) { - int i_lt = line_total + l; - - for (int i = 0; i < desc->width && - i + l * desc->width / 4 < config->conversion_buf_size; - i++) { - int i_l = i + l * desc->width / 4; - - config->conversion_buf[i_l] = - ((buf[i + (i_lt + 0) * desc->pitch] >> 6) << 0) | - ((buf[i + (i_lt + 1) * desc->pitch] >> 6) << 2) | - ((buf[i + (i_lt + 2) * desc->pitch] >> 6) << 4) | - ((buf[i + (i_lt + 3) * desc->pitch] >> 6) << 6); - } - } - mipi_desc.buf_size = l * desc->width / 4; - mipi_desc.width = desc->width; - mipi_desc.height = l; - - /* This is the wrong format, but it doesn't matter to almost all mipi drivers */ - ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, - config->conversion_buf, &mipi_desc, PIXEL_FORMAT_L_8); - if (ret < 0) { - return ret; - } - line_total += l; - } - mipi_dbi_release(config->mipi_dev, &config->dbi_config); - return 0; -} - -static int st75256_write(const struct device *dev, const uint16_t x, const uint16_t y, - const struct display_buffer_descriptor *desc, const void *buf) -{ - struct st75256_data *data = dev->data; - size_t buf_len; - - /* pitch is always width because of vtiled monochrome at 8 pixels per byte - * or greyscale at one pixel per byte converted to vtiled 4 pixels per byte - */ - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; - } - - if (data->current_pixel_format == PIXEL_FORMAT_MONO01) { - buf_len = MIN(desc->buf_size, desc->height * desc->width / 8); - if ((y % 8) != 0 || (desc->height % 8) != 0) { - LOG_ERR("Y and height must be aligned on 8 boundary"); - return -EINVAL; - } - } else if (data->current_pixel_format == PIXEL_FORMAT_L_8) { - buf_len = MIN(desc->buf_size, desc->height * desc->width / 4); - if ((y % 4) != 0 || (desc->height % 4) != 0) { - LOG_ERR("Y and height must be aligned on 4 boundary"); - return -EINVAL; - } - } else { - return -EINVAL; - } - - if (buf == NULL || buf_len == 0U) { - LOG_ERR("Display buffer is not available"); - return -EINVAL; - } - - LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, - desc->width, desc->height, buf_len); - - if (data->current_pixel_format == PIXEL_FORMAT_L_8) { - return st75256_write_pixels_L_8(dev, x, y, buf, desc); - } else { - return st75256_write_pixels_MONO01(dev, x, y, buf, desc); - } -} - -static int st75256_set_contrast(const struct device *dev, const uint8_t contrast) -{ - int err; - uint8_t contrast_out[2]; - - err = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (err < 0) { - return err; - } - contrast_out[0] = (contrast & 0x1f) << 1; - contrast_out[1] = contrast >> 5; - return st75256_write_command(dev, ST75256_SET_VOP, contrast_out, sizeof(contrast_out)); -} - -static void st75256_get_capabilities(const struct device *dev, struct display_capabilities *caps) -{ - const struct st75256_config *config = dev->config; - struct st75256_data *data = dev->data; - - memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = config->width; - caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_MONO01 | PIXEL_FORMAT_L_8; - caps->current_pixel_format = data->current_pixel_format; - caps->screen_info = data->current_screen_info; -} - -static int st75256_set_pixel_format(const struct device *dev, - const enum display_pixel_format pixel_format) -{ - struct st75256_data *data = dev->data; - uint8_t tmp; - int ret; - - if (pixel_format == PIXEL_FORMAT_MONO01) { - tmp = ST75256_MONO; - ret = st75256_write_command(dev, ST75256_COLOR_MODE, &tmp, 1); - if (ret < 0) { - return ret; - } - data->current_screen_info = SCREEN_INFO_MONO_VTILED; - data->current_pixel_format = PIXEL_FORMAT_MONO01; - } else if (pixel_format == PIXEL_FORMAT_L_8) { - tmp = ST75256_GREYSCALE; - ret = st75256_write_command(dev, ST75256_COLOR_MODE, &tmp, 1); - if (ret < 0) { - return ret; - } - data->current_screen_info = 0; - data->current_pixel_format = PIXEL_FORMAT_L_8; - } else { - LOG_ERR("Unsupported Pixel format"); - return -EINVAL; - } - return 0; -} - -static int st75256_init_device(const struct device *dev) -{ - int ret; - uint8_t data[16]; - const struct st75256_config *config = dev->config; - - ret = mipi_dbi_reset(config->mipi_dev, 1); - if (ret < 0) { - return ret; - } - k_msleep(10); - - ret = st75256_blanking_off(dev); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (ret < 0) { - return ret; - } - - /* Enable Master mode (multidisplay) */ - ret = st75256_write_command(dev, ST75256_MULTI_MASTER, NULL, 0); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_EXTCOM_2, NULL, 0); - if (ret < 0) { - return ret; - } - - data[0] = ST75256_AUTOREAD_DISABLE; - ret = st75256_write_command(dev, ST75256_AUTOREAD, data, 1); - if (ret < 0) { - return ret; - } - - data[0] = ST75256_OTP_RW_READ; - ret = st75256_write_command(dev, ST75256_OTP_RW, data, 1); - if (ret < 0) { - return ret; - } - - k_msleep(10); - /* Load OTPs */ - ret = st75256_write_command(dev, ST75256_OTP_READ, NULL, 0); - if (ret < 0) { - return ret; - } - k_msleep(20); - - ret = st75256_write_command(dev, ST75256_OTP_OUT, NULL, 0); - if (ret < 0) { - return ret; - } - - ret = st75256_blanking_off(dev); - if (ret < 0) { - return ret; - } - k_msleep(20); - - ret = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_POWER_CONTROL, &config->power_control, 1); - if (ret < 0) { - return ret; - } - - ret = st75256_set_contrast(dev, CONFIG_ST75256_DEFAULT_CONTRAST); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_EXTCOM_2, NULL, 0); - if (ret < 0) { - return ret; - } - - data[0] = 0; - data[1] = 0; - data[2] = 0; - data[3] = config->light_grey; - data[4] = config->light_grey; - data[5] = config->light_grey; - data[6] = 0; - data[7] = 0; - data[8] = config->dark_grey; - data[9] = 0; - data[10] = 0; - data[11] = config->dark_grey; - data[12] = config->dark_grey; - data[13] = config->dark_grey; - data[14] = 0; - data[15] = 0; - ret = st75256_write_command(dev, ST75256_SET_GREY, data, 16); - if (ret < 0) { - return ret; - } - - data[0] = 0; - data[1] = config->booster_frequency; - data[2] = config->bias_ratio; - ret = st75256_write_command(dev, ST75256_ANALOG_SETTINGS, data, 3); - if (ret < 0) { - return ret; - } - - data[0] = ST75256_BOOSTER_LEVEL_10; - ret = st75256_write_command(dev, ST75256_BOOSTER_LEVEL, data, 1); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command( - dev, config->external_power ? ST75256_POWER_EXTERNAL : ST75256_POWER_INTERNAL, NULL, - 0); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command(dev, ST75256_EXTCOM_1, NULL, 0); - if (ret < 0) { - return ret; - } - -#if CONFIG_ST75256_DEFAULT_GREYSCALE - data[0] = ST75256_GREYSCALE; - ret = st75256_write_command(dev, ST75256_COLOR_MODE, data, 1); - if (ret < 0) { - return ret; - } -#else - data[0] = ST75256_MONO; - ret = st75256_write_command(dev, ST75256_COLOR_MODE, data, 1); - if (ret < 0) { - return ret; - } -#endif - - ret = st75256_write_command(dev, config->lsb_invdir ? ST75256_LSB_BOTTOM : ST75256_LSB_TOP, - NULL, 0); - if (ret < 0) { - return ret; - } - - data[0] = 0; - data[1] = config->duty; - data[2] = config->fi_settings; - ret = st75256_write_command(dev, ST75256_DISP_CONTROL, data, 3); - if (ret < 0) { - return ret; - } - - data[0] = config->flip_configuration; - ret = st75256_write_command(dev, ST75256_FLIP_CONFIG, data, 1); - if (ret < 0) { - return ret; - } - - ret = st75256_write_command( - dev, config->inversion_on ? ST75256_DISPLAY_INVERT : ST75256_DISPLAY_NORMAL, NULL, - 0); - if (ret < 0) { - return ret; - } - return st75256_blanking_off(dev); -} - -static int st75256_init(const struct device *dev) -{ - const struct st75256_config *config = dev->config; - int ret; - - if (!device_is_ready(config->mipi_dev)) { - LOG_ERR("MIPI not ready!"); - return -ENODEV; - } - - ret = st75256_init_device(dev); - if (ret < 0) { - LOG_ERR("Failed to initialize device, err = %d", ret); - } - - return ret; -} - -static DEVICE_API(display, st75256_driver_api) = { - .blanking_on = st75256_blanking_on, - .blanking_off = st75256_blanking_off, - .write = st75256_write, - .set_contrast = st75256_set_contrast, - .get_capabilities = st75256_get_capabilities, - .set_pixel_format = st75256_set_pixel_format, -}; - -#define ST75256_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define ST75256_CONV_BUFFER_SIZE(node_id) \ - DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_ST75256_CONV_BUFFER_LINES, 4) - -#if CONFIG_ST75256_DEFAULT_GREYSCALE -#define ST75256_DATA(node_id) \ - static struct st75256_data data##node_id = { \ - .current_pixel_format = PIXEL_FORMAT_L_8, \ - .current_screen_info = 0, \ - }; -#else -#define ST75256_DATA(node_id) \ - static struct st75256_data data##node_id = { \ - .current_pixel_format = PIXEL_FORMAT_MONO01, \ - .current_screen_info = SCREEN_INFO_MONO_VTILED, \ - }; -#endif - -#define ST75256_DEFINE(node_id) \ - ST75256_DATA(node_id) \ - static uint8_t conversion_buf##node_id[ST75256_CONV_BUFFER_SIZE(node_id)]; \ - static const struct st75256_config config##node_id = { \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .booster_frequency = DT_PROP(node_id, booster_frequency), \ - .bias_ratio = DT_PROP(node_id, bias_ratio), \ - .lsb_invdir = DT_PROP(node_id, lsb_invdir), \ - .flip_configuration = DT_PROP(node_id, flip_configuration), \ - .duty = DT_PROP(node_id, duty), \ - .power_control = DT_PROP(node_id, power_control), \ - .light_grey = DT_PROP(node_id, light_grey), \ - .dark_grey = DT_PROP(node_id, dark_grey), \ - .external_power = DT_PROP(node_id, external_power), \ - .fi_settings = DT_PROP(node_id, fi_settings), \ - .inversion_on = DT_PROP(node_id, inversion_on), \ - .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, ST75256_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ - .conversion_buf = conversion_buf##node_id, \ - .conversion_buf_size = sizeof(conversion_buf##node_id), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, st75256_init, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &st75256_driver_api); - -DT_FOREACH_STATUS_OKAY(sitronix_st75256, ST75256_DEFINE) diff --git a/drivers/display/display_st7567.c b/drivers/display/display_st7567.c index f37db1d7690d9..15491f0561845 100644 --- a/drivers/display/display_st7567.c +++ b/drivers/display/display_st7567.c @@ -338,7 +338,7 @@ static int st7567_reset(const struct device *dev) static int st7567_clear(const struct device *dev) { const struct st7567_config *config = dev->config; - int ret = 0; + int ret; uint8_t buf = 0; uint8_t cmd_buf[] = { diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c index e1e6ab82604bd..2de41651fd9ec 100644 --- a/drivers/display/display_stm32_ltdc.c +++ b/drivers/display/display_stm32_ltdc.c @@ -94,7 +94,7 @@ static void stm32_ltdc_global_isr(const struct device *dev) data->front_buf = data->pend_buf; LTDC_LAYER(&data->hltdc, LTDC_LAYER_1)->CFBAR = (uint32_t)data->front_buf; - __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(&data->hltdc); + __HAL_LTDC_RELOAD_CONFIG(&data->hltdc); k_sem_give(&data->sem); } @@ -264,23 +264,11 @@ static int stm32_ltdc_display_blanking_off(const struct device *dev) { const struct display_stm32_ltdc_config *config = dev->config; const struct device *display_dev = config->display_controller; - int err; - - if (!display_dev && !config->bl_ctrl_gpio.port) { - return -ENOSYS; - } - - /* Turn on backlight (if its GPIO is defined in device tree) */ - if (config->bl_ctrl_gpio.port) { - err = gpio_pin_set_dt(&config->bl_ctrl_gpio, 1); - if (err < 0) { - return err; - } - } /* Panel controller's phandle is not passed to LTDC in devicetree */ - if (!display_dev) { - return 0; + if (display_dev == NULL) { + LOG_ERR("There is no panel controller to forward blanking_off call to"); + return -ENOSYS; } if (!device_is_ready(display_dev)) { @@ -295,23 +283,11 @@ static int stm32_ltdc_display_blanking_on(const struct device *dev) { const struct display_stm32_ltdc_config *config = dev->config; const struct device *display_dev = config->display_controller; - int err; - - if (!display_dev && !config->bl_ctrl_gpio.port) { - return -ENOSYS; - } - - /* Turn off backlight (if its GPIO is defined in device tree) */ - if (config->bl_ctrl_gpio.port) { - err = gpio_pin_set_dt(&config->bl_ctrl_gpio, 0); - if (err < 0) { - return err; - } - } /* Panel controller's phandle is not passed to LTDC in devicetree */ - if (!display_dev) { - return 0; + if (display_dev == NULL) { + LOG_ERR("There is no panel controller to forward blanking_on call to"); + return -ENOSYS; } if (!device_is_ready(display_dev)) { @@ -350,7 +326,7 @@ static int stm32_ltdc_init(const struct device *dev) /* Configure and set display backlight control GPIO */ if (config->bl_ctrl_gpio.port) { - err = gpio_pin_configure_dt(&config->bl_ctrl_gpio, GPIO_OUTPUT_INACTIVE); + err = gpio_pin_configure_dt(&config->bl_ctrl_gpio, GPIO_OUTPUT_ACTIVE); if (err < 0) { LOG_ERR("Configuration of display backlight control GPIO failed"); return err; @@ -443,7 +419,7 @@ static int stm32_ltdc_init(const struct device *dev) #if defined(CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP) data->frame_buffer = shared_multi_heap_aligned_alloc( - CONFIG_STM32_LTDC_FB_SMH_ATTRIBUTE, + CONFIG_VIDEO_BUFFER_SMH_ATTRIBUTE, 32, CONFIG_STM32_LTDC_FB_NUM * data->frame_buffer_len); @@ -467,7 +443,7 @@ static int stm32_ltdc_init(const struct device *dev) /* Configure RIF for LTDC layer 1 */ rimc.MasterCID = RIF_CID_1; rimc.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV; - HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC1, &rimc); + HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC1 , &rimc); HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL1, RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV); #endif @@ -560,8 +536,7 @@ static DEVICE_API(display, stm32_ltdc_display_api) = { #elif DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(psram)) #define FRAME_BUFFER_SECTION __stm32_psram_section #else -#error "LTDC ext-sdram property in device tree does not reference SDRAM1 or SDRAM2 node or PSRAM "\ - "node" +#error "LTDC ext-sdram property in device tree does not reference SDRAM1 or SDRAM2 node or PSRAM node" #define FRAME_BUFFER_SECTION #endif /* DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram1)) */ diff --git a/drivers/display/ssd1327.c b/drivers/display/ssd1327.c index f7e477877a0cf..9066c8c0d2a14 100644 --- a/drivers/display/ssd1327.c +++ b/drivers/display/ssd1327.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2024 Savoir-faire Linux - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,26 +12,19 @@ LOG_MODULE_REGISTER(ssd1327, CONFIG_DISPLAY_LOG_LEVEL); #include #include #include -#include #include #include #include "ssd1327_regs.h" -#define SSD1327_ENABLE_VDD 0x01 -#define SSD1327_UNLOCK_COMMAND 0x12 -#define SSD1327_MAXIMUM_CMD_LENGTH 16 - -typedef int (*ssd1327_write_bus_cmd_fn)(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len); -typedef int (*ssd1327_write_pixels_fn)(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc); +#define SSD1327_ENABLE_VDD 0x01 +#define SSD1327_ENABLE_SECOND_PRECHARGE 0x62 +#define SSD1327_VCOMH_VOLTAGE 0x0f +#define SSD1327_PHASES_VALUE 0xf1 +#define SSD1327_DEFAULT_PRECHARGE_V 0x08 +#define SSD1327_UNLOCK_COMMAND 0x12 struct ssd1327_config { - struct i2c_dt_spec i2c; - ssd1327_write_bus_cmd_fn write_cmd; - ssd1327_write_pixels_fn write_pixels; const struct device *mipi_dev; const struct mipi_dbi_config dbi_config; uint16_t height; @@ -43,13 +35,7 @@ struct ssd1327_config { uint8_t multiplex_ratio; uint8_t prechargep; uint8_t remap_value; - uint8_t phase_length; - uint8_t function_selection_b; - uint8_t precharge_voltage; - uint8_t vcomh_voltage; bool color_inversion; - uint8_t *conversion_buf; - size_t conversion_buf_size; }; struct ssd1327_data { @@ -57,8 +43,8 @@ struct ssd1327_data { uint8_t scan_mode; }; -static inline int ssd1327_write_bus_cmd_mipi(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) +static inline int ssd1327_write_bus_cmd(const struct device *dev, const uint8_t cmd, + const uint8_t *data, size_t len) { const struct ssd1327_config *config = dev->config; int err; @@ -81,256 +67,186 @@ static inline int ssd1327_write_bus_cmd_mipi(const struct device *dev, const uin return 0; } -static inline int ssd1327_write_bus_cmd_i2c(const struct device *dev, const uint8_t cmd, - const uint8_t *data, size_t len) -{ - const struct ssd1327_config *config = dev->config; - uint8_t buf[SSD1327_MAXIMUM_CMD_LENGTH]; - - if (len > SSD1327_MAXIMUM_CMD_LENGTH - 1) { - return -EINVAL; - } - - buf[0] = cmd; - memcpy(&(buf[1]), data, len); - - return i2c_burst_write_dt(&config->i2c, SSD1327_CONTROL_ALL_BYTES_CMD, buf, len + 1); -} - static inline int ssd1327_set_timing_setting(const struct device *dev) { const struct ssd1327_config *config = dev->config; - uint8_t buf = SSD1327_UNLOCK_COMMAND; - int err; + uint8_t buf; - err = config->write_cmd(dev, SSD1327_SET_PHASE_LENGTH, &config->phase_length, 1); - if (err < 0) { - return err; + buf = SSD1327_PHASES_VALUE; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PHASE_LENGTH, &buf, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_OSC_FREQ, &config->oscillator_freq, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_OSC_FREQ, &config->oscillator_freq, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_PRECHARGE_PERIOD, &config->prechargep, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_PERIOD, &config->prechargep, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_LINEAR_LUT, NULL, 0); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_LINEAR_LUT, NULL, 0)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_PRECHARGE_VOLTAGE, &config->precharge_voltage, 1); - if (err < 0) { - return err; + buf = SSD1327_DEFAULT_PRECHARGE_V; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_VOLTAGE, &buf, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_VCOMH, &config->vcomh_voltage, 1); - if (err < 0) { - return err; + buf = SSD1327_VCOMH_VOLTAGE; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_VCOMH, &buf, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_FUNCTION_SELECTION_B, &config->function_selection_b, - 1); - if (err < 0) { - return err; + buf = SSD1327_ENABLE_SECOND_PRECHARGE; + if (ssd1327_write_bus_cmd(dev, SSD1327_FUNCTION_SELECTION_B, &buf, 1)) { + return -EIO; + } + buf = SSD1327_UNLOCK_COMMAND; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COMMAND_LOCK, &buf, 1)) { + return -EIO; } - return config->write_cmd(dev, SSD1327_SET_COMMAND_LOCK, &buf, 1); + + return 0; } static inline int ssd1327_set_hardware_config(const struct device *dev) { const struct ssd1327_config *config = dev->config; uint8_t buf; - int err; - err = config->write_cmd(dev, SSD1327_SET_DISPLAY_START_LINE, &config->start_line, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_START_LINE, &config->start_line, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_DISPLAY_OFFSET, &config->display_offset, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_OFFSET, &config->display_offset, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_NORMAL_DISPLAY, NULL, 0); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_NORMAL_DISPLAY, NULL, 0)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1)) { + return -EIO; } buf = SSD1327_ENABLE_VDD; - return config->write_cmd(dev, SSD1327_SET_FUNCTION_A, &buf, 1); + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_FUNCTION_A, &buf, 1)) { + return -EIO; + } + + return 0; } static int ssd1327_resume(const struct device *dev) { - const struct ssd1327_config *config = dev->config; - - return config->write_cmd(dev, SSD1327_DISPLAY_ON, NULL, 0); + return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_ON, NULL, 0); } static int ssd1327_suspend(const struct device *dev) { - const struct ssd1327_config *config = dev->config; - - return config->write_cmd(dev, SSD1327_DISPLAY_OFF, NULL, 0); + return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_OFF, NULL, 0); } static int ssd1327_set_display(const struct device *dev) { const struct ssd1327_config *config = dev->config; - int err; - uint8_t x_position[] = {0, config->width - 1}; - uint8_t y_position[] = {0, config->height - 1}; + uint8_t x_position[] = { + 0, + config->width - 1 + }; + uint8_t y_position[] = { + 0, + config->height - 1 + }; - err = config->write_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position)); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position))) { + return -EIO; } - err = config->write_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position)); - if (err < 0) { - return err; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position))) { + return -EIO; } - return config->write_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1); -} - -/* Convert what the conversion buffer can hold to pixelx (3:0) and pixelx+1 (7:4) */ -static int ssd1327_convert_L_8(const struct device *dev, const uint8_t *buf, int cur_offset, - uint32_t pixel_count) -{ - const struct ssd1327_config *config = dev->config; - int i = 0; - - for (; i / 2 < config->conversion_buf_size && pixel_count > cur_offset + i; i += 2) { - config->conversion_buf[i / 2] = buf[cur_offset + i] >> 4; - config->conversion_buf[i / 2] |= (buf[cur_offset + i + 1] >> 4) << 4; - } - return i; -} - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1327fb, mipi_dbi) -static int ssd1327_write_pixels_mipi(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc) -{ - const struct ssd1327_config *config = dev->config; - struct display_buffer_descriptor mipi_desc; - int ret, i; - int total = 0; - - mipi_desc.pitch = desc->pitch; - - while (pixel_count > total) { - i = ssd1327_convert_L_8(dev, buf, total, pixel_count); - - mipi_desc.buf_size = i / 2; - mipi_desc.width = mipi_desc.buf_size / desc->height; - mipi_desc.height = mipi_desc.buf_size / desc->width; - - /* This is the wrong format, but it doesn't matter to almost all mipi drivers */ - ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, - config->conversion_buf, &mipi_desc, PIXEL_FORMAT_L_8); - if (ret < 0) { - return ret; - } - total += i; + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) { + return -EIO; } - mipi_dbi_release(config->mipi_dev, &config->dbi_config); - return 0; -} -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1327fb, i2c) -static int ssd1327_write_pixels_i2c(const struct device *dev, const uint8_t *buf, - uint32_t pixel_count, - const struct display_buffer_descriptor *desc) -{ - const struct ssd1327_config *config = dev->config; - int ret, i; - int total = 0; - while (pixel_count > total) { - i = ssd1327_convert_L_8(dev, buf, total, pixel_count); - - ret = i2c_burst_write_dt(&config->i2c, SSD1327_CONTROL_ALL_BYTES_DATA, - config->conversion_buf, i / 2); - if (ret < 0) { - return ret; - } - total += i; - } return 0; } -#endif static int ssd1327_write(const struct device *dev, const uint16_t x, const uint16_t y, const struct display_buffer_descriptor *desc, const void *buf) { const struct ssd1327_config *config = dev->config; + struct display_buffer_descriptor mipi_desc; int err; size_t buf_len; - int32_t pixel_count = desc->width * desc->height; - uint8_t x_position[] = {x / 2, (x + desc->width - 1) / 2}; - uint8_t y_position[] = {y, y + desc->height - 1}; + uint8_t x_position[] = { x, x + desc->width - 1 }; + uint8_t y_position[] = { y, y + desc->height - 1 }; - if (desc->pitch != desc->width) { - LOG_ERR("Pitch is not width"); - return -EINVAL; + if (desc->pitch < desc->width) { + LOG_ERR("Pitch is smaller than width"); + return -1; } + mipi_desc.pitch = desc->pitch; /* Following the datasheet, in the GDDRAM, two segment are split in one register */ buf_len = MIN(desc->buf_size, desc->height * desc->width / 2); if (buf == NULL || buf_len == 0U) { LOG_ERR("Display buffer is not available"); - return -EINVAL; + return -1; + } + mipi_desc.buf_size = buf_len; + + if (desc->pitch > desc->width) { + LOG_ERR("Unsupported mode"); + return -1; } - if ((x & 1) != 0U) { + if ((y & 0x7) != 0U) { LOG_ERR("Unsupported origin"); - return -EINVAL; + return -1; } + mipi_desc.height = desc->height; + mipi_desc.width = desc->width; LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, desc->width, desc->height, buf_len); - err = config->write_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position)); + err = ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position)); if (err) { return err; } - err = config->write_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position)); + err = ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position)); if (err) { return err; } - return config->write_pixels(dev, buf, pixel_count, desc); + err = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc, + PIXEL_FORMAT_MONO10); + if (err) { + return err; + } + return mipi_dbi_release(config->mipi_dev, &config->dbi_config); } static int ssd1327_set_contrast(const struct device *dev, const uint8_t contrast) { - const struct ssd1327_config *config = dev->config; - - return config->write_cmd(dev, SSD1327_SET_CONTRAST_CTRL, &contrast, 1); + return ssd1327_write_bus_cmd(dev, SSD1327_SET_CONTRAST_CTRL, &contrast, 1); } -static void ssd1327_get_capabilities(const struct device *dev, struct display_capabilities *caps) +static void ssd1327_get_capabilities(const struct device *dev, + struct display_capabilities *caps) { const struct ssd1327_config *config = dev->config; memset(caps, 0, sizeof(struct display_capabilities)); caps->x_resolution = config->width; caps->y_resolution = config->height; - caps->supported_pixel_formats = PIXEL_FORMAT_L_8; - caps->current_pixel_format = PIXEL_FORMAT_L_8; - caps->screen_info = 0; + caps->supported_pixel_formats = PIXEL_FORMAT_MONO10; + caps->current_pixel_format = PIXEL_FORMAT_MONO10; + caps->screen_info = SCREEN_INFO_MONO_VTILED; } -static int ssd1327_set_pixel_format(const struct device *dev, const enum display_pixel_format pf) +static int ssd1327_set_pixel_format(const struct device *dev, + const enum display_pixel_format pf) { - if (pf == PIXEL_FORMAT_L_8) { + if (pf == PIXEL_FORMAT_MONO10) { return 0; } LOG_ERR("Unsupported pixel format"); @@ -341,53 +257,44 @@ static int ssd1327_init_device(const struct device *dev) { const struct ssd1327_config *config = dev->config; uint8_t buf; - int err; /* Turn display off */ - err = ssd1327_suspend(dev); - if (err < 0) { - return err; + if (ssd1327_suspend(dev)) { + return -EIO; } - err = ssd1327_set_display(dev); - if (err < 0) { - return err; + if (ssd1327_set_display(dev)) { + return -EIO; } - err = ssd1327_set_contrast(dev, CONFIG_SSD1327_DEFAULT_CONTRAST); - if (err < 0) { - return err; + if (ssd1327_set_contrast(dev, CONFIG_SSD1327_DEFAULT_CONTRAST)) { + return -EIO; } - err = ssd1327_set_hardware_config(dev); - if (err < 0) { - return err; + if (ssd1327_set_hardware_config(dev)) { + return -EIO; } - buf = (config->color_inversion ? SSD1327_SET_REVERSE_DISPLAY : SSD1327_SET_NORMAL_DISPLAY); - err = config->write_cmd(dev, SSD1327_SET_ENTIRE_DISPLAY_OFF, &buf, 1); - if (err < 0) { - return err; + buf = (config->color_inversion ? + SSD1327_SET_REVERSE_DISPLAY : SSD1327_SET_NORMAL_DISPLAY); + if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ENTIRE_DISPLAY_OFF, &buf, 1)) { + return -EIO; } - err = ssd1327_set_timing_setting(dev); - if (err < 0) { - return err; + if (ssd1327_set_timing_setting(dev)) { + return -EIO; } - err = ssd1327_resume(dev); - if (err < 0) { - return err; + if (ssd1327_resume(dev)) { + return -EIO; } return 0; } -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1327fb, mipi_dbi) static int ssd1327_init(const struct device *dev) { const struct ssd1327_config *config = dev->config; - int err; LOG_DBG("Initializing device"); @@ -396,45 +303,19 @@ static int ssd1327_init(const struct device *dev) return -EINVAL; } - err = mipi_dbi_reset(config->mipi_dev, SSD1327_RESET_DELAY); - if (err < 0) { + if (mipi_dbi_reset(config->mipi_dev, SSD1327_RESET_DELAY)) { LOG_ERR("Failed to reset device!"); - return err; + return -EIO; } k_msleep(SSD1327_RESET_DELAY); - err = ssd1327_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; + if (ssd1327_init_device(dev)) { + LOG_ERR("Failed to initialize device!"); + return -EIO; } return 0; } -#endif - -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1327fb, i2c) -static int ssd1327_init_i2c(const struct device *dev) -{ - const struct ssd1327_config *config = dev->config; - int err; - - LOG_DBG("Initializing device"); - - if (!i2c_is_ready_dt(&config->i2c)) { - LOG_ERR("I2C Device not ready!"); - return -EINVAL; - } - - err = ssd1327_init_device(dev); - if (err < 0) { - LOG_ERR("Failed to initialize device! %d", err); - return err; - } - - return 0; -} -#endif static DEVICE_API(display, ssd1327_driver_api) = { .blanking_on = ssd1327_suspend, @@ -445,47 +326,15 @@ static DEVICE_API(display, ssd1327_driver_api) = { .set_pixel_format = ssd1327_set_pixel_format, }; -#define SSD1327_WORD_SIZE(inst) \ - ((DT_STRING_UPPER_TOKEN(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) \ - : SPI_WORD_SET(9)) - -#define SSD1327_CONV_BUFFER_SIZE(node_id) \ - DIV_ROUND_UP(DT_PROP(node_id, width) * CONFIG_SSD1327_CONV_BUFFER_LINES, 2) - -#define SSD1327_DEFINE_I2C(node_id) \ - static uint8_t conversion_buf##node_id[SSD1327_CONV_BUFFER_SIZE(node_id)]; \ - static struct ssd1327_data data##node_id; \ - static const struct ssd1327_config config##node_id = { \ - .i2c = I2C_DT_SPEC_GET(node_id), \ - .height = DT_PROP(node_id, height), \ - .width = DT_PROP(node_id, width), \ - .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ - .display_offset = DT_PROP(node_id, display_offset), \ - .start_line = DT_PROP(node_id, start_line), \ - .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \ - .prechargep = DT_PROP(node_id, prechargep), \ - .remap_value = DT_PROP(node_id, remap_value), \ - .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .function_selection_b = DT_PROP(node_id, function_selection_b), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .write_cmd = ssd1327_write_bus_cmd_i2c, \ - .write_pixels = ssd1327_write_pixels_i2c, \ - .conversion_buf = conversion_buf##node_id, \ - .conversion_buf_size = sizeof(conversion_buf##node_id), \ - }; \ - \ - DEVICE_DT_DEFINE(node_id, ssd1327_init_i2c, NULL, &data##node_id, &config##node_id, \ - POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1327_driver_api); - -#define SSD1327_DEFINE_MIPI(node_id) \ - static uint8_t conversion_buf##node_id[SSD1327_CONV_BUFFER_SIZE(node_id)]; \ +#define SSD1327_DEFINE(node_id) \ static struct ssd1327_data data##node_id; \ static const struct ssd1327_config config##node_id = { \ .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ - .dbi_config = MIPI_DBI_CONFIG_DT( \ - node_id, SSD1327_WORD_SIZE(node_id) | SPI_OP_MODE_MASTER, 0), \ + .dbi_config = { .mode = MIPI_DBI_MODE_SPI_4WIRE, \ + .config = MIPI_DBI_SPI_CONFIG_DT(node_id, \ + SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \ + SPI_HOLD_ON_CS | SPI_LOCK_ON, 0), \ + }, \ .height = DT_PROP(node_id, height), \ .width = DT_PROP(node_id, width), \ .oscillator_freq = DT_PROP(node_id, oscillator_freq), \ @@ -495,21 +344,9 @@ static DEVICE_API(display, ssd1327_driver_api) = { .prechargep = DT_PROP(node_id, prechargep), \ .remap_value = DT_PROP(node_id, remap_value), \ .color_inversion = DT_PROP(node_id, inversion_on), \ - .phase_length = DT_PROP(node_id, phase_length), \ - .function_selection_b = DT_PROP(node_id, function_selection_b), \ - .precharge_voltage = DT_PROP(node_id, precharge_voltage), \ - .vcomh_voltage = DT_PROP(node_id, vcomh_voltage), \ - .write_cmd = ssd1327_write_bus_cmd_mipi, \ - .write_pixels = ssd1327_write_pixels_mipi, \ - .conversion_buf = conversion_buf##node_id, \ - .conversion_buf_size = sizeof(conversion_buf##node_id), \ }; \ \ DEVICE_DT_DEFINE(node_id, ssd1327_init, NULL, &data##node_id, &config##node_id, \ POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1327_driver_api); -#define SSD1327_DEFINE(node_id) \ - COND_CODE_1(DT_ON_BUS(node_id, i2c), \ - (SSD1327_DEFINE_I2C(node_id)), (SSD1327_DEFINE_MIPI(node_id))) - DT_FOREACH_STATUS_OKAY(solomon_ssd1327fb, SSD1327_DEFINE) diff --git a/drivers/display/ssd1327_regs.h b/drivers/display/ssd1327_regs.h index 45d2338fbb9b8..443a1375a55d8 100644 --- a/drivers/display/ssd1327_regs.h +++ b/drivers/display/ssd1327_regs.h @@ -45,7 +45,4 @@ /* Time constant in ms */ #define SSD1327_RESET_DELAY 10 -#define SSD1327_CONTROL_ALL_BYTES_CMD 0x0 -#define SSD1327_CONTROL_ALL_BYTES_DATA 0x40 - #endif diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma index a07b77bb85618..e6014bb04ab18 100644 --- a/drivers/dma/Kconfig.mcux_edma +++ b/drivers/dma/Kconfig.mcux_edma @@ -38,11 +38,9 @@ config DMA_TCD_QUEUE_SIZE config DMA_MCUX_TEST_SLOT_START int "test slot start num" - depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF \ - || SOC_SERIES_S32K3 || SOC_SERIES_S32ZE || SOC_SERIES_KE1XZ) + depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3 || SOC_SERIES_S32ZE) default 58 if SOC_SERIES_KINETIS_K6X default 60 if SOC_SERIES_KINETIS_KE1XF - default 60 if SOC_SERIES_KE1XZ default 62 if SOC_SERIES_S32K3 || SOC_SERIES_S32ZE help test slot start num diff --git a/drivers/dma/dma_dw.c b/drivers/dma/dma_dw.c index d8e0e3d599a6a..8545ed7dffcfa 100644 --- a/drivers/dma/dma_dw.c +++ b/drivers/dma/dma_dw.c @@ -105,7 +105,7 @@ static DEVICE_API(dma, dw_dma_driver_api) = { }; \ \ DEVICE_DT_INST_DEFINE(inst, \ - dw_dma_init, \ + &dw_dma_init, \ NULL, \ &dw_dma##inst##_data, \ &dw_dma##inst##_config, POST_KERNEL, \ diff --git a/drivers/dma/dma_dw_axi.c b/drivers/dma/dma_dw_axi.c index 4f7b78ba2b8ab..a0df451ffef3e 100644 --- a/drivers/dma/dma_dw_axi.c +++ b/drivers/dma/dma_dw_axi.c @@ -897,7 +897,7 @@ static DEVICE_API(dma, dma_dw_axi_driver_api) = { }; \ \ DEVICE_DT_INST_DEFINE(inst, \ - dma_dw_axi_init, \ + &dma_dw_axi_init, \ NULL, \ &dma_dw_axi_data_##inst, \ &dma_dw_axi_config_##inst, POST_KERNEL, \ diff --git a/drivers/dma/dma_esp32_gdma.c b/drivers/dma/dma_esp32_gdma.c index 865eb33447853..cbdc66befe458 100644 --- a/drivers/dma/dma_esp32_gdma.c +++ b/drivers/dma/dma_esp32_gdma.c @@ -702,7 +702,7 @@ static void *irq_handlers[] = { }, \ }; \ \ - DEVICE_DT_INST_DEFINE(idx, dma_esp32_init, NULL, &dma_data_##idx, &dma_config_##idx, \ + DEVICE_DT_INST_DEFINE(idx, &dma_esp32_init, NULL, &dma_data_##idx, &dma_config_##idx, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_esp32_api); DT_INST_FOREACH_STATUS_OKAY(DMA_ESP32_INIT) diff --git a/drivers/dma/dma_gd32.c b/drivers/dma/dma_gd32.c index 1a61083833edd..ec6fb51d4fb38 100644 --- a/drivers/dma/dma_gd32.c +++ b/drivers/dma/dma_gd32.c @@ -696,7 +696,7 @@ static DEVICE_API(dma, dma_gd32_driver_api) = { .channels = dma_gd32##inst##_channels, \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, dma_gd32_init, NULL, \ + DEVICE_DT_INST_DEFINE(inst, &dma_gd32_init, NULL, \ &dma_gd32##inst##_data, \ &dma_gd32##inst##_config, POST_KERNEL, \ CONFIG_DMA_INIT_PRIORITY, &dma_gd32_driver_api); diff --git a/drivers/dma/dma_ifx_cat1.c b/drivers/dma/dma_ifx_cat1.c index 3ae5673e815c7..0c1aaf89ef671 100644 --- a/drivers/dma/dma_ifx_cat1.c +++ b/drivers/dma/dma_ifx_cat1.c @@ -742,7 +742,7 @@ static DEVICE_API(dma, ifx_cat1_dma_api) = { CONFIGURE_ALL_IRQS(n, DT_NUM_IRQS(DT_DRV_INST(n))); \ } \ \ - DEVICE_DT_INST_DEFINE(n, ifx_cat1_dma_init, NULL, &ifx_cat1_dma_data##n, \ + DEVICE_DT_INST_DEFINE(n, &ifx_cat1_dma_init, NULL, &ifx_cat1_dma_data##n, \ &ifx_cat1_dma_config##n, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &ifx_cat1_dma_api); diff --git a/drivers/dma/dma_intel_adsp_gpdma.c b/drivers/dma/dma_intel_adsp_gpdma.c index fc8d039170ca1..02c8e635c3df5 100644 --- a/drivers/dma/dma_intel_adsp_gpdma.c +++ b/drivers/dma/dma_intel_adsp_gpdma.c @@ -544,7 +544,7 @@ static DEVICE_API(dma, intel_adsp_gpdma_driver_api) = { PM_DEVICE_DT_INST_DEFINE(inst, gpdma_pm_action); \ \ DEVICE_DT_INST_DEFINE(inst, \ - intel_adsp_gpdma_init, \ + &intel_adsp_gpdma_init, \ PM_DEVICE_DT_INST_GET(inst), \ &intel_adsp_gpdma##inst##_data, \ &intel_adsp_gpdma##inst##_config, POST_KERNEL,\ diff --git a/drivers/dma/dma_intel_adsp_hda.c b/drivers/dma/dma_intel_adsp_hda.c index 796adc7315f57..de2b5b1c827a5 100644 --- a/drivers/dma/dma_intel_adsp_hda.c +++ b/drivers/dma/dma_intel_adsp_hda.c @@ -359,17 +359,6 @@ int intel_adsp_hda_dma_stop(const struct device *dev, uint32_t channel) return pm_device_runtime_put(dev); } -static void intel_adsp_hda_enable_irqs(const struct device *dev) -{ -#if CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT - const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; - - if (cfg->irq_config) { - cfg->irq_config(); - } -#endif -} - static void intel_adsp_hda_channels_init(const struct device *dev) { const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; @@ -386,15 +375,19 @@ static void intel_adsp_hda_channels_init(const struct device *dev) } } - intel_adsp_hda_enable_irqs(dev); +#if CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT + /* Configure interrupts */ + if (cfg->irq_config) { + cfg->irq_config(); + } +#endif } int intel_adsp_hda_dma_pm_action(const struct device *dev, enum pm_device_action action) { + ARG_UNUSED(dev); switch (action) { case PM_DEVICE_ACTION_RESUME: - intel_adsp_hda_enable_irqs(dev); - break; case PM_DEVICE_ACTION_SUSPEND: case PM_DEVICE_ACTION_TURN_ON: case PM_DEVICE_ACTION_TURN_OFF: diff --git a/drivers/dma/dma_intel_adsp_hda_host_in.c b/drivers/dma/dma_intel_adsp_hda_host_in.c index e204c702816f1..96695c0250789 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_in.c +++ b/drivers/dma/dma_intel_adsp_hda_host_in.c @@ -35,7 +35,7 @@ static DEVICE_API(dma, intel_adsp_hda_dma_host_in_api) = { \ PM_DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_pm_action); \ \ - DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_init, \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, \ PM_DEVICE_DT_INST_GET(inst), \ &intel_adsp_hda_dma##inst##_data, \ &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ diff --git a/drivers/dma/dma_intel_adsp_hda_host_out.c b/drivers/dma/dma_intel_adsp_hda_host_out.c index 2d665464bda2a..2072e35d942e7 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_out.c +++ b/drivers/dma/dma_intel_adsp_hda_host_out.c @@ -39,7 +39,7 @@ static DEVICE_API(dma, intel_adsp_hda_dma_host_out_api) = { \ PM_DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_pm_action); \ \ - DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_init, \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, \ PM_DEVICE_DT_INST_GET(inst), \ &intel_adsp_hda_dma##inst##_data, \ &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ diff --git a/drivers/dma/dma_intel_adsp_hda_link_in.c b/drivers/dma/dma_intel_adsp_hda_link_in.c index db9002679d9be..f6be51bfdd726 100644 --- a/drivers/dma/dma_intel_adsp_hda_link_in.c +++ b/drivers/dma/dma_intel_adsp_hda_link_in.c @@ -37,7 +37,7 @@ static DEVICE_API(dma, intel_adsp_hda_dma_link_in_api) = { \ PM_DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_pm_action); \ \ - DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_init, \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, \ PM_DEVICE_DT_INST_GET(inst), \ &intel_adsp_hda_dma##inst##_data, \ &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ diff --git a/drivers/dma/dma_intel_adsp_hda_link_out.c b/drivers/dma/dma_intel_adsp_hda_link_out.c index cef7f0f13762e..b3b5f1396d475 100644 --- a/drivers/dma/dma_intel_adsp_hda_link_out.c +++ b/drivers/dma/dma_intel_adsp_hda_link_out.c @@ -37,7 +37,7 @@ static DEVICE_API(dma, intel_adsp_hda_dma_link_out_api) = { \ PM_DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_pm_action); \ \ - DEVICE_DT_INST_DEFINE(inst, intel_adsp_hda_dma_init, \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, \ PM_DEVICE_DT_INST_GET(inst), \ &intel_adsp_hda_dma##inst##_data, \ &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ diff --git a/drivers/dma/dma_iproc_pax_v1.c b/drivers/dma/dma_iproc_pax_v1.c index 198858eba7e6c..4073238da1675 100644 --- a/drivers/dma/dma_iproc_pax_v1.c +++ b/drivers/dma/dma_iproc_pax_v1.c @@ -982,7 +982,7 @@ static const struct dma_iproc_pax_cfg pax_dma_cfg = { }; DEVICE_DT_INST_DEFINE(0, - dma_iproc_pax_init, + &dma_iproc_pax_init, NULL, &pax_dma_data, &pax_dma_cfg, diff --git a/drivers/dma/dma_iproc_pax_v2.c b/drivers/dma/dma_iproc_pax_v2.c index edab5432349ef..a3d7522a87ff2 100644 --- a/drivers/dma/dma_iproc_pax_v2.c +++ b/drivers/dma/dma_iproc_pax_v2.c @@ -1098,7 +1098,7 @@ static const struct dma_iproc_pax_cfg pax_dma_cfg = { }; DEVICE_DT_INST_DEFINE(0, - dma_iproc_pax_init, + &dma_iproc_pax_init, NULL, &pax_dma_data, &pax_dma_cfg, diff --git a/drivers/dma/dma_max32.c b/drivers/dma/dma_max32.c index dad7beea11e23..79bbb7b95ed33 100644 --- a/drivers/dma/dma_max32.c +++ b/drivers/dma/dma_max32.c @@ -347,7 +347,7 @@ static DEVICE_API(dma, max32_dma_driver_api) = { .channels = DT_INST_PROP(inst, dma_channels), \ .irq_configure = max32_dma##inst##_irq_configure, \ }; \ - DEVICE_DT_INST_DEFINE(inst, max32_dma_init, NULL, &dma##inst##_data, &dma##inst##_cfg, \ + DEVICE_DT_INST_DEFINE(inst, &max32_dma_init, NULL, &dma##inst##_data, &dma##inst##_cfg, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &max32_dma_driver_api); DT_INST_FOREACH_STATUS_OKAY(MAX32_DMA_INIT) diff --git a/drivers/dma/dma_mchp_xec.c b/drivers/dma/dma_mchp_xec.c index 25c8d6637c729..e54efd1526096 100644 --- a/drivers/dma/dma_mchp_xec.c +++ b/drivers/dma/dma_mchp_xec.c @@ -833,7 +833,7 @@ static int dma_xec_init(const struct device *dev) .irq_connect = dma_xec_irq_connect##i, \ }; \ PM_DEVICE_DT_DEFINE(i, dmac_xec_pm_action); \ - DEVICE_DT_INST_DEFINE(i, dma_xec_init, \ + DEVICE_DT_INST_DEFINE(i, &dma_xec_init, \ PM_DEVICE_DT_GET(i), \ &dma_xec_data##i, &dma_xec_cfg##i, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c index 0bf44b4888136..ab818cd18ec50 100644 --- a/drivers/dma/dma_mcux_edma.c +++ b/drivers/dma/dma_mcux_edma.c @@ -659,9 +659,8 @@ static int dma_mcux_edma_reload(const struct device *dev, uint32_t channel, /* Previous TCD index in circular list */ pre_idx = data->transfer_settings.write_idx - 1; - if (pre_idx >= CONFIG_DMA_TCD_QUEUE_SIZE) { + if (pre_idx >= CONFIG_DMA_TCD_QUEUE_SIZE) pre_idx = CONFIG_DMA_TCD_QUEUE_SIZE - 1; - } /* Configure a TCD for the transfer */ tcd = &(DEV_CFG(dev)->tcdpool[channel][data->transfer_settings.write_idx]); @@ -987,7 +986,7 @@ static int dma_mcux_edma_init(const struct device *dev) }; \ \ DEVICE_DT_INST_DEFINE(n, \ - dma_mcux_edma_init, NULL, \ + &dma_mcux_edma_init, NULL, \ &dma_data_##n, &dma_config_##n, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &dma_mcux_edma_api); \ diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c index c4402d8319614..c4d51d3926a02 100644 --- a/drivers/dma/dma_mcux_lpc.c +++ b/drivers/dma/dma_mcux_lpc.c @@ -19,7 +19,6 @@ #include #include #include -#include #define DT_DRV_COMPAT nxp_lpc_dma @@ -57,8 +56,6 @@ struct dma_otrig { }; struct dma_mcux_lpc_dma_data { - struct dma_context ctx; - struct channel_data *channel_data; struct dma_otrig *otrig_array; int8_t *channel_index; @@ -404,8 +401,6 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel, switch (config->channel_direction) { case MEMORY_TO_MEMORY: - case HOST_TO_MEMORY: - case MEMORY_TO_HOST: is_periph = false; if (block_config->source_gather_en && (block_config->source_gather_interval != 0)) { src_inc = block_config->source_gather_interval / width; @@ -830,50 +825,11 @@ static int dma_mcux_lpc_get_status(const struct device *dev, uint32_t channel, return 0; } -static int dma_mcux_lpc_get_attribute(const struct device *dev, uint32_t type, uint32_t *value) -{ - switch (type) { - case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT: - case DMA_ATTR_BUFFER_SIZE_ALIGNMENT: - case DMA_ATTR_COPY_ALIGNMENT: - *value = 4; - break; - - default: - return -EINVAL; - } - - return 0; -} - -static int dma_mcux_lpc_pm_action(const struct device *dev, enum pm_device_action action) -{ - switch (action) { - case PM_DEVICE_ACTION_RESUME: - break; - case PM_DEVICE_ACTION_SUSPEND: - break; - case PM_DEVICE_ACTION_TURN_OFF: - break; - case PM_DEVICE_ACTION_TURN_ON: - DMA_Init(DEV_BASE(dev)); - INPUTMUX_Init(INPUTMUX); - break; - default: - return -ENOTSUP; - } - - return 0; -} - static int dma_mcux_lpc_init(const struct device *dev) { const struct dma_mcux_lpc_config *config = dev->config; struct dma_mcux_lpc_dma_data *data = dev->data; - data->ctx.magic = DMA_MAGIC; - data->ctx.dma_channels = config->num_of_channels; - /* Indicate that the Otrig Muxes are not connected */ for (int i = 0; i < config->num_of_otrigs; i++) { data->otrig_array[i].source_channel = EMPTY_OTRIG; @@ -890,12 +846,12 @@ static int dma_mcux_lpc_init(const struct device *dev) data->num_channels_used = 0; + DMA_Init(DEV_BASE(dev)); + INPUTMUX_Init(INPUTMUX); + config->irq_config_func(dev); - /* Complete the remaining hardware specific init in the TURN_ON action - * of the power management handler. - */ - return pm_device_driver_init(dev, dma_mcux_lpc_pm_action); + return 0; } static DEVICE_API(dma, dma_mcux_lpc_api) = { @@ -904,7 +860,6 @@ static DEVICE_API(dma, dma_mcux_lpc_api) = { .stop = dma_mcux_lpc_stop, .reload = dma_mcux_lpc_reload, .get_status = dma_mcux_lpc_get_status, - .get_attribute = dma_mcux_lpc_get_attribute }; #define DMA_MCUX_LPC_CONFIG_FUNC(n) \ @@ -958,11 +913,9 @@ static const struct dma_mcux_lpc_config dma_##n##_config = { \ .otrig_array = dma_##n##_otrig_arr, \ }; \ \ - PM_DEVICE_DT_INST_DEFINE(n, dma_mcux_lpc_pm_action); \ - \ DEVICE_DT_INST_DEFINE(n, \ - dma_mcux_lpc_init, \ - PM_DEVICE_DT_INST_GET(n), \ + &dma_mcux_lpc_init, \ + NULL, \ &dma_data_##n, &dma_##n##_config, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &dma_mcux_lpc_api); \ diff --git a/drivers/dma/dma_mcux_pxp.c b/drivers/dma/dma_mcux_pxp.c index b0b2df1aa68fe..dadfa5c03cf56 100644 --- a/drivers/dma/dma_mcux_pxp.c +++ b/drivers/dma/dma_mcux_pxp.c @@ -218,7 +218,7 @@ static int dma_mcux_pxp_init(const struct device *dev) \ static struct dma_mcux_pxp_data dma_data_##n; \ \ - DEVICE_DT_INST_DEFINE(n, dma_mcux_pxp_init, NULL, &dma_data_##n, &dma_config_##n, \ + DEVICE_DT_INST_DEFINE(n, &dma_mcux_pxp_init, NULL, &dma_data_##n, &dma_config_##n, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_mcux_pxp_api); DT_INST_FOREACH_STATUS_OKAY(DMA_INIT) diff --git a/drivers/dma/dma_mcux_smartdma.c b/drivers/dma/dma_mcux_smartdma.c index 0b309efc1df4d..edc1645c6eaee 100644 --- a/drivers/dma/dma_mcux_smartdma.c +++ b/drivers/dma/dma_mcux_smartdma.c @@ -152,7 +152,7 @@ static DEVICE_API(dma, dma_mcux_smartdma_api) = { static struct dma_mcux_smartdma_data smartdma_##n##_data; \ \ DEVICE_DT_INST_DEFINE(n, \ - dma_mcux_smartdma_init, \ + &dma_mcux_smartdma_init, \ NULL, \ &smartdma_##n##_data, &smartdma_##n##_config, \ POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ diff --git a/drivers/dma/dma_nios2_msgdma.c b/drivers/dma/dma_nios2_msgdma.c index b047bdf773a25..21b86d31c620f 100644 --- a/drivers/dma/dma_nios2_msgdma.c +++ b/drivers/dma/dma_nios2_msgdma.c @@ -229,6 +229,6 @@ static struct nios2_msgdma_dev_data dma0_nios2_data = { .msgdma_dev = &msgdma_dev0, }; -DEVICE_DT_INST_DEFINE(0, nios2_msgdma0_initialize, +DEVICE_DT_INST_DEFINE(0, &nios2_msgdma0_initialize, NULL, &dma0_nios2_data, NULL, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &nios2_msgdma_driver_api); diff --git a/drivers/dma/dma_nxp_edma.c b/drivers/dma/dma_nxp_edma.c index 8a1097257a407..a9c134a37adc2 100644 --- a/drivers/dma/dma_nxp_edma.c +++ b/drivers/dma/dma_nxp_edma.c @@ -768,7 +768,7 @@ static struct edma_data edma_data_##inst = { \ .ctx.magic = DMA_MAGIC, \ }; \ \ -DEVICE_DT_INST_DEFINE(inst, edma_init, NULL, \ +DEVICE_DT_INST_DEFINE(inst, &edma_init, NULL, \ &edma_data_##inst, &edma_config_##inst, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &edma_api); \ diff --git a/drivers/dma/dma_nxp_sdma.c b/drivers/dma/dma_nxp_sdma.c index e6cd0e9dec825..ab45927247d5a 100644 --- a/drivers/dma/dma_nxp_sdma.c +++ b/drivers/dma/dma_nxp_sdma.c @@ -82,13 +82,12 @@ static int dma_nxp_sdma_consume(struct sdma_channel_data *chan_data, uint32_t by chan_data->stat.read_position += bytes; chan_data->stat.read_position %= chan_data->capacity; - if (chan_data->stat.read_position > chan_data->stat.write_position) { + if (chan_data->stat.read_position > chan_data->stat.write_position) chan_data->stat.free = chan_data->stat.read_position - chan_data->stat.write_position; - } else { + else chan_data->stat.free = chan_data->capacity - (chan_data->stat.write_position - chan_data->stat.read_position); - } chan_data->stat.pending_length = chan_data->capacity - chan_data->stat.free; @@ -103,13 +102,12 @@ static int dma_nxp_sdma_produce(struct sdma_channel_data *chan_data, uint32_t by chan_data->stat.write_position += bytes; chan_data->stat.write_position %= chan_data->capacity; - if (chan_data->stat.write_position > chan_data->stat.read_position) { + if (chan_data->stat.write_position > chan_data->stat.read_position) chan_data->stat.pending_length = chan_data->stat.write_position - chan_data->stat.read_position; - } else { + else chan_data->stat.pending_length = chan_data->capacity - (chan_data->stat.read_position - chan_data->stat.write_position); - } chan_data->stat.free = chan_data->capacity - chan_data->stat.pending_length; @@ -391,15 +389,13 @@ static int dma_nxp_sdma_reload(const struct device *dev, uint32_t channel, uint3 chan_data = &dev_data->chan[channel]; - if (!size) { + if (!size) return 0; - } - if (chan_data->direction == MEMORY_TO_PERIPHERAL) { + if (chan_data->direction == MEMORY_TO_PERIPHERAL) dma_nxp_sdma_produce(chan_data, size); - } else { + else dma_nxp_sdma_consume(chan_data, size); - } return 0; } @@ -428,13 +424,11 @@ static bool sdma_channel_filter(const struct device *dev, int chan_id, void *par struct sdma_dev_data *dev_data = dev->data; /* chan 0 is reserved for boot channel */ - if (chan_id == 0) { + if (chan_id == 0) return false; - } - if (chan_id >= FSL_FEATURE_SDMA_MODULE_CHANNEL) { + if (chan_id >= FSL_FEATURE_SDMA_MODULE_CHANNEL) return false; - } dev_data->chan[chan_id].event_source = *((int *)param); dev_data->chan[chan_id].index = chan_id; @@ -494,7 +488,7 @@ static int dma_nxp_sdma_init(const struct device *dev) dma_nxp_sdma_isr, DEVICE_DT_INST_GET(inst), 0); \ irq_enable(DT_INST_IRQN(inst)); \ } \ - DEVICE_DT_INST_DEFINE(inst, dma_nxp_sdma_init, NULL, \ + DEVICE_DT_INST_DEFINE(inst, &dma_nxp_sdma_init, NULL, \ &sdma_data_##inst, &sdma_cfg_##inst, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &sdma_api); \ diff --git a/drivers/dma/dma_pl330.c b/drivers/dma/dma_pl330.c index 2f28891bd246c..844c4c7657215 100644 --- a/drivers/dma/dma_pl330.c +++ b/drivers/dma/dma_pl330.c @@ -581,7 +581,7 @@ static const struct dma_pl330_config pl330_config = { static struct dma_pl330_dev_data pl330_data; -DEVICE_DT_INST_DEFINE(0, dma_pl330_initialize, NULL, +DEVICE_DT_INST_DEFINE(0, &dma_pl330_initialize, NULL, &pl330_data, &pl330_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &pl330_driver_api); diff --git a/drivers/dma/dma_rpi_pico.c b/drivers/dma/dma_rpi_pico.c index 8c458129ff988..9aa79de374895 100644 --- a/drivers/dma/dma_rpi_pico.c +++ b/drivers/dma/dma_rpi_pico.c @@ -380,7 +380,7 @@ static DEVICE_API(dma, dma_rpi_pico_driver_api) = { .channels = dma_rpi_pico##inst##_channels, \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, dma_rpi_pico_init, NULL, &dma_rpi_pico##inst##_data, \ + DEVICE_DT_INST_DEFINE(inst, &dma_rpi_pico_init, NULL, &dma_rpi_pico##inst##_data, \ &dma_rpi_pico##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ &dma_rpi_pico_driver_api); diff --git a/drivers/dma/dma_sam0.c b/drivers/dma/dma_sam0.c index d20d3bc1868ab..359162290c0b2 100644 --- a/drivers/dma/dma_sam0.c +++ b/drivers/dma/dma_sam0.c @@ -463,6 +463,6 @@ static DEVICE_API(dma, dma_sam0_api) = { .get_status = dma_sam0_get_status, }; -DEVICE_DT_INST_DEFINE(0, dma_sam0_init, NULL, +DEVICE_DT_INST_DEFINE(0, &dma_sam0_init, NULL, &dmac_data, NULL, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_sam0_api); diff --git a/drivers/dma/dma_sam_xdmac.c b/drivers/dma/dma_sam_xdmac.c index 436991a482af2..2deeeba817391 100644 --- a/drivers/dma/dma_sam_xdmac.c +++ b/drivers/dma/dma_sam_xdmac.c @@ -424,6 +424,6 @@ static const struct sam_xdmac_dev_cfg dma0_sam_config = { static struct sam_xdmac_dev_data dma0_sam_data; -DEVICE_DT_INST_DEFINE(0, sam_xdmac_initialize, NULL, +DEVICE_DT_INST_DEFINE(0, &sam_xdmac_initialize, NULL, &dma0_sam_data, &dma0_sam_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &sam_xdmac_driver_api); diff --git a/drivers/dma/dma_sedi.c b/drivers/dma/dma_sedi.c index ec21e57e47408..14ee67af850df 100644 --- a/drivers/dma/dma_sedi.c +++ b/drivers/dma/dma_sedi.c @@ -376,7 +376,7 @@ static int dma_sedi_init(const struct device *dev) .chn_num = DT_INST_PROP(inst, dma_channels), \ .irq_config = dma_sedi_##inst##_irq_config \ }; \ - DEVICE_DT_INST_DEFINE(inst, dma_sedi_init, \ + DEVICE_DT_INST_DEFINE(inst, &dma_sedi_init, \ NULL, &dma_sedi_dev_data_##inst, &dma_sedi_config_data_##inst, PRE_KERNEL_2, \ CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&dma_funcs); \ \ diff --git a/drivers/dma/dma_si32.c b/drivers/dma/dma_si32.c index 5ceca6a89ab51..4463a19fc056d 100644 --- a/drivers/dma/dma_si32.c +++ b/drivers/dma/dma_si32.c @@ -423,5 +423,5 @@ static DEVICE_API(dma, dma_si32_driver_api) = { .stop = dma_si32_stop, }; -DEVICE_DT_INST_DEFINE(0, dma_si32_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, +DEVICE_DT_INST_DEFINE(0, &dma_si32_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &dma_si32_driver_api); diff --git a/drivers/dma/dma_silabs_ldma.c b/drivers/dma/dma_silabs_ldma.c index b60442639611f..358b90b3f485f 100644 --- a/drivers/dma/dma_silabs_ldma.c +++ b/drivers/dma/dma_silabs_ldma.c @@ -611,7 +611,7 @@ int silabs_ldma_append_block(const struct device *dev, uint32_t channel, struct .dma_desc_pool = &desc_pool_##inst \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, dma_silabs_init, NULL, &dma_silabs_data_##inst, \ + DEVICE_DT_INST_DEFINE(inst, &dma_silabs_init, NULL, &dma_silabs_data_##inst, \ &dma_silabs_config_##inst, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &dma_funcs); diff --git a/drivers/dma/dma_silabs_siwx91x.c b/drivers/dma/dma_silabs_siwx91x.c index 7cd1290d336c0..5796f335600c9 100644 --- a/drivers/dma/dma_silabs_siwx91x.c +++ b/drivers/dma/dma_silabs_siwx91x.c @@ -420,11 +420,10 @@ static int siwx91x_dma_reload(const struct device *dev, uint32_t channel, uint32 const struct dma_siwx91x_config *cfg = dev->config; struct dma_siwx91x_data *data = dev->data; void *udma_handle = &data->udma_handle; - void *desc_src_addr; - void *desc_dst_addr; + uint32_t desc_src_addr; + uint32_t desc_dst_addr; uint32_t length; RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr; - uint8_t xfer_size = 1 << udma_table[channel].vsUDMAChaConfigData1.srcSize; /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= data->dma_ctx.dma_channels) { @@ -439,32 +438,31 @@ static int siwx91x_dma_reload(const struct device *dev, uint32_t channel, uint32 /* Update new channel info to dev->data structure */ data->chan_info[channel].SrcAddr = src; data->chan_info[channel].DestAddr = dst; - data->chan_info[channel].Size = size / xfer_size; + data->chan_info[channel].Size = size; /* Update new transfer size to dev->data structure */ - if (data->chan_info[channel].Size >= DMA_MAX_TRANSFER_COUNT) { - data->chan_info[channel].Cnt = DMA_MAX_TRANSFER_COUNT; + if (size >= DMA_MAX_TRANSFER_COUNT) { + data->chan_info[channel].Cnt = DMA_MAX_TRANSFER_COUNT - 1; } else { - data->chan_info[channel].Cnt = size / xfer_size; + data->chan_info[channel].Cnt = size; } /* Program the DMA descriptors with new transfer data information. */ if (udma_table[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) { length = data->chan_info[channel].Cnt << udma_table[channel].vsUDMAChaConfigData1.srcInc; - desc_src_addr = (void *)(src + length - 1); - udma_table[channel].pSrcEndAddr = desc_src_addr; + desc_src_addr = src + (length - 1); + udma_table[channel].pSrcEndAddr = (void *)desc_src_addr; } if (udma_table[channel].vsUDMAChaConfigData1.dstInc != UDMA_SRC_INC_NONE) { length = data->chan_info[channel].Cnt << udma_table[channel].vsUDMAChaConfigData1.dstInc; - desc_dst_addr = (void *)(dst + length - 1); - udma_table[channel].pDstEndAddr = desc_dst_addr; + desc_dst_addr = dst + (length - 1); + udma_table[channel].pDstEndAddr = (void *)desc_dst_addr; } - udma_table[channel].vsUDMAChaConfigData1.totalNumOfDMATrans = - data->chan_info[channel].Cnt - 1; + udma_table[channel].vsUDMAChaConfigData1.totalNumOfDMATrans = data->chan_info[channel].Cnt; udma_table[channel].vsUDMAChaConfigData1.transferType = UDMA_MODE_BASIC; return 0; @@ -701,7 +699,7 @@ static DEVICE_API(dma, siwx91x_dma_api) = { (siwx91x_dma_chan_desc##inst)), \ .irq_configure = siwx91x_dma_irq_configure_##inst, \ }; \ - DEVICE_DT_INST_DEFINE(inst, siwx91x_dma_init, NULL, &dma_data_##inst, &dma_cfg_##inst, \ + DEVICE_DT_INST_DEFINE(inst, &siwx91x_dma_init, NULL, &dma_data_##inst, &dma_cfg_##inst, \ POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &siwx91x_dma_api); DT_INST_FOREACH_STATUS_OKAY(SIWX91X_DMA_INIT) diff --git a/drivers/dma/dma_stm32.c b/drivers/dma/dma_stm32.c index 968e5b9d8d935..a50ba310a86d7 100644 --- a/drivers/dma/dma_stm32.c +++ b/drivers/dma/dma_stm32.c @@ -715,7 +715,7 @@ static struct dma_stm32_data dma_stm32_data_##index = { \ }; \ \ DEVICE_DT_INST_DEFINE(index, \ - dma_stm32_init, \ + &dma_stm32_init, \ NULL, \ &dma_stm32_data_##index, &dma_stm32_config_##index, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ diff --git a/drivers/dma/dma_stm32_bdma.c b/drivers/dma/dma_stm32_bdma.c index 1e22299600fb8..7825a5520210f 100644 --- a/drivers/dma/dma_stm32_bdma.c +++ b/drivers/dma/dma_stm32_bdma.c @@ -883,7 +883,7 @@ static struct bdma_stm32_data bdma_stm32_data_##index = { \ }; \ \ DEVICE_DT_INST_DEFINE(index, \ - bdma_stm32_init, \ + &bdma_stm32_init, \ NULL, \ &bdma_stm32_data_##index, &bdma_stm32_config_##index, \ PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ diff --git a/drivers/dma/dma_stm32u5.c b/drivers/dma/dma_stm32u5.c index 08ef460c68084..db9b9f102a929 100644 --- a/drivers/dma/dma_stm32u5.c +++ b/drivers/dma/dma_stm32u5.c @@ -823,7 +823,7 @@ static struct dma_stm32_data dma_stm32_data_##index = { \ }; \ \ DEVICE_DT_INST_DEFINE(index, \ - dma_stm32_init, \ + &dma_stm32_init, \ NULL, \ &dma_stm32_data_##index, &dma_stm32_config_##index, \ PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ diff --git a/drivers/dma/dma_ti_cc23x0.c b/drivers/dma/dma_ti_cc23x0.c index 30a06f94e0fa3..7ab852f931d4d 100644 --- a/drivers/dma/dma_ti_cc23x0.c +++ b/drivers/dma/dma_ti_cc23x0.c @@ -376,7 +376,7 @@ static DEVICE_API(dma, dma_cc23x0_api) = { .get_status = dma_cc23x0_get_status, }; -DEVICE_DT_INST_DEFINE(0, dma_cc23x0_init, NULL, +DEVICE_DT_INST_DEFINE(0, &dma_cc23x0_init, NULL, &cc23x0_data, NULL, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_cc23x0_api); diff --git a/drivers/dma/dma_wch.c b/drivers/dma/dma_wch.c index d799f4e823cd7..2174de1501528 100644 --- a/drivers/dma/dma_wch.c +++ b/drivers/dma/dma_wch.c @@ -492,7 +492,7 @@ LISTIFY(DMA_WCH_MAX_CHAN, GENERATE_ISR, ()) .channels = dma_wch##idx##_channels, \ }; \ \ - DEVICE_DT_INST_DEFINE(idx, dma_wch_init, NULL, &dma_wch##idx##_data, \ + DEVICE_DT_INST_DEFINE(idx, &dma_wch_init, NULL, &dma_wch##idx##_data, \ &dma_wch##idx##_config, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ &dma_wch_driver_api); diff --git a/drivers/dma/dma_xilinx_axi_dma.c b/drivers/dma/dma_xilinx_axi_dma.c index 2b08080e0c535..7503e64909d9b 100644 --- a/drivers/dma/dma_xilinx_axi_dma.c +++ b/drivers/dma/dma_xilinx_axi_dma.c @@ -1109,7 +1109,7 @@ static int dma_xilinx_axi_dma_init(const struct device *dev) .channels = dma_xilinx_axi_dma##inst##_channels, \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, dma_xilinx_axi_dma_init, NULL, \ + DEVICE_DT_INST_DEFINE(inst, &dma_xilinx_axi_dma_init, NULL, \ &dma_xilinx_axi_dma##inst##_data, \ &dma_xilinx_axi_dma##inst##_config, POST_KERNEL, \ CONFIG_DMA_INIT_PRIORITY, &dma_xilinx_axi_dma_driver_api); diff --git a/drivers/dma/dma_xmc4xxx.c b/drivers/dma/dma_xmc4xxx.c index 85e32ad14eb37..44217a46c3739 100644 --- a/drivers/dma/dma_xmc4xxx.c +++ b/drivers/dma/dma_xmc4xxx.c @@ -663,7 +663,7 @@ static DEVICE_API(dma, dma_xmc4xxx_driver_api) = { .channels = dma_xmc4xxx##inst##_channels, \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, dma_xmc4xxx_init, NULL, \ + DEVICE_DT_INST_DEFINE(inst, &dma_xmc4xxx_init, NULL, \ &dma_xmc4xxx##inst##_data, \ &dma_xmc4xxx##inst##_config, PRE_KERNEL_1, \ CONFIG_DMA_INIT_PRIORITY, &dma_xmc4xxx_driver_api); diff --git a/drivers/dma/dmamux_stm32.c b/drivers/dma/dmamux_stm32.c index 3a7d5d816afc3..f7a16caca7638 100644 --- a/drivers/dma/dmamux_stm32.c +++ b/drivers/dma/dmamux_stm32.c @@ -389,7 +389,7 @@ const struct dmamux_stm32_config dmamux_stm32_config_##index = { \ static struct dmamux_stm32_data dmamux_stm32_data_##index; \ \ DEVICE_DT_INST_DEFINE(index, \ - dmamux_stm32_init, \ + &dmamux_stm32_init, \ NULL, \ &dmamux_stm32_data_##index, &dmamux_stm32_config_##index,\ PRE_KERNEL_1, CONFIG_DMAMUX_STM32_INIT_PRIORITY, \ diff --git a/drivers/dp/swdp_ll_pin.h b/drivers/dp/swdp_ll_pin.h index 3da1cbead2bf7..48b4ea14cb3e1 100644 --- a/drivers/dp/swdp_ll_pin.h +++ b/drivers/dp/swdp_ll_pin.h @@ -8,11 +8,22 @@ #include #include +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) +#define CPU_CLOCK 64000000U +#else +#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#endif + +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) +#define FAST_BITBANG_HW_SUPPORT 1 +#else +#define FAST_BITBANG_HW_SUPPORT 0 +#endif + static ALWAYS_INLINE void pin_delay_asm(uint32_t delay) { #if defined(CONFIG_CPU_CORTEX_M) - __asm volatile (".syntax unified\n" - "movs r3, %[p]\n" + __asm volatile ("movs r3, %[p]\n" ".start_%=:\n" "subs r3, #1\n" "bne .start_%=\n" @@ -25,47 +36,50 @@ static ALWAYS_INLINE void pin_delay_asm(uint32_t delay) #endif } -#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) - -#include "swdp_ll_pin_nrf.h" - -#elif defined(CONFIG_SOC_FAMILY_STM32) - -#include "swdp_ll_pin_stm32.h" - -#else - -#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -#define FAST_BITBANG_HW_SUPPORT 0 - static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin) { +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) + NRF_GPIO_Type * reg = base; + + reg->PIN_CNF[pin] = 0b0000; +#endif } static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin) { +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) + NRF_GPIO_Type * reg = base; + + reg->PIN_CNF[pin] = 0b0001; +#endif } static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin) { +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) + NRF_GPIO_Type * reg = base; + + reg->OUTSET = BIT(pin); +#endif } static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin) { +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) + NRF_GPIO_Type * reg = base; + + reg->OUTCLR = BIT(pin); +#endif } static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin) { - return 0UL; -} - -#endif - -#ifndef CPU_CLOCK -#error "CPU_CLOCK not defined by any soc specific driver" -#endif +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) + NRF_GPIO_Type * reg = base; -#ifndef FAST_BITBANG_HW_SUPPORT -#error "FAST_BITBANG_HW_SUPPORT not defined by any soc specific driver" + return ((reg->IN >> pin) & 1); +#else + return 0UL; #endif +} diff --git a/drivers/dp/swdp_ll_pin_nrf.h b/drivers/dp/swdp_ll_pin_nrf.h deleted file mode 100644 index 12895a01ed9f5..0000000000000 --- a/drivers/dp/swdp_ll_pin_nrf.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define CPU_CLOCK 64000000U -#define FAST_BITBANG_HW_SUPPORT 1 - -static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin) -{ - NRF_GPIO_Type *reg = base; - - reg->PIN_CNF[pin] = 0b0000; -} - -static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin) -{ - NRF_GPIO_Type *reg = base; - - reg->PIN_CNF[pin] = 0b0001; -} - -static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin) -{ - NRF_GPIO_Type *reg = base; - - reg->OUTSET = BIT(pin); -} - -static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin) -{ - NRF_GPIO_Type *reg = base; - - reg->OUTCLR = BIT(pin); -} - -static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin) -{ - NRF_GPIO_Type *reg = base; - - return ((reg->IN >> pin) & 1); -} diff --git a/drivers/dp/swdp_ll_pin_stm32.h b/drivers/dp/swdp_ll_pin_stm32.h deleted file mode 100644 index 5b5cd3149d509..0000000000000 --- a/drivers/dp/swdp_ll_pin_stm32.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "stm32_hsem.h" - -#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -#define FAST_BITBANG_HW_SUPPORT 1 - -static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin) -{ - GPIO_TypeDef *gpio = base; - - z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - - LL_GPIO_SetPinMode(gpio, BIT(pin), LL_GPIO_MODE_INPUT); - - z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); -} - -static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin) -{ - GPIO_TypeDef *gpio = base; - - z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - - LL_GPIO_SetPinMode(gpio, BIT(pin), LL_GPIO_MODE_OUTPUT); - - z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); -} - -static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin) -{ - GPIO_TypeDef *gpio = base; - uint32_t val; - - z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - - val = LL_GPIO_ReadOutputPort(gpio); - val |= BIT(pin); - LL_GPIO_WriteOutputPort(gpio, val); - - z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); -} - -static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin) -{ - GPIO_TypeDef *gpio = base; - uint32_t val; - - z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - - val = LL_GPIO_ReadOutputPort(gpio); - val &= ~BIT(pin); - LL_GPIO_WriteOutputPort(gpio, val); - - z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); -} - -static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin) -{ - GPIO_TypeDef *gpio = base; - - return (LL_GPIO_ReadInputPort(gpio) >> pin) & 1; -} diff --git a/drivers/eeprom/eeprom_tmp11x.c b/drivers/eeprom/eeprom_tmp11x.c index f22aa51920a59..1966683ee6dcc 100644 --- a/drivers/eeprom/eeprom_tmp11x.c +++ b/drivers/eeprom/eeprom_tmp11x.c @@ -16,6 +16,11 @@ struct eeprom_tmp11x_config { const struct device *parent; }; +BUILD_ASSERT(CONFIG_EEPROM_INIT_PRIORITY > + CONFIG_SENSOR_INIT_PRIORITY, + "TMP11X eeprom driver must be initialized after TMP11X sensor " + "driver"); + static size_t eeprom_tmp11x_size(const struct device *dev) { return EEPROM_TMP11X_SIZE; diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index eaf858add89b1..c59eba033b019 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -4,6 +4,20 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/entropy.h) zephyr_library() +zephyr_library_sources_ifdef(CONFIG_ENTROPY_TELINK_B91_TRNG entropy_b91_trng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_CC13XX_CC26XX_RNG entropy_cc13xx_cc26xx.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_ESP32_RNG entropy_esp32.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNG entropy_mcux_rng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNGA entropy_mcux_rnga.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_TRNG entropy_mcux_trng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_CAAM entropy_mcux_caam.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NXP_ELE_TRNG entropy_nxp_ele.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF5_RNG entropy_nrf5.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF_CRACEN_CTR_DRBG entropy_nrf_cracen.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_SAM_RNG entropy_sam.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_SMARTBOND_TRNG entropy_smartbond.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_STM32_RNG entropy_stm32.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_LITEX_RNG entropy_litex.c) if(CONFIG_FAKE_ENTROPY_NATIVE_SIM) zephyr_library_sources(fake_entropy_native_sim.c) if(CONFIG_NATIVE_LIBRARY) @@ -13,36 +27,18 @@ if(CONFIG_FAKE_ENTROPY_NATIVE_SIM) endif() endif() -zephyr_library_sources_ifdef(CONFIG_USERSPACE entropy_handlers.c) - -# zephyr-keep-sorted-start -zephyr_library_sources_ifdef(CONFIG_ENTROPY_BRCM_IPROC_RNG200 entropy_iproc_rng200.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_CC13XX_CC26XX_RNG entropy_cc13xx_cc26xx.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_ESP32_RNG entropy_esp32.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_TRNG entropy_gecko_trng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_LITEX_RNG entropy_litex.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAX32_TRNG entropy_max32.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAXQ10XX_RNG entropy_maxq10xx.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_CAAM entropy_mcux_caam.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNG entropy_mcux_rng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNGA entropy_mcux_rnga.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_TRNG entropy_mcux_trng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG entropy_neorv32_trng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF5_RNG entropy_nrf5.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF_CRACEN_CTR_DRBG entropy_nrf_cracen.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_NXP_ELE_TRNG entropy_nxp_ele.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_RENESAS_RA entropy_renesas_ra.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_RV32M1_TRNG entropy_rv32m1_trng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_SAM_RNG entropy_sam.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_SILABS_SIWX91X entropy_silabs_siwx91x.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_SMARTBOND_TRNG entropy_smartbond.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_STM32_RNG entropy_stm32.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_SY1XX_TRNG entropy_sy1xx_trng.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_TELINK_B91_TRNG entropy_b91_trng.c) -# zephyr-keep-sorted-stop +zephyr_library_sources_ifdef(CONFIG_USERSPACE entropy_handlers.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_RV32M1_TRNG entropy_rv32m1_trng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_TRNG entropy_gecko_trng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG entropy_neorv32_trng.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_SILABS_SIWX91X entropy_silabs_siwx91x.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAX32_TRNG entropy_max32.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAXQ10XX_RNG entropy_maxq10xx.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_RENESAS_RA entropy_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_SY1XX_TRNG entropy_sy1xx_trng.c) zephyr_library_link_libraries_ifdef(CONFIG_BUILD_WITH_TFM tfm_api) diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig index e0a2080b343be..3664ce0f18416 100644 --- a/drivers/entropy/Kconfig +++ b/drivers/entropy/Kconfig @@ -20,32 +20,29 @@ config ENTROPY_INIT_PRIORITY help Entropy driver device initialization priority. -# zephyr-keep-sorted-start source "drivers/entropy/Kconfig.b91" -source "drivers/entropy/Kconfig.bt_hci" source "drivers/entropy/Kconfig.cc13xx_cc26xx" -source "drivers/entropy/Kconfig.esp32" -source "drivers/entropy/Kconfig.gecko" -source "drivers/entropy/Kconfig.iproc" -source "drivers/entropy/Kconfig.litex" -source "drivers/entropy/Kconfig.max32" -source "drivers/entropy/Kconfig.maxq10xx" source "drivers/entropy/Kconfig.mcux" -source "drivers/entropy/Kconfig.native_sim" -source "drivers/entropy/Kconfig.neorv32" -source "drivers/entropy/Kconfig.npcx" +source "drivers/entropy/Kconfig.nxp" +source "drivers/entropy/Kconfig.stm32" +source "drivers/entropy/Kconfig.esp32" source "drivers/entropy/Kconfig.nrf5" source "drivers/entropy/Kconfig.nrf_cracen" -source "drivers/entropy/Kconfig.nxp" -source "drivers/entropy/Kconfig.psa_crypto" -source "drivers/entropy/Kconfig.renesas_ra" -source "drivers/entropy/Kconfig.rv32m1" source "drivers/entropy/Kconfig.sam" -source "drivers/entropy/Kconfig.siwx91x" source "drivers/entropy/Kconfig.smartbond" -source "drivers/entropy/Kconfig.stm32" +source "drivers/entropy/Kconfig.native_sim" +source "drivers/entropy/Kconfig.rv32m1" +source "drivers/entropy/Kconfig.litex" +source "drivers/entropy/Kconfig.gecko" +source "drivers/entropy/Kconfig.siwx91x" +source "drivers/entropy/Kconfig.neorv32" +source "drivers/entropy/Kconfig.bt_hci" +source "drivers/entropy/Kconfig.psa_crypto" +source "drivers/entropy/Kconfig.npcx" +source "drivers/entropy/Kconfig.max32" +source "drivers/entropy/Kconfig.maxq10xx" +source "drivers/entropy/Kconfig.renesas_ra" source "drivers/entropy/Kconfig.sy1xx" -# zephyr-keep-sorted-stop config ENTROPY_HAS_DRIVER bool diff --git a/drivers/entropy/Kconfig.iproc b/drivers/entropy/Kconfig.iproc deleted file mode 100644 index 83233f8309d10..0000000000000 --- a/drivers/entropy/Kconfig.iproc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config ENTROPY_BRCM_IPROC_RNG200 - bool "Broadcom iProc RNG200 driver" - default y - depends on DT_HAS_BRCM_IPROC_RNG200_ENABLED - select ENTROPY_HAS_DRIVER - help - Enable the Broadcom iProc RNG200 random number generator diff --git a/drivers/entropy/Kconfig.native_sim b/drivers/entropy/Kconfig.native_sim index 87c26dd852cff..adcf3f407cd02 100644 --- a/drivers/entropy/Kconfig.native_sim +++ b/drivers/entropy/Kconfig.native_sim @@ -1,4 +1,3 @@ -# Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 config FAKE_ENTROPY_NATIVE_SIM diff --git a/drivers/entropy/entropy_iproc_rng200.c b/drivers/entropy/entropy_iproc_rng200.c deleted file mode 100644 index a15249655a1b2..0000000000000 --- a/drivers/entropy/entropy_iproc_rng200.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2025 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT brcm_iproc_rng200 - -#include -LOG_MODULE_REGISTER(iproc_rng200_entropy, CONFIG_ENTROPY_LOG_LEVEL); - -#include -#include -#include -#include -#include - -#define IPROC_RNG200_CTRL_OFFS 0x00 -#define IPROC_RNG200_RNG_RESET_OFFS 0x04 -#define IPROC_RNG200_RBG_RESET_OFFS 0x08 -#define IPROC_RNG200_RESERVED1_OFFS 0x0c -#define IPROC_RNG200_RESERVED2_OFFS 0x10 -#define IPROC_RNG200_RESERVED3_OFFS 0x14 -#define IPROC_RNG200_INT_STATUS_OFFS 0x18 -#define IPROC_RNG200_RESERVED4_OFFS 0x1c -#define IPROC_RNG200_FIFO_DATA_OFFS 0x20 -#define IPROC_RNG200_FIFO_COUNT_OFFS 0x24 - -#define IPROC_RNG200_CTRL_RBG_EN BIT(0) -#define IPROC_RNG200_RESET_EN BIT(0) -#define IPROC_RNG200_INT_STATUS_NIST_FAIL BIT(5) -#define IPROC_RNG200_INT_STATUS_MASTER_FAIL_LOCKOUT BIT(31) - -#define IPROC_RNG200_CTRL_RBG_EN_MASK BIT_MASK(13) -#define IPROC_RNG200_FIFO_COUNT_MASK BIT_MASK(8) - -/* time needed to fill fifo when empty */ -#define IPROC_RNG200_FIFO_REFILL_TIME_USEC 40 -#define IPROC_RNG200_FIFO_REFILL_MAX_RETRIES 5 - -#define DEV_CFG(dev) ((const struct iproc_rng200_config *)(dev)->config) -#define DEV_DATA(dev) ((struct iproc_rng200_data *)(dev)->data) - -struct iproc_rng200_config { - DEVICE_MMIO_NAMED_ROM(base_addr); -}; - -struct iproc_rng200_data { - DEVICE_MMIO_NAMED_RAM(base_addr); - struct k_mutex mutex; -}; - -static int iproc_rng200_driver_init(const struct device *dev) -{ - struct iproc_rng200_data *const data = dev->data; - - k_mutex_init(&data->mutex); - - DEVICE_MMIO_NAMED_MAP(dev, base_addr, K_MEM_CACHE_NONE); - - const mem_addr_t base = DEVICE_MMIO_NAMED_GET(dev, base_addr); - const uint32_t val = - sys_read32(base + IPROC_RNG200_CTRL_OFFS) & IPROC_RNG200_CTRL_RBG_EN_MASK; - - sys_write32(val & ~IPROC_RNG200_CTRL_RBG_EN, base + IPROC_RNG200_CTRL_OFFS); - - return 0; -} - -static int iproc_rng200_driver_get_entropy(const struct device *dev, uint8_t *buffer, - uint16_t length) -{ - const mem_addr_t base = DEVICE_MMIO_NAMED_GET(dev, base_addr); - const uint32_t word_count = DIV_ROUND_UP(length, 4); - struct iproc_rng200_data *const data = dev->data; - uint32_t retries_left; - uint32_t random_word; - - for (uint32_t i = 0; i < word_count; i++) { - retries_left = IPROC_RNG200_FIFO_REFILL_MAX_RETRIES; - k_mutex_lock(&data->mutex, K_FOREVER); - - while (true) { - const uint32_t status = sys_read32(base + IPROC_RNG200_INT_STATUS_OFFS); - uint32_t val; - - if (status & (IPROC_RNG200_INT_STATUS_MASTER_FAIL_LOCKOUT | - IPROC_RNG200_INT_STATUS_NIST_FAIL)) { - - sys_write32(0xFFFFFFFF, base + IPROC_RNG200_INT_STATUS_OFFS); - - val = sys_read32(base + IPROC_RNG200_RNG_RESET_OFFS); - sys_write32(val | IPROC_RNG200_RESET_EN, - base + IPROC_RNG200_RNG_RESET_OFFS); - - val = sys_read32(base + IPROC_RNG200_RBG_RESET_OFFS); - sys_write32(val | IPROC_RNG200_RESET_EN, - base + IPROC_RNG200_RBG_RESET_OFFS); - - val = sys_read32(base + IPROC_RNG200_RNG_RESET_OFFS); - sys_write32(val & ~IPROC_RNG200_RESET_EN, - base + IPROC_RNG200_RNG_RESET_OFFS); - - val = sys_read32(base + IPROC_RNG200_RBG_RESET_OFFS); - sys_write32(val & ~IPROC_RNG200_RESET_EN, - base + IPROC_RNG200_RBG_RESET_OFFS); - } - - /* make sure fifo has at least one random word */ - const uint32_t fcnt = sys_read32(base + IPROC_RNG200_FIFO_COUNT_OFFS); - - if ((fcnt & IPROC_RNG200_FIFO_COUNT_MASK) > 0) { - /* get new random word */ - random_word = sys_read32(base + IPROC_RNG200_FIFO_DATA_OFFS); - break; - } - - /* currently no random values available, thus wait */ - retries_left--; - if (!retries_left) { - /* number of retries exhausted, give up */ - k_mutex_unlock(&data->mutex); - return -ETIMEDOUT; - } - - k_sleep(K_USEC(IPROC_RNG200_FIFO_REFILL_TIME_USEC)); - } - - k_mutex_unlock(&data->mutex); - - memcpy(&buffer[i * 4], &random_word, MIN(length, 4)); - length -= 4; - } - - return 0; -} - -static DEVICE_API(entropy, iproc_rng200_entropy_api) = { - .get_entropy = iproc_rng200_driver_get_entropy, -}; - -#define IPROC_RNG200_INIT(n) \ - static const struct iproc_rng200_config iproc_rng200_##n##_cfg = { \ - DEVICE_MMIO_NAMED_ROM_INIT(base_addr, DT_DRV_INST(n)), \ - }; \ - static struct iproc_rng200_data iproc_rng200_##n##_data; \ - \ - DEVICE_DT_INST_DEFINE(n, iproc_rng200_driver_init, NULL, &iproc_rng200_##n##_data, \ - &iproc_rng200_##n##_cfg, PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY, \ - &iproc_rng200_entropy_api); - -DT_INST_FOREACH_STATUS_OKAY(IPROC_RNG200_INIT) diff --git a/drivers/entropy/entropy_stm32.c b/drivers/entropy/entropy_stm32.c index a4e8cf40f03c1..4aa0cf1d9e5d7 100644 --- a/drivers/entropy/entropy_stm32.c +++ b/drivers/entropy/entropy_stm32.c @@ -6,7 +6,6 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include #include #include #include @@ -339,7 +338,7 @@ static int recover_seed_error(RNG_TypeDef *rng) } #endif /* !STM32_CONDRST_SUPPORT */ -static int random_sample_get(rng_sample_t *rnd_sample) +static int random_byte_get(void) { int retval = -EAGAIN; unsigned int key; @@ -369,8 +368,8 @@ static int random_sample_get(rng_sample_t *rnd_sample) goto out; } - *rnd_sample = ll_rng_read_rand_data(rng); - if (*rnd_sample == 0) { + retval = ll_rng_read_rand_data(rng); + if (retval == 0) { /* A seed error could have occurred between RNG_SR * polling and RND_DR output reading. */ @@ -378,7 +377,7 @@ static int random_sample_get(rng_sample_t *rnd_sample) goto out; } - retval = 0; + retval &= 0xFF; } out: @@ -391,8 +390,6 @@ static int random_sample_get(rng_sample_t *rnd_sample) static uint16_t generate_from_isr(uint8_t *buf, uint16_t len) { uint16_t remaining_len = len; - rng_sample_t rnd_sample; - int ret; #if !IRQLESS_TRNG __ASSERT_NO_MSG(!irq_is_enabled(IRQN)); @@ -406,7 +403,7 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len) if (ll_rng_is_active_secs(entropy_stm32_rng_data.rng) || ll_rng_is_active_seis(entropy_stm32_rng_data.rng)) { - (void)random_sample_get(&rnd_sample); /* this will recover the error */ + (void)random_byte_get(); /* this will recover the error */ return 0; /* return cnt is null : no random data available */ } @@ -421,6 +418,8 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len) #endif /* !IRQLESS_TRNG */ do { + int byte; + while (ll_rng_is_active_drdy( entropy_stm32_rng_data.rng) != 1) { #if !IRQLESS_TRNG @@ -442,23 +441,16 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len) #endif /* !IRQLESS_TRNG */ } - ret = random_sample_get(&rnd_sample); + byte = random_byte_get(); #if !IRQLESS_TRNG NVIC_ClearPendingIRQ(IRQN); #endif /* IRQLESS_TRNG */ - if (ret < 0) { + if (byte < 0) { continue; } - /* push each byte of the RNG sample in buffer */ - size_t i = sizeof(rnd_sample); - - while (remaining_len && i) { - buf[--remaining_len] = (uint8_t)(rnd_sample & 0xFFu); - rnd_sample >>= 8; - i--; - } + buf[--remaining_len] = byte; } while (remaining_len); return len; @@ -612,47 +604,31 @@ static void rng_pool_init(struct rng_pool *rngp, uint16_t size, static int perform_pool_refill(void) { - rng_sample_t rnd_sample; - bool refilled_thr = false; - int ret; + int byte, ret; - ret = random_sample_get(&rnd_sample); - if (ret < 0) { - return ret; + byte = random_byte_get(); + if (byte < 0) { + return -EIO; } - /* push each byte of the RNG sample in pools */ - for (size_t i = 0; i < sizeof(rnd_sample); i++, rnd_sample >>= 8) { - uint8_t byte = rnd_sample & 0xFFu; - - ret = rng_pool_put((struct rng_pool *)(entropy_stm32_rng_data.isr), byte); + ret = rng_pool_put((struct rng_pool *)(entropy_stm32_rng_data.isr), + byte); + if (ret < 0) { + ret = rng_pool_put( + (struct rng_pool *)(entropy_stm32_rng_data.thr), + byte); if (ret < 0) { - /* Take note that data has been added to thread pool */ - refilled_thr = true; - - ret = rng_pool_put((struct rng_pool *)(entropy_stm32_rng_data.thr), byte); - if (ret < 0) { #if !IRQLESS_TRNG - irq_disable(IRQN); + irq_disable(IRQN); #endif /* !IRQLESS_TRNG */ - release_rng(); - pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, - PM_ALL_SUBSTATES); - if (IS_ENABLED(CONFIG_PM_S2RAM)) { - pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, - PM_ALL_SUBSTATES); - } - entropy_stm32_rng_data.filling_pools = false; - break; + release_rng(); + pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); + if (IS_ENABLED(CONFIG_PM_S2RAM)) { + pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES); } + entropy_stm32_rng_data.filling_pools = false; } - } - if (refilled_thr) { - /** - * Wake up threads that may be waiting for new data to be - * available in thread pool if we added entropy in it. - */ k_sem_give(&entropy_stm32_rng_data.sem_sync); } @@ -669,8 +645,7 @@ static void trng_poll_work_item(struct k_work *work) if (ll_rng_is_active_secs(entropy_stm32_rng_data.rng) || ll_rng_is_active_seis(entropy_stm32_rng_data.rng)) { - rng_sample_t dummy; - (void)random_sample_get(&dummy); /* this will recover the error */ + (void)random_byte_get(); /* this will recover the error */ } else if (ll_rng_is_active_drdy(rng)) { /* Entropy available: read it and fill pools */ int res = perform_pool_refill(); diff --git a/drivers/entropy/entropy_stm32.h b/drivers/entropy/entropy_stm32.h index 420841c20203c..533cc03149325 100644 --- a/drivers/entropy/entropy_stm32.h +++ b/drivers/entropy/entropy_stm32.h @@ -88,18 +88,10 @@ static inline uint32_t ll_rng_is_active_drdy(RNG_TypeDef *RNGx) #endif /* CONFIG_SOC_SERIES_STM32WB0X */ } -#if defined(CONFIG_SOC_SERIES_STM32WB0X) && !defined(CONFIG_SOC_STM32WB09XX) -/* STM32WB05, STM32WB06 and STM32WB07 have 16-bit data register */ -typedef uint16_t rng_sample_t; -#else -/* All other TRNG IPs have 32-bit data register */ -typedef uint32_t rng_sample_t; -#endif - -static inline rng_sample_t ll_rng_read_rand_data(RNG_TypeDef *RNGx) +static inline uint16_t ll_rng_read_rand_data(RNG_TypeDef *RNGx) { #if defined(CONFIG_SOC_STM32WB09XX) - rng_sample_t rnd = LL_RNG_GetRndVal(RNGx); + uint16_t rnd = (uint16_t)LL_RNG_GetRndVal(RNGx); /** * STM32WB09 TRNG does not clear IRQ flags in hardware. @@ -116,6 +108,6 @@ static inline rng_sample_t ll_rng_read_rand_data(RNG_TypeDef *RNGx) /* STM32WB05 / STM32WB06 / STM32WB07 */ return LL_RNG_ReadRandData16(RNGx); #else - return LL_RNG_ReadRandData32(RNGx); + return (uint16_t)LL_RNG_ReadRandData32(RNGx); #endif /* CONFIG_SOC_SERIES_STM32WB0X */ } diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c index 6ade9b60d83d2..b42b270a2e8fb 100644 --- a/drivers/espi/espi_npcx.c +++ b/drivers/espi/espi_npcx.c @@ -997,12 +997,11 @@ static int espi_npcx_send_oob(const struct device *dev, /* Write GET_OOB data into 32-bits tx buffer in little endian */ for (idx_tx_buf = 0; idx_tx_buf < sz_oob_tx/4; idx_tx_buf++, - oob_buf += 4) { + oob_buf += 4) inst->OOBTXBUF[idx_tx_buf + 1] = oob_buf[0] | (oob_buf[1] << 8) | (oob_buf[2] << 16) | (oob_buf[3] << 24); - } /* Write remaining bytes of package */ if (sz_oob_tx % 4) { diff --git a/drivers/ethernet/eth_enc28j60.c b/drivers/ethernet/eth_enc28j60.c index e19e4201b67df..0268661784f7c 100644 --- a/drivers/ethernet/eth_enc28j60.c +++ b/drivers/ethernet/eth_enc28j60.c @@ -757,39 +757,6 @@ static enum ethernet_hw_caps eth_enc28j60_get_capabilities(const struct device * ; } -static int eth_enc28j60_set_config(const struct device *dev, - enum ethernet_config_type type, - const struct ethernet_config *config) -{ - struct eth_enc28j60_runtime *context = dev->data; - - /* Compile time check that the memcpy below won't overflow */ - BUILD_ASSERT(sizeof(context->mac_address) <= sizeof(config->mac_address.addr), - "ENC28j60 Runtime MAC address buffer too small"); - - if (type == ETHERNET_CONFIG_TYPE_MAC_ADDRESS) { - memcpy(context->mac_address, config->mac_address.addr, - sizeof(config->mac_address.addr)); - eth_enc28j60_init_mac(dev); - - if (context->iface != NULL) { - net_if_set_link_addr(context->iface, context->mac_address, - sizeof(context->mac_address), - NET_LINK_ETHERNET); - } - - LOG_INF("Set cfg - MAC %02x:%02x:%02x:%02x:%02x:%02x", - context->mac_address[0], context->mac_address[1], - context->mac_address[2], context->mac_address[3], - context->mac_address[4], context->mac_address[5]); - - return 0; - } - - /* Only mac address config supported */ - return -ENOTSUP; -} - static void eth_enc28j60_iface_init(struct net_if *iface) { const struct device *dev = net_if_get_device(iface); @@ -816,7 +783,7 @@ static void eth_enc28j60_iface_init(struct net_if *iface) static const struct ethernet_api api_funcs = { .iface_api.init = eth_enc28j60_iface_init, - .set_config = eth_enc28j60_set_config, + .get_capabilities = eth_enc28j60_get_capabilities, .send = eth_enc28j60_tx, }; diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c index 166064db2d53d..4cd3d5b13d724 100644 --- a/drivers/ethernet/eth_esp32.c +++ b/drivers/ethernet/eth_esp32.c @@ -282,10 +282,9 @@ int eth_esp32_initialize(const struct device *dev) if (strcmp(phy_connection_type, "rmii") == 0) { emac_hal_iomux_init_rmii(); #if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios) - BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 0 || - DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 || + BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 || DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17, - "Only GPIO0/16/17 are allowed as a GPIO REF_CLK source!"); + "Only GPIO16/17 are allowed as a GPIO REF_CLK source!"); int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios); emac_hal_iomux_rmii_clk_output(ref_clk_gpio); emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs); diff --git a/drivers/ethernet/eth_litex_liteeth.c b/drivers/ethernet/eth_litex_liteeth.c index 97cb73599d560..2eb8cbef2552f 100644 --- a/drivers/ethernet/eth_litex_liteeth.c +++ b/drivers/ethernet/eth_litex_liteeth.c @@ -139,7 +139,7 @@ static void eth_rx(const struct device *port) pkt = net_pkt_rx_alloc_with_buffer(context->iface, len, AF_UNSPEC, 0, K_NO_WAIT); if (pkt == NULL) { - LOG_ERR("Failed to obtain RX buffer of length %u", len); + LOG_ERR("Failed to obtain RX buffer"); return; } diff --git a/drivers/ethernet/eth_native_tap.c b/drivers/ethernet/eth_native_tap.c index 8507e58c14a41..8e8f696e14e34 100644 --- a/drivers/ethernet/eth_native_tap.c +++ b/drivers/ethernet/eth_native_tap.c @@ -108,7 +108,7 @@ static struct gptp_hdr *check_gptp_msg(struct net_if *iface, bool is_tx) { uint8_t *msg_start = net_pkt_data(pkt); - struct gptp_hdr *ghdr; + struct gptp_hdr *gptp_hdr; int eth_hlen; struct net_eth_hdr *hdr; @@ -129,12 +129,12 @@ static struct gptp_hdr *check_gptp_msg(struct net_if *iface, return false; } - ghdr = (struct gptp_hdr *)pkt->frags->frags->data; + gptp_hdr = (struct gptp_hdr *)pkt->frags->frags->data; } else { - ghdr = (struct gptp_hdr *)(pkt->frags->data + eth_hlen); + gptp_hdr = (struct gptp_hdr *)(pkt->frags->data + eth_hlen); } - return ghdr; + return gptp_hdr; } static void update_pkt_priority(struct gptp_hdr *hdr, struct net_pkt *pkt) @@ -307,7 +307,7 @@ static void create_rx_handler(struct eth_context *ctx) static void eth_iface_init(struct net_if *iface) { struct eth_context *ctx = net_if_get_device(iface)->data; - struct net_linkaddr *ll_addr; + struct net_linkaddr *ll_addr = eth_get_mac(ctx); #if !defined(CONFIG_ETH_NATIVE_TAP_RANDOM_MAC) const char *mac_addr = mac_addr_cmd_opt ? mac_addr_cmd_opt : CONFIG_ETH_NATIVE_TAP_MAC_ADDR; @@ -355,8 +355,6 @@ static void eth_iface_init(struct net_if *iface) } #endif - ll_addr = eth_get_mac(ctx); - /* If we have only one network interface, then use the name * defined in the Kconfig directly. This way there is no need to * change the documentation etc. and break things. diff --git a/drivers/ethernet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c index 005279938868a..501a50c9f7c7f 100644 --- a/drivers/ethernet/eth_nxp_enet.c +++ b/drivers/ethernet/eth_nxp_enet.c @@ -106,7 +106,8 @@ struct nxp_enet_mac_data { struct k_mutex tx_frame_buf_mutex; struct k_mutex rx_frame_buf_mutex; #ifdef CONFIG_PTP_CLOCK_NXP_ENET - struct nxp_enet_ptp_data ptp; + struct k_sem ptp_ts_sem; + struct k_mutex *ptp_mutex; /* created in PTP driver */ #endif uint8_t *tx_frame_buf; uint8_t *rx_frame_buf; @@ -164,16 +165,15 @@ static inline void ts_register_tx_event(const struct device *dev, if (pkt && atomic_get(&pkt->atomic_ref) > 0) { if (eth_get_ptp_data(net_pkt_iface(pkt), pkt) && frameinfo->isTsAvail) { - /* Timestamp is written to packet in ISR. - * Semaphore ensures sequential execution of writing - * the timestamp here and subsequently reading the timestamp - * after waiting for the semaphore in eth_wait_for_ptp_ts(). - */ + k_mutex_lock(data->ptp_mutex, K_FOREVER); + pkt->timestamp.nanosecond = frameinfo->timeStamp.nanosecond; pkt->timestamp.second = frameinfo->timeStamp.second; net_if_add_tx_timestamp(pkt); - k_sem_give(&data->ptp.ptp_ts_sem); + k_sem_give(&data->ptp_ts_sem); + + k_mutex_unlock(data->ptp_mutex); } net_pkt_unref(pkt); } @@ -184,7 +184,7 @@ static inline void eth_wait_for_ptp_ts(const struct device *dev, struct net_pkt struct nxp_enet_mac_data *data = dev->data; net_pkt_ref(pkt); - k_sem_take(&data->ptp.ptp_ts_sem, K_FOREVER); + k_sem_take(&data->ptp_ts_sem, K_FOREVER); } #else #define eth_get_ptp_data(...) false @@ -389,7 +389,7 @@ static int eth_nxp_enet_rx(const struct device *dev) } #if defined(CONFIG_PTP_CLOCK_NXP_ENET) - k_mutex_lock(data->ptp.ptp_mutex, K_FOREVER); + k_mutex_lock(data->ptp_mutex, K_FOREVER); /* Invalid value by default. */ pkt->timestamp.nanosecond = UINT32_MAX; @@ -411,7 +411,7 @@ static int eth_nxp_enet_rx(const struct device *dev) pkt->timestamp.nanosecond = ts; pkt->timestamp.second = ptp_time.second; } - k_mutex_unlock(data->ptp.ptp_mutex); + k_mutex_unlock(data->ptp_mutex); #endif /* CONFIG_PTP_CLOCK_NXP_ENET */ iface = get_iface(data); @@ -627,9 +627,6 @@ static void eth_nxp_enet_isr(const struct device *dev) nxp_enet_driver_cb(config->mdio, NXP_ENET_MDIO, NXP_ENET_INTERRUPT, NULL); } -#ifdef CONFIG_PTP_CLOCK_NXP_ENET - ENET_TimeStampIRQHandler(data->base, &data->enet_handle); -#endif irq_unlock(irq_lock_key); } @@ -712,7 +709,7 @@ static int eth_nxp_enet_init(const struct device *dev) k_sem_init(&data->tx_buf_sem, CONFIG_ETH_NXP_ENET_TX_BUFFERS, CONFIG_ETH_NXP_ENET_TX_BUFFERS); #if defined(CONFIG_PTP_CLOCK_NXP_ENET) - k_sem_init(&data->ptp.ptp_ts_sem, 0, 1); + k_sem_init(&data->ptp_ts_sem, 0, 1); #endif k_work_init(&data->rx_work, eth_nxp_enet_rx_thread); @@ -784,9 +781,8 @@ static int eth_nxp_enet_init(const struct device *dev) nxp_enet_driver_cb(config->mdio, NXP_ENET_MDIO, NXP_ENET_MODULE_RESET, NULL); #if defined(CONFIG_PTP_CLOCK_NXP_ENET) - data->ptp.enet = &data->enet_handle; nxp_enet_driver_cb(config->ptp_clock, NXP_ENET_PTP_CLOCK, - NXP_ENET_MODULE_RESET, &data->ptp); + NXP_ENET_MODULE_RESET, &data->ptp_mutex); ENET_SetTxReclaim(&data->enet_handle, true, 0); #endif diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c index 69cb88f921fed..dafa4e9dab6a1 100644 --- a/drivers/ethernet/eth_stm32_hal.c +++ b/drivers/ethernet/eth_stm32_hal.c @@ -88,15 +88,17 @@ static const struct device *eth_stm32_phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, #define ETH_RMII_MODE ETH_MEDIA_INTERFACE_RMII #endif +#define MAC_NODE DT_NODELABEL(mac) + #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet) -#define STM32_ETH_PHY_MODE(inst) \ - ((DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, rgmii) ? ETH_RGMII_MODE : \ - (DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, gmii) ? ETH_GMII_MODE : \ - (DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? ETH_MII_MODE : \ +#define STM32_ETH_PHY_MODE(node_id) \ + ((DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rgmii) ? ETH_RGMII_MODE : \ + (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, gmii) ? ETH_GMII_MODE : \ + (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? ETH_MII_MODE : \ ETH_RMII_MODE)))) #else -#define STM32_ETH_PHY_MODE(inst) \ - (DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? \ +#define STM32_ETH_PHY_MODE(node_id) \ + (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? \ ETH_MII_MODE : ETH_RMII_MODE) #endif @@ -258,21 +260,23 @@ static inline void setup_mac_filter(ETH_HandleTypeDef *heth) { __ASSERT_NO_MSG(heth != NULL); -#if defined(CONFIG_ETH_STM32_HAL_API_V2) +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) ETH_MACFilterConfigTypeDef MACFilterConf; HAL_ETH_GetMACFilterConfig(heth, &MACFilterConf); - - MACFilterConf.HashMulticast = - IS_ENABLED(CONFIG_ETH_STM32_MULTICAST_FILTER) ? ENABLE : DISABLE; - MACFilterConf.PassAllMulticast = - IS_ENABLED(CONFIG_ETH_STM32_MULTICAST_FILTER) ? DISABLE : ENABLE; +#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) + MACFilterConf.HashMulticast = ENABLE; + MACFilterConf.PassAllMulticast = DISABLE; +#else + MACFilterConf.HashMulticast = DISABLE; + MACFilterConf.PassAllMulticast = ENABLE; +#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ MACFilterConf.HachOrPerfectFilter = DISABLE; HAL_ETH_SetMACFilterConfig(heth, &MACFilterConf); k_sleep(K_MSEC(1)); -#else /* CONFIG_ETH_STM32_HAL_API_V2 */ +#else uint32_t tmp = heth->Instance->MACFFR; /* clear all multicast filter bits, resulting in perfect filtering */ @@ -297,7 +301,7 @@ static inline void setup_mac_filter(ETH_HandleTypeDef *heth) tmp = heth->Instance->MACFFR; k_sleep(K_MSEC(1)); heth->Instance->MACFFR = tmp; -#endif /* CONFIG_ETH_STM32_HAL_API_V2 */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */ } #if defined(CONFIG_PTP_CLOCK_STM32_HAL) @@ -326,7 +330,7 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) static int eth_tx(const struct device *dev, struct net_pkt *pkt) { struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + ETH_HandleTypeDef *heth; int res; size_t total_len; #if defined(CONFIG_ETH_STM32_HAL_API_V2) @@ -344,6 +348,10 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) __ASSERT_NO_MSG(pkt != NULL); __ASSERT_NO_MSG(pkt->frags != NULL); + __ASSERT_NO_MSG(dev != NULL); + __ASSERT_NO_MSG(dev_data != NULL); + + heth = &dev_data->heth; total_len = net_pkt_get_len(pkt); if (total_len > (ETH_STM32_TX_BUF_SIZE * ETH_TXBUFNB)) { @@ -514,8 +522,8 @@ static struct net_if *get_iface(struct eth_stm32_hal_dev_data *ctx) static struct net_pkt *eth_rx(const struct device *dev) { - struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + struct eth_stm32_hal_dev_data *dev_data; + ETH_HandleTypeDef *heth; struct net_pkt *pkt; size_t total_len = 0; #if defined(CONFIG_ETH_STM32_HAL_API_V2) @@ -534,6 +542,14 @@ static struct net_pkt *eth_rx(const struct device *dev) timestamp.nanosecond = UINT32_MAX; #endif /* CONFIG_PTP_CLOCK_STM32_HAL */ + __ASSERT_NO_MSG(dev != NULL); + + dev_data = dev->data; + + __ASSERT_NO_MSG(dev_data != NULL); + + heth = &dev_data->heth; + #if defined(CONFIG_ETH_STM32_HAL_API_V2) if (HAL_ETH_ReadData(heth, &appbuf) != HAL_OK) { /* no frame available */ @@ -645,15 +661,21 @@ static struct net_pkt *eth_rx(const struct device *dev) static void rx_thread(void *arg1, void *unused1, void *unused2) { - const struct device *dev = (const struct device *)arg1; - struct eth_stm32_hal_dev_data *dev_data = dev->data; + const struct device *dev; + struct eth_stm32_hal_dev_data *dev_data; struct net_if *iface; struct net_pkt *pkt; int res; + __ASSERT_NO_MSG(arg1 != NULL); ARG_UNUSED(unused1); ARG_UNUSED(unused2); + dev = (const struct device *)arg1; + dev_data = dev->data; + + __ASSERT_NO_MSG(dev_data != NULL); + while (1) { res = k_sem_take(&dev_data->rx_int_sem, K_FOREVER); if (res == 0) { @@ -678,8 +700,18 @@ static void rx_thread(void *arg1, void *unused1, void *unused2) static void eth_isr(const struct device *dev) { - struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + struct eth_stm32_hal_dev_data *dev_data; + ETH_HandleTypeDef *heth; + + __ASSERT_NO_MSG(dev != NULL); + + dev_data = dev->data; + + __ASSERT_NO_MSG(dev_data != NULL); + + heth = &dev_data->heth; + + __ASSERT_NO_MSG(heth != NULL); HAL_ETH_IRQHandler(heth); } @@ -847,12 +879,22 @@ static void RISAF_Config(void) static int eth_initialize(const struct device *dev) { - struct eth_stm32_hal_dev_data *dev_data = dev->data; - const struct eth_stm32_hal_dev_cfg *cfg = dev->config; - ETH_HandleTypeDef *heth = &dev_data->heth; + struct eth_stm32_hal_dev_data *dev_data; + const struct eth_stm32_hal_dev_cfg *cfg; + ETH_HandleTypeDef *heth; int ret = 0; - if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) { + __ASSERT_NO_MSG(dev != NULL); + + dev_data = dev->data; + cfg = dev->config; + + __ASSERT_NO_MSG(dev_data != NULL); + __ASSERT_NO_MSG(cfg != NULL); + + dev_data->clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); + + if (!device_is_ready(dev_data->clock)) { LOG_ERR("clock control device not ready"); return -ENODEV; } @@ -863,14 +905,14 @@ static int eth_initialize(const struct device *dev) #endif /* enable clock */ - ret = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + ret = clock_control_on(dev_data->clock, (clock_control_subsys_t)&cfg->pclken); - ret |= clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + ret |= clock_control_on(dev_data->clock, (clock_control_subsys_t)&cfg->pclken_tx); - ret |= clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + ret |= clock_control_on(dev_data->clock, (clock_control_subsys_t)&cfg->pclken_rx); #if DT_INST_CLOCKS_HAS_NAME(0, mac_clk_ptp) - ret |= clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + ret |= clock_control_on(dev_data->clock, (clock_control_subsys_t)&cfg->pclken_ptp); #endif @@ -886,6 +928,8 @@ static int eth_initialize(const struct device *dev) return ret; } + heth = &dev_data->heth; + generate_mac(dev_data->mac_addr); heth->Init.MACAddr = dev_data->mac_addr; @@ -938,11 +982,13 @@ static int eth_initialize(const struct device *dev) static void eth_stm32_mcast_filter(const struct device *dev, const struct ethernet_filter *filter) { struct eth_stm32_hal_dev_data *dev_data = (struct eth_stm32_hal_dev_data *)dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + ETH_HandleTypeDef *heth; uint32_t crc; uint32_t hash_table[2]; uint32_t hash_index; + heth = &dev_data->heth; + crc = __RBIT(crc32_ieee(filter->mac_address.addr, sizeof(struct net_eth_addr))); hash_index = (crc >> 26) & 0x3f; @@ -986,8 +1032,11 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern static int eth_init_api_v2(const struct device *dev) { HAL_StatusTypeDef hal_ret = HAL_OK; - struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + struct eth_stm32_hal_dev_data *dev_data; + ETH_HandleTypeDef *heth; + + dev_data = dev->data; + heth = &dev_data->heth; #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet) for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) { @@ -1140,10 +1189,21 @@ static void phy_link_state_changed(const struct device *phy_dev, struct phy_link static void eth_iface_init(struct net_if *iface) { - const struct device *dev = net_if_get_device(iface); - struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + const struct device *dev; + struct eth_stm32_hal_dev_data *dev_data; bool is_first_init = false; + ETH_HandleTypeDef *heth; + + __ASSERT_NO_MSG(iface != NULL); + + dev = net_if_get_device(iface); + __ASSERT_NO_MSG(dev != NULL); + + dev_data = dev->data; + __ASSERT_NO_MSG(dev_data != NULL); + + heth = &dev_data->heth; + __ASSERT_NO_MSG(heth != NULL); if (dev_data->iface == NULL) { dev_data->iface = iface; @@ -1233,44 +1293,54 @@ static enum ethernet_hw_caps eth_stm32_hal_get_capabilities(const struct device static int eth_stm32_hal_get_config(const struct device *dev, enum ethernet_config_type type, struct ethernet_config *config) { - struct eth_stm32_hal_dev_data *dev_data = dev->data; + int ret = -ENOTSUP; + struct eth_stm32_hal_dev_data *dev_data; + ETH_HandleTypeDef *heth; + + dev_data = dev->data; + heth = &dev_data->heth; switch (type) { case ETHERNET_CONFIG_TYPE_MAC_ADDRESS: memcpy(config->mac_address.addr, dev_data->mac_addr, sizeof(config->mac_address.addr)); - return 0; -#if defined(CONFIG_NET_PROMISCUOUS_MODE) + ret = 0; + break; case ETHERNET_CONFIG_TYPE_PROMISC_MODE: - ETH_HandleTypeDef *heth = &dev_data->heth; -#if defined(CONFIG_ETH_STM32_HAL_API_V2) - ETH_MACFilterConfigTypeDef MACFilterConf; - - HAL_ETH_GetMACFilterConfig(heth, &MACFilterConf); - - config->promisc_mode = (MACFilterConf.PromiscuousMode == ENABLE); +#if defined(CONFIG_NET_PROMISCUOUS_MODE) +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) + if (heth->Instance->MACPFR & ETH_MACPFR_PR) { + config->promisc_mode = true; + } else { + config->promisc_mode = false; + } #else if (heth->Instance->MACFFR & ETH_MACFFR_PM) { config->promisc_mode = true; } else { config->promisc_mode = false; } -#endif /* CONFIG_ETH_STM32_HAL_API_V2 */ - return 0; +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */ + ret = 0; #endif /* CONFIG_NET_PROMISCUOUS_MODE */ + break; default: break; } - return -ENOTSUP; + return ret; } static int eth_stm32_hal_set_config(const struct device *dev, enum ethernet_config_type type, const struct ethernet_config *config) { - struct eth_stm32_hal_dev_data *dev_data = dev->data; - ETH_HandleTypeDef *heth = &dev_data->heth; + int ret = -ENOTSUP; + struct eth_stm32_hal_dev_data *dev_data; + ETH_HandleTypeDef *heth; + + dev_data = dev->data; + heth = &dev_data->heth; switch (type) { case ETHERNET_CONFIG_TYPE_MAC_ADDRESS: @@ -1284,36 +1354,36 @@ static int eth_stm32_hal_set_config(const struct device *dev, net_if_set_link_addr(dev_data->iface, dev_data->mac_addr, sizeof(dev_data->mac_addr), NET_LINK_ETHERNET); - return 0; -#if defined(CONFIG_NET_PROMISCUOUS_MODE) + ret = 0; + break; case ETHERNET_CONFIG_TYPE_PROMISC_MODE: -#if defined(CONFIG_ETH_STM32_HAL_API_V2) - ETH_MACFilterConfigTypeDef MACFilterConf; - - HAL_ETH_GetMACFilterConfig(heth, &MACFilterConf); - - MACFilterConf.PromiscuousMode = config->promisc_mode ? ENABLE : DISABLE; - - HAL_ETH_SetMACFilterConfig(heth, &MACFilterConf); +#if defined(CONFIG_NET_PROMISCUOUS_MODE) +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) + if (config->promisc_mode) { + heth->Instance->MACPFR |= ETH_MACPFR_PR; + } else { + heth->Instance->MACPFR &= ~ETH_MACPFR_PR; + } #else if (config->promisc_mode) { heth->Instance->MACFFR |= ETH_MACFFR_PM; } else { heth->Instance->MACFFR &= ~ETH_MACFFR_PM; } -#endif /* CONFIG_ETH_STM32_HAL_API_V2 */ - return 0; +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */ + ret = 0; #endif /* CONFIG_NET_PROMISCUOUS_MODE */ + break; #if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) case ETHERNET_CONFIG_TYPE_FILTER: eth_stm32_mcast_filter(dev, &config->filter); - return 0; + break; #endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ default: break; } - return -ENOTSUP; + return ret; } static const struct device *eth_stm32_hal_get_phy(const struct device *dev) @@ -1383,11 +1453,11 @@ static const struct eth_stm32_hal_dev_cfg eth0_config = { .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), }; -BUILD_ASSERT(DT_INST_ENUM_HAS_VALUE(0, phy_connection_type, mii) - || DT_INST_ENUM_HAS_VALUE(0, phy_connection_type, rmii) +BUILD_ASSERT(DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, mii) + || DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, rmii) IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet), - (|| DT_INST_ENUM_HAS_VALUE(0, phy_connection_type, rgmii) - || DT_INST_ENUM_HAS_VALUE(0, phy_connection_type, gmii))), + (|| DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, rgmii) + || DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, gmii))), "Unsupported PHY connection type"); static struct eth_stm32_hal_dev_data eth0_data = { @@ -1402,7 +1472,7 @@ static struct eth_stm32_hal_dev_data eth0_data = { .ChecksumMode = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ? ETH_CHECKSUM_BY_HARDWARE : ETH_CHECKSUM_BY_SOFTWARE, #endif /* CONFIG_ETH_STM32_HAL_API_V1 */ - .MediaInterface = STM32_ETH_PHY_MODE(0), + .MediaInterface = STM32_ETH_PHY_MODE(MAC_NODE), }, }, }; @@ -1617,7 +1687,7 @@ static int ptp_stm32_init(const struct device *port) #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */ /* Query ethernet clock rate */ - ret = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + ret = clock_control_get_rate(eth_dev_data->clock, #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) (clock_control_subsys_t)ð_cfg->pclken, #else diff --git a/drivers/ethernet/eth_stm32_hal_priv.h b/drivers/ethernet/eth_stm32_hal_priv.h index d1a6ec0218f3a..53a01462c37ce 100644 --- a/drivers/ethernet/eth_stm32_hal_priv.h +++ b/drivers/ethernet/eth_stm32_hal_priv.h @@ -46,6 +46,8 @@ struct eth_stm32_hal_dev_data { struct net_if *iface; uint8_t mac_addr[6]; ETH_HandleTypeDef heth; + /* clock device */ + const struct device *clock; struct k_mutex tx_mutex; struct k_sem rx_int_sem; #if defined(CONFIG_ETH_STM32_HAL_API_V2) diff --git a/drivers/ethernet/eth_xlnx_gem.c b/drivers/ethernet/eth_xlnx_gem.c index 1a99dbbe393fd..79c3f005497ac 100644 --- a/drivers/ethernet/eth_xlnx_gem.c +++ b/drivers/ethernet/eth_xlnx_gem.c @@ -48,9 +48,6 @@ static enum ethernet_hw_caps static int eth_xlnx_gem_get_config(const struct device *dev, enum ethernet_config_type type, struct ethernet_config *config); -static int eth_xlnx_gem_set_config(const struct device *dev, - enum ethernet_config_type type, - const struct ethernet_config *config); #if defined(CONFIG_NET_STATISTICS_ETHERNET) static struct net_stats_eth *eth_xlnx_gem_stats(const struct device *dev); #endif @@ -76,7 +73,6 @@ static const struct ethernet_api eth_xlnx_gem_apis = { .start = eth_xlnx_gem_start_device, .stop = eth_xlnx_gem_stop_device, .get_config = eth_xlnx_gem_get_config, - .set_config = eth_xlnx_gem_set_config, #if defined(CONFIG_NET_STATISTICS_ETHERNET) .get_stats = eth_xlnx_gem_stats, #endif @@ -653,7 +649,9 @@ static enum ethernet_hw_caps eth_xlnx_gem_get_capabilities( caps |= ETHERNET_DUPLEX_SET; } - caps |= ETHERNET_PROMISC_MODE; + if (dev_conf->copy_all_frames) { + caps |= ETHERNET_PROMISC_MODE; + } return caps; } @@ -710,55 +708,6 @@ static int eth_xlnx_gem_get_config(const struct device *dev, }; } -/** - * @brief GEM hardware configuration data set function - * Modifies hardware configuration details of the specified device - * instance. Multiple hardware configuration items can be addressed - * depending on the type parameter. Currently supports setting the - * controller's MAC address and enabling/disabling promiscuous mode - * if this is enabled at the system level. - * - * @param dev Pointer to the device data - * @param type The hardware configuration item to be modified - * @param config Pointer to the struct containing the configuration - * data to be applied. - * @return 0 if the specified configuration item was successfully - * modified, -ENOTSUP if the specified configuration item - * is not supported by this function. - */ -static int eth_xlnx_gem_set_config(const struct device *dev, - enum ethernet_config_type type, - const struct ethernet_config *config) -{ - struct eth_xlnx_gem_dev_data *dev_data = dev->data; - - switch (type) { -#ifdef CONFIG_NET_PROMISCUOUS_MODE - case ETHERNET_CONFIG_TYPE_PROMISC_MODE: - const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; - uint32_t reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCFG_OFFSET); - - if (config->promisc_mode) { - reg_val |= ETH_XLNX_GEM_NWCFG_COPYALLEN_BIT; - } else { - reg_val &= ~ETH_XLNX_GEM_NWCFG_COPYALLEN_BIT; - } - sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCFG_OFFSET); - break; -#endif - case ETHERNET_CONFIG_TYPE_MAC_ADDRESS: - memcpy(dev_data->mac_addr, config->mac_address.addr, sizeof(dev_data->mac_addr)); - eth_xlnx_gem_set_mac_address(dev); - net_if_set_link_addr(dev_data->iface, dev_data->mac_addr, - sizeof(dev_data->mac_addr), NET_LINK_ETHERNET); - break; - default: - return -ENOTSUP; - }; - - return 0; -} - #ifdef CONFIG_NET_STATISTICS_ETHERNET /** * @brief GEM statistics data request function @@ -1035,6 +984,10 @@ static void eth_xlnx_gem_set_initial_nwcfg(const struct device *dev) /* [05] Do not receive broadcast frames */ reg_val |= ETH_XLNX_GEM_NWCFG_BCASTDIS_BIT; } + if (dev_conf->copy_all_frames) { + /* [04] Copy all frames */ + reg_val |= ETH_XLNX_GEM_NWCFG_COPYALLEN_BIT; + } if (dev_conf->discard_non_vlan) { /* [02] Receive only VLAN frames */ reg_val |= ETH_XLNX_GEM_NWCFG_NVLANDISC_BIT; diff --git a/drivers/ethernet/eth_xlnx_gem_priv.h b/drivers/ethernet/eth_xlnx_gem_priv.h index a4cb88f93b98c..a1787eb756973 100644 --- a/drivers/ethernet/eth_xlnx_gem_priv.h +++ b/drivers/ethernet/eth_xlnx_gem_priv.h @@ -464,6 +464,7 @@ static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\ .enable_ucast_hash = DT_INST_PROP(port, unicast_hash),\ .enable_mcast_hash = DT_INST_PROP(port, multicast_hash),\ .disable_bcast = DT_INST_PROP(port, reject_broadcast),\ + .copy_all_frames = DT_INST_PROP(port, promiscuous_mode),\ .discard_non_vlan = DT_INST_PROP(port, discard_non_vlan),\ .enable_fdx = DT_INST_PROP(port, full_duplex),\ .disc_rx_ahb_unavail = DT_INST_PROP(port, discard_rx_frame_ahb_unavail),\ @@ -721,6 +722,7 @@ struct eth_xlnx_gem_dev_cfg { bool enable_ucast_hash : 1; bool enable_mcast_hash : 1; bool disable_bcast : 1; + bool copy_all_frames : 1; bool discard_non_vlan : 1; bool enable_fdx : 1; bool disc_rx_ahb_unavail : 1; diff --git a/drivers/ethernet/phy/phy_microchip_vsc8541.c b/drivers/ethernet/phy/phy_microchip_vsc8541.c index 9be5a1deaea0d..121418fd52b1f 100644 --- a/drivers/ethernet/phy/phy_microchip_vsc8541.c +++ b/drivers/ethernet/phy/phy_microchip_vsc8541.c @@ -85,8 +85,6 @@ struct mc_vsc8541_config { uint8_t addr; const struct device *mdio_dev; enum vsc8541_interface microchip_interface_type; - uint8_t rgmii_rx_clk_delay; - uint8_t rgmii_tx_clk_delay; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) const struct gpio_dt_spec reset_gpio; #endif @@ -152,9 +150,9 @@ static int phy_mc_vsc8541_verify_phy_id(const struct device *dev) */ static int phy_mc_vsc8541_reset(const struct device *dev) { - const struct mc_vsc8541_config *cfg = dev->config; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) + const struct mc_vsc8541_config *cfg = dev->config; if (!cfg->reset_gpio.port) { LOG_WRN("missing reset port definition"); @@ -229,11 +227,12 @@ static int phy_mc_vsc8541_reset(const struct device *dev) } /* configure the RGMII clk delay */ + /* this is highly hardware dependent and may vary between pcb designs */ reg = 0x0; /* RX_CLK delay */ - reg |= (cfg->rgmii_rx_clk_delay << 4); + reg |= (0x5 << 4); /* TX_CLK delay */ - reg |= (cfg->rgmii_tx_clk_delay << 0); + reg |= (0x5 << 0); ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE2_RGMII_CONTROL, reg); if (ret) { return ret; @@ -441,6 +440,7 @@ void phy_mc_vsc8541_link_monitor(void *arg1, void *arg2, void *arg3) { const struct device *dev = arg1; struct mc_vsc8541_data *data = dev->data; + const struct mc_vsc8541_config *cfg = dev->config; struct phy_link_state new_state; @@ -565,8 +565,6 @@ static DEVICE_API(ethphy, mc_vsc8541_phy_api) = { .addr = DT_INST_REG_ADDR(n), \ .mdio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \ .microchip_interface_type = DT_INST_ENUM_IDX(n, microchip_interface_type), \ - .rgmii_rx_clk_delay = DT_INST_PROP(n, microchip_rgmii_rx_clk_delay), \ - .rgmii_tx_clk_delay = DT_INST_PROP(n, microchip_rgmii_tx_clk_delay), \ RESET_GPIO(n) INTERRUPT_GPIO(n)}; \ \ static struct mc_vsc8541_data mc_vsc8541_##n##_data; \ diff --git a/drivers/firmware/CMakeLists.txt b/drivers/firmware/CMakeLists.txt index 062106cf92b3a..167d21addb5f2 100644 --- a/drivers/firmware/CMakeLists.txt +++ b/drivers/firmware/CMakeLists.txt @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # zephyr-keep-sorted-start +add_subdirectory(nrf_ironside) add_subdirectory_ifdef(CONFIG_ARM_SCMI scmi) -add_subdirectory_ifdef(CONFIG_NRF_IRONSIDE nrf_ironside) # zephyr-keep-sorted-stop diff --git a/drivers/firmware/nrf_ironside/Kconfig b/drivers/firmware/nrf_ironside/Kconfig index 20545669e926c..adfdf97f648f8 100644 --- a/drivers/firmware/nrf_ironside/Kconfig +++ b/drivers/firmware/nrf_ironside/Kconfig @@ -1,16 +1,10 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config NRF_IRONSIDE - bool - depends on SOC_NRF54H20_IRON - help - This is selected by drivers interacting with Nordic IRONside firmware. - config NRF_IRONSIDE_CALL bool depends on DT_HAS_NORDIC_IRONSIDE_CALL_ENABLED - select NRF_IRONSIDE + depends on SOC_NRF54H20_IRON select EVENTS select MBOX help diff --git a/drivers/firmware/nrf_ironside/call.c b/drivers/firmware/nrf_ironside/call.c index f120c01754904..8d77119828c84 100644 --- a/drivers/firmware/nrf_ironside/call.c +++ b/drivers/firmware/nrf_ironside/call.c @@ -29,8 +29,8 @@ BUILD_ASSERT((sizeof(struct ironside_call_buf) % CONFIG_DCACHE_LINE_SIZE) == 0); static const struct mbox_dt_spec mbox_rx = MBOX_DT_SPEC_INST_GET(0, rx); static const struct mbox_dt_spec mbox_tx = MBOX_DT_SPEC_INST_GET(0, tx); -static K_EVENT_DEFINE(alloc_evts); -static K_EVENT_DEFINE(rsp_evts); +K_EVENT_DEFINE(alloc_evts); +K_EVENT_DEFINE(rsp_evts); static void ironside_call_rsp(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index b72aa37a3608a..089259a2572a4 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -51,12 +51,12 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ITE_IT8XXX2 flash_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_LPC soc_flash_lpc.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_MAX32 flash_max32.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_MCUX soc_flash_mcux.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF soc_flash_nrf.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAM soc_flash_nrf_mram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER_RMC soc_flash_numaker_rmc.c) -zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RTS5912 flash_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM flash_sam.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c) @@ -159,7 +159,7 @@ if(CONFIG_FLASH_NXP_S32_QSPI_NOR OR CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH) zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) endif() -if(CONFIG_SOC_FLASH_RENESAS_RA_HP) - zephyr_library_sources(soc_flash_renesas_ra_hp.c) - zephyr_library_sources_ifdef(CONFIG_FLASH_EX_OP_ENABLED soc_flash_renesas_ra_hp_ex_op.c) +if(CONFIG_RA_FLASH_HP) + zephyr_library_sources(flash_hp_ra.c) + zephyr_library_sources_ifdef(CONFIG_FLASH_EX_OP_ENABLED flash_hp_ra_ex_op.c) endif() diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index cfa34d3e1c410..bdd84f25814b4 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -181,6 +181,7 @@ source "drivers/flash/Kconfig.lpc" source "drivers/flash/Kconfig.max32" source "drivers/flash/Kconfig.mcux" source "drivers/flash/Kconfig.mspi" +source "drivers/flash/Kconfig.nios2_qspi" source "drivers/flash/Kconfig.nor" source "drivers/flash/Kconfig.nordic_qspi_nor" source "drivers/flash/Kconfig.npcx_fiu" @@ -192,7 +193,6 @@ source "drivers/flash/Kconfig.numaker_rmc" source "drivers/flash/Kconfig.nxp_s32" source "drivers/flash/Kconfig.renesas_ra" source "drivers/flash/Kconfig.rpi_pico" -source "drivers/flash/Kconfig.rts5912" source "drivers/flash/Kconfig.rv32m1" source "drivers/flash/Kconfig.sam" source "drivers/flash/Kconfig.sam0" diff --git a/drivers/flash/Kconfig.mspi b/drivers/flash/Kconfig.mspi index d0f244957d215..d699aa4930937 100644 --- a/drivers/flash/Kconfig.mspi +++ b/drivers/flash/Kconfig.mspi @@ -26,7 +26,7 @@ config FLASH_MSPI_ATXP032 select FLASH_HAS_PAGE_LAYOUT select FLASH_HAS_EXPLICIT_ERASE select FLASH_JESD216 - select MSPI_AMBIQ_CONTROLLER if SOC_FAMILY_AMBIQ + select MSPI_AMBIQ_AP3 if SOC_SERIES_APOLLO3X menuconfig FLASH_MSPI_NOR bool "Generic MSPI NOR Flash" diff --git a/drivers/flash/Kconfig.nios2_qspi b/drivers/flash/Kconfig.nios2_qspi new file mode 100644 index 0000000000000..ab834b5b95635 --- /dev/null +++ b/drivers/flash/Kconfig.nios2_qspi @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FLASH_NIOS2_QSPI + bool "Nios-II QSPI flash driver" + default y + depends on HAS_ALTERA_HAL + depends on DT_HAS_ALTR_NIOS2_QSPI_NOR_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_EXPLICIT_ERASE + help + Enables the Nios-II QSPI flash driver. diff --git a/drivers/flash/Kconfig.renesas_ra b/drivers/flash/Kconfig.renesas_ra index 19078f1d0d856..e93d37564eb87 100644 --- a/drivers/flash/Kconfig.renesas_ra +++ b/drivers/flash/Kconfig.renesas_ra @@ -1,10 +1,10 @@ # Renesas RA Family -# Copyright (c) 2024-2025 Renesas Electronics Corporation +# Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -config SOC_FLASH_RENESAS_RA_HP - bool "RA Flash HP driver" +config RA_FLASH_HP + bool "RA flash driver" depends on DT_HAS_RENESAS_RA_FLASH_HP_CONTROLLER_ENABLED default y select FLASH_HAS_DRIVER_ENABLED @@ -14,30 +14,20 @@ config SOC_FLASH_RENESAS_RA_HP select FLASH_HAS_EX_OP if(SOC_SERIES_RA8M1 || SOC_SERIES_RA8D1 || SOC_SERIES_RA8T1) select USE_RA_FSP_FLASH_HP help - Enable Flash HP driver for RA series + Enable flash driver for RA series -if SOC_FLASH_RENESAS_RA_HP +if RA_FLASH_HP -config FLASH_RENESAS_RA_HP_WRITE_PROTECT +config FLASH_RA_WRITE_PROTECT bool "Extended operation for flash write protection control" default n help Enables flash extended operation to enable/disable flash write protection from external devices -config FLASH_RENESAS_RA_HP_BGO - bool "Background operations feature" - default y - help - Enable Background operations (BGOs) - -config FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING - bool "Verify area before reading it" - default $(dt_nodelabel_bool_prop,flash1,erase-value-undefined) +config DUAL_BANK_MODE + bool "Dual bank mode" help - Do a blank check flash command before reading an area. - This feature prevents erroneous reading. Values read from an - area of the data flash that has been erased but not programmed - are undefined. + Enable dual bank mode -endif # SOC_FLASH_RENESAS_RA_HP +endif # RA_FLASH_HP diff --git a/drivers/flash/Kconfig.rts5912 b/drivers/flash/Kconfig.rts5912 deleted file mode 100644 index fe289276a4fd3..0000000000000 --- a/drivers/flash/Kconfig.rts5912 +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7 -# - -config SOC_FLASH_RTS5912 - bool "Realtek RTS5912 flash driver" - default y - depends on DT_HAS_REALTEK_RTS5912_FLASH_CONTROLLER_ENABLED - select FLASH_HAS_PAGE_LAYOUT - select FLASH_HAS_DRIVER_ENABLED - select FLASH_HAS_EXPLICIT_ERASE - select FLASH_HAS_EX_OP - select HAS_FLASH_LOAD_OFFSET - help - The flash driver includes support for read, write and - erase flash operations. It also supports protection. - The rts5912 flash size is 960K byte. diff --git a/drivers/flash/Kconfig.stm32 b/drivers/flash/Kconfig.stm32 index caa28854331b7..c7c9bb1e00c31 100644 --- a/drivers/flash/Kconfig.stm32 +++ b/drivers/flash/Kconfig.stm32 @@ -7,12 +7,13 @@ # SPDX-License-Identifier: Apache-2.0 config STM32_MEMMAP - bool "NOR Flash in MemoryMapped" - depends on DT_HAS_ST_STM32_QSPI_NOR_ENABLED || \ - DT_HAS_ST_STM32_OSPI_NOR_ENABLED || \ - DT_HAS_ST_STM32_XSPI_NOR_ENABLED + bool "NOR Flash in MemoryMapped for XiP" + depends on XIP && \ + (DT_HAS_ST_STM32_OSPI_NOR_ENABLED || \ + DT_HAS_ST_STM32_QSPI_NOR_ENABLED || \ + DT_HAS_ST_STM32_XSPI_NOR_ENABLED) help - This option enables the MemoryMapped mode for the external NOR flash + This option enables the XIP mode for the external NOR flash mounted on STM32 boards. menuconfig SOC_FLASH_STM32 diff --git a/drivers/flash/flash_ambiq.c b/drivers/flash/flash_ambiq.c index 45cc199e860ff..d3998e3e200c2 100644 --- a/drivers/flash/flash_ambiq.c +++ b/drivers/flash/flash_ambiq.c @@ -18,11 +18,11 @@ LOG_MODULE_REGISTER(flash_ambiq, CONFIG_FLASH_LOG_LEVEL); #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) #define SOC_NV_FLASH_ADDR DT_REG_ADDR(SOC_NV_FLASH_NODE) #define SOC_NV_FLASH_SIZE DT_REG_SIZE(SOC_NV_FLASH_NODE) -#if (CONFIG_SOC_SERIES_APOLLO3X) -#define MIN_WRITE_SIZE 4 -#else +#if (CONFIG_SOC_SERIES_APOLLO4X) #define MIN_WRITE_SIZE 16 -#endif +#else +#define MIN_WRITE_SIZE 4 +#endif /* CONFIG_SOC_SERIES_APOLLO4X */ #define FLASH_WRITE_BLOCK_SIZE MAX(DT_PROP(SOC_NV_FLASH_NODE, write_block_size), MIN_WRITE_SIZE) #define FLASH_ERASE_BLOCK_SIZE DT_PROP(SOC_NV_FLASH_NODE, erase_block_size) @@ -48,7 +48,7 @@ static struct k_sem flash_ambiq_sem; static const struct flash_parameters flash_ambiq_parameters = { .write_block_size = FLASH_WRITE_BLOCK_SIZE, .erase_value = FLASH_ERASE_BYTE, -#if !defined(CONFIG_SOC_SERIES_APOLLO3X) +#if defined(CONFIG_SOC_SERIES_APOLLO4X) .caps = { .no_explicit_erase = true, }, @@ -113,17 +113,17 @@ static int flash_ambiq_write(const struct device *dev, off_t offset, const void aligned[j] = UNALIGNED_GET((uint32_t *)src); src++; } -#if defined(CONFIG_SOC_SERIES_APOLLO3X) - ret = am_hal_flash_program_main( - AM_HAL_FLASH_PROGRAM_KEY, aligned, - (uint32_t *)(SOC_NV_FLASH_ADDR + offset + i * FLASH_WRITE_BLOCK_SIZE), - FLASH_WRITE_BLOCK_SIZE / sizeof(uint32_t)); -#else +#if (CONFIG_SOC_SERIES_APOLLO4X) ret = am_hal_mram_main_program( AM_HAL_MRAM_PROGRAM_KEY, aligned, (uint32_t *)(SOC_NV_FLASH_ADDR + offset + i * FLASH_WRITE_BLOCK_SIZE), FLASH_WRITE_BLOCK_SIZE / sizeof(uint32_t)); -#endif +#elif (CONFIG_SOC_SERIES_APOLLO3X) + ret = am_hal_flash_program_main( + AM_HAL_FLASH_PROGRAM_KEY, aligned, + (uint32_t *)(SOC_NV_FLASH_ADDR + offset + i * FLASH_WRITE_BLOCK_SIZE), + FLASH_WRITE_BLOCK_SIZE / sizeof(uint32_t)); +#endif /* CONFIG_SOC_SERIES_APOLLO4X */ if (ret) { break; } @@ -150,7 +150,9 @@ static int flash_ambiq_erase(const struct device *dev, off_t offset, size_t len) return 0; } -#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#if (CONFIG_SOC_SERIES_APOLLO4X) + /* The erase address and length alignment check will be done in HAL.*/ +#elif (CONFIG_SOC_SERIES_APOLLO3X) if ((offset % FLASH_ERASE_BLOCK_SIZE) != 0) { LOG_ERR("offset 0x%lx is not on a page boundary", (long)offset); return -EINVAL; @@ -160,13 +162,15 @@ static int flash_ambiq_erase(const struct device *dev, off_t offset, size_t len) LOG_ERR("len %zu is not multiple of a page size", len); return -EINVAL; } -#else - /* The erase address and length alignment check will be done in HAL.*/ -#endif +#endif /* CONFIG_SOC_SERIES_APOLLO4X */ FLASH_SEM_TAKE(); -#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#if (CONFIG_SOC_SERIES_APOLLO4X) + ret = am_hal_mram_main_fill(AM_HAL_MRAM_PROGRAM_KEY, FLASH_ERASE_WORD, + (uint32_t *)(SOC_NV_FLASH_ADDR + offset), + (len / sizeof(uint32_t))); +#elif (CONFIG_SOC_SERIES_APOLLO3X) unsigned int key = 0; key = irq_lock(); @@ -177,11 +181,7 @@ static int flash_ambiq_erase(const struct device *dev, off_t offset, size_t len) AM_HAL_FLASH_ADDR2PAGE(((uint32_t)SOC_NV_FLASH_ADDR + offset))); irq_unlock(key); -#else - ret = am_hal_mram_main_fill(AM_HAL_MRAM_PROGRAM_KEY, FLASH_ERASE_WORD, - (uint32_t *)(SOC_NV_FLASH_ADDR + offset), - (len / sizeof(uint32_t))); -#endif +#endif /* CONFIG_SOC_SERIES_APOLLO4X */ FLASH_SEM_GIVE(); diff --git a/drivers/flash/flash_hp_ra.c b/drivers/flash/flash_hp_ra.c new file mode 100644 index 0000000000000..d58985c8ea3ad --- /dev/null +++ b/drivers/flash/flash_hp_ra.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL +#include +#include +#include +#include +#include +#include +#include +#include +#include "flash_hp_ra.h" + +#define DT_DRV_COMPAT renesas_ra_flash_hp_controller + +LOG_MODULE_REGISTER(flash_hp_ra, CONFIG_FLASH_LOG_LEVEL); + +#define ERASE_BLOCK_SIZE_0 DT_PROP(DT_INST(0, renesas_ra_nv_flash), erase_block_size) +#define ERASE_BLOCK_SIZE_1 DT_PROP(DT_INST(1, renesas_ra_nv_flash), erase_block_size) + +BUILD_ASSERT((ERASE_BLOCK_SIZE_0 % FLASH_HP_CF_BLOCK_8KB_SIZE) == 0, + "erase-block-size expected to be a multiple of a block size"); +BUILD_ASSERT((ERASE_BLOCK_SIZE_1 % FLASH_HP_DF_BLOCK_SIZE) == 0, + "erase-block-size expected to be a multiple of a block size"); + +/* Flags, set from Callback function */ +static volatile struct event_flash g_event_flash = { + .erase_complete = false, + .write_complete = false, +}; + +static struct flash_pages_layout flash_ra_layout[5]; + +void fcu_frdyi_isr(void); +void fcu_fiferr_isr(void); + +void bgo_callback(flash_callback_args_t *p_args) +{ + if (FLASH_EVENT_ERASE_COMPLETE == p_args->event) { + g_event_flash.erase_complete = true; + } else { + g_event_flash.write_complete = true; + } +} + +static bool flash_ra_valid_range(struct flash_hp_ra_data *flash_data, off_t offset, size_t len) +{ +#if defined(CONFIG_DUAL_BANK_MODE) + if (flash_data->FlashRegion == DATA_FLASH) { + if ((offset < 0) || (offset >= flash_data->area_size) || + (flash_data->area_size - offset < len) || (len > UINT32_MAX - offset)) { + return false; + } + } else { + if ((offset < 0) || (offset >= FLASH_HP_CF_DUAL_HIGH_END_ADDRESS) || + (offset >= FLASH_HP_CF_DUAL_LOW_END_ADDRESS && + offset < FLASH_HP_BANK2_OFFSET) || + ((len + offset) > FLASH_HP_CF_DUAL_HIGH_END_ADDRESS) || + ((len + offset) > FLASH_HP_CF_DUAL_LOW_END_ADDRESS && + (len + offset) < FLASH_HP_BANK2_OFFSET) || + (len > UINT32_MAX - offset)) { + return false; + } + } +#else + if ((offset < 0) || (offset >= flash_data->area_size) || + (flash_data->area_size - offset < len) || (len > UINT32_MAX - offset)) { + return false; + } +#endif + return true; +} + +static int flash_ra_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + struct flash_hp_ra_data *flash_data = dev->data; + + if (!flash_ra_valid_range(flash_data, offset, len)) { + return -EINVAL; + } + + if (!len) { + return 0; + } + + LOG_DBG("flash: read 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); + + memcpy(data, (uint8_t *)(offset + flash_data->area_address), len); + + return 0; +} + +static int flash_ra_erase(const struct device *dev, off_t offset, size_t len) +{ + struct flash_hp_ra_data *flash_data = dev->data; + struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; + static struct flash_pages_info page_info_off, page_info_len; + fsp_err_t err; + uint32_t block_num; + int rc, rc2; + int key = 0; + bool is_contain_end_block = false; + + if (!flash_ra_valid_range(flash_data, offset, len)) { + return -EINVAL; + } + + if (!len) { + return 0; + } + + LOG_DBG("flash: erase 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); + + rc = flash_get_page_info_by_offs(dev, offset, &page_info_off); + + if (rc != 0) { + return -EINVAL; + } + + if (offset != page_info_off.start_offset) { + return -EINVAL; + } + + if (flash_data->FlashRegion == CODE_FLASH) { +#if defined(CONFIG_DUAL_BANK_MODE) + if ((offset + len) == (uint32_t)FLASH_HP_CF_DUAL_HIGH_END_ADDRESS) { + page_info_len.index = FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_END + 1; + is_contain_end_block = true; + } +#else + if ((offset + len) == (uint32_t)DT_REG_SIZE(DT_NODELABEL(flash0))) { + page_info_len.index = FLASH_HP_CF_BLOCK_32KB_LINEAR_END + 1; + is_contain_end_block = true; + } +#endif + } else { + if ((offset + len) == (uint32_t)DT_REG_SIZE(DT_NODELABEL(flash1))) { + page_info_len.index = FLASH_HP_DF_BLOCK_END; + is_contain_end_block = true; + } + } + + if (!is_contain_end_block) { + rc2 = flash_get_page_info_by_offs(dev, (offset + len), &page_info_len); + if (rc2 != 0) { + return -EINVAL; + } + if ((offset + len) != (page_info_len.start_offset)) { + return -EIO; + } + } + + block_num = (uint32_t)((page_info_len.index) - page_info_off.index); + + if (block_num > 0) { + if (flash_data->FlashRegion == CODE_FLASH) { + /* Disable interrupts during code flash operations */ + key = irq_lock(); + } else { + k_sem_take(&dev_ctrl->ctrl_sem, K_FOREVER); + } + + err = R_FLASH_HP_Erase(&dev_ctrl->flash_ctrl, + (long)(flash_data->area_address + offset), block_num); + + if (err != FSP_SUCCESS) { + if (flash_data->FlashRegion == CODE_FLASH) { + irq_unlock(key); + } else { + k_sem_give(&dev_ctrl->ctrl_sem); + } + return -EIO; + } + + if (flash_data->FlashRegion == DATA_FLASH) { + /* Wait for the erase complete event flag, if BGO is SET */ + if (true == dev_ctrl->fsp_config.data_flash_bgo) { + while (!g_event_flash.erase_complete) { + k_sleep(K_USEC(10)); + } + g_event_flash.erase_complete = false; + } + } + + if (flash_data->FlashRegion == CODE_FLASH) { + irq_unlock(key); + } else { + k_sem_give(&dev_ctrl->ctrl_sem); + } + } + + return 0; +} + +static int flash_ra_write(const struct device *dev, off_t offset, const void *data, size_t len) +{ + fsp_err_t err; + struct flash_hp_ra_data *flash_data = dev->data; + struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; + int key = 0; + + if (!flash_ra_valid_range(flash_data, offset, len)) { + return -EINVAL; + } + + if (!len) { + return 0; + } + + LOG_DBG("flash: write 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); + + if (flash_data->FlashRegion == CODE_FLASH) { + /* Disable interrupts during code flash operations */ + key = irq_lock(); + } else { + k_sem_take(&dev_ctrl->ctrl_sem, K_FOREVER); + } + + err = R_FLASH_HP_Write(&dev_ctrl->flash_ctrl, (uint32_t)data, + (long)(offset + flash_data->area_address), len); + + if (err != FSP_SUCCESS) { + if (flash_data->FlashRegion == CODE_FLASH) { + irq_unlock(key); + } else { + k_sem_give(&dev_ctrl->ctrl_sem); + } + return -EIO; + } + + if (flash_data->FlashRegion == DATA_FLASH) { + /* Wait for the write complete event flag, if BGO is SET */ + if (true == dev_ctrl->fsp_config.data_flash_bgo) { + while (!g_event_flash.write_complete) { + k_sleep(K_USEC(10)); + } + g_event_flash.write_complete = false; + } + } + + if (flash_data->FlashRegion == CODE_FLASH) { + irq_unlock(key); + } else { + k_sem_give(&dev_ctrl->ctrl_sem); + } + + return 0; +} + +static int flash_ra_get_size(const struct device *dev, uint64_t *size) +{ + struct flash_hp_ra_data *flash_data = dev->data; + *size = (uint64_t)flash_data->area_size; + + return 0; +} + +#ifdef CONFIG_FLASH_PAGE_LAYOUT +void flash_ra_page_layout(const struct device *dev, const struct flash_pages_layout **layout, + size_t *layout_size) +{ + struct flash_hp_ra_data *flash_data = dev->data; + + if (flash_data->FlashRegion == DATA_FLASH) { + flash_ra_layout[0].pages_count = flash_data->area_size / FLASH_HP_DF_BLOCK_SIZE; + flash_ra_layout[0].pages_size = FLASH_HP_DF_BLOCK_SIZE; + + *layout_size = 1; + } else { +#if defined(CONFIG_DUAL_BANK_MODE) + flash_ra_layout[0].pages_count = + (FLASH_HP_CF_BLOCK_8KB_LOW_END - FLASH_HP_CF_BLOCK_8KB_LOW_START) + 1; + flash_ra_layout[0].pages_size = FLASH_HP_CF_BLOCK_8KB_SIZE; + + flash_ra_layout[1].pages_count = (FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_END - + FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_START) + + 1; + flash_ra_layout[1].pages_size = FLASH_HP_CF_BLOCK_32KB_SIZE; + + flash_ra_layout[2].pages_count = FLASH_HP_CF_NUM_BLOCK_RESERVED; + flash_ra_layout[2].pages_size = + (FLASH_HP_BANK2_OFFSET - + (flash_ra_layout[0].pages_count * flash_ra_layout[0].pages_size) - + (flash_ra_layout[1].pages_count * flash_ra_layout[1].pages_size)) / + FLASH_HP_CF_NUM_BLOCK_RESERVED; + + flash_ra_layout[3].pages_count = + (FLASH_HP_CF_BLOCK_8KB_HIGH_END - FLASH_HP_CF_BLOCK_8KB_HIGH_START) + 1; + flash_ra_layout[3].pages_size = FLASH_HP_CF_BLOCK_8KB_SIZE; + + /* The final block is the dummy block */ + flash_ra_layout[4].pages_count = (FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_END + 1 - + FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_START) + + 1; + flash_ra_layout[4].pages_size = FLASH_HP_CF_BLOCK_32KB_SIZE; + + *layout_size = 5; +#else + flash_ra_layout[0].pages_count = + (FLASH_HP_CF_BLOCK_8KB_LOW_END - FLASH_HP_CF_BLOCK_8KB_LOW_START) + 1; + flash_ra_layout[0].pages_size = FLASH_HP_CF_BLOCK_8KB_SIZE; + flash_ra_layout[1].pages_count = + (FLASH_HP_CF_BLOCK_32KB_LINEAR_END - FLASH_HP_CF_BLOCK_32KB_LINEAR_START) + + 1; + flash_ra_layout[1].pages_size = FLASH_HP_CF_BLOCK_32KB_SIZE; + + *layout_size = 2; +#endif + } + + *layout = flash_ra_layout; +} +#endif + +static const struct flash_parameters *flash_ra_get_parameters(const struct device *dev) +{ + const struct flash_hp_ra_config *config = dev->config; + + return &config->flash_ra_parameters; +} + +static struct flash_hp_ra_controller flash_hp_ra_controller = { + .fsp_config = { + .data_flash_bgo = true, + .p_callback = bgo_callback, + .p_context = NULL, + .irq = (IRQn_Type)DT_INST_IRQ_BY_NAME(0, frdyi, irq), + .err_irq = (IRQn_Type)DT_INST_IRQ_BY_NAME(0, fiferr, irq), + .err_ipl = DT_INST_IRQ_BY_NAME(0, fiferr, priority), + .ipl = DT_INST_IRQ_BY_NAME(0, frdyi, priority), + }}; + +#ifdef CONFIG_FLASH_EX_OP_ENABLED +static int flash_ra_ex_op(const struct device *dev, uint16_t code, const uintptr_t in, void *out) +{ + int err = -ENOTSUP; + + switch (code) { +#if defined(CONFIG_FLASH_RA_WRITE_PROTECT) + case FLASH_RA_EX_OP_WRITE_PROTECT: + err = flash_ra_ex_op_write_protect(dev, in, out); + break; +#endif /* CONFIG_FLASH_RA_WRITE_PROTECT */ + + default: + break; + } + + return err; +} +#endif + +static int flash_ra_init(const struct device *dev) +{ + const struct device *dev_ctrl = DEVICE_DT_INST_GET(0); + struct flash_hp_ra_data *flash_data = dev->data; + + if (!device_is_ready(dev_ctrl)) { + return -ENODEV; + } + + if (flash_data->area_address == FLASH_HP_DF_START) { + flash_data->FlashRegion = DATA_FLASH; + } else { + flash_data->FlashRegion = CODE_FLASH; + } + + flash_data->controller = dev_ctrl->data; + + return 0; +} + +static void flash_controller_ra_irq_config_func(const struct device *dev) +{ + ARG_UNUSED(dev); + + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq)] = + BSP_PRV_IELS_ENUM(EVENT_FCU_FRDYI); + R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq)] = + BSP_PRV_IELS_ENUM(EVENT_FCU_FIFERR); + + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq), + DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, priority), fcu_frdyi_isr, + DEVICE_DT_INST_GET(0), 0); + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq), + DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, priority), fcu_fiferr_isr, + DEVICE_DT_INST_GET(0), 0); + + irq_enable(DT_INST_IRQ_BY_NAME(0, frdyi, irq)); + irq_enable(DT_INST_IRQ_BY_NAME(0, fiferr, irq)); +} + +static int flash_controller_ra_init(const struct device *dev) +{ + fsp_err_t err; + const struct flash_hp_ra_controller_config *cfg = dev->config; + struct flash_hp_ra_controller *data = dev->data; + + cfg->irq_config(dev); + + err = R_FLASH_HP_Open(&data->flash_ctrl, &data->fsp_config); + + if (err != FSP_SUCCESS) { + LOG_DBG("flash: open error=%d", (int)err); + return -EIO; + } + + k_sem_init(&data->ctrl_sem, 1, 1); + + return 0; +} + +static struct flash_hp_ra_controller_config flash_hp_ra_controller_config = { + .irq_config = flash_controller_ra_irq_config_func, +}; + +static DEVICE_API(flash, flash_ra_api) = { + .erase = flash_ra_erase, + .write = flash_ra_write, + .read = flash_ra_read, + .get_parameters = flash_ra_get_parameters, + .get_size = flash_ra_get_size, +#ifdef CONFIG_FLASH_PAGE_LAYOUT + .page_layout = flash_ra_page_layout, +#endif +#ifdef CONFIG_FLASH_EX_OP_ENABLED + .ex_op = flash_ra_ex_op, +#endif +}; + +#define RA_FLASH_INIT(index) \ + struct flash_hp_ra_data flash_hp_ra_data_##index = {.area_address = DT_REG_ADDR(index), \ + .area_size = DT_REG_SIZE(index)}; \ + static struct flash_hp_ra_config flash_hp_ra_config_##index = { \ + .flash_ra_parameters = { \ + .write_block_size = GET_SIZE( \ + (CHECK_EQ(DT_REG_ADDR(index), FLASH_HP_DF_START)), 4, 128), \ + .erase_value = 0xff, \ + }}; \ + \ + DEVICE_DT_DEFINE(index, flash_ra_init, NULL, &flash_hp_ra_data_##index, \ + &flash_hp_ra_config_##index, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, \ + &flash_ra_api); + +DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(0), RA_FLASH_INIT); + +/* define the flash controller device just to run the init. */ +DEVICE_DT_DEFINE(DT_DRV_INST(0), flash_controller_ra_init, NULL, &flash_hp_ra_controller, + &flash_hp_ra_controller_config, PRE_KERNEL_1, CONFIG_FLASH_INIT_PRIORITY, NULL); diff --git a/drivers/flash/flash_hp_ra.h b/drivers/flash/flash_hp_ra.h new file mode 100644 index 0000000000000..f5592c72af55b --- /dev/null +++ b/drivers/flash/flash_hp_ra.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_FLASH_RA_HP_H_ +#define ZEPHYR_DRIVERS_FLASH_RA_HP_H_ + +#include +#include +#include +#include + +#define CHECK_EQ(val1, val2) ((val1) == (val2) ? 1 : 0) +#define GET_SIZE(COND, value, default_value) ((COND) ? (value) : (default_value)) + +#define FLASH_HP_BANK2_OFFSET \ + (BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START - BSP_FEATURE_FLASH_CODE_FLASH_START) + +#define FLASH_HP_CF_BLOCK_8KB_SIZE BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE +#define FLASH_HP_CF_BLOCK_32KB_SIZE BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE +#define FLASH_HP_DF_BLOCK_SIZE BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE +#define FLASH_HP_DF_START BSP_FEATURE_FLASH_DATA_FLASH_START + +#define FLASH_HP_CF_BLOCK_8KB_LOW_START (0) +#define FLASH_HP_CF_BLOCK_8KB_LOW_END (7) +#define FLASH_HP_CF_BLOCK_8KB_HIGH_START (70) +#define FLASH_HP_CF_BLOCK_8KB_HIGH_END (77) + +#define FLASH_HP_CF_BLOCK_32KB_LINEAR_START (8) +#define FLASH_HP_CF_BLOCK_32KB_LINEAR_END (DT_PROP(DT_NODELABEL(flash), block_32kb_linear_end)) + +#define FLASH_HP_DF_BLOCK_END (DT_REG_SIZE(DT_NODELABEL(flash1)) / FLASH_HP_DF_BLOCK_SIZE) + +#if defined(CONFIG_DUAL_BANK_MODE) +#define FLASH_HP_CF_NUM_BLOCK_RESERVED (DT_PROP(DT_NODELABEL(flash), reserved_area_num)) +#define FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_START (8) +#define FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_START (78) + +#define FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_END (DT_PROP(DT_NODELABEL(flash), block_32kb_dual_low_end)) +#define FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_END \ + (DT_PROP(DT_NODELABEL(flash), block_32kb_dual_high_end)) + +#define FLASH_HP_CF_DUAL_HIGH_START_ADDRESS BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START + +#define FLASH_HP_CF_DUAL_LOW_END_ADDRESS \ + (DT_REG_SIZE(DT_NODELABEL(flash0)) - \ + ((FLASH_HP_CF_BLOCK_32KB_LINEAR_END - FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_END) * \ + FLASH_HP_CF_BLOCK_32KB_SIZE)) + +#define FLASH_HP_CF_DUAL_HIGH_END_ADDRESS \ + (DT_REG_SIZE(DT_NODELABEL(flash0)) + \ + (FLASH_HP_CF_NUM_BLOCK_RESERVED * FLASH_HP_CF_BLOCK_32KB_SIZE)) +#endif + +#if defined(CONFIG_FLASH_EX_OP_ENABLED) +#define FLASH_HP_FCU_CONFIG_SET_BPS (0x1300A1C0U) +#define FLASH_HP_FCU_CONFIG_SET_BPS_SEC (0x0300A240U) +#define FLASH_HP_FCU_CONFIG_SET_BPS_SEL (0x0300A2C0U) + +#define FLASH_HP_FCU_CONFIG_SET_PBPS (0x1300A1E0U) +#define FLASH_HP_FCU_CONFIG_SET_PBPS_SEC (0x0300A260U) +#endif /* CONFIG_FLASH_EX_OP_ENABLED */ + +/* Zero based offset into g_configuration_area_data[] for BPS */ +#define FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET (0U) + +enum flash_region { + CODE_FLASH, + DATA_FLASH, +}; + +typedef void (*irq_config_func_t)(const struct device *dev); + +struct flash_hp_ra_controller { + struct st_flash_hp_instance_ctrl flash_ctrl; + struct k_sem ctrl_sem; + struct st_flash_cfg fsp_config; +}; + +struct flash_hp_ra_controller_config { + irq_config_func_t irq_config; +}; + +struct flash_hp_ra_data { + struct flash_hp_ra_controller *controller; + enum flash_region FlashRegion; + uint32_t area_address; + uint32_t area_size; +}; + +struct flash_hp_ra_config { + struct flash_parameters flash_ra_parameters; +}; + +struct event_flash { + volatile bool erase_complete; + volatile bool write_complete; +}; + +#if defined(CONFIG_FLASH_RA_WRITE_PROTECT) +int flash_ra_ex_op_write_protect(const struct device *dev, const uintptr_t in, void *out); +#endif /*CONFIG_FLASH_RA_WRITE_PROTECT*/ + +#endif /* ZEPHYR_DRIVERS_FLASH_RA_HP_H_ */ diff --git a/drivers/flash/flash_hp_ra_ex_op.c b/drivers/flash/flash_hp_ra_ex_op.c new file mode 100644 index 0000000000000..aa9c9f3c9fc66 --- /dev/null +++ b/drivers/flash/flash_hp_ra_ex_op.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_USERSPACE +#include +#include +#endif + +#include +#include "flash_hp_ra.h" + +#define FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT (8U) + +#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) +extern uint16_t g_configuration_area_data[FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT]; +#endif +extern fsp_err_t +flash_hp_enter_pe_cf_mode(flash_hp_instance_ctrl_t *const p_ctrl) PLACE_IN_RAM_SECTION; + +extern fsp_err_t flash_hp_stop(void) PLACE_IN_RAM_SECTION; + +extern fsp_err_t flash_hp_configuration_area_write(flash_hp_instance_ctrl_t *p_ctrl, + uint32_t fsaddr, + uint16_t *src_address) PLACE_IN_RAM_SECTION; + +extern fsp_err_t flash_hp_check_errors(fsp_err_t previous_error, uint32_t error_bits, + fsp_err_t return_error) PLACE_IN_RAM_SECTION; + +extern fsp_err_t flash_hp_pe_mode_exit(void) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_val_ns, uint8_t *pbps_val_ns, + uint32_t size) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_val_sec, uint8_t *pbps_val_sec, + uint32_t size) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_set_block_protect_sel(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_sel_val, + uint32_t size) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_val_ns, uint8_t *pbps_val_ns, + uint32_t size) +{ + /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ + int key = irq_lock(); + + /* Update Flash state and enter Code Flash P/E mode */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + if (bps_val_ns != NULL) { + memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_ns, + size); + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS, + &g_configuration_area_data); + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + } + + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + if (pbps_val_ns != NULL) { + memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_ns, + size); + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS, + &g_configuration_area_data); + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (err == FSP_SUCCESS) { + err = pe_exit_err; + } + + /* Enable interrupts after code flash operations are complete. */ + irq_unlock(key); + + return err; +} + +static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_val_sec, uint8_t *pbps_val_sec, + uint32_t size) +{ + /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ + int key = irq_lock(); + /* Update Flash state and enter Code Flash P/E mode */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + if (bps_val_sec != NULL) { + memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_sec, + size); + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEC, + &g_configuration_area_data); + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + } + + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + if (pbps_val_sec != NULL) { + memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_sec, + size); + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS_SEC, + &g_configuration_area_data); + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (err == FSP_SUCCESS) { + err = pe_exit_err; + } + + /* Enable interrupts after code flash operations are complete. */ + irq_unlock(key); + + return err; +} + +static fsp_err_t flash_hp_set_block_protect_sel(flash_hp_instance_ctrl_t *p_ctrl, + uint8_t *bps_sel_val, uint32_t size) +{ + /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ + int key = irq_lock(); + + /* Update Flash state and enter Code Flash P/E mode */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_sel_val, size); + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEL, + &g_configuration_area_data); + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (err == FSP_SUCCESS) { + err = pe_exit_err; + } + + /* Enable interrupts after code flash operations are complete. */ + irq_unlock(key); + + return err; +} + +static fsp_err_t R_FLASH_HP_BlockProtectSet(flash_ctrl_t *const p_api_ctrl, uint8_t *bps_val_ns, + uint8_t *bps_val_sec, uint8_t *bps_val_sel, + uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, + uint32_t size); + +static fsp_err_t R_FLASH_HP_BlockProtectGet(flash_ctrl_t *const p_api_ctrl, uint32_t *bps_val_ns, + uint32_t *bps_val_sec, uint8_t *bps_val_sel, + uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, + uint32_t *size); + +int flash_ra_block_protect_set(const struct device *dev, + const struct flash_ra_ex_write_protect_in *request); + +int flash_ra_block_protect_get(const struct device *dev, + struct flash_ra_ex_write_protect_out *response); + +static fsp_err_t R_FLASH_HP_BlockProtectSet(flash_ctrl_t *const p_api_ctrl, uint8_t *bps_val_ns, + uint8_t *bps_val_sec, uint8_t *bps_val_sel, + uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, + uint32_t size) +{ + flash_hp_instance_ctrl_t *p_ctrl = (flash_hp_instance_ctrl_t *)p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) + + /* if non-secure BPS (PBPS) buffers are not null and size is smaller than 16 bytes */ + if (((bps_val_ns != NULL) || (pbps_val_ns != NULL)) && + (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { + err = flash_hp_set_block_protect_ns(p_ctrl, bps_val_ns, pbps_val_ns, size); + } + + /* if secure BPS (PBPS) buffers are not null and size is smaller than 16 bytes */ + if (((bps_val_sec != NULL) || (pbps_val_sec != NULL)) && + (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { + err = flash_hp_set_block_protect_sec(p_ctrl, bps_val_sec, pbps_val_sec, size); + } + + /* if BPS SEL buffer is not null and size is smaller than 16 bytes */ + if ((bps_val_sel != NULL) && + (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { + err = flash_hp_set_block_protect_sel(p_ctrl, bps_val_sel, size); + } +#else + + err = FSP_ERR_UNSUPPORTED; /* For consistency with _LP API we return error if Code Flash */ + +#endif + + return err; +} + +static fsp_err_t R_FLASH_HP_BlockProtectGet(flash_ctrl_t *const p_api_ctrl, uint32_t *bps_val_ns, + uint32_t *bps_val_sec, uint8_t *bps_val_sel, + uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, + uint32_t *size) +{ + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) + + err = FSP_SUCCESS; + + if (bps_val_ns != NULL) { + bps_val_ns[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 0)); + bps_val_ns[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 3)); + bps_val_ns[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 7)); + bps_val_ns[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 11)); + } + + if (bps_val_sec != NULL) { + bps_val_sec[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 0)); + bps_val_sec[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 3)); + bps_val_sec[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 7)); + bps_val_sec[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 11)); + } + + if (bps_val_sel != NULL) { + bps_val_sel[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 0)); + bps_val_sel[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 3)); + bps_val_sel[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 7)); + bps_val_sel[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 11)); + } + + if (pbps_val_ns != NULL) { + pbps_val_ns[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 0)); + pbps_val_ns[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 3)); + pbps_val_ns[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 7)); + pbps_val_ns[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 11)); + } + + if (pbps_val_sec != NULL) { + pbps_val_sec[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 0)); + pbps_val_sec[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 3)); + pbps_val_sec[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 7)); + pbps_val_sec[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 11)); + } + + if (size != NULL) { + *size = 4; + } +#endif + + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return err; +} + +#if defined(CONFIG_FLASH_RA_WRITE_PROTECT) +int flash_ra_block_protect_get(const struct device *dev, + struct flash_ra_ex_write_protect_out *response) +{ + fsp_err_t err = FSP_ERR_ASSERTION; + struct flash_hp_ra_data *flash_data = dev->data; + struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; + flash_ra_cf_block_map bps_ns; + + /* get the current non-secure BPS register values */ + err = R_FLASH_HP_BlockProtectGet(&dev_ctrl->flash_ctrl, (uint32_t *)&bps_ns, NULL, NULL, + NULL, NULL, NULL); + memcpy(&response->protected_enabled, &bps_ns, sizeof(flash_ra_cf_block_map)); + + return err; +} + +int flash_ra_ex_op_write_protect(const struct device *dev, const uintptr_t in, void *out) +{ + const struct flash_ra_ex_write_protect_in *request = + (const struct flash_ra_ex_write_protect_in *)in; + struct flash_ra_ex_write_protect_out *result = (struct flash_ra_ex_write_protect_out *)out; + + int rc = 0, rc2 = 0; +#ifdef CONFIG_USERSPACE + bool syscall_trap = z_syscall_trap(); +#endif + + if (request != NULL) { +#ifdef CONFIG_USERSPACE + struct flash_ra_ex_write_protect_in copy_in; + + if (syscall_trap) { + Z_OOPS(z_user_from_copy(©_in, request, sizeof(copy_in))); + request = ©_in; + } +#endif + /* if both enable and disable are set */ + if ((request->protect_enable.BPS[0] & request->protect_disable.BPS[0]) || + (request->protect_enable.BPS[1] & request->protect_disable.BPS[1]) || + (request->protect_enable.BPS[2] & request->protect_disable.BPS[2]) || + (request->protect_enable.BPS[3] & request->protect_disable.BPS[3])) { + return EINVAL; + } + + rc = flash_ra_block_protect_set(dev, request); + } + + if (result != NULL) { +#ifdef CONFIG_USERSPACE + struct flash_ra_ex_write_protect_out copy_out; + + if (syscall_trap) { + result = ©_out; + } +#endif + rc2 = flash_ra_block_protect_get(dev, result); + if (!rc) { + rc = rc2; + } + +#ifdef CONFIG_USERSPACE + if (syscall_trap) { + Z_OOPS(z_user_to_copy(out, result, sizeof(copy_out))); + } +#endif + } + + return rc; +} + +int flash_ra_block_protect_set(const struct device *dev, + const struct flash_ra_ex_write_protect_in *request) +{ + fsp_err_t err = FSP_ERR_ASSERTION; + struct flash_hp_ra_data *flash_data = dev->data; + struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; + flash_ra_cf_block_map bps_ns; + + /* get the current non-secure BPS register values */ + err = R_FLASH_HP_BlockProtectGet(&dev_ctrl->flash_ctrl, (uint32_t *)&bps_ns, NULL, NULL, + NULL, NULL, NULL); + + if (err != FSP_SUCCESS) { + __ASSERT(false, "flash: block get current value error =%d", err); + return -EIO; + } + + /* enable block protect */ + bps_ns.BPS[0] &= ~(request->protect_enable.BPS[0]); + bps_ns.BPS[1] &= ~(request->protect_enable.BPS[1]); + bps_ns.BPS[2] &= ~(request->protect_enable.BPS[2]); + bps_ns.BPS[3] &= ~(request->protect_enable.BPS[3]); + + /* disable block protect */ + bps_ns.BPS[0] |= (request->protect_disable.BPS[0]); + bps_ns.BPS[1] |= (request->protect_disable.BPS[1]); + bps_ns.BPS[2] |= (request->protect_disable.BPS[2]); + bps_ns.BPS[3] |= (request->protect_disable.BPS[3]); + + /* reset default all from non-secure */ + err = R_FLASH_HP_BlockProtectSet(&dev_ctrl->flash_ctrl, (uint8_t *)&bps_ns, NULL, NULL, + NULL, NULL, sizeof(bps_ns)); + + if (err != FSP_SUCCESS) { + __ASSERT(false, "flash: block protect error=%d", err); + return -EIO; + } + return 0; +} + +#endif /* CONFIG_FLASH_RA_WRITE_PROTECT */ diff --git a/drivers/flash/flash_mspi_atxp032.c b/drivers/flash/flash_mspi_atxp032.c index 187d10a95dc83..c8fd82218d657 100644 --- a/drivers/flash/flash_mspi_atxp032.c +++ b/drivers/flash/flash_mspi_atxp032.c @@ -124,7 +124,6 @@ static int flash_mspi_atxp032_command_write(const struct device *flash, uint8_t data->trans.async = false; data->trans.xfer_mode = MSPI_PIO; data->trans.tx_dummy = tx_dummy; - data->trans.rx_dummy = data->dev_cfg.rx_dummy; data->trans.cmd_length = 1; data->trans.addr_length = addr_len; data->trans.hold_ce = false; @@ -156,7 +155,6 @@ static int flash_mspi_atxp032_command_read(const struct device *flash, uint8_t c data->trans.async = false; data->trans.xfer_mode = MSPI_PIO; - data->trans.tx_dummy = data->dev_cfg.tx_dummy; data->trans.rx_dummy = rx_dummy; data->trans.cmd_length = 1; data->trans.addr_length = addr_len; @@ -263,7 +261,7 @@ static int flash_mspi_atxp032_get_vendor_id(const struct device *flash, uint8_t ret = flash_mspi_atxp032_command_read(flash, SPI_NOR_CMD_RDID, 0, 0, 0, buffer, 11); *vendor_id = buffer[7]; - memcpy(&data->jedec_id, buffer + 7, 3); + data->jedec_id = (buffer[7] << 16) | (buffer[8] << 8) | buffer[9]; return ret; } @@ -328,11 +326,10 @@ static int flash_mspi_atxp032_page_program(const struct device *flash, off_t off data->trans.async = false; data->trans.xfer_mode = MSPI_DMA; data->trans.tx_dummy = data->dev_cfg.tx_dummy; - data->trans.rx_dummy = data->dev_cfg.rx_dummy; data->trans.cmd_length = data->dev_cfg.cmd_length; data->trans.addr_length = data->dev_cfg.addr_length; data->trans.hold_ce = false; - data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM; + data->trans.priority = 1; data->trans.packets = &data->packet; data->trans.num_packet = 1; data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE; @@ -378,7 +375,6 @@ static int flash_mspi_atxp032_busy_wait(const struct device *flash) return ret; } LOG_DBG("status: 0x%x", status); - k_sleep(K_MSEC(1)); } while (status & SPI_NOR_WIP_BIT); if (data->dev_cfg.io_mode != MSPI_IO_MODE_SINGLE) { @@ -411,12 +407,11 @@ static int flash_mspi_atxp032_read(const struct device *flash, off_t offset, voi data->trans.async = false; data->trans.xfer_mode = MSPI_DMA; - data->trans.tx_dummy = data->dev_cfg.tx_dummy; data->trans.rx_dummy = data->dev_cfg.rx_dummy; data->trans.cmd_length = data->dev_cfg.cmd_length; data->trans.addr_length = data->dev_cfg.addr_length; data->trans.hold_ce = false; - data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM; + data->trans.priority = 1; data->trans.packets = &data->packet; data->trans.num_packet = 1; data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE; @@ -686,7 +681,6 @@ static int flash_mspi_atxp032_init(const struct device *flash) } data->timing_cfg = cfg->tar_timing_cfg; -#if CONFIG_MSPI_XIP if (cfg->tar_xip_cfg.enable) { if (mspi_xip_config(cfg->bus, &cfg->dev_id, &cfg->tar_xip_cfg)) { LOG_ERR("Failed to enable XIP/%u", __LINE__); @@ -694,9 +688,7 @@ static int flash_mspi_atxp032_init(const struct device *flash) } data->xip_cfg = cfg->tar_xip_cfg; } -#endif /* CONFIG_MSPI_XIP */ -#if CONFIG_MSPI_SCRAMBLE if (cfg->tar_scramble_cfg.enable) { if (mspi_scramble_config(cfg->bus, &cfg->dev_id, &cfg->tar_scramble_cfg)) { LOG_ERR("Failed to enable scrambling/%u", __LINE__); @@ -704,7 +696,6 @@ static int flash_mspi_atxp032_init(const struct device *flash) } data->scramble_cfg = cfg->tar_scramble_cfg; } -#endif /* MSPI_SCRAMBLE */ release(flash); @@ -729,12 +720,11 @@ static int flash_mspi_atxp032_read_sfdp(const struct device *flash, off_t addr, data->trans.async = false; data->trans.xfer_mode = MSPI_DMA; - data->trans.tx_dummy = data->dev_cfg.tx_dummy; data->trans.rx_dummy = 8; data->trans.cmd_length = 1; data->trans.addr_length = 3; data->trans.hold_ce = false; - data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM; + data->trans.priority = 1; data->trans.packets = &data->packet; data->trans.num_packet = 1; data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE; @@ -755,7 +745,7 @@ static int flash_mspi_atxp032_read_jedec_id(const struct device *flash, uint8_t { struct flash_mspi_atxp032_data *data = flash->data; - memcpy(id, &data->jedec_id, 3); + id = &data->jedec_id; return 0; } #endif /* CONFIG_FLASH_JESD216_API */ @@ -818,17 +808,23 @@ static DEVICE_API(flash, flash_mspi_atxp032_api) = { .time_to_break = 0, \ } +#if CONFIG_SOC_FAMILY_AMBIQ #define MSPI_TIMING_CONFIG(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_TIMING_CONFIG(n)), ({})) \ - -#define MSPI_TIMING_CONFIG_MASK(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_TIMING_CONFIG_MASK(n)), (MSPI_TIMING_PARAM_DUMMY)) \ - -#define MSPI_PORT(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_PORT(n)), (0)) \ + { \ + .ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \ + .ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \ + .bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \ + .bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \ + .bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \ + .ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \ + .ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \ + .ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \ + } +#define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask) +#else +#define MSPI_TIMING_CONFIG(n) +#define MSPI_TIMING_CONFIG_MASK(n) +#endif #define FLASH_MSPI_ATXP032(n) \ static const struct flash_mspi_atxp032_config flash_mspi_atxp032_config_##n = { \ diff --git a/drivers/flash/flash_mspi_emul_device.c b/drivers/flash/flash_mspi_emul_device.c index 8438e98a30d93..55657283a02f5 100644 --- a/drivers/flash/flash_mspi_emul_device.c +++ b/drivers/flash/flash_mspi_emul_device.c @@ -215,7 +215,7 @@ static int flash_mspi_emul_write(const struct device *flash, off_t offset, data->xfer.cmd_length = data->dev_cfg.cmd_length; data->xfer.addr_length = data->dev_cfg.addr_length; data->xfer.hold_ce = false; - data->xfer.priority = MSPI_XFER_PRIORITY_MEDIUM; + data->xfer.priority = 1; data->xfer.packets = &data->packet; data->xfer.num_packet = 1; data->xfer.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE; @@ -288,7 +288,7 @@ static int flash_mspi_emul_read(const struct device *flash, off_t offset, data->xfer.cmd_length = data->dev_cfg.cmd_length; data->xfer.addr_length = data->dev_cfg.addr_length; data->xfer.hold_ce = false; - data->xfer.priority = MSPI_XFER_PRIORITY_MEDIUM; + data->xfer.priority = 1; data->xfer.packets = &data->packet; data->xfer.num_packet = 1; data->xfer.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE; diff --git a/drivers/flash/flash_nxp_s32_qspi.c b/drivers/flash/flash_nxp_s32_qspi.c index d9cd5114d2c5d..424960935ba3a 100644 --- a/drivers/flash/flash_nxp_s32_qspi.c +++ b/drivers/flash/flash_nxp_s32_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright 2023-2025 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -93,11 +93,7 @@ int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t len; int ret = 0; - if (!size) { - return 0; - } - - if (!src) { + if (!src || !size) { return -EINVAL; } @@ -191,11 +187,7 @@ int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size) size_t erase_size; int ret = 0; - if (!size) { - return 0; - } - - if (!area_is_subregion(dev, offset, size)) { + if (!area_is_subregion(dev, offset, size) || !size) { return -EINVAL; } diff --git a/drivers/flash/flash_realtek_rts5912.c b/drivers/flash/flash_realtek_rts5912.c deleted file mode 100644 index 4bfa19d1f1e34..0000000000000 --- a/drivers/flash/flash_realtek_rts5912.c +++ /dev/null @@ -1,826 +0,0 @@ -/* - * Copyright (c) 2025 Realtek, SIBG-SD7 - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT realtek_rts5912_flash_controller -#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) - -#define FLASH_PAGE_SZ 256 -#define FLASH_WRITE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, write_block_size) -#define FLASH_ERASE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, erase_block_size) - -#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL -#include -LOG_MODULE_REGISTER(flash_rts5912); - -#include -#include -#ifdef CONFIG_FLASH_EX_OP_ENABLED -#include -#endif -#include -#include -#include -#include - -#include "spi_nor.h" -#include "reg/reg_spic.h" - -#define FLASH_CMD_RDSFDP 0x5A /* Read SFDP */ -#define FLASH_CMD_EX4B 0xE9 /* Exit 4-byte mode */ -#define FLASH_CMD_EXTNADDR_WREAR 0xC5 /* Write extended address register */ -#define FLASH_CMD_EXTNADDR_RDEAR 0xC8 /* Read extended address register */ - -#define MODE(x) (((x) << 6) & SPIC_CTRL0_SCPH) -#define TMOD(x) (((x) << SPIC_CTRL0_TMOD_Pos) & SPIC_CTRL0_TMOD_Msk) -#define CMD_CH(x) (((x) << SPIC_CTRL0_CMDCH_Pos) & SPIC_CTRL0_CMDCH_Msk) -#define ADDR_CH(x) (((x) << SPIC_CTRL0_ADDRCH_Pos) & SPIC_CTRL0_ADDRCH_Msk) -#define DATA_CH(x) (((x) << SPIC_CTRL0_DATACH_Pos) & SPIC_CTRL0_DATACH_Msk) - -#define USER_CMD_LENGTH(x) (((x) << SPIC_USERLENGTH_CMDLEN_Pos) & SPIC_USERLENGTH_CMDLEN_Msk) -#define USER_ADDR_LENGTH(x) (((x) << SPIC_USERLENGTH_ADDRLEN_Pos) & SPIC_USERLENGTH_ADDRLEN_Msk) -#define USER_RD_DUMMY_LENGTH(x) \ - (((x) << SPIC_USERLENGTH_RDDUMMYLEN_Pos) & SPIC_USERLENGTH_RDDUMMYLEN_Msk) - -#define TX_NDF(x) (((x) << SPIC_TXNDF_NUM_Pos) & SPIC_TXNDF_NUM_Msk) -#define RX_NDF(x) (((x) << SPIC_RXNDF_NUM_Pos) & SPIC_RXNDF_NUM_Msk) - -#define TIMEOUT_SPICEN 10UL -#define TIMEOUT_SPIBUSY 10000UL - -enum { - COMMAND_READ = 0, - COMMAND_WRITE = 1, -}; - -enum spic_freq { - SPIC_FREQ_SYS_CLK_DIV2 = 1, - SPIC_FREQ_SYS_CLK_DIV4, - SPIC_FREQ_SYS_CLK_DIV8, - SPIC_FREQ_SYS_CLK_DIV16, -}; - -enum spic_bus_width { - SPIC_CFG_BUS_SINGLE, - SPIC_CFG_BUS_DUAL, - SPIC_CFG_BUS_QUAD, -}; - -enum spic_address_size { - SPIC_CFG_ADDR_SIZE_8, - SPIC_CFG_ADDR_SIZE_16, - SPIC_CFG_ADDR_SIZE_24, - SPIC_CFG_ADDR_SIZE_32, -}; - -struct qspi_cmd { - struct { - enum spic_bus_width bus_width; /* Bus width for the instruction */ - uint8_t value; /* Instruction value */ - uint8_t disabled; /* Instruction phase skipped if disabled is set to true */ - } instruction; - struct { - enum spic_bus_width bus_width; /* Bus width for the address */ - enum spic_address_size size; /* Address size */ - uint32_t value; /* Address value */ - uint8_t disabled; /* Address phase skipped if disabled is set to true */ - } address; - struct { - enum spic_bus_width bus_width; /* Bus width for alternative */ - uint8_t size; /* Alternative size */ - uint32_t value; /* Alternative value */ - uint8_t disabled; /* Alternative phase skipped if disabled is set to true */ - } alt; - uint8_t dummy_count; /* Dummy cycles count */ - struct { - enum spic_bus_width bus_width; /* Bus width for data */ - } data; -}; - -struct flash_rts5912_dev_config { - volatile struct reg_spic_reg *regs; - struct flash_parameters flash_rts5912_parameters; -}; - -struct flash_rts5912_dev_data { - struct k_sem sem; - struct qspi_cmd command_default; -}; - -static const uint8_t user_addr_len[] = { - [SPIC_CFG_ADDR_SIZE_8] = 1, - [SPIC_CFG_ADDR_SIZE_16] = 2, - [SPIC_CFG_ADDR_SIZE_24] = 3, - [SPIC_CFG_ADDR_SIZE_32] = 4, -}; - -static int config_command(struct qspi_cmd *command, uint8_t cmd, uint32_t addr, - enum spic_address_size addr_size, uint8_t dummy_count) -{ - int ret = 0; - - switch (cmd) { - case SPI_NOR_CMD_WREN: - case SPI_NOR_CMD_WRDI: - case SPI_NOR_CMD_WRSR: - case SPI_NOR_CMD_RDID: - case SPI_NOR_CMD_RDSR: - case SPI_NOR_CMD_RDSR2: - case SPI_NOR_CMD_CE: - case SPI_NOR_CMD_4BA: - case FLASH_CMD_EX4B: - case FLASH_CMD_EXTNADDR_WREAR: - case FLASH_CMD_EXTNADDR_RDEAR: - case SPI_NOR_CMD_RESET_EN: - case SPI_NOR_CMD_RESET_MEM: - command->address.disabled = 1; - command->data.bus_width = SPIC_CFG_BUS_SINGLE; - break; - case SPI_NOR_CMD_READ: - case SPI_NOR_CMD_READ_FAST: - case SPI_NOR_CMD_SE: - case SPI_NOR_CMD_BE: - case FLASH_CMD_RDSFDP: - case SPI_NOR_CMD_PP: - command->address.disabled = 0; - command->address.bus_width = SPIC_CFG_BUS_SINGLE; - command->data.bus_width = SPIC_CFG_BUS_SINGLE; - break; - case SPI_NOR_CMD_DREAD: - command->address.disabled = 0; - command->address.bus_width = SPIC_CFG_BUS_SINGLE; - command->data.bus_width = SPIC_CFG_BUS_DUAL; - break; - case SPI_NOR_CMD_QREAD: - command->address.disabled = 0; - command->address.bus_width = SPIC_CFG_BUS_SINGLE; - command->data.bus_width = SPIC_CFG_BUS_QUAD; - break; - case SPI_NOR_CMD_2READ: - command->address.disabled = 0; - command->address.bus_width = SPIC_CFG_BUS_DUAL; - command->data.bus_width = SPIC_CFG_BUS_DUAL; - break; - case SPI_NOR_CMD_4READ: - case SPI_NOR_CMD_PP_1_4_4: - command->address.disabled = 0; - command->address.bus_width = SPIC_CFG_BUS_QUAD; - command->data.bus_width = SPIC_CFG_BUS_QUAD; - break; - default: - ret = -EINVAL; - break; - } - - command->instruction.value = cmd; - command->address.size = addr_size; - command->address.value = addr; - command->dummy_count = dummy_count; - - return ret; -} - -static int spic_wait_finish(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - int count = TIMEOUT_SPICEN; - - while (spic_reg->SSIENR & SPIC_SSIENR_SPICEN && count) { - --count; - } - if (!count) { - return -ETIMEDOUT; - } - return 0; -} - -static inline void spic_flush_fifo(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - spic_reg->FLUSH = SPIC_FLUSH_ALL; -} - -static inline void spic_cs_active(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - spic_reg->SER = 1UL; -} - -static inline void spic_cs_deactivate(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - spic_reg->SER = 0UL; -} - -static inline void spic_usermode(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - spic_reg->CTRL0 |= SPIC_CTRL0_USERMD; -} - -static inline void spic_automode(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - spic_reg->CTRL0 &= ~SPIC_CTRL0_USERMD; -} - -static void spic_prepare_command(const struct device *dev, const struct qspi_cmd *command, - uint32_t tx_size, uint32_t rx_size, uint8_t write) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - uint8_t addr_len = user_addr_len[command->address.size]; - - spic_flush_fifo(dev); - - /* set SSIENR: deactivate to program this transfer */ - spic_reg->SSIENR = 0UL; - - /* set CTRLR0: TX mode and channel */ - spic_reg->CTRL0 &= ~(TMOD(3) | CMD_CH(3) | ADDR_CH(3) | DATA_CH(3)); - spic_reg->CTRL0 |= TMOD(write == 0x01 ? 0x00UL : 0x03UL) | - ADDR_CH(command->address.bus_width) | DATA_CH(command->data.bus_width); - - /* set USER_LENGTH */ - spic_reg->USERLENGTH = USER_CMD_LENGTH(1) | - USER_ADDR_LENGTH(command->address.disabled ? 0 : addr_len) | - USER_RD_DUMMY_LENGTH(command->dummy_count * spic_reg->BAUDR * 2); - - /* Write command */ - if (!command->instruction.disabled) { - spic_reg->DR.BYTE = command->instruction.value; - } - - /* Write address */ - if (!command->address.disabled) { - for (int i = 0; i < addr_len; i++) { - spic_reg->DR.BYTE = - (uint8_t)(command->address.value >> (8 * (addr_len - i - 1))); - } - } - - /* Set TX_NDF: frame number of Tx data */ - spic_reg->TXNDF = TX_NDF(tx_size); - - /* Set RX_NDF: frame number of receiving data. */ - spic_reg->RXNDF = RX_NDF(rx_size); -} - -static void spic_transmit_data(const struct device *dev, const void *data, uint32_t *length) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - uint32_t len = *length; - - /* set SSIENR to start the transfer */ - spic_reg->SSIENR = SPIC_SSIENR_SPICEN; - - /* write the remaining data into fifo */ - for (int i = 0; i < len;) { - if (spic_reg->SR & SPIC_SR_TFNF) { - spic_reg->DR.BYTE = ((const uint8_t *)data)[i]; - i++; - } - } -} - -static void spic_receive_data(const struct device *dev, void *data, uint32_t *length) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - - uint32_t i, cnt, rx_num, fifo, len; - uint8_t *rx_data = data; - - len = *length; - rx_data = data; - - /* set SSIENR to start the transfer */ - spic_reg->SSIENR = SPIC_SSIENR_SPICEN; - - rx_num = 0; - while (rx_num < len) { - cnt = spic_reg->RXFLR; - - for (i = 0; i < (cnt / 4); i++) { - fifo = spic_reg->DR.WORD; - memcpy((void *)(rx_data + rx_num), (void *)&fifo, 4); - rx_num += 4; - } - - if (rx_num < len) { - uint32_t remaining = (len - rx_num < cnt % 4) ? len - rx_num : cnt % 4; - - for (i = 0; i < remaining; i++) { - *(uint8_t *)(rx_data + rx_num) = spic_reg->DR.BYTE; - rx_num += 1; - } - } - } -} - -static int spic_write(const struct device *dev, const struct qspi_cmd *command, const void *data, - uint32_t *length) -{ - int ret; - - spic_usermode(dev); - spic_prepare_command(dev, command, *length, 0, COMMAND_WRITE); - spic_cs_active(dev); - - spic_transmit_data(dev, data, length); - ret = spic_wait_finish(dev); - - spic_cs_deactivate(dev); - spic_automode(dev); - - return ret; -} - -static int spic_read(const struct device *dev, const struct qspi_cmd *command, void *data, - size_t *length) -{ - int ret; - - spic_usermode(dev); - spic_prepare_command(dev, command, 0, *length, COMMAND_READ); - spic_cs_active(dev); - - spic_receive_data(dev, data, length); - ret = spic_wait_finish(dev); - - spic_cs_deactivate(dev); - spic_automode(dev); - - return ret; -} - -static int flash_write_enable(const struct device *dev) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - uint32_t len = 0; - - config_command(command, SPI_NOR_CMD_WREN, 0, 0, 0); - return spic_write(dev, command, NULL, &len); -} - -static int flash_write_disable(const struct device *dev) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - uint32_t len = 0; - - config_command(command, SPI_NOR_CMD_WRDI, 0, 0, 0); - return spic_write(dev, command, NULL, &len); -} - -static int flash_read_sr(const struct device *dev, uint8_t *val) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - int status; - uint32_t len = 1; - uint8_t sr; - - config_command(command, SPI_NOR_CMD_RDSR, 0, 0, 0); - status = spic_read(dev, command, &sr, &len); - if (status) { - return status; - } - *val = sr; - - return 0; -} - -#ifdef CONFIG_FLASH_EX_OP_ENABLED -static int flash_read_sr2(const struct device *dev, uint8_t *val) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - int status; - uint32_t len = 1; - uint8_t sr; - - config_command(command, SPI_NOR_CMD_RDSR2, 0, 0, 0); - status = spic_read(dev, command, &sr, &len); - if (status) { - return status; - } - *val = sr; - - return 0; -} -#endif - -static int flash_wait_till_ready(const struct device *dev) -{ - int ret; - int timeout = TIMEOUT_SPIBUSY; - uint8_t sr = 0; - - /* If it's a sector erase loop, it requires approximately 3000 cycles, - * while a program page requires about 40 cycles. - */ - do { - ret = flash_read_sr(dev, &sr); - if (ret < 0) { - return ret; - } - if (!(sr & SPI_NOR_WIP_BIT)) { - return 0; - } - timeout--; - } while (timeout > 0); - - LOG_ERR("Flash wait timed out"); - return -ETIMEDOUT; -} - -#ifdef CONFIG_FLASH_EX_OP_ENABLED -static int flash_write_status_reg(const struct device *dev, uint8_t *val, uint8_t cnt) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - int ret; - uint32_t len = cnt; - - ret = flash_write_enable(dev); - if (ret < 0) { - return ret; - } - - config_command(command, SPI_NOR_CMD_WRSR, 0, 0, 0); - ret = spic_write(dev, command, val, &len); - if (ret < 0) { - goto exit; - } - - ret = flash_wait_till_ready(dev); -exit: - flash_write_disable(dev); - return ret; -} - -static int flash_write_status_reg2(const struct device *dev, uint8_t *val, uint8_t cnt) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - int ret; - uint32_t len = cnt; - - ret = flash_write_enable(dev); - if (ret < 0) { - return ret; - } - - config_command(command, SPI_NOR_CMD_WRSR2, 0, 0, 0); - ret = spic_write(dev, command, val, &len); - if (ret < 0) { - goto exit; - } - - ret = flash_wait_till_ready(dev); -exit: - flash_write_disable(dev); - return ret; -} -#endif - -static int flash_erase_sector(const struct device *dev, uint32_t address) -{ - struct flash_rts5912_dev_data *data = dev->data; - struct qspi_cmd *command = &data->command_default; - enum spic_address_size addr_size = SPIC_CFG_ADDR_SIZE_24; - int ret; - uint32_t len = 0; - - ret = flash_write_enable(dev); - if (ret < 0) { - return ret; - } - - config_command(command, SPI_NOR_CMD_SE, address, addr_size, 0); - ret = spic_write(dev, command, NULL, &len); - if (ret < 0) { - goto err_exit; - } - ret = flash_wait_till_ready(dev); - -err_exit: - flash_write_disable(dev); - return ret; -} - -static int flash_program_page(const struct device *dev, uint32_t address, const uint8_t *data, - uint32_t size) -{ - struct flash_rts5912_dev_data *dev_data = dev->data; - struct qspi_cmd *command = &dev_data->command_default; - enum spic_address_size addr_size = SPIC_CFG_ADDR_SIZE_24; - int ret = 0; - uint32_t offset = 0, chunk = 0, page_size = FLASH_PAGE_SZ; - - while (size > 0) { - ret = flash_write_enable(dev); - if (ret < 0) { - return ret; - } - - offset = address % page_size; - chunk = (offset + size < page_size) ? size : (page_size - offset); - - config_command(command, SPI_NOR_CMD_PP, address, addr_size, 0); - ret = spic_write(dev, command, data, (size_t *)&chunk); - if (ret < 0) { - goto err_exit; - } - - data += chunk; - address += chunk; - size -= chunk; - - flash_wait_till_ready(dev); - } - -err_exit: - flash_write_disable(dev); - return ret; -} - -static int flash_normal_read(const struct device *dev, uint8_t rdcmd, uint32_t address, - uint8_t *data, uint32_t size) -{ - struct flash_rts5912_dev_data *dev_data = dev->data; - struct qspi_cmd *command = &dev_data->command_default; - enum spic_address_size addr_size = SPIC_CFG_ADDR_SIZE_24; - int ret; - - uint32_t src_addr = address; - uint8_t *dst_idx = data; - - uint32_t remind_size = size; - uint32_t block_size = 0x8000UL; - uint8_t dummy_count = (rdcmd == SPI_NOR_CMD_READ) ? 0 : 8; - - config_command(command, rdcmd, src_addr, addr_size, dummy_count); - - while (remind_size > 0) { - command->address.value = src_addr; - - if (remind_size >= block_size) { - ret = spic_read(dev, command, dst_idx, (size_t *)&block_size); - src_addr += block_size; - remind_size -= block_size; - dst_idx += block_size; - } else { - ret = spic_read(dev, command, dst_idx, (size_t *)&remind_size); - dst_idx += remind_size; - remind_size = 0; - } - - if (ret < 0) { - return ret; - } - } - - return 0; -} - -static int check_boundary(off_t offset, size_t len) -{ - if (offset < 0) { - return -EINVAL; - } - - if (offset >= DT_REG_SIZE(SOC_NV_FLASH_NODE)) { - return -EINVAL; - } - - if (len > DT_REG_SIZE(SOC_NV_FLASH_NODE) - offset) { - return -EINVAL; - } - - return 0; -} - -static int flash_rts5912_erase(const struct device *dev, off_t offset, size_t len) -{ - struct flash_rts5912_dev_data *data = dev->data; - int ret = -EINVAL; - - if (len == 0) { - return 0; - } - - if ((offset % FLASH_ERASE_BLK_SZ) != 0) { - return -EINVAL; - } - - if ((len % FLASH_ERASE_BLK_SZ) != 0) { - return -EINVAL; - } - - ret = check_boundary(offset, len); - if (ret < 0) { - return ret; - } - - k_sem_take(&data->sem, K_FOREVER); - - for (; len > 0; len -= FLASH_ERASE_BLK_SZ) { - ret = flash_erase_sector(dev, offset); - if (ret < 0) { - LOG_ERR("erase @0x%08lx fail", offset); - } - offset += FLASH_ERASE_BLK_SZ; - } - - k_sem_give(&data->sem); - - return ret; -} - -static int flash_rts5912_write(const struct device *dev, off_t offset, const void *data, size_t len) -{ - struct flash_rts5912_dev_data *dev_data = dev->data; - int ret; - unsigned int key; - - if (len == 0) { - return 0; - } - - ret = check_boundary(offset, len); - if (ret < 0) { - return ret; - } - - k_sem_take(&dev_data->sem, K_FOREVER); - key = irq_lock(); - ret = flash_program_page(dev, offset, data, len); - irq_unlock(key); - k_sem_give(&dev_data->sem); - - return ret; -} - -static int flash_rts5912_read(const struct device *dev, off_t offset, void *data, size_t len) -{ - struct flash_rts5912_dev_data *dev_data = dev->data; - int ret; - - if (len == 0) { - return 0; - } - - ret = check_boundary(offset, len); - if (ret < 0) { - return ret; - } - - k_sem_take(&dev_data->sem, K_FOREVER); - ret = flash_normal_read(dev, SPI_NOR_CMD_READ, offset, data, len); - k_sem_give(&dev_data->sem); - - return ret; -} - -static const struct flash_parameters *flash_rts5912_get_parameters(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - - return &config->flash_rts5912_parameters; -} - -#if defined(CONFIG_FLASH_PAGE_LAYOUT) -static const struct flash_pages_layout dev_layout = { - .pages_count = - DT_REG_SIZE(SOC_NV_FLASH_NODE) / DT_PROP(SOC_NV_FLASH_NODE, erase_block_size), - .pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size), -}; - -static void flash_rts5912_pages_layout(const struct device *dev, - const struct flash_pages_layout **layout, - size_t *layout_size) -{ - *layout = &dev_layout; - *layout_size = 1; -} -#endif /* CONFIG_FLASH_PAGE_LAYOUT */ - -#ifdef CONFIG_FLASH_EX_OP_ENABLED -static int flash_rts5912_ex_op(const struct device *dev, uint16_t opcode, const uintptr_t in, - void *out) -{ - struct flash_rts5912_dev_data *dev_data = dev->data; - int ret = -EINVAL; - - k_sem_take(&dev_data->sem, K_FOREVER); - - switch (opcode) { - case FLASH_RTS5912_EX_OP_WR_ENABLE: - ret = flash_write_enable(dev); - break; - case FLASH_RTS5912_EX_OP_WR_DISABLE: - ret = flash_write_disable(dev); - break; - case FLASH_RTS5912_EX_OP_WR_SR: - ret = flash_write_status_reg(dev, (uint8_t *)out, 1); - break; - case FLASH_RTS5912_EX_OP_WR_SR2: - ret = flash_write_status_reg2(dev, (uint8_t *)out, 1); - break; - case FLASH_RTS5912_EX_OP_RD_SR: - ret = flash_read_sr(dev, (uint8_t *)in); - break; - case FLASH_RTS5912_EX_OP_RD_SR2: - ret = flash_read_sr2(dev, (uint8_t *)in); - break; - } - - k_sem_give(&dev_data->sem); - - return ret; -} -#endif - -static DEVICE_API(flash, flash_rts5912_api) = { - .erase = flash_rts5912_erase, - .write = flash_rts5912_write, - .read = flash_rts5912_read, - .get_parameters = flash_rts5912_get_parameters, -#ifdef CONFIG_FLASH_PAGE_LAYOUT - .page_layout = flash_rts5912_pages_layout, -#endif -#ifdef CONFIG_FLASH_EX_OP_ENABLED - .ex_op = flash_rts5912_ex_op, -#endif -}; - -static int flash_rts5912_init(const struct device *dev) -{ - const struct flash_rts5912_dev_config *config = dev->config; - volatile struct reg_spic_reg *spic_reg = config->regs; - struct flash_rts5912_dev_data *data = dev->data; - - spic_reg->SSIENR = 0UL; - spic_reg->IMR = 0UL; - - spic_reg->CTRL0 = ((spic_reg->CTRL0 & SPIC_CTRL0_CK_MTIMES_Msk) | CMD_CH(0) | DATA_CH(0) | - ADDR_CH(0) | MODE(0) | ((spic_reg->CTRL0 & SPIC_CTRL0_SIPOL_Msk))); - - spic_reg->BAUDR = 1UL; - spic_reg->FBAUD = 1UL; - - k_sem_init(&data->sem, 1, 1); - - return 0; -} - -static struct flash_rts5912_dev_data flash_rts5912_data = { - .command_default = { - .instruction = { - .bus_width = SPIC_CFG_BUS_SINGLE, - .disabled = 0, - }, - .address = { - .bus_width = SPIC_CFG_BUS_SINGLE, - .size = SPIC_CFG_ADDR_SIZE_24, - .disabled = 0, - }, - .alt = { - .size = 0, - .disabled = 1, - }, - .dummy_count = 0, - .data = { - .bus_width = SPIC_CFG_BUS_SINGLE, - }, - }, -}; - -static const struct flash_rts5912_dev_config flash_rts5912_config = { - .regs = (volatile struct reg_spic_reg *)DT_INST_REG_ADDR(0), - .flash_rts5912_parameters = { - .write_block_size = FLASH_WRITE_BLK_SZ, - .erase_value = 0xff, - }, -}; - -DEVICE_DT_INST_DEFINE(0, flash_rts5912_init, NULL, &flash_rts5912_data, &flash_rts5912_config, - PRE_KERNEL_1, CONFIG_FLASH_INIT_PRIORITY, &flash_rts5912_api); diff --git a/drivers/flash/flash_stm32.c b/drivers/flash/flash_stm32.c index 6589a86bf1bbd..c07ccd9d056af 100644 --- a/drivers/flash/flash_stm32.c +++ b/drivers/flash/flash_stm32.c @@ -13,16 +13,12 @@ #define DT_DRV_COMPAT st_stm32_flash_controller #include -#if defined(CONFIG_SOC_SERIES_STM32H5X) -#include -#endif /* CONFIG_SOC_SERIES_STM32H5X */ #include #include #include #include #include #include -#include #include #include "flash_stm32.h" @@ -46,6 +42,8 @@ static const struct flash_parameters flash_stm32_parameters = { #endif }; +static int flash_stm32_cr_lock(const struct device *dev, bool enable); + bool __weak flash_stm32_valid_range(const struct device *dev, off_t offset, uint32_t len, bool write) { @@ -230,7 +228,7 @@ static int flash_stm32_write(const struct device *dev, off_t offset, return rc; } -int flash_stm32_cr_lock(const struct device *dev, bool enable) +static int flash_stm32_cr_lock(const struct device *dev, bool enable) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); @@ -290,6 +288,81 @@ int flash_stm32_cr_lock(const struct device *dev, bool enable) return rc; } +int flash_stm32_option_bytes_lock(const struct device *dev, bool enable) +{ + FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); + +#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */ + if (enable) { + regs->OPTCR |= FLASH_OPTCR_OPTLOCK; + } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { + regs->OPTKEYR = FLASH_OPT_KEY1; + regs->OPTKEYR = FLASH_OPT_KEY2; + } +#else + int rc; + + /* Unlock CR/PECR/NSCR register if needed. */ + if (!enable) { + rc = flash_stm32_cr_lock(dev, false); + if (rc) { + return rc; + } + } +#if defined(FLASH_CR_OPTWRE) /* F0, F1 and F3 */ + if (enable) { + regs->CR &= ~FLASH_CR_OPTWRE; + } else if (!(regs->CR & FLASH_CR_OPTWRE)) { + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; + } +#elif defined(FLASH_CR_OPTLOCK) /* G0, G4, L4, WB and WL */ + if (enable) { + regs->CR |= FLASH_CR_OPTLOCK; + } else if (regs->CR & FLASH_CR_OPTLOCK) { + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; + } +#elif defined(FLASH_PECR_OPTLOCK) /* L0 and L1 */ + if (enable) { + regs->PECR |= FLASH_PECR_OPTLOCK; + } else if (regs->PECR & FLASH_PECR_OPTLOCK) { + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; + } +#elif defined(FLASH_NSCR_OPTLOCK) /* L5 and U5 */ + if (enable) { + regs->NSCR |= FLASH_NSCR_OPTLOCK; + } else if (regs->NSCR & FLASH_NSCR_OPTLOCK) { + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; + } +#elif defined(FLASH_NSCR1_OPTLOCK) /* WBA */ + if (enable) { + regs->NSCR1 |= FLASH_NSCR1_OPTLOCK; + } else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) { + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; + } +#endif + /* Lock CR/PECR/NSCR register if needed. */ + if (enable) { + rc = flash_stm32_cr_lock(dev, true); + if (rc) { + return rc; + } + } +#endif + + if (enable) { + LOG_DBG("Option bytes locked"); + } else { + LOG_DBG("Option bytes unlocked"); + } + + return 0; +} + #if defined(CONFIG_FLASH_EX_OP_ENABLED) && defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS) int flash_stm32_control_register_disable(const struct device *dev) { @@ -358,29 +431,6 @@ flash_stm32_get_parameters(const struct device *dev) return &flash_stm32_parameters; } -/* Gives the total logical device size in bytes and return 0. */ -static int flash_stm32_get_size(const struct device *dev, uint64_t *size) -{ - ARG_UNUSED(dev); - -#if defined(CONFIG_SOC_SERIES_STM32H5X) - /* Disable the ICACHE to ensure all memory accesses are non-cacheable. - * This is required on STM32H5, where the manufacturing flash must be - * accessed in non-cacheable mode - otherwise, a bus error occurs. - */ - cache_instr_disable(); -#endif /* CONFIG_SOC_SERIES_STM32H5X */ - - *size = (uint64_t)LL_GetFlashSize() * 1024U; - -#if defined(CONFIG_SOC_SERIES_STM32H5X) - /* Re-enable the ICACHE (unconditonally - it should always be turned on) */ - cache_instr_enable(); -#endif /* CONFIG_SOC_SERIES_STM32H5X */ - - return 0; -} - static struct flash_stm32_priv flash_data = { .regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0), /* Getting clocks information from device tree description depending @@ -399,7 +449,6 @@ static DEVICE_API(flash, flash_stm32_api) = { .write = flash_stm32_write, .read = flash_stm32_read, .get_parameters = flash_stm32_get_parameters, - .get_size = flash_stm32_get_size, #ifdef CONFIG_FLASH_PAGE_LAYOUT .page_layout = flash_stm32_page_layout, #endif diff --git a/drivers/flash/flash_stm32.h b/drivers/flash/flash_stm32.h index dd63d5bc54388..3480f152b4cdf 100644 --- a/drivers/flash/flash_stm32.h +++ b/drivers/flash/flash_stm32.h @@ -71,9 +71,11 @@ struct flash_stm32_priv { #define FLASH_STM32_SR SR #endif + #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data)) #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs) + /* Redefinitions of flags and masks to harmonize stm32 series: */ #if defined(CONFIG_SOC_SERIES_STM32U5X) #define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK @@ -327,13 +329,13 @@ int flash_stm32_block_erase_loop(const struct device *dev, int flash_stm32_wait_flash_idle(const struct device *dev); +int flash_stm32_option_bytes_lock(const struct device *dev, bool enable); + uint32_t flash_stm32_option_bytes_read(const struct device *dev); int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask, uint32_t value); -int flash_stm32_cr_lock(const struct device *dev, bool enable); - #ifdef CONFIG_SOC_SERIES_STM32WBX int flash_stm32_check_status(const struct device *dev); #endif /* CONFIG_SOC_SERIES_STM32WBX */ diff --git a/drivers/flash/flash_stm32_ex_op.c b/drivers/flash/flash_stm32_ex_op.c index 2d5f754261624..a129e30b306f7 100644 --- a/drivers/flash/flash_stm32_ex_op.c +++ b/drivers/flash/flash_stm32_ex_op.c @@ -20,82 +20,6 @@ LOG_MODULE_REGISTER(flash_stm32_ex_op, CONFIG_FLASH_LOG_LEVEL); -int flash_stm32_option_bytes_lock(const struct device *dev, bool enable) -{ - FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); - -#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 or H7 */ - if (enable) { - regs->OPTCR |= FLASH_OPTCR_OPTLOCK; - } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { - regs->OPTKEYR = FLASH_OPT_KEY1; - regs->OPTKEYR = FLASH_OPT_KEY2; - } -#else - int rc; - - /* Unlock CR/PECR/NSCR register if needed. */ - if (!enable) { - rc = flash_stm32_cr_lock(dev, false); - if (rc) { - return rc; - } - } - -#if defined(FLASH_CR_OPTWRE) /* F0, F1 and F3 */ - if (enable) { - regs->CR &= ~FLASH_CR_OPTWRE; - } else if (!(regs->CR & FLASH_CR_OPTWRE)) { - regs->OPTKEYR = FLASH_OPTKEY1; - regs->OPTKEYR = FLASH_OPTKEY2; - } -#elif defined(FLASH_CR_OPTLOCK) /* G0, G4, L4, WB and WL */ - if (enable) { - regs->CR |= FLASH_CR_OPTLOCK; - } else if (regs->CR & FLASH_CR_OPTLOCK) { - regs->OPTKEYR = FLASH_OPTKEY1; - regs->OPTKEYR = FLASH_OPTKEY2; - } -#elif defined(FLASH_PECR_OPTLOCK) /* L0 and L1 */ - if (enable) { - regs->PECR |= FLASH_PECR_OPTLOCK; - } else if (regs->PECR & FLASH_PECR_OPTLOCK) { - regs->OPTKEYR = FLASH_OPTKEY1; - regs->OPTKEYR = FLASH_OPTKEY2; - } -#elif defined(FLASH_NSCR_OPTLOCK) /* L5 and U5 */ - if (enable) { - regs->NSCR |= FLASH_NSCR_OPTLOCK; - } else if (regs->NSCR & FLASH_NSCR_OPTLOCK) { - regs->OPTKEYR = FLASH_OPTKEY1; - regs->OPTKEYR = FLASH_OPTKEY2; - } -#elif defined(FLASH_NSCR1_OPTLOCK) /* WBA */ - if (enable) { - regs->NSCR1 |= FLASH_NSCR1_OPTLOCK; - } else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) { - regs->OPTKEYR = FLASH_OPTKEY1; - regs->OPTKEYR = FLASH_OPTKEY2; - } -#endif - /* Lock CR/PECR/NSCR register if needed. */ - if (enable) { - rc = flash_stm32_cr_lock(dev, true); - if (rc) { - return rc; - } - } -#endif - - if (enable) { - LOG_DBG("Option bytes locked"); - } else { - LOG_DBG("Option bytes unlocked"); - } - - return 0; -} - #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT) int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in, void *out) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index 6e90e19d3295b..3c9fe5e542a05 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -1845,49 +1845,6 @@ static int stm32_ospi_write_status_register(const struct device *dev, uint8_t re return ospi_write_access(dev, &s_command, regs_p, size); } -static int stm32_ospi_program_addr_4b(const struct device *dev, bool write_enable) -{ - uint8_t statReg; - struct flash_stm32_ospi_data *data = dev->data; - OSPI_HandleTypeDef *hospi = &data->hospi; - uint8_t nor_mode = OSPI_SPI_MODE; - uint8_t nor_rate = OSPI_STR_TRANSFER; - OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate); - - if (write_enable) { - if (stm32_ospi_write_enable(data, nor_mode, nor_rate) < 0) { - LOG_DBG("program_addr_4b failed to write_enable"); - return -EIO; - } - } - - /* Initialize the write enable command */ - s_command.Instruction = SPI_NOR_CMD_4BA; - if (nor_mode != OSPI_OPI_MODE) { - /* force 1-line InstructionMode for any non-OSPI transfer */ - s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; - } - s_command.AddressMode = HAL_OSPI_ADDRESS_NONE; - s_command.DataMode = HAL_OSPI_DATA_NONE; - s_command.DummyCycles = 0U; - - if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - LOG_DBG("OSPI Address Mode Change cmd failed"); - return -EIO; - } - - /* Check that ADS Bit in Status Reg 3 is now set indicating 4 Byte Address mode */ - if (stm32_ospi_read_status_register(dev, 3, &statReg)) { - LOG_DBG("Status reg read failed"); - return -EIO; - } - - if (statReg & 0x01) { - return 0; - } - return -EIO; -} - static int stm32_ospi_enable_qe(const struct device *dev) { struct flash_stm32_ospi_data *data = dev->data; @@ -2026,7 +1983,6 @@ static int spi_nor_process_bfp(const struct device *dev, const size_t flash_size = jesd216_bfp_density(bfp) / 8U; struct jesd216_instr read_instr = { 0 }; struct jesd216_bfp_dw15 dw15; - uint8_t addr_mode; if (flash_size != dev_cfg->flash_size) { LOG_DBG("Unexpected flash size: %u", flash_size); @@ -2046,29 +2002,8 @@ static int spi_nor_process_bfp(const struct device *dev, ++etp; } - addr_mode = jesd216_bfp_addrbytes(bfp); - spi_nor_process_bfp_addrbytes(dev, addr_mode); + spi_nor_process_bfp_addrbytes(dev, jesd216_bfp_addrbytes(bfp)); LOG_DBG("Address width: %u Bytes", data->address_width); - /* 4 Byte Address Mode has to be explicitly enabled for Winbond Flash */ - if (addr_mode == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B) { - struct jesd216_bfp_dw16 dw16; - - if (jesd216_bfp_decode_dw16(php, bfp, &dw16) == 0) { - /* - * According to JESD216, the bit0 of dw16.enter_4ba - * portion of flash description register 16 indicates - * if it is enough to use 0xB7 instruction without - * write enable to switch to 4 bytes addressing mode. - * If bit 1 is set, a write enable is needed. - */ - if (dw16.enter_4ba & 0x3) { - if (stm32_ospi_program_addr_4b(dev, dw16.enter_4ba & 2)) { - LOG_ERR("Unable to enter 4B mode."); - return -EIO; - } - } - } - } /* use PP opcode based on configured data mode if nothing is set in DTS */ if (data->write_opcode == SPI_NOR_WRITEOC_NONE) { diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c index aec6e99a57816..d1d7985473679 100644 --- a/drivers/flash/flash_stm32_qspi.c +++ b/drivers/flash/flash_stm32_qspi.c @@ -317,12 +317,11 @@ static int qspi_read_jedec_id(const struct device *dev, uint8_t *id) { struct flash_stm32_qspi_data *dev_data = dev->data; uint8_t data[JESD216_READ_ID_LEN]; - uint32_t dummy_cycles = DT_INST_PROP(0, st_read_id_dummy_cycles); QSPI_CommandTypeDef cmd = { .Instruction = JESD216_CMD_READ_ID, .AddressSize = QSPI_ADDRESS_NONE, - .DummyCycles = dummy_cycles, + .DummyCycles = 8, .InstructionMode = QSPI_INSTRUCTION_1_LINE, .AddressMode = QSPI_ADDRESS_1_LINE, .DataMode = QSPI_DATA_1_LINE, @@ -334,7 +333,7 @@ static int qspi_read_jedec_id(const struct device *dev, uint8_t *id) hal_ret = HAL_QSPI_Command_IT(&dev_data->hqspi, &cmd); if (hal_ret != HAL_OK) { - LOG_ERR("%d: Failed to send QSPI instruction", hal_ret); + LOG_ERR("%d: Failed to send OSPI instruction", hal_ret); return -EIO; } diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 78068413600e6..29b352dee6b48 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -37,11 +37,13 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); (_CONCAT(HAL_XSPIM_, DT_STRING_TOKEN(STM32_XSPI_NODE, prop))), \ ((default_value))) -/* Get the base address of the flash from the DTS st,stm32-xspi node */ -#define STM32_XSPI_BASE_ADDRESS DT_REG_ADDR_BY_IDX(STM32_XSPI_NODE, 1) +/* Get the base address of the flash from the DTS node */ +#define STM32_XSPI_BASE_ADDRESS DT_INST_REG_ADDR(0) #define STM32_XSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios) +#define STM32_XSPI_DLYB_BYPASSED DT_PROP(STM32_XSPI_NODE, dlyb_bypass) + #define STM32_XSPI_USE_DMA DT_NODE_HAS_PROP(STM32_XSPI_NODE, dmas) #if STM32_XSPI_USE_DMA @@ -50,11 +52,6 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #include #endif /* STM32_XSPI_USE_DMA */ -#if defined(CONFIG_SOC_SERIES_STM32H7RSX) -#include -#include -#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ - #include "flash_stm32_xspi.h" static inline void xspi_lock_thread(const struct device *dev) @@ -746,13 +743,6 @@ static int stm32_xspi_config_mem(const struct device *dev) return -EIO; } - if (stm32_xspi_read_cfg2reg(&dev_data->hxspi, - XSPI_OCTO_MODE, XSPI_DTR_TRANSFER, reg) != 0) { - /* Check the configuration has been correctly done on SPI_NOR_REG2_ADDR1 */ - LOG_ERR("XSPI flash config read failed"); - return -EIO; - } - LOG_INF("XSPI flash config is OCTO / DTR"); } @@ -856,7 +846,7 @@ static int stm32_xspi_set_memorymap(const struct device *dev) const struct flash_stm32_xspi_config *dev_cfg = dev->config; struct flash_stm32_xspi_data *dev_data = dev->data; XSPI_RegularCmdTypeDef s_command = {0}; /* Non-zero values disturb the command */ - XSPI_MemoryMappedTypeDef s_MemMappedCfg = {0}; + XSPI_MemoryMappedTypeDef s_MemMappedCfg; /* Configure octoflash in MemoryMapped mode */ if ((dev_cfg->data_mode == XSPI_SPI_MODE) && @@ -949,13 +939,6 @@ static int stm32_xspi_set_memorymap(const struct device *dev) /* Enable the memory-mapping */ s_MemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE; -#ifdef XSPI_CR_NOPREF - s_MemMappedCfg.NoPrefetchData = HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE; -#ifdef XSPI_CR_NOPREF_AXI - s_MemMappedCfg.NoPrefetchAXI = HAL_XSPI_AXI_PREFETCH_DISABLE; -#endif /* XSPI_CR_NOPREF_AXI */ -#endif /* XSPI_CR_NOPREF */ - ret = HAL_XSPI_MemoryMapped(&dev_data->hxspi, &s_MemMappedCfg); if (ret != HAL_OK) { LOG_ERR("%d: Failed to enable memory mapped", ret); @@ -2048,19 +2031,12 @@ static int flash_stm32_xspi_init(const struct device *dev) } #ifdef CONFIG_STM32_MEMMAP - /* If MemoryMapped then configure skip init - * Check clock status first as reading CR register without bus clock doesn't work on N6 - * If clock is off, then MemoryMapped is off too and we do init - */ - if (clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken) - == CLOCK_CONTROL_STATUS_ON) { - if (stm32_xspi_is_memorymap(dev)) { - LOG_ERR("NOR init'd in MemMapped mode"); - /* Force HAL instance in correct state */ - dev_data->hxspi.State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; - return 0; - } + /* If MemoryMapped then configure skip init */ + if (stm32_xspi_is_memorymap(dev)) { + LOG_DBG("NOR init'd in MemMapped mode"); + /* Force HAL instance in correct state */ + dev_data->hxspi.State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; + return 0; } #endif /* CONFIG_STM32_MEMMAP */ @@ -2071,11 +2047,6 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_ERR("XSPI mode SPI|DUAL|QUAD/DTR is not valid"); return -ENOTSUP; } -#if defined(CONFIG_SOC_SERIES_STM32H7RSX) - LL_PWR_EnableXSPIM2(); - __HAL_RCC_SBS_CLK_ENABLE(); - LL_SBS_EnableXSPI2SpeedOptim(); -#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ /* Signals configuration */ ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); @@ -2084,44 +2055,53 @@ static int flash_stm32_xspi_init(const struct device *dev) return ret; } + if (dev_cfg->pclk_len > 3) { + /* Max 3 domain clock are expected */ + LOG_ERR("Could not select %d XSPI domain clock", dev_cfg->pclk_len); + return -EIO; + } + /* Clock configuration */ if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken) != 0) { + (clock_control_subsys_t) &dev_cfg->pclken[0]) != 0) { LOG_ERR("Could not enable XSPI clock"); return -EIO; } if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken, + (clock_control_subsys_t) &dev_cfg->pclken[0], &ahb_clock_freq) < 0) { LOG_ERR("Failed call clock_control_get_rate(pclken)"); return -EIO; } - -#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) - /* Kernel clock config for peripheral if any */ - if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken_ker, - NULL) != 0) { - LOG_ERR("Could not select XSPI domain clock"); - return -EIO; - } - - if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken_ker, - &ahb_clock_freq) < 0) { - LOG_ERR("Failed call clock_control_get_rate(pclken_ker)"); - return -EIO; + /* Alternate clock config for peripheral if any */ + if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 1)) { + if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken[1], + NULL) != 0) { + LOG_ERR("Could not select XSPI domain clock"); + return -EIO; + } + /* + * Get the clock rate from this one (update ahb_clock_freq) + * TODO: retrieve index in the clocks property where clocks has "xspi-ker" + * Assuming index is 1 + */ + if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken[1], + &ahb_clock_freq) < 0) { + LOG_ERR("Failed call clock_control_get_rate(pclken)"); + return -EIO; + } } -#endif /* xspi_ker */ - -#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) /* Clock domain corresponding to the IO-Mgr (XSPIM) */ - if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) { - LOG_ERR("Could not enable XSPI Manager clock"); - return -EIO; + if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 2)) { + if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken[2]) != 0) { + LOG_ERR("Could not enable XSPI Manager clock"); + return -EIO; + } + /* Do NOT Get the clock rate from this one */ } -#endif /* xspi_mgr */ for (; prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX; prescaler++) { uint32_t clk = STM32_XSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler); @@ -2130,11 +2110,8 @@ static int flash_stm32_xspi_init(const struct device *dev) break; } } - - if (prescaler > STM32_XSPI_CLOCK_PRESCALER_MAX) { - LOG_ERR("XSPI could not find valid prescaler value"); - return -EINVAL; - } + __ASSERT_NO_MSG(prescaler >= STM32_XSPI_CLOCK_PRESCALER_MIN && + prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX); /* Initialize XSPI HAL structure completely */ dev_data->hxspi.Init.ClockPrescaler = prescaler; @@ -2147,7 +2124,17 @@ static int flash_stm32_xspi_init(const struct device *dev) if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) { dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; + } else { + } +#if defined(XSPI_DCR1_DLYBYP) +#if STM32_XSPI_DLYB_BYPASSED + dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS; +#else + dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON; +#endif /* STM32_XSPI_DLYB_BYPASSED */ +#endif /* XSPI_DCR1_DLYBYP */ + if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) { LOG_ERR("XSPI Init failed"); @@ -2156,8 +2143,7 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_DBG("XSPI Init'd"); -#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) || \ - defined(XSPIM) || defined(XSPIM1) || defined(XSPIM2) +#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) /* XSPI I/O manager init Function */ XSPIM_CfgTypeDef xspi_mgr_cfg; @@ -2177,7 +2163,7 @@ static int flash_stm32_xspi_init(const struct device *dev) #endif /* XSPIM */ -#if defined(XSPI_DCR1_DLYBYP) +#if defined(DLYB_XSPI1) || defined(DLYB_XSPI2) || defined(DLYB_OCTOSPI1) || defined(DLYB_OCTOSPI2) /* XSPI delay block init Function */ HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0}; @@ -2191,7 +2177,7 @@ static int flash_stm32_xspi_init(const struct device *dev) } LOG_DBG("Delay Block Init"); -#endif /* XSPI_DCR1_DLYBYP */ +#endif /* DLYB_ */ #if STM32_XSPI_USE_DMA /* Configure and enable the DMA channels after XSPI config */ @@ -2419,27 +2405,15 @@ static int flash_stm32_xspi_init(const struct device *dev) static void flash_stm32_xspi_irq_config_func(const struct device *dev); +static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(STM32_XSPI_NODE); + PINCTRL_DT_DEFINE(STM32_XSPI_NODE); static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = { - .pclken = { - .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bus), - .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bits) - }, -#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) - .pclken_ker = { - .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bus), - .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bits) - }, -#endif /* xspi_ker */ -#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) - .pclken_mgr = { - .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus), - .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits) - }, -#endif /* xspi_mgr */ + .pclken = pclken, + .pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE), .irq_config = flash_stm32_xspi_irq_config_func, - .flash_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ + .flash_size = DT_INST_REG_SIZE(0), .max_frequency = DT_INST_PROP(0, ospi_max_frequency), .data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */ .data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */ @@ -2470,17 +2444,9 @@ static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = { : HAL_XSPI_CSSEL_NCS2), #endif .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE, -#if defined(XSPI_DCR1_DLYBYP) - .DelayBlockBypass = (DT_PROP(STM32_XSPI_NODE, dlyb_bypass) - ? HAL_XSPI_DELAY_BLOCK_BYPASS - : HAL_XSPI_DELAY_BLOCK_ON), -#endif /* XSPI_DCR1_DLYBYP */ -#if defined(XSPI_DCR3_MAXTRAN) - .MaxTran = 0, -#endif /* XSPI_DCR3_MAXTRAN */ -#if defined(XSPI_DCR4_REFRESH) +#if defined(OCTOSPI_DCR4_REFRESH) .Refresh = 0, -#endif /* XSPI_DCR4_REFRESH */ +#endif /* OCTOSPI_DCR4_REFRESH */ }, }, .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6), diff --git a/drivers/flash/flash_stm32_xspi.h b/drivers/flash/flash_stm32_xspi.h index 3c1c149e0b2d8..316efdbcd8788 100644 --- a/drivers/flash/flash_stm32_xspi.h +++ b/drivers/flash/flash_stm32_xspi.h @@ -67,9 +67,8 @@ struct stream { typedef void (*irq_config_func_t)(const struct device *dev); struct flash_stm32_xspi_config { - const struct stm32_pclken pclken; - const struct stm32_pclken pclken_ker; - const struct stm32_pclken pclken_mgr; + const struct stm32_pclken *pclken; + size_t pclk_len; irq_config_func_t irq_config; size_t flash_size; uint32_t max_frequency; diff --git a/drivers/flash/flash_stm32g4x.c b/drivers/flash/flash_stm32g4x.c index 3c26874b1a9ce..bdb0da182a138 100644 --- a/drivers/flash/flash_stm32g4x.c +++ b/drivers/flash/flash_stm32g4x.c @@ -246,7 +246,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset, int i, rc = 0; for (i = 0; i < len; i += 8, offset += 8) { - rc = write_dword(dev, offset, UNALIGNED_GET((const uint64_t *) data + (i>>3))); + rc = write_dword(dev, offset, ((const uint64_t *) data)[i>>3]); if (rc < 0) { return rc; } diff --git a/drivers/flash/flash_stm32h7x.c b/drivers/flash/flash_stm32h7x.c index 8e2ac53ab655e..3873e9e13753c 100644 --- a/drivers/flash/flash_stm32h7x.c +++ b/drivers/flash/flash_stm32h7x.c @@ -309,6 +309,31 @@ int flash_stm32_option_bytes_disable(const struct device *dev) } #endif /* CONFIG_FLASH_STM32_BLOCK_REGISTERS */ +int flash_stm32_option_bytes_lock(const struct device *dev, bool enable) +{ + FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); + + if (enable) { + regs->OPTCR |= FLASH_OPTCR_OPTLOCK; + } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { +#ifdef CONFIG_SOC_SERIES_STM32H7RSX + regs->OPTKEYR = FLASH_OPTKEY1; + regs->OPTKEYR = FLASH_OPTKEY2; +#else + regs->OPTKEYR = FLASH_OPT_KEY1; + regs->OPTKEYR = FLASH_OPT_KEY2; +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ + } + + if (enable) { + LOG_DBG("Option bytes locked"); + } else { + LOG_DBG("Option bytes unlocked"); + } + + return 0; +} + bool flash_stm32_valid_range(const struct device *dev, off_t offset, uint32_t len, bool write) { #if defined(DUAL_BANK) @@ -836,18 +861,6 @@ static const struct flash_parameters *flash_stm32h7_get_parameters(const struct return &flash_stm32h7_parameters; } -#ifndef CONFIG_SOC_SERIES_STM32H7RSX -/* Gives the total logical device size in bytes and return 0. */ -static int flash_stm32h7_get_size(const struct device *dev, uint64_t *size) -{ - ARG_UNUSED(dev); - - *size = (uint64_t)LL_GetFlashSize() * 1024U; - - return 0; -} -#endif /* !CONFIG_SOC_SERIES_STM32H7RSX */ - void flash_stm32_page_layout(const struct device *dev, const struct flash_pages_layout **layout, size_t *layout_size) { @@ -905,9 +918,6 @@ static DEVICE_API(flash, flash_stm32h7_api) = { .write = flash_stm32h7_write, .read = flash_stm32h7_read, .get_parameters = flash_stm32h7_get_parameters, -#ifndef CONFIG_SOC_SERIES_STM32H7RSX - .get_size = flash_stm32h7_get_size, -#endif #ifdef CONFIG_FLASH_PAGE_LAYOUT .page_layout = flash_stm32_page_layout, #endif diff --git a/drivers/flash/flash_stm32wb0x.c b/drivers/flash/flash_stm32wb0x.c index a2d4287a0e02b..bfa2286adf27f 100644 --- a/drivers/flash/flash_stm32wb0x.c +++ b/drivers/flash/flash_stm32wb0x.c @@ -22,7 +22,6 @@ #include #include #include -#include #include LOG_MODULE_REGISTER(flash_stm32wb0x, CONFIG_FLASH_LOG_LEVEL); @@ -401,8 +400,6 @@ int flash_wb0x_erase(const struct device *dev, off_t offset, size_t size) const struct flash_parameters *flash_wb0x_get_parameters( const struct device *dev) { - ARG_UNUSED(dev); - static const struct flash_parameters fp = { .write_block_size = WRITE_BLOCK_SIZE, .erase_value = 0xff, @@ -411,16 +408,6 @@ const struct flash_parameters *flash_wb0x_get_parameters( return &fp; } -/* Gives the total logical device size in bytes and return 0. */ -static int flash_wb0x_get_size(const struct device *dev, uint64_t *size) -{ - ARG_UNUSED(dev); - - *size = (uint64_t)LL_GetFlashSize() * 1024U; - - return 0; -} - #if defined(CONFIG_FLASH_PAGE_LAYOUT) void flash_wb0x_pages_layout(const struct device *dev, const struct flash_pages_layout **layout, @@ -445,7 +432,6 @@ static DEVICE_API(flash, flash_wb0x_api) = { .write = flash_wb0x_write, .read = flash_wb0x_read, .get_parameters = flash_wb0x_get_parameters, - .get_size = flash_wb0x_get_size, #ifdef CONFIG_FLASH_PAGE_LAYOUT .page_layout = flash_wb0x_pages_layout, #endif diff --git a/drivers/flash/flash_stm32wba_fm.c b/drivers/flash/flash_stm32wba_fm.c index c842c95ff7a7b..8ebf1a35bd9bc 100644 --- a/drivers/flash/flash_stm32wba_fm.c +++ b/drivers/flash/flash_stm32wba_fm.c @@ -18,8 +18,6 @@ LOG_MODULE_REGISTER(flash_stm32wba, CONFIG_FLASH_LOG_LEVEL); #include "flash_manager.h" #include "flash_driver.h" -#include - /* Let's wait for double the max erase time to be sure that the operation is * completed. */ @@ -165,16 +163,6 @@ static const struct flash_parameters * return &flash_stm32_parameters; } -/* Gives the total logical device size in bytes and return 0. */ -static int flash_stm32h7_get_size(const struct device *dev, uint64_t *size) -{ - ARG_UNUSED(dev); - - *size = (uint64_t)LL_GetFlashSize() * 1024U; - - return 0; -} - static struct flash_stm32_priv flash_data = { .regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0), }; @@ -204,7 +192,6 @@ static DEVICE_API(flash, flash_stm32_api) = { .write = flash_stm32_write, .read = flash_stm32_read, .get_parameters = flash_stm32_get_parameters, - .get_size = flash_stm32_get_size, #ifdef CONFIG_FLASH_PAGE_LAYOUT .page_layout = flash_stm32wba_page_layout, #endif diff --git a/drivers/flash/soc_flash_cc23x0.c b/drivers/flash/soc_flash_cc23x0.c index 91b5a8590fe97..dbcbad776ae57 100644 --- a/drivers/flash/soc_flash_cc23x0.c +++ b/drivers/flash/soc_flash_cc23x0.c @@ -12,6 +12,7 @@ #include #include +#include #define DT_DRV_COMPAT ti_cc23x0_flash_controller #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) @@ -39,9 +40,44 @@ static int flash_cc23x0_init(const struct device *dev) return 0; } +static void flash_cc23x0_cache_restore(uint32_t vims_mode) +{ + while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) { + ; + } + + /* Restore VIMS mode and line buffers */ + if (vims_mode != VIMS_MODE_DISABLED) { + VIMSModeSafeSet(VIMS_BASE, vims_mode, true); + } + + VIMSLineBufEnable(VIMS_BASE); +} + +static uint32_t flash_cc23x0_cache_disable(void) +{ + uint32_t vims_mode; + + /* VIMS and both line buffers should be off during flash update */ + VIMSLineBufDisable(VIMS_BASE); + + while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) { + ; + } + + /* Save current VIMS mode for restoring it later */ + vims_mode = VIMSModeGet(VIMS_BASE); + if (vims_mode != VIMS_MODE_DISABLED) { + VIMSModeSafeSet(VIMS_BASE, VIMS_MODE_DISABLED, true); + } + + return vims_mode; +} + static int flash_cc23x0_erase(const struct device *dev, off_t offs, size_t size) { struct flash_cc23x0_data *data = dev->data; + uint32_t vims_mode; unsigned int key; int i; int rc = 0; @@ -60,6 +96,7 @@ static int flash_cc23x0_erase(const struct device *dev, off_t offs, size_t size) return -EACCES; } + vims_mode = flash_cc23x0_cache_disable(); /* * Disable all interrupts to prevent flash read, from TI's TRF: * @@ -84,6 +121,8 @@ static int flash_cc23x0_erase(const struct device *dev, off_t offs, size_t size) irq_unlock(key); + flash_cc23x0_cache_restore(vims_mode); + k_sem_give(&data->mutex); return rc; } @@ -91,6 +130,7 @@ static int flash_cc23x0_erase(const struct device *dev, off_t offs, size_t size) static int flash_cc23x0_write(const struct device *dev, off_t offs, const void *data, size_t size) { struct flash_cc23x0_data *flash_data = dev->data; + uint32_t vims_mode; unsigned int key; int rc = 0; @@ -119,6 +159,8 @@ static int flash_cc23x0_write(const struct device *dev, off_t offs, const void * return -EACCES; } + vims_mode = flash_cc23x0_cache_disable(); + key = irq_lock(); while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) { @@ -132,6 +174,8 @@ static int flash_cc23x0_write(const struct device *dev, off_t offs, const void * irq_unlock(key); + flash_cc23x0_cache_restore(vims_mode); + k_sem_give(&flash_data->mutex); return rc; diff --git a/drivers/flash/soc_flash_nios2_qspi.c b/drivers/flash/soc_flash_nios2_qspi.c new file mode 100644 index 0000000000000..b68a67081c0e8 --- /dev/null +++ b/drivers/flash/soc_flash_nios2_qspi.c @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This driver is written based on the Altera's + * Nios-II QSPI Controller HAL driver. + */ + +#define DT_DRV_COMPAT altr_nios2_qspi_nor + +#include +#include +#include +#include +#include +#include +#include +#include +#include "flash_priv.h" +#include "altera_generic_quad_spi_controller2_regs.h" +#include "altera_generic_quad_spi_controller2.h" + +#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL +#include +LOG_MODULE_REGISTER(flash_nios2_qspi); + +/* + * Remove the following macros once the Altera HAL + * supports the QSPI Controller v2 IP. + */ +#define ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG 0x0000001C +#define FLAG_STATUS_PROTECTION_ERROR (1 << 1) +#define FLAG_STATUS_PROGRAM_SUSPENDED (1 << 2) +#define FLAG_STATUS_PROGRAM_ERROR (1 << 4) +#define FLAG_STATUS_ERASE_ERROR (1 << 5) +#define FLAG_STATUS_ERASE_SUSPENDED (1 << 6) +#define FLAG_STATUS_CONTROLLER_READY (1 << 7) + +/* ALTERA_QSPI_CONTROLLER2_STATUS_REG bits */ +#define STATUS_PROTECTION_POS 2 +#define STATUS_PROTECTION_MASK 0x1F +#define STATUS_PROTECTION_EN_VAL 0x17 +#define STATUS_PROTECTION_DIS_VAL 0x0 + +/* ALTERA_QSPI_CONTROLLER2_MEM_OP_REG bits */ +#define MEM_OP_ERASE_CMD 0x00000002 +#define MEM_OP_WRITE_EN_CMD 0x00000004 +#define MEM_OP_SECTOR_OFFSET_BIT_POS 8 +#define MEM_OP_UNLOCK_ALL_SECTORS 0x00000003 +#define MEM_OP_LOCK_ALL_SECTORS 0x00000F03 + +#define NIOS2_QSPI_BLANK_WORD 0xFFFFFFFF + +#define NIOS2_WRITE_BLOCK_SIZE 4 + +#define USEC_TO_MSEC(x) (x / 1000) + +struct flash_nios2_qspi_config { + alt_qspi_controller2_dev qspi_dev; + struct k_sem sem_lock; +}; + +static const struct flash_parameters flash_nios2_qspi_parameters = { + .write_block_size = NIOS2_WRITE_BLOCK_SIZE, + .erase_value = 0xff, +}; + +static int flash_nios2_qspi_write_protection(const struct device *dev, + bool enable); + +static int flash_nios2_qspi_erase(const struct device *dev, off_t offset, + size_t len) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; + uint32_t block_offset, offset_in_block, length_to_erase; + uint32_t erase_offset = offset; /* address of next byte to erase */ + uint32_t remaining_length = len; /* length of data left to be erased */ + uint32_t flag_status; + int32_t rc = 0, i, timeout, rc2; + + k_sem_take(&flash_cfg->sem_lock, K_FOREVER); + + rc = flash_nios2_qspi_write_protection(dev, false); + if (rc) { + goto qspi_erase_err; + } + /* + * check if offset is word aligned and + * length is with in the range + */ + if (((offset + len) > qspi_dev->data_end) || + (0 != (erase_offset & + (NIOS2_WRITE_BLOCK_SIZE - 1)))) { + LOG_ERR("erase failed at offset 0x%lx", (long)offset); + rc = -EINVAL; + goto qspi_erase_err; + } + + for (i = offset/qspi_dev->sector_size; + i < qspi_dev->number_of_sectors; i++) { + + if ((remaining_length <= 0U) || + erase_offset >= (offset + len)) { + break; + } + + block_offset = 0U; /* block offset in byte addressing */ + offset_in_block = 0U; /* offset into current sector to erase */ + length_to_erase = 0U; /* length to erase in current sector */ + + /* calculate current sector/block offset in byte addressing */ + block_offset = erase_offset & ~(qspi_dev->sector_size - 1); + + /* calculate offset into sector/block if there is one */ + if (block_offset != erase_offset) { + offset_in_block = erase_offset - block_offset; + } + + /* calculate the byte size of data to be written in a sector */ + length_to_erase = MIN(qspi_dev->sector_size - offset_in_block, + remaining_length); + + /* Erase sector */ + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + MEM_OP_WRITE_EN_CMD); + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + (i << MEM_OP_SECTOR_OFFSET_BIT_POS) + | MEM_OP_ERASE_CMD); + + /* + * poll the status register to know the + * completion of the erase operation. + */ + timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE; + while (timeout > 0) { + /* wait for 1 usec */ + k_busy_wait(1); + + flag_status = IORD_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG); + + if (flag_status & FLAG_STATUS_CONTROLLER_READY) { + break; + } + + timeout--; + } + + if ((flag_status & FLAG_STATUS_ERASE_ERROR) || + (flag_status & FLAG_STATUS_PROTECTION_ERROR)) { + LOG_ERR("erase failed, Flag Status Reg:0x%x", + flag_status); + rc = -EIO; + goto qspi_erase_err; + } + + /* update remaining length and erase_offset */ + remaining_length -= length_to_erase; + erase_offset += length_to_erase; + } + +qspi_erase_err: + rc2 = flash_nios2_qspi_write_protection(dev, true); + + if (!rc) { + rc = rc2; + } + + k_sem_give(&flash_cfg->sem_lock); + return rc; + +} + +static int flash_nios2_qspi_write_block(const struct device *dev, + int block_offset, + int mem_offset, const void *data, + size_t len) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; + uint32_t buffer_offset = 0U; /* offset into data buffer to get write data */ + int32_t remaining_length = len; /* length left to write */ + uint32_t write_offset = mem_offset; /* offset into flash to write too */ + uint32_t word_to_write, padding, bytes_to_copy; + uint32_t flag_status; + int32_t rc = 0; + + while (remaining_length > 0) { + /* initialize word to write to blank word */ + word_to_write = NIOS2_QSPI_BLANK_WORD; + + /* bytes to pad the next word that is written */ + padding = 0U; + + /* number of bytes from source to copy */ + bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE; + + /* + * we need to make sure the write is word aligned + * this should only be true at most 1 time + */ + if (0 != (write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1))) { + /* + * data is not word aligned calculate padding bytes + * need to add before start of a data offset + */ + padding = write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1); + + /* + * update variables to account + * for padding being added + */ + bytes_to_copy -= padding; + + if (bytes_to_copy > remaining_length) { + bytes_to_copy = remaining_length; + } + + write_offset = write_offset - padding; + + if (0 != (write_offset & + (NIOS2_WRITE_BLOCK_SIZE - 1))) { + rc = -EINVAL; + goto qspi_write_block_err; + } + } else { + if (bytes_to_copy > remaining_length) { + bytes_to_copy = remaining_length; + } + } + + /* Check memcpy length is within NIOS2_WRITE_BLOCK_SIZE */ + if (padding + bytes_to_copy > NIOS2_WRITE_BLOCK_SIZE) { + rc = -EINVAL; + goto qspi_write_block_err; + } + + /* prepare the word to be written */ + memcpy((uint8_t *)&word_to_write + padding, + (const uint8_t *)data + buffer_offset, + bytes_to_copy); + + /* enable write */ + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + MEM_OP_WRITE_EN_CMD); + + /* write to flash 32 bits at a time */ + IOWR_32DIRECT(qspi_dev->data_base, write_offset, word_to_write); + + /* check whether write operation is successful */ + flag_status = IORD_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG); + + if ((flag_status & FLAG_STATUS_PROGRAM_ERROR) || + (flag_status & FLAG_STATUS_PROTECTION_ERROR)) { + LOG_ERR("write failed, Flag Status Reg:0x%x", + flag_status); + rc = -EIO; /* sector might be protected */ + goto qspi_write_block_err; + } + + /* update offset and length variables */ + buffer_offset += bytes_to_copy; + remaining_length -= bytes_to_copy; + write_offset = write_offset + NIOS2_WRITE_BLOCK_SIZE; + } + +qspi_write_block_err: + return rc; +} + +static int flash_nios2_qspi_write(const struct device *dev, off_t offset, + const void *data, size_t len) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; + uint32_t block_offset, offset_in_block, length_to_write; + uint32_t write_offset = offset; /* address of next byte to write */ + uint32_t buffer_offset = 0U; /* offset into source buffer */ + uint32_t remaining_length = len; /* length of data left to be written */ + int32_t rc = 0, i, rc2; + + k_sem_take(&flash_cfg->sem_lock, K_FOREVER); + + rc = flash_nios2_qspi_write_protection(dev, false); + if (rc) { + goto qspi_write_err; + } + /* + * check if offset is word aligned and + * length is with in the range + */ + if ((data == NULL) || ((offset + len) > qspi_dev->data_end) || + (0 != (write_offset & + (NIOS2_WRITE_BLOCK_SIZE - 1)))) { + LOG_ERR("write failed at offset 0x%lx", (long)offset); + rc = -EINVAL; + goto qspi_write_err; + } + + for (i = offset/qspi_dev->sector_size; + i < qspi_dev->number_of_sectors; i++) { + + if (remaining_length <= 0U) { + break; + } + + block_offset = 0U; /* block offset in byte addressing */ + offset_in_block = 0U; /* offset into current sector to write */ + length_to_write = 0U; /* length to write to current sector */ + + /* calculate current sector/block offset in byte addressing */ + block_offset = write_offset & ~(qspi_dev->sector_size - 1); + + /* calculate offset into sector/block if there is one */ + if (block_offset != write_offset) { + offset_in_block = write_offset - block_offset; + } + + /* calculate the byte size of data to be written in a sector */ + length_to_write = MIN(qspi_dev->sector_size - offset_in_block, + remaining_length); + + rc = flash_nios2_qspi_write_block(dev, + block_offset, write_offset, + (const uint8_t *)data + buffer_offset, + length_to_write); + if (rc < 0) { + goto qspi_write_err; + } + + /* update remaining length and buffer_offset */ + remaining_length -= length_to_write; + buffer_offset += length_to_write; + write_offset += length_to_write; + } + +qspi_write_err: + rc2 = flash_nios2_qspi_write_protection(dev, true); + + if (!rc) { + rc = rc2; + } + + k_sem_give(&flash_cfg->sem_lock); + return rc; +} + +static int flash_nios2_qspi_read(const struct device *dev, off_t offset, + void *data, size_t len) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; + uint32_t buffer_offset = 0U; /* offset into data buffer to get read data */ + uint32_t remaining_length = len; /* length left to read */ + uint32_t read_offset = offset; /* offset into flash to read from */ + uint32_t word_to_read, bytes_to_copy; + int32_t rc = 0; + + /* + * check if offset and length are within the range + */ + if ((data == NULL) || (offset < qspi_dev->data_base) || + ((offset + len) > qspi_dev->data_end)) { + LOG_ERR("read failed at offset 0x%lx", (long)offset); + return -EINVAL; + } + + if (!len) { + return 0; + } + + k_sem_take(&flash_cfg->sem_lock, K_FOREVER); + + /* first unaligned start */ + read_offset &= ~(NIOS2_WRITE_BLOCK_SIZE - 1U); + if (offset > read_offset) { + /* number of bytes from source to copy */ + bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE - (offset - read_offset); + if (bytes_to_copy > remaining_length) { + bytes_to_copy = remaining_length; + } + /* read from flash 32 bits at a time */ + word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset); + memcpy((uint8_t *)data, (uint8_t *)&word_to_read + offset - + read_offset, bytes_to_copy); + /* update offset and length variables */ + read_offset += NIOS2_WRITE_BLOCK_SIZE; + buffer_offset += bytes_to_copy; + remaining_length -= bytes_to_copy; + } + + /* aligned part, including unaligned end */ + while (remaining_length > 0) { + /* number of bytes from source to copy */ + bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE; + + if (bytes_to_copy > remaining_length) { + bytes_to_copy = remaining_length; + } + + /* read from flash 32 bits at a time */ + word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset); + memcpy((uint8_t *)data + buffer_offset, &word_to_read, + bytes_to_copy); + /* update offset and length variables */ + read_offset += bytes_to_copy; + buffer_offset += bytes_to_copy; + remaining_length -= bytes_to_copy; + } + + k_sem_give(&flash_cfg->sem_lock); + return rc; +} + +static int flash_nios2_qspi_write_protection(const struct device *dev, + bool enable) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; + uint32_t status, lock_val; + int32_t rc = 0, timeout; + + /* set write enable */ + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + MEM_OP_WRITE_EN_CMD); + if (enable) { + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + MEM_OP_LOCK_ALL_SECTORS); + lock_val = STATUS_PROTECTION_EN_VAL; + } else { + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_MEM_OP_REG, + MEM_OP_UNLOCK_ALL_SECTORS); + lock_val = STATUS_PROTECTION_DIS_VAL; + } + + /* + * poll the status register to know the + * completion of the erase operation. + */ + timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE; + while (timeout > 0) { + /* wait for 1 usec */ + k_busy_wait(1); + + /* + * read flash flag status register before + * checking the QSPI status + */ + IORD_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG); + + /* read QPSI status register */ + status = IORD_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_STATUS_REG); + if (((status >> STATUS_PROTECTION_POS) & + STATUS_PROTECTION_MASK) == lock_val) { + break; + } + + timeout--; + } + + if (timeout <= 0) { + LOG_ERR("locking failed, status-reg 0x%x", status); + rc = -EIO; + } + + /* clear flag status register */ + IOWR_32DIRECT(qspi_dev->csr_base, + ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG, 0x0); + return rc; +} + +static const struct flash_parameters * +flash_nios2_qspi_get_parameters(const struct device *dev) +{ + ARG_UNUSED(dev); + + return &flash_nios2_qspi_parameters; +} + +static DEVICE_API(flash, flash_nios2_qspi_api) = { + .erase = flash_nios2_qspi_erase, + .write = flash_nios2_qspi_write, + .read = flash_nios2_qspi_read, + .get_parameters = flash_nios2_qspi_get_parameters, +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + .page_layout = (flash_api_pages_layout) + flash_page_layout_not_implemented, +#endif +}; + +static int flash_nios2_qspi_init(const struct device *dev) +{ + struct flash_nios2_qspi_config *flash_cfg = dev->data; + + k_sem_init(&flash_cfg->sem_lock, 1, 1); + return 0; +} + +struct flash_nios2_qspi_config flash_cfg = { + .qspi_dev = { + .data_base = EXT_FLASH_AVL_MEM_BASE, + .data_end = EXT_FLASH_AVL_MEM_BASE + EXT_FLASH_AVL_MEM_SPAN, + .csr_base = EXT_FLASH_AVL_CSR_BASE, + .size_in_bytes = EXT_FLASH_AVL_MEM_SPAN, + .is_epcs = EXT_FLASH_AVL_MEM_IS_EPCS, + .number_of_sectors = EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS, + .sector_size = EXT_FLASH_AVL_MEM_SECTOR_SIZE, + .page_size = EXT_FLASH_AVL_MEM_PAGE_SIZE, + } +}; + +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, + "only one 'altr,nios2-qspi-nor' compatible node may be present"); + +DEVICE_DT_INST_DEFINE(0, + flash_nios2_qspi_init, NULL, &flash_cfg, NULL, + POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, + &flash_nios2_qspi_api); diff --git a/drivers/flash/soc_flash_renesas_ra_hp.c b/drivers/flash/soc_flash_renesas_ra_hp.c deleted file mode 100644 index dcf61fd3f8bf8..0000000000000 --- a/drivers/flash/soc_flash_renesas_ra_hp.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Copyright (c) 2024-2025 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL -#include -#include -#include -#include -#include -#include -#include -#include -#include "soc_flash_renesas_ra_hp.h" - -#define DT_DRV_COMPAT renesas_ra_flash_hp_controller - -LOG_MODULE_REGISTER(flash_renesas_ra_hp, CONFIG_FLASH_LOG_LEVEL); - -static struct flash_pages_layout code_flash_ra_layout[FLASH_HP_CF_LAYOUT_SIZE]; -static struct flash_pages_layout data_flash_ra_layout[FLASH_HP_DF_LAYOUT_SIZE]; - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) -void fcu_frdyi_isr(void); -void fcu_fiferr_isr(void); - -void flash_bgo_callback(flash_callback_args_t *p_args) -{ - atomic_t *event_flag = (atomic_t *)(p_args->p_context); - - if (FLASH_EVENT_ERASE_COMPLETE == p_args->event) { - atomic_or(event_flag, FLASH_FLAG_ERASE_COMPLETE); - } else if (FLASH_EVENT_WRITE_COMPLETE == p_args->event) { - atomic_or(event_flag, FLASH_FLAG_WRITE_COMPLETE); - } -#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING) - else if (FLASH_EVENT_BLANK == p_args->event) { - atomic_or(event_flag, FLASH_FLAG_BLANK); - } else if (FLASH_EVENT_NOT_BLANK == p_args->event) { - atomic_or(event_flag, FLASH_FLAG_NOT_BLANK); - } -#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */ - else { - atomic_or(event_flag, FLASH_FLAG_GET_ERROR); - } -} -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - -static bool flash_ra_valid_range(struct flash_hp_ra_data *flash_data, off_t offset, size_t len) -{ - if ((offset < 0) || (offset >= flash_data->area_size) || - (flash_data->area_size - offset < len) || (len > UINT32_MAX - offset)) { - return false; - } - - return true; -} - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING) -/* This feature prevents erroneous reading. Values read from an - * area of the data flash that has been erased but not programmed - * are undefined. - */ -static int is_area_readable(const struct device *dev, off_t offset, size_t len) -{ - struct flash_hp_ra_data *flash_data = dev->data; - struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; - int ret = 0; - flash_result_t result = FLASH_RESULT_BGO_ACTIVE; - fsp_err_t err; - - k_sem_take(&dev_ctrl->ctrl_sem, K_FOREVER); - - err = R_FLASH_HP_BlankCheck(&dev_ctrl->flash_ctrl, - (long)(flash_data->area_address + offset), len, &result); - - if (err != FSP_SUCCESS) { - ret = -EIO; - goto end; - } - - /* Wait for the blank check result event if BGO is SET */ - if (true == dev_ctrl->fsp_config.data_flash_bgo) { - while (!(dev_ctrl->flags & (FLASH_FLAG_BLANK | FLASH_FLAG_NOT_BLANK))) { - if (dev_ctrl->flags & FLASH_FLAG_GET_ERROR) { - ret = -EIO; - atomic_and(&dev_ctrl->flags, ~FLASH_FLAG_GET_ERROR); - break; - } - k_sleep(K_USEC(10)); - } - if (dev_ctrl->flags & FLASH_FLAG_BLANK) { - LOG_DBG("read request on erased offset:0x%lx size:%d", - offset, len); - result = FLASH_RESULT_BLANK; - } - atomic_and(&dev_ctrl->flags, ~(FLASH_FLAG_BLANK | FLASH_FLAG_NOT_BLANK)); - } - -end: - k_sem_give(&dev_ctrl->ctrl_sem); - - if (result == FLASH_RESULT_BLANK) { - return -ENODATA; - } - - return ret; -} -#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */ - -static int flash_ra_read(const struct device *dev, off_t offset, void *data, size_t len) -{ - struct flash_hp_ra_data *flash_data = dev->data; - int rc = 0; - - if (!flash_ra_valid_range(flash_data, offset, len)) { - return -EINVAL; - } - - if (!len) { - return 0; - } - - LOG_DBG("flash: read 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING) - if (flash_data->FlashRegion == DATA_FLASH) { - rc = is_area_readable(dev, offset, len); - } -#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */ - - if (!rc) { - memcpy(data, (uint8_t *)(offset + flash_data->area_address), len); -#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING) - } else if (rc == -ENODATA) { - /* Erased area, return dummy data as an erased page. */ - memset(data, 0xFF, len); - rc = 0; -#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */ - } - - return rc; -} - -static int flash_ra_erase(const struct device *dev, off_t offset, size_t len) -{ - struct flash_hp_ra_data *flash_data = dev->data; - struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; - static struct flash_pages_info page_info_off, page_info_len; - fsp_err_t err; - uint32_t block_num; - int rc, rc2, ret = 0; - int key = 0; - bool is_contain_end_block = false; - - if (!flash_ra_valid_range(flash_data, offset, len)) { - return -EINVAL; - } - - if (!len) { - return 0; - } - - LOG_DBG("flash: erase 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); - - rc = flash_get_page_info_by_offs(dev, offset, &page_info_off); - - if (rc != 0) { - return -EINVAL; - } - - if (offset != page_info_off.start_offset) { - return -EINVAL; - } - - if (flash_data->FlashRegion == CODE_FLASH) { - if ((offset + len) == (uint32_t)DT_REG_SIZE(DT_NODELABEL(flash0))) { - page_info_len.index = FLASH_HP_CF_END_BLOCK; - is_contain_end_block = true; - } - } else { - if ((offset + len) == (uint32_t)FLASH_HP_DF_SIZE) { - page_info_len.index = FLASH_HP_DF_END_BLOCK; - is_contain_end_block = true; - } - } - - if (!is_contain_end_block) { - rc2 = flash_get_page_info_by_offs(dev, (offset + len), &page_info_len); - if (rc2 != 0) { - return -EINVAL; - } - if ((offset + len) != (page_info_len.start_offset)) { - return -EIO; - } - } - - block_num = (uint32_t)(page_info_len.index - page_info_off.index); - - if (block_num > 0) { - if (flash_data->FlashRegion == CODE_FLASH) { - /* Disable interrupts during code flash operations */ - key = irq_lock(); - } else { - k_sem_take(&dev_ctrl->ctrl_sem, K_FOREVER); - } - - err = R_FLASH_HP_Erase(&dev_ctrl->flash_ctrl, - (long)(flash_data->area_address + offset), block_num); - - if (err != FSP_SUCCESS) { - ret = -EIO; - goto end; - } - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) - if (flash_data->FlashRegion == DATA_FLASH) { - /* Wait for the erase complete event flag, if BGO is SET */ - while (!(dev_ctrl->flags & FLASH_FLAG_ERASE_COMPLETE)) { - if (dev_ctrl->flags & FLASH_FLAG_GET_ERROR) { - ret = -EIO; - atomic_and(&dev_ctrl->flags, ~FLASH_FLAG_GET_ERROR); - break; - } - k_sleep(K_USEC(10)); - } - atomic_and(&dev_ctrl->flags, ~FLASH_FLAG_ERASE_COMPLETE); - } -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - -end: - if (flash_data->FlashRegion == CODE_FLASH) { - irq_unlock(key); - } else { - k_sem_give(&dev_ctrl->ctrl_sem); - } - } - - return ret; -} - -static int flash_ra_write(const struct device *dev, off_t offset, const void *data, size_t len) -{ - fsp_err_t err; - struct flash_hp_ra_data *flash_data = dev->data; - struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; - int key = 0; - int ret = 0; - - if (!flash_ra_valid_range(flash_data, offset, len)) { - return -EINVAL; - } - - if (!len) { - return 0; - } - - LOG_DBG("flash: write 0x%lx, len: %u", (long)(offset + flash_data->area_address), len); - - if (flash_data->FlashRegion == CODE_FLASH) { - /* Disable interrupts during code flash operations */ - key = irq_lock(); - } else { - k_sem_take(&dev_ctrl->ctrl_sem, K_FOREVER); - } - - err = R_FLASH_HP_Write(&dev_ctrl->flash_ctrl, (uint32_t)data, - (long)(offset + flash_data->area_address), len); - - if (err != FSP_SUCCESS) { - ret = -EIO; - goto end; - } - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) - if (flash_data->FlashRegion == DATA_FLASH) { - /* Wait for the write complete event flag, if BGO is SET */ - while (!(dev_ctrl->flags & FLASH_FLAG_WRITE_COMPLETE)) { - if (dev_ctrl->flags & FLASH_FLAG_GET_ERROR) { - ret = -EIO; - atomic_and(&dev_ctrl->flags, ~FLASH_FLAG_GET_ERROR); - break; - } - k_sleep(K_USEC(10)); - } - atomic_and(&dev_ctrl->flags, ~FLASH_FLAG_WRITE_COMPLETE); - } -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - -end: - if (flash_data->FlashRegion == CODE_FLASH) { - irq_unlock(key); - } else { - k_sem_give(&dev_ctrl->ctrl_sem); - } - - return ret; -} - -static int flash_ra_get_size(const struct device *dev, uint64_t *size) -{ - struct flash_hp_ra_data *flash_data = dev->data; - *size = (uint64_t)flash_data->area_size; - - return 0; -} - -#ifdef CONFIG_FLASH_PAGE_LAYOUT -void flash_ra_page_layout(const struct device *dev, const struct flash_pages_layout **layout, - size_t *layout_size) -{ - struct flash_hp_ra_data *flash_data = dev->data; - - if (flash_data->FlashRegion == DATA_FLASH) { - data_flash_ra_layout[0].pages_count = FLASH_HP_DF_BLOCKS_COUNT; - data_flash_ra_layout[0].pages_size = FLASH_HP_DF_BLOCK_SIZE; - *layout = data_flash_ra_layout; - *layout_size = FLASH_HP_DF_LAYOUT_SIZE; - } else { - code_flash_ra_layout[0].pages_count = FLASH_HP_CF_REGION0_BLOCKS_COUNT; - code_flash_ra_layout[0].pages_size = FLASH_HP_CF_REGION0_BLOCK_SIZE; -#if (FLASH_HP_VERSION == 40) - code_flash_ra_layout[1].pages_count = FLASH_HP_CF_REGION1_BLOCKS_COUNT; - code_flash_ra_layout[1].pages_size = FLASH_HP_CF_REGION1_BLOCK_SIZE; - -#endif /* FLASH_HP_VERSION == 40 */ - *layout = code_flash_ra_layout; - *layout_size = FLASH_HP_CF_LAYOUT_SIZE; - } -} -#endif /* CONFIG_FLASH_PAGE_LAYOUT */ - -static const struct flash_parameters *flash_ra_get_parameters(const struct device *dev) -{ - const struct flash_hp_ra_config *config = dev->config; - - return &config->flash_ra_parameters; -} - -static struct flash_hp_ra_controller flash_hp_ra_controller = { - .fsp_config = { - .data_flash_bgo = IS_ENABLED(CONFIG_FLASH_RENESAS_RA_HP_BGO), -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) - .p_callback = flash_bgo_callback, - .p_context = NULL, - .irq = (IRQn_Type)DT_INST_IRQ_BY_NAME(0, frdyi, irq), - .err_irq = (IRQn_Type)DT_INST_IRQ_BY_NAME(0, fiferr, irq), - .err_ipl = DT_INST_IRQ_BY_NAME(0, fiferr, priority), - .ipl = DT_INST_IRQ_BY_NAME(0, frdyi, priority), -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - }}; - -#ifdef CONFIG_FLASH_EX_OP_ENABLED -static int flash_ra_ex_op(const struct device *dev, uint16_t code, const uintptr_t in, void *out) -{ - int err = -ENOTSUP; - - switch (code) { -#if defined(CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT) - case FLASH_RA_EX_OP_WRITE_PROTECT: - err = flash_ra_ex_op_write_protect(dev, in, out); - break; -#endif /* CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT */ - - default: - break; - } - - return err; -} -#endif /* CONFIG_FLASH_EX_OP_ENABLED */ - -static int flash_ra_init(const struct device *dev) -{ - const struct device *dev_ctrl = DEVICE_DT_INST_GET(0); - struct flash_hp_ra_data *flash_data = dev->data; - - if (!device_is_ready(dev_ctrl)) { - return -ENODEV; - } - - if (flash_data->area_address == FLASH_HP_DF_START_ADDRESS) { - flash_data->FlashRegion = DATA_FLASH; - } else { - flash_data->FlashRegion = CODE_FLASH; - } - - flash_data->controller = dev_ctrl->data; - - return 0; -} - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) -#define FLASH_CONTROLLER_RA_IRQ_INIT \ - { \ - R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq)] = \ - BSP_PRV_IELS_ENUM(EVENT_FCU_FRDYI); \ - R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq)] = \ - BSP_PRV_IELS_ENUM(EVENT_FCU_FIFERR); \ - \ - IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq), \ - DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, priority), fcu_frdyi_isr, \ - DEVICE_DT_INST_GET(0), 0); \ - IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq), \ - DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, priority), fcu_fiferr_isr, \ - DEVICE_DT_INST_GET(0), 0); \ - \ - irq_enable(DT_INST_IRQ_BY_NAME(0, frdyi, irq)); \ - irq_enable(DT_INST_IRQ_BY_NAME(0, fiferr, irq)); \ - } -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - -static int flash_controller_ra_init(const struct device *dev) -{ - fsp_err_t err; - struct flash_hp_ra_controller *data = dev->data; - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) - FLASH_CONTROLLER_RA_IRQ_INIT -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - - k_sem_init(&data->ctrl_sem, 1, 1); - - data->fsp_config.p_context = &data->flags; - - err = R_FLASH_HP_Open(&data->flash_ctrl, &data->fsp_config); - - if (err != FSP_SUCCESS) { - LOG_DBG("flash: open error=%d", (int)err); - return -EIO; - } - - return 0; -} - -static DEVICE_API(flash, flash_ra_api) = { - .erase = flash_ra_erase, - .write = flash_ra_write, - .read = flash_ra_read, - .get_parameters = flash_ra_get_parameters, - .get_size = flash_ra_get_size, -#ifdef CONFIG_FLASH_PAGE_LAYOUT - .page_layout = flash_ra_page_layout, -#endif -#ifdef CONFIG_FLASH_EX_OP_ENABLED - .ex_op = flash_ra_ex_op, -#endif -}; - -#define RA_FLASH_INIT(index) \ - struct flash_hp_ra_data flash_hp_ra_data_##index = {.area_address = DT_REG_ADDR(index), \ - .area_size = DT_REG_SIZE(index)}; \ - static struct flash_hp_ra_config flash_hp_ra_config_##index = { \ - .flash_ra_parameters = { \ - .write_block_size = DT_PROP(index, write_block_size), \ - .erase_value = 0xff, \ - }}; \ - \ - DEVICE_DT_DEFINE(index, flash_ra_init, NULL, &flash_hp_ra_data_##index, \ - &flash_hp_ra_config_##index, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, \ - &flash_ra_api); - -DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(0), RA_FLASH_INIT); - -/* define the flash controller device just to run the init. */ -DEVICE_DT_DEFINE(DT_DRV_INST(0), flash_controller_ra_init, NULL, &flash_hp_ra_controller, NULL, - PRE_KERNEL_1, CONFIG_FLASH_INIT_PRIORITY, NULL); diff --git a/drivers/flash/soc_flash_renesas_ra_hp.h b/drivers/flash/soc_flash_renesas_ra_hp.h deleted file mode 100644 index 2a2ce66250be3..0000000000000 --- a/drivers/flash/soc_flash_renesas_ra_hp.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2024-2025 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_FLASH_SOC_FLASH_RENESAS_RA_HP_H_ -#define ZEPHYR_DRIVERS_FLASH_SOC_FLASH_RENESAS_RA_HP_H_ - -#include -#include -#include -#include -#include - -#define FLASH_HP_CF_START_ADDRESS DT_REG_ADDR(DT_NODELABEL(flash0)) -#define FLASH_HP_DF_START_ADDRESS DT_REG_ADDR(DT_NODELABEL(flash1)) - -#define FLASH_HP_CF_SIZE DT_REG_SIZE(DT_NODELABEL(flash0)) -#define FLASH_HP_DF_SIZE DT_REG_SIZE(DT_NODELABEL(flash1)) - -#define FLASH_HP_VERSION DT_PROP(DT_PARENT(DT_NODELABEL(flash0)), flash_hardware_version) - -#if (FLASH_HP_VERSION == 40) - -#define FLASH_HP_CF_REGION0_BLOCKS_COUNT \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 0, pages_count) -#define FLASH_HP_CF_REGION0_BLOCK_SIZE \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 0, pages_size) -#define FLASH_HP_CF_REGION0_SIZE (FLASH_HP_CF_REGION0_BLOCKS_COUNT * FLASH_HP_CF_REGION0_BLOCK_SIZE) - -BUILD_ASSERT(FLASH_HP_CF_REGION0_BLOCK_SIZE == BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE, - "erase-block-size expected to be equal with block size"); - -#define FLASH_HP_CF_REGION1_BLOCKS_COUNT \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 1, pages_count) -#define FLASH_HP_CF_REGION1_BLOCK_SIZE \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 1, pages_size) - -BUILD_ASSERT(FLASH_HP_CF_REGION1_BLOCK_SIZE == BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE, - "erase-block-size expected to be equal with block size"); - -#define FLASH_HP_CF_LAYOUT_SIZE (2UL) - -#define FLASH_HP_CF_END_BLOCK (FLASH_HP_CF_REGION0_BLOCKS_COUNT + FLASH_HP_CF_REGION1_BLOCKS_COUNT) - -#elif (FLASH_HP_VERSION == 4) - -#define FLASH_HP_CF_REGION0_BLOCKS_COUNT \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 0, pages_count) -#define FLASH_HP_CF_REGION0_BLOCK_SIZE \ - DT_PHA_BY_IDX(DT_NODELABEL(flash0), erase_blocks, 0, pages_size) -#define FLASH_HP_CF_REGION0_SIZE (FLASH_HP_CF_REGION0_BLOCKS_COUNT * FLASH_HP_CF_REGION0_BLOCK_SIZE) - -BUILD_ASSERT(FLASH_HP_CF_REGION0_BLOCK_SIZE == BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE, - "erase-block-size expected to be equal with block size"); - -#define FLASH_HP_CF_LAYOUT_SIZE (1UL) - -#define FLASH_HP_CF_END_BLOCK FLASH_HP_CF_REGION0_BLOCKS_COUNT - -#endif - -#define FLASH_HP_DF_LAYOUT_SIZE (1UL) -#define FLASH_HP_DF_BLOCK_SIZE DT_PROP(DT_NODELABEL(flash1), erase_block_size) -#define FLASH_HP_DF_BLOCKS_COUNT (FLASH_HP_DF_SIZE / FLASH_HP_DF_BLOCK_SIZE) -#define FLASH_HP_DF_END_BLOCK FLASH_HP_DF_BLOCKS_COUNT - -BUILD_ASSERT(FLASH_HP_DF_BLOCK_SIZE == BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, - "erase-block-size expected to be equal with block size"); - -#if defined(CONFIG_FLASH_EX_OP_ENABLED) -#define FLASH_HP_FCU_CONFIG_SET_BPS (0x1300A1C0U) -#define FLASH_HP_FCU_CONFIG_SET_BPS_SEC (0x0300A240U) -#define FLASH_HP_FCU_CONFIG_SET_BPS_SEL (0x0300A2C0U) - -#define FLASH_HP_FCU_CONFIG_SET_PBPS (0x1300A1E0U) -#define FLASH_HP_FCU_CONFIG_SET_PBPS_SEC (0x0300A260U) -#endif /* CONFIG_FLASH_EX_OP_ENABLED */ - -/* Zero based offset into g_configuration_area_data[] for BPS */ -#define FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET (0U) - -enum flash_region { - CODE_FLASH, - DATA_FLASH, -}; - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_BGO) -#define FLASH_FLAG_ERASE_COMPLETE BIT(0) -#define FLASH_FLAG_WRITE_COMPLETE BIT(1) -#define FLASH_FLAG_GET_ERROR BIT(2) - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING) -#define FLASH_FLAG_BLANK BIT(3) -#define FLASH_FLAG_NOT_BLANK BIT(4) -#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */ - -#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */ - -struct flash_hp_ra_controller { - struct st_flash_hp_instance_ctrl flash_ctrl; - struct k_sem ctrl_sem; - struct st_flash_cfg fsp_config; - atomic_t flags; -}; - -struct flash_hp_ra_data { - struct flash_hp_ra_controller *controller; - enum flash_region FlashRegion; - uint32_t area_address; - uint32_t area_size; -}; - -struct flash_hp_ra_config { - struct flash_parameters flash_ra_parameters; -}; - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT) -int flash_ra_ex_op_write_protect(const struct device *dev, const uintptr_t in, void *out); -#endif /* CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT */ - -#endif /* ZEPHYR_DRIVERS_FLASH_SOC_FLASH_RENESAS_RA_HP_H_ */ diff --git a/drivers/flash/soc_flash_renesas_ra_hp_ex_op.c b/drivers/flash/soc_flash_renesas_ra_hp_ex_op.c deleted file mode 100644 index 1cba238fe14a0..0000000000000 --- a/drivers/flash/soc_flash_renesas_ra_hp_ex_op.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Copyright (c) 2024-2025 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#ifdef CONFIG_USERSPACE -#include -#include -#endif - -#include -#include "soc_flash_renesas_ra_hp.h" - -#define FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT (8U) - -#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) -extern uint16_t g_configuration_area_data[FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT]; -#endif -extern fsp_err_t -flash_hp_enter_pe_cf_mode(flash_hp_instance_ctrl_t *const p_ctrl) PLACE_IN_RAM_SECTION; - -extern fsp_err_t flash_hp_stop(void) PLACE_IN_RAM_SECTION; - -extern fsp_err_t flash_hp_configuration_area_write(flash_hp_instance_ctrl_t *p_ctrl, - uint32_t fsaddr, - uint16_t *src_address) PLACE_IN_RAM_SECTION; - -extern fsp_err_t flash_hp_check_errors(fsp_err_t previous_error, uint32_t error_bits, - fsp_err_t return_error) PLACE_IN_RAM_SECTION; - -extern fsp_err_t flash_hp_pe_mode_exit(void) PLACE_IN_RAM_SECTION; - -static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_val_ns, uint8_t *pbps_val_ns, - uint32_t size) PLACE_IN_RAM_SECTION; - -static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_val_sec, uint8_t *pbps_val_sec, - uint32_t size) PLACE_IN_RAM_SECTION; - -static fsp_err_t flash_hp_set_block_protect_sel(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_sel_val, - uint32_t size) PLACE_IN_RAM_SECTION; - -static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_val_ns, uint8_t *pbps_val_ns, - uint32_t size) -{ - /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ - int key = irq_lock(); - - /* Update Flash state and enter Code Flash P/E mode */ - fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); - - FSP_ERROR_RETURN(err == FSP_SUCCESS, err); - - memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); - if (bps_val_ns != NULL) { - memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_ns, - size); - err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS, - &g_configuration_area_data); - err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); - } - - memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); - if (pbps_val_ns != NULL) { - memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_ns, - size); - err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS, - &g_configuration_area_data); - err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); - } - - /* Return to read mode*/ - fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); - - if (err == FSP_SUCCESS) { - err = pe_exit_err; - } - - /* Enable interrupts after code flash operations are complete. */ - irq_unlock(key); - - return err; -} - -static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_val_sec, uint8_t *pbps_val_sec, - uint32_t size) -{ - /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ - int key = irq_lock(); - /* Update Flash state and enter Code Flash P/E mode */ - fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); - - FSP_ERROR_RETURN(err == FSP_SUCCESS, err); - - memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); - if (bps_val_sec != NULL) { - memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_sec, - size); - err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEC, - &g_configuration_area_data); - err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); - } - - memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); - if (pbps_val_sec != NULL) { - memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_sec, - size); - err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS_SEC, - &g_configuration_area_data); - err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); - } - - /* Return to read mode*/ - fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); - - if (err == FSP_SUCCESS) { - err = pe_exit_err; - } - - /* Enable interrupts after code flash operations are complete. */ - irq_unlock(key); - - return err; -} - -static fsp_err_t flash_hp_set_block_protect_sel(flash_hp_instance_ctrl_t *p_ctrl, - uint8_t *bps_sel_val, uint32_t size) -{ - /* Disable interrupts to prevent vector table access while code flash is in P/E mode. */ - int key = irq_lock(); - - /* Update Flash state and enter Code Flash P/E mode */ - fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); - - FSP_ERROR_RETURN(err == FSP_SUCCESS, err); - - memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); - memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_sel_val, size); - err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEL, - &g_configuration_area_data); - err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); - - /* Return to read mode*/ - fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); - - if (err == FSP_SUCCESS) { - err = pe_exit_err; - } - - /* Enable interrupts after code flash operations are complete. */ - irq_unlock(key); - - return err; -} - -static fsp_err_t R_FLASH_HP_BlockProtectSet(flash_ctrl_t *const p_api_ctrl, uint8_t *bps_val_ns, - uint8_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, - uint32_t size); - -static fsp_err_t R_FLASH_HP_BlockProtectGet(flash_ctrl_t *const p_api_ctrl, uint32_t *bps_val_ns, - uint32_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, - uint32_t *size); - -int flash_ra_block_protect_set(const struct device *dev, - const struct flash_ra_ex_write_protect_in *request); - -int flash_ra_block_protect_get(const struct device *dev, - struct flash_ra_ex_write_protect_out *response); - -static fsp_err_t R_FLASH_HP_BlockProtectSet(flash_ctrl_t *const p_api_ctrl, uint8_t *bps_val_ns, - uint8_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, - uint32_t size) -{ - flash_hp_instance_ctrl_t *p_ctrl = (flash_hp_instance_ctrl_t *)p_api_ctrl; - fsp_err_t err = FSP_SUCCESS; - -#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) - - /* if non-secure BPS (PBPS) buffers are not null and size is smaller than 16 bytes */ - if (((bps_val_ns != NULL) || (pbps_val_ns != NULL)) && - (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { - err = flash_hp_set_block_protect_ns(p_ctrl, bps_val_ns, pbps_val_ns, size); - } - - /* if secure BPS (PBPS) buffers are not null and size is smaller than 16 bytes */ - if (((bps_val_sec != NULL) || (pbps_val_sec != NULL)) && - (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { - err = flash_hp_set_block_protect_sec(p_ctrl, bps_val_sec, pbps_val_sec, size); - } - - /* if BPS SEL buffer is not null and size is smaller than 16 bytes */ - if ((bps_val_sel != NULL) && - (size <= (sizeof(uint16_t) * FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT))) { - err = flash_hp_set_block_protect_sel(p_ctrl, bps_val_sel, size); - } -#else - - err = FSP_ERR_UNSUPPORTED; /* For consistency with _LP API we return error if Code Flash */ - -#endif - - return err; -} - -static fsp_err_t R_FLASH_HP_BlockProtectGet(flash_ctrl_t *const p_api_ctrl, uint32_t *bps_val_ns, - uint32_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, - uint32_t *size) -{ - fsp_err_t err = FSP_ERR_UNSUPPORTED; - -#if (DT_PROP(DT_NODELABEL(flash0), renesas_programming_enable)) - - err = FSP_SUCCESS; - - if (bps_val_ns != NULL) { - bps_val_ns[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 0)); - bps_val_ns[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 3)); - bps_val_ns[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 7)); - bps_val_ns[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS + 11)); - } - - if (bps_val_sec != NULL) { - bps_val_sec[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 0)); - bps_val_sec[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 3)); - bps_val_sec[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 7)); - bps_val_sec[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEC + 11)); - } - - if (bps_val_sel != NULL) { - bps_val_sel[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 0)); - bps_val_sel[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 3)); - bps_val_sel[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 7)); - bps_val_sel[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_BPS_SEL + 11)); - } - - if (pbps_val_ns != NULL) { - pbps_val_ns[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 0)); - pbps_val_ns[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 3)); - pbps_val_ns[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 7)); - pbps_val_ns[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS + 11)); - } - - if (pbps_val_sec != NULL) { - pbps_val_sec[0] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 0)); - pbps_val_sec[1] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 3)); - pbps_val_sec[2] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 7)); - pbps_val_sec[3] = *((uint32_t *)(FLASH_HP_FCU_CONFIG_SET_PBPS_SEC + 11)); - } - - if (size != NULL) { - *size = 4; - } -#endif - - FSP_PARAMETER_NOT_USED(p_api_ctrl); - - return err; -} - -#if defined(CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT) -int flash_ra_block_protect_get(const struct device *dev, - struct flash_ra_ex_write_protect_out *response) -{ - fsp_err_t err = FSP_ERR_ASSERTION; - struct flash_hp_ra_data *flash_data = dev->data; - struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; - flash_ra_cf_block_map bps_ns; - - /* get the current non-secure BPS register values */ - err = R_FLASH_HP_BlockProtectGet(&dev_ctrl->flash_ctrl, (uint32_t *)&bps_ns, NULL, NULL, - NULL, NULL, NULL); - memcpy(&response->protected_enabled, &bps_ns, sizeof(flash_ra_cf_block_map)); - - return err; -} - -int flash_ra_ex_op_write_protect(const struct device *dev, const uintptr_t in, void *out) -{ - const struct flash_ra_ex_write_protect_in *request = - (const struct flash_ra_ex_write_protect_in *)in; - struct flash_ra_ex_write_protect_out *result = (struct flash_ra_ex_write_protect_out *)out; - - int rc = 0, rc2 = 0; -#ifdef CONFIG_USERSPACE - bool syscall_trap = z_syscall_trap(); -#endif - - if (request != NULL) { -#ifdef CONFIG_USERSPACE - struct flash_ra_ex_write_protect_in copy_in; - - if (syscall_trap) { - Z_OOPS(z_user_from_copy(©_in, request, sizeof(copy_in))); - request = ©_in; - } -#endif - /* if both enable and disable are set */ - if ((request->protect_enable.BPS[0] & request->protect_disable.BPS[0]) || - (request->protect_enable.BPS[1] & request->protect_disable.BPS[1]) || - (request->protect_enable.BPS[2] & request->protect_disable.BPS[2]) || - (request->protect_enable.BPS[3] & request->protect_disable.BPS[3])) { - return EINVAL; - } - - rc = flash_ra_block_protect_set(dev, request); - } - - if (result != NULL) { -#ifdef CONFIG_USERSPACE - struct flash_ra_ex_write_protect_out copy_out; - - if (syscall_trap) { - result = ©_out; - } -#endif - rc2 = flash_ra_block_protect_get(dev, result); - if (!rc) { - rc = rc2; - } - -#ifdef CONFIG_USERSPACE - if (syscall_trap) { - Z_OOPS(z_user_to_copy(out, result, sizeof(copy_out))); - } -#endif - } - - return rc; -} - -int flash_ra_block_protect_set(const struct device *dev, - const struct flash_ra_ex_write_protect_in *request) -{ - fsp_err_t err = FSP_ERR_ASSERTION; - struct flash_hp_ra_data *flash_data = dev->data; - struct flash_hp_ra_controller *dev_ctrl = flash_data->controller; - flash_ra_cf_block_map bps_ns; - - /* get the current non-secure BPS register values */ - err = R_FLASH_HP_BlockProtectGet(&dev_ctrl->flash_ctrl, (uint32_t *)&bps_ns, NULL, NULL, - NULL, NULL, NULL); - - if (err != FSP_SUCCESS) { - __ASSERT(false, "flash: block get current value error =%d", err); - return -EIO; - } - - /* enable block protect */ - bps_ns.BPS[0] &= ~(request->protect_enable.BPS[0]); - bps_ns.BPS[1] &= ~(request->protect_enable.BPS[1]); - bps_ns.BPS[2] &= ~(request->protect_enable.BPS[2]); - bps_ns.BPS[3] &= ~(request->protect_enable.BPS[3]); - - /* disable block protect */ - bps_ns.BPS[0] |= (request->protect_disable.BPS[0]); - bps_ns.BPS[1] |= (request->protect_disable.BPS[1]); - bps_ns.BPS[2] |= (request->protect_disable.BPS[2]); - bps_ns.BPS[3] |= (request->protect_disable.BPS[3]); - - /* reset default all from non-secure */ - err = R_FLASH_HP_BlockProtectSet(&dev_ctrl->flash_ctrl, (uint8_t *)&bps_ns, NULL, NULL, - NULL, NULL, sizeof(bps_ns)); - - if (err != FSP_SUCCESS) { - __ASSERT(false, "flash: block protect error=%d", err); - return -EIO; - } - return 0; -} - -#endif /* CONFIG_FLASH_RENESAS_RA_HP_WRITE_PROTECT */ diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index 383a6065394bc..c02e77bf9a653 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -53,9 +53,6 @@ LOG_MODULE_REGISTER(spi_nor, CONFIG_FLASH_LOG_LEVEL); #define ANY_INST_HAS_WP_GPIOS DT_ANY_INST_HAS_PROP_STATUS_OKAY(wp_gpios) #define ANY_INST_HAS_HOLD_GPIOS DT_ANY_INST_HAS_PROP_STATUS_OKAY(hold_gpios) #define ANY_INST_USE_4B_ADDR_OPCODES DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_4b_addr_opcodes) -#define ANY_INST_HAS_FLSR \ - DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_flag_status_register) -#define ANY_INST_USE_FAST_READ DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_fast_read) #ifdef CONFIG_SPI_NOR_ACTIVE_DWELL_MS #define ACTIVE_DWELL_MS CONFIG_SPI_NOR_ACTIVE_DWELL_MS @@ -153,8 +150,6 @@ struct spi_nor_config { bool requires_ulbpr_exist:1; bool wp_gpios_exist:1; bool hold_gpios_exist:1; - bool has_flsr: 1; - bool use_fast_read: 1; }; /** @@ -361,10 +356,6 @@ static inline void delay_until_exit_dpd_ok(const struct device *const dev) */ #define NOR_ACCESS_32BIT_ADDR BIT(2) -/* Indicates that a dummy byte is to be sent following the address. - */ -#define NOR_ACCESS_DUMMY_BYTE BIT(3) - /* Indicates that an access command is performing a write. If not * provided access is a read. */ @@ -390,9 +381,8 @@ static int spi_nor_access(const struct device *const dev, struct spi_nor_data *const driver_data = dev->data; bool is_addressed = (access & NOR_ACCESS_ADDRESSED) != 0U; bool is_write = (access & NOR_ACCESS_WRITE) != 0U; - bool has_dummy = (access & NOR_ACCESS_DUMMY_BYTE) != 0U; - uint8_t buf[6] = {opcode}; - struct spi_buf spi_buf_tx[2] = { + uint8_t buf[5] = { 0 }; + struct spi_buf spi_buf[2] = { { .buf = buf, .len = 1, @@ -402,17 +392,8 @@ static int spi_nor_access(const struct device *const dev, .len = length } }; - struct spi_buf spi_buf_rx[2] = { - { - .buf = NULL, - .len = 1, - }, - { - .buf = data, - .len = length - } - }; + buf[0] = opcode; if (is_addressed) { bool access_24bit = (access & NOR_ACCESS_24BIT_ADDR) != 0; bool access_32bit = (access & NOR_ACCESS_32BIT_ADDR) != 0; @@ -428,26 +409,20 @@ static int spi_nor_access(const struct device *const dev, if (use_32bit) { memcpy(&buf[1], &addr32.u8[0], 4); - spi_buf_tx[0].len += 4; - spi_buf_rx[0].len += 4; + spi_buf[0].len += 4; } else { memcpy(&buf[1], &addr32.u8[1], 3); - spi_buf_tx[0].len += 3; - spi_buf_rx[0].len += 3; + spi_buf[0].len += 3; } }; - if (has_dummy) { - spi_buf_tx[0].len++; - spi_buf_rx[0].len++; - } const struct spi_buf_set tx_set = { - .buffers = spi_buf_tx, - .count = (is_write && length != 0) ? 2 : 1, + .buffers = spi_buf, + .count = (length != 0) ? 2 : 1, }; const struct spi_buf_set rx_set = { - .buffers = spi_buf_rx, + .buffers = spi_buf, .count = 2, }; @@ -468,17 +443,6 @@ static int spi_nor_access(const struct device *const dev, #define spi_nor_cmd_addr_read_4b(dev, opcode, addr, dest, length) \ spi_nor_access(dev, opcode, NOR_ACCESS_32BIT_ADDR | NOR_ACCESS_ADDRESSED, addr, dest, \ length) -#define spi_nor_cmd_addr_fast_read(dev, opcode, addr, dest, length) \ - spi_nor_access(dev, opcode, NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, dest, \ - length) -#define spi_nor_cmd_addr_fast_read_3b(dev, opcode, addr, dest, length) \ - spi_nor_access(dev, opcode, \ - NOR_ACCESS_24BIT_ADDR | NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, \ - dest, length) -#define spi_nor_cmd_addr_fast_read_4b(dev, opcode, addr, dest, length) \ - spi_nor_access(dev, opcode, \ - NOR_ACCESS_32BIT_ADDR | NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, \ - dest, length) #define spi_nor_cmd_write(dev, opcode) \ spi_nor_access(dev, opcode, NOR_ACCESS_WRITE, 0, NULL, 0) #define spi_nor_cmd_addr_write(dev, opcode, addr, src, length) \ @@ -510,53 +474,16 @@ static int spi_nor_access(const struct device *const dev, */ static int spi_nor_wait_until_ready(const struct device *dev, k_timeout_t poll_delay) { - const struct spi_nor_config *cfg = dev->config; int ret; uint8_t reg; ARG_UNUSED(poll_delay); while (true) { - /* If flag status register is present, check it rather than the standard - * status register since it allows better error detection. Also, some devices - * that have it require it to be read after a program operation. - */ - if (IS_ENABLED(ANY_INST_HAS_FLSR) && cfg->has_flsr) { - ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDFLSR, ®, sizeof(reg)); - if (ret) { - break; - } - if (reg & SPI_NOR_FLSR_READY) { - if (reg & SPI_NOR_FLSR_ERASE_FAIL) { - LOG_ERR("Erase failure"); - ret = -EIO; - } - if (reg & SPI_NOR_FLSR_PROGRAM_FAIL) { - LOG_ERR("Program failure"); - ret = -EIO; - } - if (reg & SPI_NOR_FLSR_PROT_ERROR) { - LOG_ERR("Protection violation"); - ret = -EIO; - } - - if (ret) { - /* Clear flag status register for next operation */ - int ret2 = spi_nor_cmd_write(dev, SPI_NOR_CMD_CLRFLSR); - - if (ret2) { - LOG_ERR("Failed to clear flag status register: %d", - ret2); - } - } - break; - } - } else { - ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDSR, ®, sizeof(reg)); - /* Exit on error or no longer WIP */ - if (ret || !(reg & SPI_NOR_WIP_BIT)) { - break; - } + ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDSR, ®, sizeof(reg)); + /* Exit on error or no longer WIP */ + if (ret || !(reg & SPI_NOR_WIP_BIT)) { + break; } #ifdef CONFIG_SPI_NOR_SLEEP_WHILE_WAITING_UNTIL_READY /* Don't monopolise the CPU while waiting for ready */ @@ -861,7 +788,6 @@ static int mxicy_configure(const struct device *dev, const uint8_t *jedec_id) static int spi_nor_read(const struct device *dev, off_t addr, void *dest, size_t size) { - const struct spi_nor_config *cfg = dev->config; const size_t flash_size = dev_flash_size(dev); int ret; @@ -877,31 +803,14 @@ static int spi_nor_read(const struct device *dev, off_t addr, void *dest, acquire_device(dev); - if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && cfg->use_4b_addr_opcodes) { + if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && DEV_CFG(dev)->use_4b_addr_opcodes) { if (addr > SPI_NOR_3B_ADDR_MAX) { - if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) { - ret = spi_nor_cmd_addr_fast_read_4b(dev, SPI_NOR_CMD_READ_FAST_4B, - addr, dest, size); - } else { - ret = spi_nor_cmd_addr_read_4b(dev, SPI_NOR_CMD_READ_4B, addr, dest, - size); - } + ret = spi_nor_cmd_addr_read_4b(dev, SPI_NOR_CMD_READ_4B, addr, dest, size); } else { - if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) { - ret = spi_nor_cmd_addr_fast_read_3b(dev, SPI_NOR_CMD_READ_FAST, - addr, dest, size); - } else { - ret = spi_nor_cmd_addr_read_3b(dev, SPI_NOR_CMD_READ, addr, dest, - size); - } + ret = spi_nor_cmd_addr_read_3b(dev, SPI_NOR_CMD_READ, addr, dest, size); } } else { - if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) { - ret = spi_nor_cmd_addr_fast_read(dev, SPI_NOR_CMD_READ_FAST, addr, dest, - size); - } else { - ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr, dest, size); - } + ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr, dest, size); } release_device(dev); @@ -1898,8 +1807,6 @@ static DEVICE_API(flash, spi_nor_api) = { .wp_gpios_exist = DT_INST_NODE_HAS_PROP(idx, wp_gpios), \ .hold_gpios_exist = DT_INST_NODE_HAS_PROP(idx, hold_gpios), \ .use_4b_addr_opcodes = DT_INST_PROP(idx, use_4b_addr_opcodes), \ - .has_flsr = DT_INST_PROP(idx, use_flag_status_register), \ - .use_fast_read = DT_INST_PROP(idx, use_fast_read), \ IF_ENABLED(INST_HAS_LOCK(idx), (.has_lock = DT_INST_PROP(idx, has_lock),)) \ IF_ENABLED(ANY_INST_HAS_DPD, (INIT_T_ENTER_DPD(idx),)) \ IF_ENABLED(UTIL_AND(ANY_INST_HAS_DPD, ANY_INST_HAS_T_EXIT_DPD), \ diff --git a/drivers/flash/spi_nor.h b/drivers/flash/spi_nor.h index 08d2c6bccd4b6..a918e0a99d053 100644 --- a/drivers/flash/spi_nor.h +++ b/drivers/flash/spi_nor.h @@ -15,15 +15,6 @@ #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */ #define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */ -/* Flag status register bits */ -#define SPI_NOR_FLSR_READY BIT(7) /* Ready (program/erase not in progress) */ -#define SPI_NOR_FLSR_ERASE_SUSPEND BIT(6) /* Erase suspend active */ -#define SPI_NOR_FLSR_ERASE_FAIL BIT(5) /* Last erase failed */ -#define SPI_NOR_FLSR_PROGRAM_FAIL BIT(4) /* Last program failed */ -#define SPI_NOR_FLSR_PROGRAM_SUSPEND BIT(2) /* Program suspend active */ -#define SPI_NOR_FLSR_PROT_ERROR BIT(1) /* Protection violation */ -#define SPI_NOR_FLSR_4BA BIT(0) /* 4-byte address mode active */ - /* Flash opcodes */ #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */ #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */ @@ -69,8 +60,6 @@ #define SPI_NOR_CMD_PP_4B 0x12 /* Page Program 4 Byte Address */ #define SPI_NOR_CMD_PP_1_1_4_4B 0x34 /* Quad Page program (1-1-4) 4 Byte Address */ #define SPI_NOR_CMD_PP_1_4_4_4B 0x3e /* Quad Page program (1-4-4) 4 Byte Address */ -#define SPI_NOR_CMD_RDFLSR 0x70 /* Read Flag Status Register */ -#define SPI_NOR_CMD_CLRFLSR 0x50 /* Clear Flag Status Register */ /* Flash octal opcodes */ #define SPI_NOR_OCMD_SE 0x21DE /* Octal Sector erase */ diff --git a/drivers/fpga/fpga_ice40_bitbang.c b/drivers/fpga/fpga_ice40_bitbang.c index decd98cbe42eb..37ca04d5808f3 100644 --- a/drivers/fpga/fpga_ice40_bitbang.c +++ b/drivers/fpga/fpga_ice40_bitbang.c @@ -38,7 +38,7 @@ * direct register access to the set and clear registers. */ -LOG_MODULE_DECLARE(fpga_ice40, CONFIG_FPGA_LOG_LEVEL); +LOG_MODULE_DECLARE(fpga_ice40); struct fpga_ice40_config_bitbang { struct gpio_dt_spec clk; diff --git a/drivers/fpga/fpga_ice40_common.c b/drivers/fpga/fpga_ice40_common.c index d0edbfb55271c..588c1cb7c6297 100644 --- a/drivers/fpga/fpga_ice40_common.c +++ b/drivers/fpga/fpga_ice40_common.c @@ -10,7 +10,7 @@ #include "fpga_ice40_common.h" -LOG_MODULE_REGISTER(fpga_ice40, CONFIG_FPGA_LOG_LEVEL); +LOG_MODULE_REGISTER(fpga_ice40); void fpga_ice40_crc_to_str(uint32_t crc, char *s) { diff --git a/drivers/fpga/fpga_ice40_spi.c b/drivers/fpga/fpga_ice40_spi.c index 8ba7ccb72cca7..7c2f299e78255 100644 --- a/drivers/fpga/fpga_ice40_spi.c +++ b/drivers/fpga/fpga_ice40_spi.c @@ -15,7 +15,7 @@ #include "fpga_ice40_common.h" -LOG_MODULE_DECLARE(fpga_ice40, CONFIG_FPGA_LOG_LEVEL); +LOG_MODULE_DECLARE(fpga_ice40); static int fpga_ice40_load(const struct device *dev, uint32_t *image_ptr, uint32_t img_size) { diff --git a/drivers/fuel_gauge/CMakeLists.txt b/drivers/fuel_gauge/CMakeLists.txt index d8fa11f6a3398..835046304944e 100644 --- a/drivers/fuel_gauge/CMakeLists.txt +++ b/drivers/fuel_gauge/CMakeLists.txt @@ -6,7 +6,7 @@ add_subdirectory_ifdef(CONFIG_SBS_GAUGE_NEW_API sbs_gauge) add_subdirectory_ifdef(CONFIG_FUEL_GAUGE_COMPOSITE composite) add_subdirectory_ifdef(CONFIG_MAX17048 max17048) add_subdirectory_ifdef(CONFIG_BQ27Z746 bq27z746) -add_subdirectory_ifdef(CONFIG_FUEL_GAUGE_AXP2101 axp2101) +add_subdirectory_ifdef(CONFIG_LC709203F lc709203f) zephyr_library_sources_ifdef(CONFIG_USERSPACE fuel_gauge_syscall_handlers.c) diff --git a/drivers/fuel_gauge/Kconfig b/drivers/fuel_gauge/Kconfig index c0eab696880c0..7bd2a1c8136dc 100644 --- a/drivers/fuel_gauge/Kconfig +++ b/drivers/fuel_gauge/Kconfig @@ -23,6 +23,6 @@ source "drivers/fuel_gauge/max17048/Kconfig" source "drivers/fuel_gauge/sbs_gauge/Kconfig" source "drivers/fuel_gauge/bq27z746/Kconfig" source "drivers/fuel_gauge/composite/Kconfig" -source "drivers/fuel_gauge/axp2101/Kconfig" +source "drivers/fuel_gauge/lc709203f/Kconfig" endif # FUEL_GAUGE diff --git a/drivers/fuel_gauge/axp2101/CMakeLists.txt b/drivers/fuel_gauge/axp2101/CMakeLists.txt deleted file mode 100644 index e4085647c3b18..0000000000000 --- a/drivers/fuel_gauge/axp2101/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(fuel_gauge_axp2101.c) diff --git a/drivers/fuel_gauge/axp2101/Kconfig b/drivers/fuel_gauge/axp2101/Kconfig deleted file mode 100644 index 85dd84e9ef2bf..0000000000000 --- a/drivers/fuel_gauge/axp2101/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Zephyr axp2101 fuel-gauge device - -# Copyright (c) 2025 Felix Moessbauer -# SPDX-License-Identifier: Apache-2.0 - -config FUEL_GAUGE_AXP2101 - bool "X-Powers AXP2101 fuel gauge" - default y - depends on DT_HAS_X_POWERS_AXP2101_FUEL_GAUGE_ENABLED - depends on DT_HAS_X_POWERS_AXP2101_ENABLED - select I2C - select MFD - help - Enable driver for the x-powers axp2101 fuel gauge device. diff --git a/drivers/fuel_gauge/axp2101/fuel_gauge_axp2101.c b/drivers/fuel_gauge/axp2101/fuel_gauge_axp2101.c deleted file mode 100644 index 5f863e3f797ef..0000000000000 --- a/drivers/fuel_gauge/axp2101/fuel_gauge_axp2101.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2025, Felix Moessbauer - * - * SPDX-License-Identifier: Apache-2.0 - * - * Note: The functions that query the raw values via i2c are named similar - * to the ones in the reference implementation in the XPowersLib. This also - * applies to the register names (defines). - * - * Datasheet: - * https://github.com/lewisxhe/XPowersLib/blob/a7d06b98c1136c8fee7854b1d29a9f012b2aba83/datasheet/AXP2101_Datasheet_V1.0_en.pdf - */ - -#define DT_DRV_COMPAT x_powers_axp2101_fuel_gauge - -#include -#include -#include -#include -#include - -LOG_MODULE_REGISTER(fuel_gauge_axp2101, CONFIG_FUEL_GAUGE_LOG_LEVEL); - -/* clang-format off */ -/* registers */ -#define AXP2101_STATUS1 0x00 - #define BAT_PRESENT_MASK BIT(3) -#define AXP2101_CHARGE_GAUGE_WDT_CTRL 0x18 - #define GAUGE_ENABLE_MASK BIT(3) -#define AXP2101_ADC_DATA_VBAT_H 0x34 - #define GAUGE_VBAT_H_MASK 0x1F -#define AXP2101_ADC_DATA_VBAT_L 0x35 -#define AXP2101_BAT_DET_CTRL 0x68 - #define BAT_TYPE_DET_MASK BIT(0) -#define AXP2101_BAT_PERCENT_DATA 0xA4 - -/* internal feature flags */ -#define GAUGE_FEATURE_BAT_DET BIT(0) -#define GAUGE_FEATURE_GAUGE BIT(1) -#define GAUGE_FEATURE_ALL (GAUGE_FEATURE_BAT_DET | GAUGE_FEATURE_GAUGE) -/* clang-format on */ - -struct axp2101_config { - struct i2c_dt_spec i2c; -}; - -struct axp2101_data { - uint8_t features; -}; - -static int enable_fuel_gauge(const struct device *dev) -{ - const struct axp2101_config *cfg = dev->config; - struct axp2101_data *data = dev->data; - int ret = 0; - - ret = i2c_reg_update_byte_dt(&cfg->i2c, AXP2101_CHARGE_GAUGE_WDT_CTRL, GAUGE_ENABLE_MASK, - GAUGE_ENABLE_MASK); - if (ret < 0) { - data->features &= ~GAUGE_FEATURE_GAUGE; - } - return ret; -} - -static int enable_batt_detection(const struct device *dev) -{ - const struct axp2101_config *cfg = dev->config; - struct axp2101_data *data = dev->data; - int ret = 0; - - ret = i2c_reg_update_byte_dt(&cfg->i2c, AXP2101_BAT_DET_CTRL, BAT_TYPE_DET_MASK, - BAT_TYPE_DET_MASK); - if (ret < 0) { - data->features &= ~GAUGE_FEATURE_BAT_DET; - } - return ret; -} - -static int is_battery_connect(const struct device *dev, union fuel_gauge_prop_val *val) -{ - const struct axp2101_config *cfg = dev->config; - struct axp2101_data *data = dev->data; - uint8_t tmp; - int ret; - - if ((data->features & GAUGE_FEATURE_BAT_DET) == 0) { - return -ENOTSUP; - } - - ret = i2c_reg_read_byte_dt(&cfg->i2c, AXP2101_STATUS1, &tmp); - if (ret < 0) { - return ret; - } - - val->present_state = tmp & BAT_PRESENT_MASK; - return 0; -} - -static int get_battery_percent(const struct device *dev, union fuel_gauge_prop_val *val) -{ - const struct axp2101_config *cfg = dev->config; - struct axp2101_data *data = dev->data; - uint8_t tmp; - int ret; - - if ((data->features & GAUGE_FEATURE_GAUGE) == 0) { - return -ENOTSUP; - } - - ret = i2c_reg_read_byte_dt(&cfg->i2c, AXP2101_BAT_PERCENT_DATA, &tmp); - if (ret < 0) { - return ret; - } - - val->relative_state_of_charge = tmp; - return 0; -} - -static int get_bat_voltage(const struct device *dev, union fuel_gauge_prop_val *val) -{ - const struct axp2101_config *cfg = dev->config; - struct axp2101_data *data = dev->data; - uint8_t h5, l8; - int ret; - - if ((data->features & GAUGE_FEATURE_GAUGE) == 0) { - return -ENOTSUP; - } - - ret = i2c_reg_read_byte_dt(&cfg->i2c, AXP2101_ADC_DATA_VBAT_H, &h5); - if (ret < 0) { - return ret; - } - - ret = i2c_reg_read_byte_dt(&cfg->i2c, AXP2101_ADC_DATA_VBAT_L, &l8); - if (ret < 0) { - return ret; - } - - val->voltage = (((h5 & GAUGE_VBAT_H_MASK) << 8) | l8) * 1000; - return 0; -} - -static int axp2101_get_prop(const struct device *dev, fuel_gauge_prop_t prop, - union fuel_gauge_prop_val *val) -{ - switch (prop) { - case FUEL_GAUGE_PRESENT_STATE: - case FUEL_GAUGE_CONNECT_STATE: - return is_battery_connect(dev, val); - case FUEL_GAUGE_VOLTAGE: - return get_bat_voltage(dev, val); - case FUEL_GAUGE_ABSOLUTE_STATE_OF_CHARGE: - case FUEL_GAUGE_RELATIVE_STATE_OF_CHARGE: - return get_battery_percent(dev, val); - default: - return -ENOTSUP; - } -} - -static int axp2101_init(const struct device *dev) -{ - struct axp2101_data *data = dev->data; - const struct axp2101_config *cfg; - int ret = 0; - - cfg = dev->config; - - if (!device_is_ready(cfg->i2c.bus)) { - LOG_ERR("Bus device is not ready"); - return -ENODEV; - } - - ret = enable_fuel_gauge(dev); - if (ret < 0) { - LOG_WRN("Failed to enable fuel gauge"); - data->features &= ~GAUGE_FEATURE_GAUGE; - } - - ret = enable_batt_detection(dev); - if (ret < 0) { - LOG_WRN("Failed to enable battery detection"); - data->features &= ~GAUGE_FEATURE_BAT_DET; - } - return 0; -} - -static DEVICE_API(fuel_gauge, axp2101_api) = { - .get_property = axp2101_get_prop, -}; - -#define AXP2101_INIT(inst) \ - static const struct axp2101_config axp2101_config_##inst = { \ - .i2c = I2C_DT_SPEC_GET(DT_PARENT(DT_INST(inst, DT_DRV_COMPAT))), \ - }; \ - static struct axp2101_data axp2101_data_##inst = { \ - .features = GAUGE_FEATURE_ALL, \ - }; \ - DEVICE_DT_INST_DEFINE(inst, &axp2101_init, NULL, &axp2101_data_##inst, \ - &axp2101_config_##inst, POST_KERNEL, \ - CONFIG_FUEL_GAUGE_INIT_PRIORITY, &axp2101_api); - -DT_INST_FOREACH_STATUS_OKAY(AXP2101_INIT) diff --git a/drivers/fuel_gauge/lc709203f/CMakeLists.txt b/drivers/fuel_gauge/lc709203f/CMakeLists.txt new file mode 100644 index 0000000000000..4944c62a33bd6 --- /dev/null +++ b/drivers/fuel_gauge/lc709203f/CMakeLists.txt @@ -0,0 +1,6 @@ +zephyr_library() + +zephyr_library_sources(lc709203f.c) + +zephyr_include_directories_ifdef(CONFIG_EMUL_LC709203F .) +zephyr_library_sources_ifdef(CONFIG_EMUL_LC709203F ./emul_lc709203f.c) diff --git a/drivers/fuel_gauge/lc709203f/Kconfig b/drivers/fuel_gauge/lc709203f/Kconfig new file mode 100644 index 0000000000000..a55a70645911c --- /dev/null +++ b/drivers/fuel_gauge/lc709203f/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Philipp Steiner +# +# SPDX-License-Identifier: Apache-2.0 + +config LC709203F + bool "LC709203F Fuel Gauge" + default y + depends on DT_HAS_ONNN_LC709203F_ENABLED + select CRC + select I2C + help + Enable I2C-based driver for LC709203F Fuel Gauge. + +config EMUL_LC709203F + bool "Emulate an LC709203F fuel gague" + default y + depends on EMUL + depends on LC709203F + help + It provides readings which follow a simple sequence, thus allowing + test code to check that things are working as expected. diff --git a/drivers/fuel_gauge/lc709203f/emul_lc709203f.c b/drivers/fuel_gauge/lc709203f/emul_lc709203f.c new file mode 100644 index 0000000000000..0935d382801d0 --- /dev/null +++ b/drivers/fuel_gauge/lc709203f/emul_lc709203f.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + * + * Emulator for lc709203f fuel gauge + */ + +#include +#define DT_DRV_COMPAT onnn_lc709203f + +#include +LOG_MODULE_REGISTER(EMUL_LC709203F); + +#include +#include +#include +#include +#include +#include + +#include "lc709203f.h" + +/* You can store as many registers as you need. + * Note: The LC709203F typically uses 16-bit registers. + */ +struct lc709203f_emul_data { + /* This emulator object (required for i2c_emul). */ + struct i2c_emul emul; + /* The I2C emulation config (pointer to our dev_config). */ + const struct i2c_emul_api *api; + /* A backing store for registers in the device. */ + uint16_t regs[0x1B]; /* or enough to hold all used registers */ +}; + +struct lc709203f_emul_cfg { + /** I2C address of emulator */ + uint16_t addr; +}; + +/* Polynomial to calculate CRC-8-ATM */ +#define LC709203F_CRC_POLYNOMIAL 0x07 + +/* Reset handler (optional). You can reset internal state here if desired. */ +static int lc709203f_emul_reset(const struct emul *target) +{ + struct lc709203f_emul_data *data = (struct lc709203f_emul_data *)target->data; + + memset(data->regs, 0, sizeof(data->regs)); + + /* Set default values for registers that your real hardware starts with */ + data->regs[LC709203F_REG_BEFORE_RSOC] = 0x0000; /* - */ + data->regs[LC709203F_REG_THERMISTOR_B] = 0x0D34; /* B -constant */ + data->regs[LC709203F_REG_INITIAL_RSOC] = 0x0000; /* - */ + data->regs[LC709203F_REG_CELL_TEMPERATURE] = 0x0BA6; /* 25.0 °C 298.2 °K -> */ + data->regs[LC709203F_REG_CELL_VOLTAGE] = 3700; /* 3.7 V in mV */ + data->regs[LC709203F_REG_CURRENT_DIRECTION] = 0x0000; /* Auto mode */ + data->regs[LC709203F_REG_APA] = 0x0000; /* - */ + data->regs[LC709203F_REG_APT] = 0x001E; /* initial value */ + data->regs[LC709203F_REG_RSOC] = 50; /* 50% battery level */ + data->regs[LC709203F_REG_CELL_ITE] = 500; /* 50.0% battery level */ + data->regs[LC709203F_REG_IC_VERSION] = 0x1234; /* Example chip ID */ + data->regs[LC709203F_REG_BAT_PROFILE] = 0x0000; /* - */ + data->regs[LC709203F_REG_ALARM_LOW_RSOC] = 0x0008; /* 8% */ + data->regs[LC709203F_REG_ALARM_LOW_VOLTAGE] = 0x0000; /* initial value */ + data->regs[LC709203F_REG_IC_POWER_MODE] = 0x0002; /* - */ + data->regs[LC709203F_REG_STATUS_BIT] = 0x0000; /* initial value */ + data->regs[LC709203F_REG_NUM_PARAMETER] = 0x0301; /* - */ + + return 0; +} + +static int emul_lc709203f_reg_write(const struct emul *target, uint8_t *buf, size_t len) +{ + struct lc709203f_emul_data *data = target->data; + const struct lc709203f_emul_cfg *lc709203f_emul_cfg = target->cfg; + const uint8_t reg = buf[0]; + const uint16_t value = sys_get_le16(&buf[1]); + const uint8_t crc = buf[3]; + uint8_t crc_buf[4]; + + crc_buf[0] = lc709203f_emul_cfg->addr << 1; + crc_buf[1] = reg; + crc_buf[2] = buf[1]; + crc_buf[3] = buf[2]; + + const uint8_t crc_calc = crc8(crc_buf, sizeof(crc_buf), LC709203F_CRC_POLYNOMIAL, 0, false); + + if (crc != crc_calc) { + LOG_ERR("CRC mismatch on reg 0x%02x", reg); + return -EIO; + } + + switch (reg) { + case LC709203F_REG_RSOC: + data->regs[LC709203F_REG_RSOC] = value; + data->regs[LC709203F_REG_CELL_ITE] = value / 10; + break; + case LC709203F_REG_BEFORE_RSOC: + case LC709203F_REG_THERMISTOR_B: + case LC709203F_REG_INITIAL_RSOC: + case LC709203F_REG_CELL_TEMPERATURE: + case LC709203F_REG_CURRENT_DIRECTION: + case LC709203F_REG_APA: + case LC709203F_REG_APT: + case LC709203F_REG_BAT_PROFILE: + case LC709203F_REG_ALARM_LOW_RSOC: + case LC709203F_REG_ALARM_LOW_VOLTAGE: + case LC709203F_REG_IC_POWER_MODE: + case LC709203F_REG_STATUS_BIT: + data->regs[reg] = value; + break; + default: + LOG_ERR("Unknown or read only register 0x%x write", reg); + return -EIO; + } + + LOG_INF("write 0x%x", reg); + return 0; +} + +static int emul_lc709203f_reg_read(const struct emul *target, int reg, uint8_t *buf, size_t len) +{ + struct lc709203f_emul_data *data = target->data; + const struct lc709203f_emul_cfg *lc709203f_emul_cfg = target->cfg; + uint16_t val = 0; + + switch (reg) { + case LC709203F_REG_CELL_TEMPERATURE: + if (data->regs[LC709203F_REG_STATUS_BIT] == 0x0000) { + LOG_ERR("Temperature obtaining method is not set to Thermistor mode, " + "instead its set to I2C mode"); + return -EIO; + } + case LC709203F_REG_THERMISTOR_B: + case LC709203F_REG_CELL_VOLTAGE: + case LC709203F_REG_CURRENT_DIRECTION: + case LC709203F_REG_APA: + case LC709203F_REG_APT: + case LC709203F_REG_RSOC: + case LC709203F_REG_CELL_ITE: + case LC709203F_REG_IC_VERSION: + case LC709203F_REG_BAT_PROFILE: + case LC709203F_REG_ALARM_LOW_RSOC: + case LC709203F_REG_ALARM_LOW_VOLTAGE: + case LC709203F_REG_IC_POWER_MODE: + case LC709203F_REG_STATUS_BIT: + case LC709203F_REG_NUM_PARAMETER: + val = data->regs[reg]; + break; + default: + LOG_ERR("Unknown or write only register 0x%x read", reg); + return -EIO; + } + + sys_put_le16(val, buf); + + uint8_t crc_buf[5]; + + /* Build buffer for CRC calculation */ + crc_buf[0] = lc709203f_emul_cfg->addr << 1; + crc_buf[1] = reg; + crc_buf[2] = (lc709203f_emul_cfg->addr << 1) | 0x01; + crc_buf[3] = buf[0]; /* LSB */ + crc_buf[4] = buf[1]; /* MSB */ + + /* Calculate CRC and write it into the receive buffer */ + buf[2] = crc8(crc_buf, sizeof(crc_buf), LC709203F_CRC_POLYNOMIAL, 0, false); + + return 0; +} + +static int lc709203f_emul_transfer_i2c(const struct emul *target, struct i2c_msg *msgs, + int num_msgs, int addr) +{ + int reg; + + __ASSERT_NO_MSG(msgs && num_msgs); + + i2c_dump_msgs_rw(target->dev, msgs, num_msgs, addr, false); + switch (num_msgs) { + case 1: + if (msgs->flags & I2C_MSG_READ) { + LOG_ERR("Unexpected read"); + return -EIO; + } + + if (msgs->len == 4) { + return emul_lc709203f_reg_write(target, msgs->buf, msgs->len); + } + + LOG_ERR("Unexpected msg length %d", msgs->len); + return -EIO; + + case 2: + if (msgs->flags & I2C_MSG_READ) { + LOG_ERR("Unexpected read"); + return -EIO; + } + if (msgs->len != 1) { + LOG_ERR("Unexpected msg0 length %d", msgs->len); + return -EIO; + } + reg = msgs->buf[0]; + + /* Now process the 'read' part of the message */ + msgs++; + if (msgs->flags & I2C_MSG_READ) { + if (msgs->len == 3) { + return emul_lc709203f_reg_read(target, reg, msgs->buf, msgs->len); + } + + LOG_ERR("Unexpected msg length %d", msgs->len); + return -EIO; + } + LOG_ERR("Second message must be an I2C write"); + return -EIO; + default: + LOG_ERR("Invalid number of messages: %d", num_msgs); + return -EIO; + } + + return 0; +} +/* The I2C emulator API required by Zephyr. */ +static const struct i2c_emul_api lc709203f_emul_api_i2c = { + .transfer = lc709203f_emul_transfer_i2c, +}; + +#ifdef CONFIG_ZTEST +#include + +/* Add test reset handlers in when using emulators with tests */ +#define LC709203F_EMUL_RESET_RULE_BEFORE(inst) lc709203f_emul_reset(EMUL_DT_GET(DT_DRV_INST(inst))); + +static void lc709203f_gauge_reset_rule_after(const struct ztest_unit_test *test, void *data) +{ + ARG_UNUSED(test); + ARG_UNUSED(data); + + DT_INST_FOREACH_STATUS_OKAY(LC709203F_EMUL_RESET_RULE_BEFORE) +} +ZTEST_RULE(lc709203f_gauge_reset, NULL, lc709203f_gauge_reset_rule_after); +#endif /* CONFIG_ZTEST */ + +/** + * Set up a new emulator (I2C) + * + * @param emul Emulation information + * @param parent Device to emulate + * @return 0 indicating success (always) + */ +static int lc709203f_emul_init(const struct emul *target, const struct device *parent) +{ + ARG_UNUSED(parent); + lc709203f_emul_reset(target); + return 0; +} + +/* + * Main instantiation macro. + */ +#define DEFINE_LC709203F_EMUL(n) \ + static struct lc709203f_emul_data lc709203f_emul_data_##n; \ + static const struct lc709203f_emul_cfg lc709203f_emul_cfg_##n = { \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DT_INST_DEFINE(n, lc709203f_emul_init, &lc709203f_emul_data_##n, \ + &lc709203f_emul_cfg_##n, &lc709203f_emul_api_i2c, NULL) + +DT_INST_FOREACH_STATUS_OKAY(DEFINE_LC709203F_EMUL); diff --git a/drivers/fuel_gauge/lc709203f/lc709203f.c b/drivers/fuel_gauge/lc709203f/lc709203f.c new file mode 100644 index 0000000000000..1ae794de0bb0f --- /dev/null +++ b/drivers/fuel_gauge/lc709203f/lc709203f.c @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + * + * Zephyr driver for LC709203F Battery Monitor + * + * This driver implements the sensor API for the LC709203F battery monitor, + * providing battery voltage, state-of-charge (SOC), and temperature measurements. + * + * Note: + * - The LC709203F is assumed to be connected via I2C. + * - The register addresses and conversion factors used here are based on + * common LC709203F implementations. Consult your datasheet and adjust as needed. + * - To use this driver, create a matching device tree node (with a "compatible" + * string, I2C bus, and register address) so that the DT_INST_* macros can pick it up. + * - The LC chip works best when queried every few seconds at the fastest. Don't disconnect the LiPo + * battery, it is used to power the LC chip! + */ + +#define DT_DRV_COMPAT onnn_lc709203f + +#include "lc709203f.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(lc709203f); + +/* Battery temperature source */ +enum lc709203f_temp_mode { + LC709203F_TEMPERATURE_I2C = 0x0000, + LC709203F_TEMPERATURE_THERMISTOR = 0x0001, +}; + +/* Chip power state */ +enum lc709203f_power_mode { + LC709203F_POWER_MODE_OPERATIONAL = 0x0001, + LC709203F_POWER_MODE_SLEEP = 0x0002, +}; + +/* Current Direction Auto/Charge/Discharge mode */ +enum lc709203f_current_direction { + LC709203F_DIRECTION_AUTO = 0x0000, + LC709203F_DIRECTION_CHARGE = 0x0001, + LC709203F_DIRECTION_DISCHARGE = 0xFFFF, +}; + +/* Selects a battery profile */ +enum lc709203f_battery_profile { + LC709203F_BATTERY_PROFILE_0 = 0x0000, + LC709203F_BATTERY_PROFILE_1 = 0x0001, +}; + +/* Approx battery pack size. Pick the closest of the following values for your battery size. */ +enum lc709203f_battery_apa { + LC709203F_APA_100MAH = 0x08, + LC709203F_APA_200MAH = 0x0B, + LC709203F_APA_500MAH = 0x10, + LC709203F_APA_1000MAH = 0x19, + LC709203F_APA_2000MAH = 0x2D, + LC709203F_APA_3000MAH = 0x36, +}; + +struct lc709203f_config { + struct i2c_dt_spec i2c; + bool initial_rsoc; + char *battery_apa; + enum lc709203f_battery_profile battery_profile; + bool thermistor; + int thermistor_b_value; + int thermistor_apt; + enum lc709203f_temp_mode thermistor_mode; +}; + +#define LC709203F_INIT_RSOC_VAL 0xAA55 /* RSOC initialization value */ +#define LC709203F_CRC_POLYNOMIAL 0x07 /* Polynomial to calculate CRC-8-ATM */ + +static int lc709203f_read_word(const struct device *dev, uint8_t reg, uint16_t *value); +static int lc709203f_write_word(const struct device *dev, uint8_t reg, uint16_t value); + +static int lc709203f_get_alarm_low_rsoc(const struct device *dev, uint8_t *rsoc); +static int lc709203f_get_alarm_low_voltage(const struct device *dev, uint16_t *voltage); +static int lc709203f_get_apa(const struct device *dev, enum lc709203f_battery_apa *apa); +static int lc709203f_get_cell_temperature(const struct device *dev, uint16_t *temperature); +static int lc709203f_get_cell_voltage(const struct device *dev, uint16_t *voltage); +static int lc709203f_get_current_direction(const struct device *dev, + enum lc709203f_current_direction *direction); +static int lc709203f_get_power_mode(const struct device *dev, enum lc709203f_power_mode *mode); +static int lc709203f_get_rsoc(const struct device *dev, uint8_t *rsoc); + +static int lc709203f_set_initial_rsoc(const struct device *dev); +static int lc709203f_set_alarm_low_rsoc(const struct device *dev, uint8_t rsoc); +static int lc709203f_set_alarm_low_voltage(const struct device *dev, uint16_t voltage); +static int lc709203f_set_apa(const struct device *dev, enum lc709203f_battery_apa apa); +static int lc709203f_set_apt(const struct device *dev, uint16_t apt); +static int lc709203f_set_battery_profile(const struct device *dev, + enum lc709203f_battery_profile profile); +static int lc709203f_set_current_direction(const struct device *dev, + enum lc709203f_current_direction direction); +static int lc709203f_set_power_mode(const struct device *dev, enum lc709203f_power_mode mode); +static int lc709203f_set_temp_mode(const struct device *dev, enum lc709203f_temp_mode mode); +static int lc709203f_set_thermistor_b(const struct device *dev, uint16_t value); + +/* + * Read a 16-bit register value (with CRC check). + * + * The LC709203F expects the following transaction: + * Write: [reg] + * Read: [LSB, MSB, CRC] + * + * The CRC is computed over: + * [I2C_addr (write), reg, I2C_addr (read), LSB, MSB] + */ +static int lc709203f_read_word(const struct device *dev, uint8_t reg, uint16_t *value) +{ + const struct lc709203f_config *config = dev->config; + uint8_t buf[3]; + int ret; + + ret = i2c_write_read_dt(&config->i2c, ®, sizeof(reg), buf, sizeof(buf)); + if (ret) { + LOG_ERR("i2c_write_read failed (reg 0x%02x): %d", reg, ret); + return ret; + } + + uint8_t crc_buf[5]; + + /* Build buffer for CRC calculation */ + crc_buf[0] = config->i2c.addr << 1; + crc_buf[1] = reg; + crc_buf[2] = (config->i2c.addr << 1) | 0x01; + crc_buf[3] = buf[0]; /* LSB */ + crc_buf[4] = buf[1]; /* MSB */ + + uint8_t crc = crc8(crc_buf, sizeof(crc_buf), LC709203F_CRC_POLYNOMIAL, 0, false); + + if (crc != buf[2]) { + LOG_ERR("CRC mismatch on reg 0x%02x", reg); + return -EIO; + } + + if (value) { + *value = sys_get_le16(buf); /* LSB, MSB */ + } + + return 0; +} + +/* + * Write a 16-bit word to a register (with CRC appended). + * + * The transaction is: + * Write: [reg, LSB, MSB, CRC] + * + * The CRC is computed over: + * [I2C_addr (write), reg, LSB, MSB] + */ +static int lc709203f_write_word(const struct device *dev, uint8_t reg, uint16_t value) +{ + const struct lc709203f_config *config = dev->config; + uint8_t crc_buf[4]; + uint8_t write_buf[4]; + + crc_buf[0] = config->i2c.addr << 1; + crc_buf[1] = reg; + sys_put_le16(value, &crc_buf[2]); /* LSB, MSB */ + + write_buf[0] = reg; + sys_put_le16(value, &write_buf[1]); /* LSB, MSB */ + write_buf[3] = crc8(crc_buf, sizeof(crc_buf), LC709203F_CRC_POLYNOMIAL, 0, false); + + return i2c_write_dt(&config->i2c, write_buf, sizeof(write_buf)); +} + +static int lc709203f_get_alarm_low_rsoc(const struct device *dev, uint8_t *rsoc) +{ + uint16_t tmp; + int ret; + + if (!dev || !rsoc) { + return -EINVAL; + } + + ret = lc709203f_read_word(dev, LC709203F_REG_ALARM_LOW_RSOC, &tmp); + if (ret) { + return ret; + } + + *rsoc = (uint8_t)tmp; + return 0; +} + +static int lc709203f_get_alarm_low_voltage(const struct device *dev, uint16_t *voltage) +{ + if (!dev || !voltage) { + return -EINVAL; + } + return lc709203f_read_word(dev, LC709203F_REG_ALARM_LOW_VOLTAGE, voltage); +} + +static int lc709203f_get_apa(const struct device *dev, enum lc709203f_battery_apa *apa) +{ + uint16_t tmp; + int ret; + + if (!dev || !apa) { + return -EINVAL; + } + + ret = lc709203f_read_word(dev, LC709203F_REG_APA, &tmp); + if (ret) { + return ret; + } + + *apa = (enum lc709203f_battery_apa)tmp; + return 0; +} + +static int lc709203f_get_cell_temperature(const struct device *dev, uint16_t *temperature) +{ + if (!dev || !temperature) { + return -EINVAL; + } + return lc709203f_read_word(dev, LC709203F_REG_CELL_TEMPERATURE, temperature); +} + +static int lc709203f_get_cell_voltage(const struct device *dev, uint16_t *voltage) +{ + if (!dev || !voltage) { + return -EINVAL; + } + return lc709203f_read_word(dev, LC709203F_REG_CELL_VOLTAGE, voltage); +} + +static int lc709203f_get_current_direction(const struct device *dev, + enum lc709203f_current_direction *direction) +{ + uint16_t tmp; + int ret; + + if (!dev || !direction) { + return -EINVAL; + } + + ret = lc709203f_read_word(dev, LC709203F_REG_CURRENT_DIRECTION, &tmp); + if (ret) { + return ret; + } + + *direction = (enum lc709203f_current_direction)tmp; + return 0; +} + +static int lc709203f_get_power_mode(const struct device *dev, enum lc709203f_power_mode *mode) +{ + uint16_t tmp; + int ret; + + if (!dev || !mode) { + return -EINVAL; + } + + ret = lc709203f_read_word(dev, LC709203F_REG_IC_POWER_MODE, &tmp); + if (ret) { + return ret; + } + + *mode = (enum lc709203f_power_mode)tmp; + return 0; +} + +static int lc709203f_get_rsoc(const struct device *dev, uint8_t *rsoc) +{ + uint16_t tmp; + int ret; + + if (!dev || !rsoc) { + return -EINVAL; + } + + ret = lc709203f_read_word(dev, LC709203F_REG_RSOC, &tmp); + if (ret) { + return ret; + } + + *rsoc = (uint8_t)tmp; + return 0; +} + +static int lc709203f_set_initial_rsoc(const struct device *dev) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_INITIAL_RSOC, LC709203F_INIT_RSOC_VAL); +} + +static int lc709203f_set_alarm_low_rsoc(const struct device *dev, uint8_t rsoc) +{ + if (!dev) { + return -EINVAL; + } + if (rsoc > 100) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_ALARM_LOW_RSOC, rsoc); +} + +static int lc709203f_set_alarm_low_voltage(const struct device *dev, uint16_t voltage) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_ALARM_LOW_VOLTAGE, voltage); +} + +static int lc709203f_set_apa(const struct device *dev, enum lc709203f_battery_apa apa) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_APA, (uint16_t)apa); +} + +static int lc709203f_set_apt(const struct device *dev, uint16_t apt) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_APT, apt); +} + +static int lc709203f_set_battery_profile(const struct device *dev, + enum lc709203f_battery_profile profile) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_BAT_PROFILE, (uint16_t)profile); +} + +static int lc709203f_set_current_direction(const struct device *dev, + enum lc709203f_current_direction direction) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_CURRENT_DIRECTION, (uint16_t)direction); +} + +static int lc709203f_set_power_mode(const struct device *dev, enum lc709203f_power_mode mode) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_IC_POWER_MODE, (uint16_t)mode); +} + +static int lc709203f_set_temp_mode(const struct device *dev, enum lc709203f_temp_mode mode) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_STATUS_BIT, (uint16_t)mode); +} + +static int lc709203f_set_thermistor_b(const struct device *dev, uint16_t value) +{ + if (!dev) { + return -EINVAL; + } + return lc709203f_write_word(dev, LC709203F_REG_THERMISTOR_B, value); +} + +enum lc709203f_battery_apa lc709203f_string_to_apa(const char *apa_string) +{ + static const char *const apas[] = {"100mAh", "200mAh", "500mAh", + "1000mAh", "2000mAh", "3000mAh"}; + + static const enum lc709203f_battery_apa apa_values[] = { + LC709203F_APA_100MAH, LC709203F_APA_200MAH, LC709203F_APA_500MAH, + LC709203F_APA_1000MAH, LC709203F_APA_2000MAH, LC709203F_APA_3000MAH}; + + /* Check if the string is NULL or empty */ + for (size_t i = 0; i < ARRAY_SIZE(apas); i++) { + if (strncmp(apa_string, apas[i], strlen(apas[i])) == 0) { + return apa_values[i]; + } + } + LOG_ERR("Invalid apa_string: %s, returning default: %d", apa_string, LC709203F_APA_100MAH); + return LC709203F_APA_100MAH; +} + +enum lc709203f_power_mode lc709203f_num_to_power_mode(uint16_t num) +{ + switch (num) { + case 1: + return LC709203F_POWER_MODE_OPERATIONAL; + case 2: + return LC709203F_POWER_MODE_SLEEP; + default: + LOG_ERR("Invalid power mode: %d", num); + return LC709203F_POWER_MODE_OPERATIONAL; + } +} + +enum lc709203f_current_direction lc709203f_num_to_current_direction(uint16_t num) +{ + switch (num) { + case 0: + return LC709203F_DIRECTION_AUTO; + case 1: + return LC709203F_DIRECTION_CHARGE; + case 0xFFFF: + return LC709203F_DIRECTION_DISCHARGE; + default: + LOG_ERR("Invalid current direction: %d", num); + return LC709203F_DIRECTION_AUTO; + } +} + +/* + * Device initialization function. + */ +static int lc709203f_init(const struct device *dev) +{ + const struct lc709203f_config *config = dev->config; + int ret = 0; + + if (!device_is_ready(config->i2c.bus)) { + LOG_ERR("I2C bus not ready"); + return -ENODEV; + } + + enum lc709203f_power_mode mode = LC709203F_POWER_MODE_OPERATIONAL; + + LOG_INF("Get power mode"); + ret = lc709203f_get_power_mode(dev, &mode); + if (ret) { + LOG_ERR("Failed to get power mode: %d", ret); + } + + LOG_INF("Power mode: %d", mode); + if (mode == LC709203F_POWER_MODE_SLEEP) { + LOG_INF("Set Power mode"); + ret = lc709203f_set_power_mode(dev, LC709203F_POWER_MODE_OPERATIONAL); + + if (ret) { + LOG_ERR("Failed to set power mode: %d", ret); + } + } + + LOG_INF("Set battery pack: %s", config->battery_apa); + ret = lc709203f_set_apa(dev, lc709203f_string_to_apa(config->battery_apa)); + + if (ret) { + LOG_ERR("Failed to set battery pack: %d", ret); + } + + LOG_INF("Set battery profile: %d", config->battery_profile); + ret = lc709203f_set_battery_profile(dev, config->battery_profile); + + if (ret) { + LOG_ERR("Failed to set battery profile: %d", ret); + } + + if (config->thermistor) { + LOG_INF("Set temperature mode: %d", config->thermistor_mode); + lc709203f_set_temp_mode(dev, config->thermistor_mode); + if (ret) { + LOG_ERR("Failed to set temperature mode: %d", ret); + } + + LOG_INF("Set thermistor B value: %d", config->thermistor_b_value); + ret = lc709203f_set_thermistor_b(dev, config->thermistor_b_value); + + if (ret) { + LOG_ERR("Failed to set thermistor B value: %d", ret); + } + + LOG_INF("Set thermistor APT: %d", config->thermistor_apt); + ret = lc709203f_set_apt(dev, config->thermistor_apt); + + if (ret) { + LOG_ERR("Failed to set thermistor APT: %d", ret); + } + } + + if (config->initial_rsoc) { + LOG_INF("lc709203f_set_initial_rsoc"); + ret = lc709203f_set_initial_rsoc(dev); + + if (ret) { + LOG_ERR("Quickstart failed: %d", ret); + return ret; + } + } + + LOG_INF("initialized"); + return 0; +} + +static int lc709203f_get_prop(const struct device *dev, fuel_gauge_prop_t prop, + union fuel_gauge_prop_val *val) +{ + int rc = 0; + uint16_t tmp_val = 0; + const struct lc709203f_config *config = dev->config; + + switch (prop) { + case FUEL_GAUGE_RELATIVE_STATE_OF_CHARGE: + rc = lc709203f_get_rsoc(dev, &val->relative_state_of_charge); + break; + case FUEL_GAUGE_TEMPERATURE: + if (!config->thermistor) { + LOG_ERR("Thermistor not enabled"); + return -ENOTSUP; + } + rc = lc709203f_get_cell_temperature(dev, &val->temperature); + break; + case FUEL_GAUGE_VOLTAGE: + rc = lc709203f_get_cell_voltage(dev, &tmp_val); + val->voltage = tmp_val * 1000; + break; + case FUEL_GAUGE_SBS_MODE: + rc = lc709203f_get_power_mode(dev, (enum lc709203f_power_mode *)&val->sbs_mode); + break; + case FUEL_GAUGE_DESIGN_CAPACITY: + enum lc709203f_battery_apa apa = LC709203F_APA_100MAH; + + rc = lc709203f_get_apa(dev, &apa); + + switch (apa) { + case LC709203F_APA_100MAH: + val->design_cap = 100; + break; + case LC709203F_APA_200MAH: + val->design_cap = 200; + break; + case LC709203F_APA_500MAH: + val->design_cap = 500; + break; + case LC709203F_APA_1000MAH: + val->design_cap = 1000; + break; + case LC709203F_APA_2000MAH: + val->design_cap = 2000; + break; + case LC709203F_APA_3000MAH: + val->design_cap = 3000; + break; + default: + LOG_ERR("Invalid battery capacity: %d", apa); + return -EINVAL; + } + break; + case FUEL_GAUGE_CURRENT_DIRECTION: + rc = lc709203f_get_current_direction( + dev, (enum lc709203f_current_direction *)&val->current_direction); + break; + case FUEL_GAUGE_STATE_OF_CHARGE_ALARM: + rc = lc709203f_get_alarm_low_rsoc(dev, &val->state_of_charge_alarm); + break; + case FUEL_GAUGE_LOW_VOLTAGE_ALARM: + rc = lc709203f_get_alarm_low_voltage(dev, &tmp_val); + val->low_voltage_alarm = tmp_val * 1000; + break; + default: + rc = -ENOTSUP; + break; + } + + return rc; +} + +static int lc709203f_set_prop(const struct device *dev, fuel_gauge_prop_t prop, + union fuel_gauge_prop_val val) +{ + int rc = 0; + + switch (prop) { + case FUEL_GAUGE_SBS_MODE: + rc = lc709203f_set_power_mode(dev, lc709203f_num_to_power_mode(val.sbs_mode)); + break; + case FUEL_GAUGE_CURRENT_DIRECTION: + rc = lc709203f_set_current_direction( + dev, lc709203f_num_to_current_direction(val.current_direction)); + break; + case FUEL_GAUGE_STATE_OF_CHARGE_ALARM: + rc = lc709203f_set_alarm_low_rsoc(dev, val.state_of_charge_alarm); + break; + case FUEL_GAUGE_LOW_VOLTAGE_ALARM: + rc = lc709203f_set_alarm_low_voltage(dev, val.low_voltage_alarm / 1000); + break; + default: + rc = -ENOTSUP; + break; + } + + return rc; +} + +static DEVICE_API(fuel_gauge, lc709203f_driver_api) = { + .get_property = &lc709203f_get_prop, + .set_property = &lc709203f_set_prop, +}; + +#define LC709203F_INIT(inst) \ + \ + static const struct lc709203f_config lc709203f_config_##inst = { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + .initial_rsoc = DT_INST_PROP(inst, initial_rsoc), \ + .battery_apa = DT_INST_PROP(inst, apa), \ + .battery_profile = DT_INST_PROP(inst, battery_profile), \ + .thermistor = DT_INST_PROP(inst, thermistor), \ + .thermistor_b_value = DT_INST_PROP(inst, thermistor_b_value), \ + .thermistor_apt = DT_INST_PROP(inst, apt), \ + .thermistor_mode = DT_INST_PROP(inst, thermistor_mode), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, &lc709203f_init, NULL, NULL, &lc709203f_config_##inst, \ + POST_KERNEL, CONFIG_FUEL_GAUGE_INIT_PRIORITY, \ + &lc709203f_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(LC709203F_INIT) diff --git a/drivers/fuel_gauge/lc709203f/lc709203f.h b/drivers/fuel_gauge/lc709203f/lc709203f.h new file mode 100644 index 0000000000000..36d880c9c4bec --- /dev/null +++ b/drivers/fuel_gauge/lc709203f/lc709203f.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_LC709203F_LC709203F_H_ +#define ZEPHYR_DRIVERS_SENSOR_LC709203F_LC709203F_H_ + +#include + +enum lc709203f_regs { + LC709203F_REG_BEFORE_RSOC = 0x04, /* Initialize before RSOC */ + LC709203F_REG_THERMISTOR_B = 0x06, /* Read/write thermistor B */ + LC709203F_REG_INITIAL_RSOC = 0x07, /* Initialize RSOC calculation */ + LC709203F_REG_CELL_TEMPERATURE = 0x08, /* Read/write cell temperature */ + LC709203F_REG_CELL_VOLTAGE = 0x09, /* Read batt voltage */ + LC709203F_REG_CURRENT_DIRECTION = 0x0A, /* Read/write current direction */ + LC709203F_REG_APA = 0x0B, /* Adjustment Pack Application */ + LC709203F_REG_APT = 0x0C, /* Read/write Adjustment Pack Thermistor */ + LC709203F_REG_RSOC = 0x0D, /* Read state of charge; 1% 0−100 scale */ + LC709203F_REG_CELL_ITE = 0x0F, /* Read batt indicator to empty */ + LC709203F_REG_IC_VERSION = 0x11, /* Read IC version */ + LC709203F_REG_BAT_PROFILE = 0x12, /* Set the battery profile */ + LC709203F_REG_ALARM_LOW_RSOC = 0x13, /* Alarm on percent threshold */ + LC709203F_REG_ALARM_LOW_VOLTAGE = 0x14, /* Alarm on voltage threshold */ + LC709203F_REG_IC_POWER_MODE = 0x15, /* Sets sleep/power mode */ + LC709203F_REG_STATUS_BIT = 0x16, /* Temperature obtaining method */ + LC709203F_REG_NUM_PARAMETER = 0x1A /* Batt profile code */ +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_LC709203F_LC709203F_H_ */ diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 728a883e1093c..195ce116e8295 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -61,7 +61,6 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_LPC gpio_mcux_lpc.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_RGPIO gpio_mcux_rgpio.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MFXSTM32L152 gpio_mfxstm32l152.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MMIO32 gpio_mmio32.c) -zephyr_library_sources_ifdef(CONFIG_GPIO_MSPM0 gpio_mspm0.c) zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX gpio_nct38xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX gpio_nct38xx_port.c) zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX_ALERT gpio_nct38xx_alert.c) @@ -83,7 +82,6 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c) -zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RX gpio_renesas_rx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZ gpio_renesas_rz.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZA2M gpio_renesas_rza2m.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RP1 gpio_rp1.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e95aded5613a8..486f81467293b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -149,7 +149,6 @@ source "drivers/gpio/Kconfig.mcux_rgpio" source "drivers/gpio/Kconfig.mec5" source "drivers/gpio/Kconfig.mfxstm32l152" source "drivers/gpio/Kconfig.mmio32" -source "drivers/gpio/Kconfig.mspm0" source "drivers/gpio/Kconfig.nct38xx" source "drivers/gpio/Kconfig.neorv32" source "drivers/gpio/Kconfig.npcx" @@ -169,7 +168,6 @@ source "drivers/gpio/Kconfig.pcf857x" source "drivers/gpio/Kconfig.psoc6" source "drivers/gpio/Kconfig.rcar" source "drivers/gpio/Kconfig.renesas_ra_ioport" -source "drivers/gpio/Kconfig.renesas_rx" source "drivers/gpio/Kconfig.renesas_rz" source "drivers/gpio/Kconfig.renesas_rza2m" source "drivers/gpio/Kconfig.rp1" diff --git a/drivers/gpio/Kconfig.mspm0 b/drivers/gpio/Kconfig.mspm0 deleted file mode 100644 index 719b3511c7944..0000000000000 --- a/drivers/gpio/Kconfig.mspm0 +++ /dev/null @@ -1,12 +0,0 @@ -# TI MSPM0 GPIO configuration options - -# Copyright (c) 2025 Texas Instruments -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_MSPM0 - bool "TI MSPM0 GPIO driver" - default y - depends on DT_HAS_TI_MSPM0_GPIO_ENABLED - select USE_MSPM0_DL_GPIO - help - Enable the TI MSPM0 GPIO driver. diff --git a/drivers/gpio/Kconfig.renesas_rx b/drivers/gpio/Kconfig.renesas_rx deleted file mode 100644 index efd08ee0c1794..0000000000000 --- a/drivers/gpio/Kconfig.renesas_rx +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_RENESAS_RX - bool "Renesas RX GPIO driver" - default y - depends on DT_HAS_RENESAS_RX_GPIO_ENABLED - select PINCTRL - help - Enable the Renesas RX GPIO driver. diff --git a/drivers/gpio/Kconfig.sn74hc595 b/drivers/gpio/Kconfig.sn74hc595 index ea3add9c6238b..0ade0adb38d95 100644 --- a/drivers/gpio/Kconfig.sn74hc595 +++ b/drivers/gpio/Kconfig.sn74hc595 @@ -2,12 +2,12 @@ # SPDX-License-Identifier: Apache-2.0 config GPIO_SN74HC595 - bool "SN74HC595 shift register as GPIO expander" + bool "SN74HC595 shift register as GPIO extender" default y depends on DT_HAS_TI_SN74HC595_ENABLED depends on SPI help - Use SN74HC595 as GPIO expander + Use SN74HC595 as GPIO extender if GPIO_SN74HC595 diff --git a/drivers/gpio/gpio_davinci.c b/drivers/gpio/gpio_davinci.c index 35be3975c677a..a116831100290 100644 --- a/drivers/gpio/gpio_davinci.c +++ b/drivers/gpio/gpio_davinci.c @@ -33,8 +33,7 @@ LOG_MODULE_REGISTER(gpio_davinci, CONFIG_GPIO_LOG_LEVEL); #define GPIO_DAVINCI_DIR_RESET_VAL (0xFFFFFFFF) struct gpio_davinci_regs { - uint32_t UNUSED[4]; /* 0x00-0x0C */ - uint32_t dir; /* 0x10 */ + uint32_t dir; uint32_t out_data; uint32_t set_data; uint32_t clr_data; @@ -153,14 +152,17 @@ static DEVICE_API(gpio, gpio_davinci_driver_api) = { static int gpio_davinci_init(const struct device *dev) { const struct gpio_davinci_config *config = DEV_CFG(dev); + volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); int ret; DEVICE_MMIO_NAMED_MAP(dev, port_base, K_MEM_CACHE_NONE); + regs->dir = GPIO_DAVINCI_DIR_RESET_VAL; + config->bank_config(dev); ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0 && ret != -ENOENT) { + if (ret < 0) { LOG_ERR("failed to apply pinctrl"); return ret; } @@ -171,7 +173,7 @@ static int gpio_davinci_init(const struct device *dev) static void gpio_davinci_bank_##n##_config(const struct device *dev) \ { \ volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); \ - regs->dir = GPIO_DAVINCI_DIR_RESET_VAL; \ + ARG_UNUSED(regs); \ } #define GPIO_DAVINCI_INIT(n) \ diff --git a/drivers/gpio/gpio_ifx_cat1.c b/drivers/gpio/gpio_ifx_cat1.c index a7b804213d27a..5e205db45221b 100644 --- a/drivers/gpio/gpio_ifx_cat1.c +++ b/drivers/gpio/gpio_ifx_cat1.c @@ -203,7 +203,7 @@ static int gpio_cat1_pin_interrupt_configure(const struct device *dev, gpio_pin_ break; default: - break; + return -ENOTSUP; } Cy_GPIO_SetInterruptEdge(base, pin, trig_pdl); diff --git a/drivers/gpio/gpio_ite_it51xxx.c b/drivers/gpio/gpio_ite_it51xxx.c index 363dcb7a8266f..daa49180c5fe9 100644 --- a/drivers/gpio/gpio_ite_it51xxx.c +++ b/drivers/gpio/gpio_ite_it51xxx.c @@ -22,7 +22,6 @@ LOG_MODULE_REGISTER(gpio_ite_it51xxx, LOG_LEVEL_ERR); #define IT515XX_GPIO_MAX_PINS 8 -#define IT515XX_GPxyVS BIT(3) struct it51xxx_gpio_wuc_map_cfg { /* WUC control device structure */ @@ -47,7 +46,7 @@ struct gpio_ite_cfg { /* GPIO port output type register (bit mapping to pin) */ uintptr_t reg_gpotr; /* GPIO port 1.8V select register (bit mapping to pin) */ - uintptr_t reg_gpxycr1; + uintptr_t reg_p18scr; /* GPIO port control register (byte mapping to pin) */ uintptr_t reg_gpcr; /* GPIO/KBS function selection register (bit mapping to pin) */ @@ -124,15 +123,14 @@ static int gpio_ite_configure(const struct device *dev, gpio_pin_t pin, gpio_fla /* 1.8V or 3.3V */ if (config->has_volt_sel[pin]) { gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK; - mm_reg_t reg_gpxycr1_pin = config->reg_gpxycr1 + (pin * 2); if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) { __ASSERT(!(flags & GPIO_PULL_UP), "Don't enable internal pullup if 1.8V voltage is used"); - sys_write8(sys_read8(reg_gpxycr1_pin) | IT515XX_GPxyVS, reg_gpxycr1_pin); + sys_write8(sys_read8(config->reg_p18scr) | mask, config->reg_p18scr); data->volt_default_set &= ~mask; } else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) { - sys_write8(sys_read8(reg_gpxycr1_pin) & ~IT515XX_GPxyVS, reg_gpxycr1_pin); + sys_write8(sys_read8(config->reg_p18scr) & ~mask, config->reg_p18scr); /* * A variable is needed to store the difference between * 3.3V and default so that the flag can be distinguished @@ -140,7 +138,7 @@ static int gpio_ite_configure(const struct device *dev, gpio_pin_t pin, gpio_fla */ data->volt_default_set &= ~mask; } else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) { - sys_write8(sys_read8(reg_gpxycr1_pin) & ~IT515XX_GPxyVS, reg_gpxycr1_pin); + sys_write8(sys_read8(config->reg_p18scr) & ~mask, config->reg_p18scr); data->volt_default_set |= mask; } else { rc = -EINVAL; @@ -193,7 +191,6 @@ static int gpio_ite_get_config(const struct device *dev, gpio_pin_t pin, gpio_fl { const struct gpio_ite_cfg *config = dev->config; struct gpio_ite_data *data = dev->data; - mm_reg_t reg_gpxycr1_pin = config->reg_gpxycr1 + (pin * 2); uint8_t mask = BIT(pin); gpio_flags_t flags = 0; @@ -208,7 +205,7 @@ static int gpio_ite_get_config(const struct device *dev, gpio_pin_t pin, gpio_fl if (data->volt_default_set & mask) { flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT; } else { - if (sys_read8(reg_gpxycr1_pin) & IT515XX_GPxyVS) { + if (sys_read8(config->reg_p18scr) & mask) { flags |= IT8XXX2_GPIO_VOLTAGE_1P8; } else { flags |= IT8XXX2_GPIO_VOLTAGE_3P3; @@ -455,7 +452,7 @@ static DEVICE_API(gpio, gpio_ite_driver_api) = { .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \ .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \ .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \ - .reg_gpxycr1 = DT_INST_REG_ADDR_BY_IDX(inst, 3), \ + .reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \ .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \ .reg_ksfselr = DT_INST_REG_ADDR_BY_IDX(inst, 5), \ .gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst), \ diff --git a/drivers/gpio/gpio_mcux_lpc.c b/drivers/gpio/gpio_mcux_lpc.c index 9e3118565ae28..ab8d9981170a2 100644 --- a/drivers/gpio/gpio_mcux_lpc.c +++ b/drivers/gpio/gpio_mcux_lpc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -53,7 +52,6 @@ struct gpio_mcux_lpc_config { MCI_IO_MUX_Type * pinmux_base; #endif uint32_t port_no; - const struct pinctrl_dev_config *pincfg; }; struct gpio_mcux_lpc_data { @@ -419,7 +417,6 @@ static int gpio_mcux_lpc_manage_cb(const struct device *port, static int gpio_mcux_lpc_pm_action(const struct device *dev, enum pm_device_action action) { const struct gpio_mcux_lpc_config *config = dev->config; - int error; switch (action) { case PM_DEVICE_ACTION_RESUME: @@ -430,10 +427,6 @@ static int gpio_mcux_lpc_pm_action(const struct device *dev, enum pm_device_acti break; case PM_DEVICE_ACTION_TURN_ON: GPIO_PortInit(config->gpio_base, config->port_no); - error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); - if (error) { - return error; - } break; default: return -ENOTSUP; @@ -486,7 +479,6 @@ static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = { #define GPIO_MCUX_LPC(n) \ - PINCTRL_DT_INST_DEFINE(n); \ static int lpc_gpio_init_##n(const struct device *dev); \ \ static const struct gpio_mcux_lpc_config gpio_mcux_lpc_config_##n = { \ @@ -496,8 +488,7 @@ static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = { .gpio_base = (GPIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \ .pinmux_base = PINMUX_BASE, \ .int_source = DT_INST_ENUM_IDX(n, int_source), \ - .port_no = DT_INST_REG_ADDR(n), \ - .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n) \ + .port_no = DT_INST_REG_ADDR(n) \ }; \ \ static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n; \ diff --git a/drivers/gpio/gpio_mspm0.c b/drivers/gpio/gpio_mspm0.c deleted file mode 100644 index 87b9e429aa3c2..0000000000000 --- a/drivers/gpio/gpio_mspm0.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments - * Copyright (c) 2025 Linumiz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ti_mspm0_gpio - -/* Zephyr includes */ -#include -#include -#include - -/* Driverlib includes */ -#include - -struct gpio_mspm0_config { - /* gpio_mspm0_config needs to be first (doesn't actually get used) */ - struct gpio_driver_config common; - /* port base address */ - GPIO_Regs *base; - /* port pincm lookup table */ - uint32_t *pincm_lut; -}; - -struct gpio_mspm0_data { - /* gpio_driver_data needs to be first */ - struct gpio_driver_data common; - sys_slist_t callbacks; /* List of interrupt callbacks */ -}; - -/* Two polarity registers and HAL api used for pins (0-15) and pins (16-32) */ -#define MSPM0_PINS_LOW_GROUP 16 - -/* GPIO defines */ -#define GPIOA_NODE DT_NODELABEL(gpioa) -#if DT_NODE_HAS_STATUS(GPIOA_NODE, okay) -#if CONFIG_SOC_SERIES_MSPM0G -#define NUM_GPIOA_PIN 32 -#define gpioa_pins NUM_GPIOA_PIN -static uint32_t gpioa_pincm_lut[NUM_GPIOA_PIN] = { - IOMUX_PINCM1, IOMUX_PINCM2, IOMUX_PINCM7, IOMUX_PINCM8, IOMUX_PINCM9, IOMUX_PINCM10, - IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20, IOMUX_PINCM21, IOMUX_PINCM22, - IOMUX_PINCM34, IOMUX_PINCM35, IOMUX_PINCM36, IOMUX_PINCM37, IOMUX_PINCM38, IOMUX_PINCM39, - IOMUX_PINCM40, IOMUX_PINCM41, IOMUX_PINCM42, IOMUX_PINCM46, IOMUX_PINCM47, IOMUX_PINCM53, - IOMUX_PINCM54, IOMUX_PINCM55, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM3, IOMUX_PINCM4, - IOMUX_PINCM5, IOMUX_PINCM6, -}; -#else -#error "Series lookup table not supported" -#endif /* if CONFIG_SOC_SERIES_MSPM0G */ -#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */ - -#define GPIOB_NODE DT_NODELABEL(gpiob) -#if DT_NODE_HAS_STATUS(GPIOB_NODE, okay) -#ifdef CONFIG_SOC_SERIES_MSPM0G -#define NUM_GPIOB_PIN 28 -#define gpiob_pins NUM_GPIOB_PIN -static uint32_t gpiob_pincm_lut[NUM_GPIOB_PIN] = { - IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17, IOMUX_PINCM18, - IOMUX_PINCM23, IOMUX_PINCM24, IOMUX_PINCM25, IOMUX_PINCM26, IOMUX_PINCM27, IOMUX_PINCM28, - IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31, IOMUX_PINCM32, IOMUX_PINCM33, IOMUX_PINCM43, - IOMUX_PINCM44, IOMUX_PINCM45, IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51, - IOMUX_PINCM52, IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM58, -}; -#endif /* CONFIG_SOC_SERIES_MSPM0G */ -#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */ - -static int gpio_mspm0_port_get_raw(const struct device *port, uint32_t *value) -{ - const struct gpio_mspm0_config *config = port->config; - - /* Read entire port */ - *value = DL_GPIO_readPins(config->base, UINT32_MAX); - - return 0; -} - -static int gpio_mspm0_port_set_masked_raw(const struct device *port, - uint32_t mask, uint32_t value) -{ - const struct gpio_mspm0_config *config = port->config; - - DL_GPIO_writePinsVal(config->base, mask, value); - - return 0; -} - -static int gpio_mspm0_port_set_bits_raw(const struct device *port, - uint32_t mask) -{ - const struct gpio_mspm0_config *config = port->config; - - DL_GPIO_setPins(config->base, mask); - - return 0; -} - -static int gpio_mspm0_port_clear_bits_raw(const struct device *port, - uint32_t mask) -{ - const struct gpio_mspm0_config *config = port->config; - - DL_GPIO_clearPins(config->base, mask); - - return 0; -} - -static int gpio_mspm0_port_toggle_bits(const struct device *port, - uint32_t mask) -{ - const struct gpio_mspm0_config *config = port->config; - - DL_GPIO_togglePins(config->base, mask); - - return 0; -} - -static int gpio_mspm0_pin_configure(const struct device *port, - gpio_pin_t pin, - gpio_flags_t flags) -{ - const struct gpio_mspm0_config *config = port->config; - /* determine pull up resistor value based on flags */ - DL_GPIO_RESISTOR pull_res; - - if (flags & GPIO_PULL_UP) { - pull_res = DL_GPIO_RESISTOR_PULL_UP; - } else if (flags & GPIO_PULL_DOWN) { - pull_res = DL_GPIO_RESISTOR_PULL_DOWN; - } else { - pull_res = DL_GPIO_RESISTOR_NONE; - } - - /* Config pin based on flags */ - switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) { - case GPIO_INPUT: - DL_GPIO_initDigitalInputFeatures(config->pincm_lut[pin], - DL_GPIO_INVERSION_DISABLE, - pull_res, - DL_GPIO_HYSTERESIS_DISABLE, - DL_GPIO_WAKEUP_DISABLE); - break; - case GPIO_OUTPUT: - DL_GPIO_initDigitalOutputFeatures(config->pincm_lut[pin], - DL_GPIO_INVERSION_DISABLE, - pull_res, - DL_GPIO_DRIVE_STRENGTH_LOW, - DL_GPIO_HIZ_DISABLE); - - /* Set initial state */ - if (flags & GPIO_OUTPUT_INIT_HIGH) { - gpio_mspm0_port_set_bits_raw(port, BIT(pin)); - } else if (flags & GPIO_OUTPUT_INIT_LOW) { - gpio_mspm0_port_clear_bits_raw(port, BIT(pin)); - } - /* Enable output */ - DL_GPIO_enableOutput(config->base, BIT(pin)); - break; - case GPIO_DISCONNECTED: - DL_GPIO_disableOutput(config->base, BIT(pin)); - break; - default: - return -ENOTSUP; - } - - return 0; -} - -static int gpio_mspm0_pin_interrupt_configure(const struct device *port, - gpio_pin_t pin, - enum gpio_int_mode mode, - enum gpio_int_trig trig) -{ - const struct gpio_mspm0_config *config = port->config; - - /* Config interrupt */ - switch (mode) { - case GPIO_INT_MODE_DISABLED: - DL_GPIO_clearInterruptStatus(config->base, BIT(pin)); - DL_GPIO_disableInterrupt(config->base, BIT(pin)); - break; - case GPIO_INT_MODE_EDGE: - uint32_t polarity = 0x00; - - if (trig & GPIO_INT_TRIG_LOW) { - polarity |= BIT(0); - } - - if (trig & GPIO_INT_TRIG_HIGH) { - polarity |= BIT(1); - } - - if (pin < MSPM0_PINS_LOW_GROUP) { - DL_GPIO_setLowerPinsPolarity(config->base, - polarity << (2 * pin)); - } else { - DL_GPIO_setUpperPinsPolarity(config->base, - polarity << (2 * (pin - MSPM0_PINS_LOW_GROUP))); - } - - DL_GPIO_clearInterruptStatus(config->base, BIT(pin)); - DL_GPIO_enableInterrupt(config->base, BIT(pin)); - break; - case GPIO_INT_MODE_LEVEL: - return -ENOTSUP; - } - - return 0; -} - -static int gpio_mspm0_manage_callback(const struct device *port, - struct gpio_callback *callback, - bool set) -{ - struct gpio_mspm0_data *data = port->data; - - return gpio_manage_callback(&data->callbacks, callback, set); -} - -static uint32_t gpio_mspm0_get_pending_int(const struct device *port) -{ - const struct gpio_mspm0_config *config = port->config; - - return DL_GPIO_getPendingInterrupt(config->base); -} - -static void gpio_mspm0_isr(const struct device *port) -{ - struct gpio_mspm0_data *data; - const struct gpio_mspm0_config *config; - const struct device *dev_list[] = { - DEVICE_DT_GET_OR_NULL(GPIOA_NODE), - DEVICE_DT_GET_OR_NULL(GPIOB_NODE), - }; - - for (uint8_t i = 0; i < ARRAY_SIZE(dev_list); i++) { - uint32_t status; - - if (dev_list[i] == NULL) { - continue; - } - - data = dev_list[i]->data; - config = dev_list[i]->config; - - status = DL_GPIO_getRawInterruptStatus(config->base, - 0xFFFFFFFF); - - DL_GPIO_clearInterruptStatus(config->base, status); - if (status != 0) { - gpio_fire_callbacks(&data->callbacks, - dev_list[i], status); - } - } -} - -static int gpio_mspm0_init(const struct device *dev) -{ - const struct gpio_mspm0_config *cfg = dev->config; - static bool init_irq = true; - - /* Reset and enable GPIO banks */ - DL_GPIO_reset(cfg->base); - DL_GPIO_enablePower(cfg->base); - - /* All the interrupt port share the same irq number, do it once */ - if (init_irq) { - init_irq = false; - - IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), - gpio_mspm0_isr, DEVICE_DT_INST_GET(0), 0); - irq_enable(DT_INST_IRQN(0)); - } - - return 0; -} - -static const struct gpio_driver_api gpio_mspm0_driver_api = { - .pin_configure = gpio_mspm0_pin_configure, - .port_get_raw = gpio_mspm0_port_get_raw, - .port_set_masked_raw = gpio_mspm0_port_set_masked_raw, - .port_set_bits_raw = gpio_mspm0_port_set_bits_raw, - .port_clear_bits_raw = gpio_mspm0_port_clear_bits_raw, - .port_toggle_bits = gpio_mspm0_port_toggle_bits, - .pin_interrupt_configure = gpio_mspm0_pin_interrupt_configure, - .manage_callback = gpio_mspm0_manage_callback, - .get_pending_int = gpio_mspm0_get_pending_int, -}; - -#define GPIO_DEVICE_INIT(n, __suffix, __base_addr) \ - static const struct gpio_mspm0_config gpio_mspm0_cfg_##__suffix = { \ - .common = { .port_pin_mask = \ - GPIO_PORT_PIN_MASK_FROM_NGPIOS(gpio##__suffix##_pins), \ - }, \ - .base = (GPIO_Regs *)__base_addr, \ - .pincm_lut = gpio##__suffix##_pincm_lut, \ - }; \ - static struct gpio_mspm0_data gpio_mspm0_data_##__suffix; \ - DEVICE_DT_DEFINE(n, gpio_mspm0_init, NULL, &gpio_mspm0_data_##__suffix, \ - &gpio_mspm0_cfg_##__suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ - &gpio_mspm0_driver_api) - -#define GPIO_DEVICE_INIT_MSPM0(__suffix) \ - GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), __suffix, \ - DT_REG_ADDR(DT_NODELABEL(gpio##__suffix))) - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) -GPIO_DEVICE_INIT_MSPM0(a); -#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */ - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) -GPIO_DEVICE_INIT_MSPM0(b); -#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */ diff --git a/drivers/gpio/gpio_neorv32.c b/drivers/gpio/gpio_neorv32.c index b2a50f68d8833..90546ef1abe01 100644 --- a/drivers/gpio/gpio_neorv32.c +++ b/drivers/gpio/gpio_neorv32.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -22,19 +21,17 @@ LOG_MODULE_REGISTER(gpio_neorv32, CONFIG_GPIO_LOG_LEVEL); #include /* Register offsets */ -#define NEORV32_GPIO_PORT_IN 0x00 -#define NEORV32_GPIO_PORT_OUT 0x04 -#define NEORV32_GPIO_IRQ_TYPE 0x10 -#define NEORV32_GPIO_IRQ_POLARITY 0x14 -#define NEORV32_GPIO_IRQ_ENABLE 0x18 -#define NEORV32_GPIO_IRQ_PENDING 0x1c +#define NEORV32_GPIO_PORT_IN 0x00 +#define NEORV32_GPIO_PORT_OUT 0x04 + +/* Maximum number of GPIOs supported */ +#define MAX_GPIOS 32 struct neorv32_gpio_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; const struct device *syscon; mm_reg_t base; - void (*irq_config_func)(void); }; struct neorv32_gpio_data { @@ -42,29 +39,28 @@ struct neorv32_gpio_data { struct gpio_driver_data common; /* Shadow register for output */ uint32_t output; - struct k_spinlock lock; - sys_slist_t callbacks; }; -static inline uint32_t neorv32_gpio_read(const struct device *dev, uint16_t reg) +static inline uint32_t neorv32_gpio_read(const struct device *dev) { const struct neorv32_gpio_config *config = dev->config; - return sys_read32(config->base + reg); + return sys_read32(config->base + NEORV32_GPIO_PORT_IN); } -static inline void neorv32_gpio_write(const struct device *dev, uint16_t reg, uint32_t val) +static inline void neorv32_gpio_write(const struct device *dev, uint32_t val) { const struct neorv32_gpio_config *config = dev->config; - sys_write32(val, config->base + reg); + sys_write32(val, config->base + NEORV32_GPIO_PORT_OUT); } -static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, + gpio_flags_t flags) { const struct neorv32_gpio_config *config = dev->config; struct neorv32_gpio_data *data = dev->data; - k_spinlock_key_t key; + unsigned int key; if (!(BIT(pin) & config->common.port_pin_mask)) { return -EINVAL; @@ -79,7 +75,7 @@ static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, } if ((flags & GPIO_OUTPUT) != 0) { - key = k_spin_lock(&data->lock); + key = irq_lock(); if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { data->output |= BIT(pin); @@ -87,156 +83,91 @@ static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, data->output &= ~BIT(pin); } - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - k_spin_unlock(&data->lock, key); + neorv32_gpio_write(dev, data->output); + irq_unlock(key); } return 0; } -static int neorv32_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) +static int neorv32_gpio_port_get_raw(const struct device *dev, + gpio_port_value_t *value) { - *value = neorv32_gpio_read(dev, NEORV32_GPIO_PORT_IN); + *value = neorv32_gpio_read(dev); return 0; } -static int neorv32_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) +static int neorv32_gpio_port_set_masked_raw(const struct device *dev, + gpio_port_pins_t mask, + gpio_port_value_t value) { struct neorv32_gpio_data *data = dev->data; - k_spinlock_key_t key; + unsigned int key; - key = k_spin_lock(&data->lock); + key = irq_lock(); data->output = (data->output & ~mask) | (mask & value); - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - k_spin_unlock(&data->lock, key); + neorv32_gpio_write(dev, data->output); + irq_unlock(key); return 0; } -static int neorv32_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int neorv32_gpio_port_set_bits_raw(const struct device *dev, + gpio_port_pins_t pins) { struct neorv32_gpio_data *data = dev->data; - k_spinlock_key_t key; + unsigned int key; - key = k_spin_lock(&data->lock); + key = irq_lock(); data->output |= pins; - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - k_spin_unlock(&data->lock, key); + neorv32_gpio_write(dev, data->output); + irq_unlock(key); return 0; } -static int neorv32_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +static int neorv32_gpio_port_clear_bits_raw(const struct device *dev, + gpio_port_pins_t pins) { struct neorv32_gpio_data *data = dev->data; - k_spinlock_key_t key; + unsigned int key; - key = k_spin_lock(&data->lock); + key = irq_lock(); data->output &= ~pins; - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - k_spin_unlock(&data->lock, key); + neorv32_gpio_write(dev, data->output); + irq_unlock(key); return 0; } -static int neorv32_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +static int neorv32_gpio_port_toggle_bits(const struct device *dev, + gpio_port_pins_t pins) { struct neorv32_gpio_data *data = dev->data; - k_spinlock_key_t key; + unsigned int key; - key = k_spin_lock(&data->lock); + key = irq_lock(); data->output ^= pins; - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - k_spin_unlock(&data->lock, key); + neorv32_gpio_write(dev, data->output); + irq_unlock(key); return 0; } -static int neorv32_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, - enum gpio_int_mode mode, enum gpio_int_trig trig) -{ - const struct neorv32_gpio_config *config = dev->config; - struct neorv32_gpio_data *data = dev->data; - const uint32_t mask = BIT(pin); - k_spinlock_key_t key; - uint32_t polarity; - uint32_t enable; - uint32_t type; - int err = 0; - - if (!(mask & config->common.port_pin_mask)) { - return -EINVAL; - } - - key = k_spin_lock(&data->lock); - - type = neorv32_gpio_read(dev, NEORV32_GPIO_IRQ_TYPE); - polarity = neorv32_gpio_read(dev, NEORV32_GPIO_IRQ_POLARITY); - enable = neorv32_gpio_read(dev, NEORV32_GPIO_IRQ_ENABLE); - - if (mode == GPIO_INT_MODE_DISABLED) { - enable &= ~mask; - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_ENABLE, enable); - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_PENDING, ~mask); - } else { - enable |= mask; - - if (mode == GPIO_INT_MODE_LEVEL) { - type &= ~mask; - } else if (mode == GPIO_INT_MODE_EDGE) { - type |= mask; - } else { - LOG_ERR("unsupported interrupt mode 0x%02x", mode); - err = -ENOTSUP; - goto unlock; - } - - if (trig == GPIO_INT_TRIG_LOW) { - polarity &= ~mask; - } else if (trig == GPIO_INT_TRIG_HIGH) { - polarity |= mask; - } else { - LOG_ERR("unsupported interrupt trig 0x%02x", trig); - err = -ENOTSUP; - goto unlock; - } - - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_TYPE, type); - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_POLARITY, polarity); - - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_PENDING, ~mask); - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_ENABLE, enable); - } - -unlock: - k_spin_unlock(&data->lock, key); - - return err; -} - -static int neorv32_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, +static int neorv32_gpio_manage_callback(const struct device *dev, + struct gpio_callback *cb, bool set) { - struct neorv32_gpio_data *data = dev->data; + ARG_UNUSED(dev); + ARG_UNUSED(cb); + ARG_UNUSED(set); - return gpio_manage_callback(&data->callbacks, cb, set); + return -ENOTSUP; } static uint32_t neorv32_gpio_get_pending_int(const struct device *dev) { - return neorv32_gpio_read(dev, NEORV32_GPIO_IRQ_PENDING); -} - -static void neorv32_gpio_isr(const struct device *dev) -{ - struct neorv32_gpio_data *data = dev->data; - uint32_t pending; - - pending = neorv32_gpio_read(dev, NEORV32_GPIO_IRQ_PENDING); - neorv32_gpio_write(dev, NEORV32_GPIO_IRQ_PENDING, ~(pending)); - - gpio_fire_callbacks(&data->callbacks, dev, pending); + return 0; } static int neorv32_gpio_init(const struct device *dev) @@ -262,9 +193,7 @@ static int neorv32_gpio_init(const struct device *dev) return -ENODEV; } - neorv32_gpio_write(dev, NEORV32_GPIO_PORT_OUT, data->output); - - config->irq_config_func(); + neorv32_gpio_write(dev, data->output); return 0; } @@ -276,19 +205,11 @@ static DEVICE_API(gpio, neorv32_gpio_driver_api) = { .port_set_bits_raw = neorv32_gpio_port_set_bits_raw, .port_clear_bits_raw = neorv32_gpio_port_clear_bits_raw, .port_toggle_bits = neorv32_gpio_port_toggle_bits, - .pin_interrupt_configure = neorv32_gpio_pin_interrupt_configure, .manage_callback = neorv32_gpio_manage_callback, .get_pending_int = neorv32_gpio_get_pending_int, }; #define NEORV32_GPIO_INIT(n) \ - static void neorv32_gpio_config_func_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ - neorv32_gpio_isr, DEVICE_DT_INST_GET(n), 0);\ - irq_enable(DT_INST_IRQN(n)); \ - } \ - \ static struct neorv32_gpio_data neorv32_gpio_##n##_data = { \ .output = 0, \ }; \ @@ -299,7 +220,6 @@ static DEVICE_API(gpio, neorv32_gpio_driver_api) = { }, \ .syscon = DEVICE_DT_GET(DT_INST_PHANDLE(n, syscon)), \ .base = DT_INST_REG_ADDR(n), \ - .irq_config_func = neorv32_gpio_config_func_##n, \ }; \ \ DEVICE_DT_INST_DEFINE(n, \ diff --git a/drivers/gpio/gpio_nrfx.c b/drivers/gpio/gpio_nrfx.c index 4c6a3b733e1bf..3d2c1a12f46d7 100644 --- a/drivers/gpio/gpio_nrfx.c +++ b/drivers/gpio/gpio_nrfx.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include @@ -64,37 +62,53 @@ static nrf_gpio_pin_pull_t get_pull(gpio_flags_t flags) return NRF_GPIO_PIN_NOPULL; } -static void gpio_nrfx_gpd_retain_set(const struct device *port, uint32_t mask, gpio_flags_t flags) +static int gpio_nrfx_gpd_retain_set(const struct device *port, uint32_t mask, gpio_flags_t flags) { #ifdef CONFIG_SOC_NRF54H20_GPD const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); - if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1 || !(flags & GPIO_OUTPUT)) { - return; - } + if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { + int ret; + + if (flags & GPIO_OUTPUT) { + nrf_gpio_port_retain_enable(cfg->port, mask); + } - nrf_gpio_port_retain_enable(cfg->port, mask); + ret = nrf_gpd_release(NRF_GPD_FAST_ACTIVE1); + if (ret < 0) { + return ret; + } + } #else ARG_UNUSED(port); ARG_UNUSED(mask); ARG_UNUSED(flags); #endif + + return 0; } -static void gpio_nrfx_gpd_retain_clear(const struct device *port, uint32_t mask) +static int gpio_nrfx_gpd_retain_clear(const struct device *port, uint32_t mask) { #ifdef CONFIG_SOC_NRF54H20_GPD const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); - if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1) { - return; - } + if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { + int ret; + + ret = nrf_gpd_request(NRF_GPD_FAST_ACTIVE1); + if (ret < 0) { + return ret; + } - nrf_gpio_port_retain_disable(cfg->port, mask); + nrf_gpio_port_retain_disable(cfg->port, mask); + } #else ARG_UNUSED(port); ARG_UNUSED(mask); #endif + + return 0; } static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, @@ -138,13 +152,11 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, return -EINVAL; } - ret = pm_device_runtime_get(port); + ret = gpio_nrfx_gpd_retain_clear(port, BIT(pin)); if (ret < 0) { return ret; } - gpio_nrfx_gpd_retain_clear(port, BIT(pin)); - if (flags & GPIO_OUTPUT_INIT_HIGH) { nrf_gpio_port_out_set(cfg->port, BIT(pin)); } else if (flags & GPIO_OUTPUT_INIT_LOW) { @@ -225,8 +237,8 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, } end: - gpio_nrfx_gpd_retain_set(port, BIT(pin), flags); - return pm_device_runtime_put(port); + (void)gpio_nrfx_gpd_retain_set(port, BIT(pin), flags); + return ret; } #ifdef CONFIG_GPIO_GET_CONFIG @@ -242,9 +254,6 @@ static int gpio_nrfx_pin_get_config(const struct device *port, gpio_pin_t pin, if (dir == NRF_GPIO_PIN_DIR_OUTPUT) { *flags |= GPIO_OUTPUT; - *flags |= nrf_gpio_pin_out_read(abs_pin) - ? GPIO_OUTPUT_INIT_HIGH - : GPIO_OUTPUT_INIT_LOW; } nrf_gpio_pin_input_t input = nrf_gpio_pin_input_get(abs_pin); @@ -319,16 +328,15 @@ static int gpio_nrfx_port_set_masked_raw(const struct device *port, const uint32_t set_mask = value & mask; const uint32_t clear_mask = (~set_mask) & mask; - ret = pm_device_runtime_get(port); + ret = gpio_nrfx_gpd_retain_clear(port, mask); if (ret < 0) { return ret; } - gpio_nrfx_gpd_retain_clear(port, mask); nrf_gpio_port_out_set(reg, set_mask); nrf_gpio_port_out_clear(reg, clear_mask); - gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); - return pm_device_runtime_put(port); + + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_set_bits_raw(const struct device *port, @@ -337,15 +345,14 @@ static int gpio_nrfx_port_set_bits_raw(const struct device *port, NRF_GPIO_Type *reg = get_port_cfg(port)->port; int ret; - ret = pm_device_runtime_get(port); + ret = gpio_nrfx_gpd_retain_clear(port, mask); if (ret < 0) { return ret; } - gpio_nrfx_gpd_retain_clear(port, mask); nrf_gpio_port_out_set(reg, mask); - gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); - return pm_device_runtime_put(port); + + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_clear_bits_raw(const struct device *port, @@ -354,15 +361,14 @@ static int gpio_nrfx_port_clear_bits_raw(const struct device *port, NRF_GPIO_Type *reg = get_port_cfg(port)->port; int ret; - ret = pm_device_runtime_get(port); + ret = gpio_nrfx_gpd_retain_clear(port, mask); if (ret < 0) { return ret; } - gpio_nrfx_gpd_retain_clear(port, mask); nrf_gpio_port_out_clear(reg, mask); - gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); - return pm_device_runtime_put(port); + + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_toggle_bits(const struct device *port, @@ -374,16 +380,15 @@ static int gpio_nrfx_port_toggle_bits(const struct device *port, const uint32_t clear_mask = (~value) & mask; int ret; - ret = pm_device_runtime_get(port); + ret = gpio_nrfx_gpd_retain_clear(port, mask); if (ret < 0) { return ret; } - gpio_nrfx_gpd_retain_clear(port, mask); nrf_gpio_port_out_set(reg, set_mask); nrf_gpio_port_out_clear(reg, clear_mask); - gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); - return pm_device_runtime_put(port); + + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } #ifdef CONFIG_GPIO_NRFX_INTERRUPT @@ -542,68 +547,17 @@ static void nrfx_gpio_handler(nrfx_gpiote_pin_t abs_pin, IRQ_CONNECT(DT_IRQN(node_id), DT_IRQ(node_id, priority), nrfx_isr, \ NRFX_CONCAT(nrfx_gpiote_, DT_PROP(node_id, instance), _irq_handler), 0); -static int gpio_nrfx_pm_suspend(const struct device *port) -{ -#ifdef CONFIG_SOC_NRF54H20_GPD - const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); - - if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1) { - return 0; - } - - return nrf_gpd_release(NRF_GPD_FAST_ACTIVE1); -#else - ARG_UNUSED(port); - return 0; -#endif -} - -static int gpio_nrfx_pm_resume(const struct device *port) -{ -#ifdef CONFIG_SOC_NRF54H20_GPD - const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); - - if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1) { - return 0; - } - - return nrf_gpd_request(NRF_GPD_FAST_ACTIVE1); -#else - ARG_UNUSED(port); - return 0; -#endif -} - -static int gpio_nrfx_pm_hook(const struct device *port, enum pm_device_action action) -{ - int ret; - - switch (action) { - case PM_DEVICE_ACTION_SUSPEND: - ret = gpio_nrfx_pm_suspend(port); - break; - case PM_DEVICE_ACTION_RESUME: - ret = gpio_nrfx_pm_resume(port); - break; - default: - ret = -ENOTSUP; - break; - } - - return ret; -} - static int gpio_nrfx_init(const struct device *port) { const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); nrfx_err_t err; if (!has_gpiote(cfg)) { - goto pm_init; + return 0; } if (nrfx_gpiote_init_check(&cfg->gpiote)) { - goto pm_init; + return 0; } err = nrfx_gpiote_init(&cfg->gpiote, 0 /*not used*/); @@ -616,8 +570,7 @@ static int gpio_nrfx_init(const struct device *port) DT_FOREACH_STATUS_OKAY(nordic_nrf_gpiote, GPIOTE_IRQ_HANDLER_CONNECT); #endif /* CONFIG_GPIO_NRFX_INTERRUPT */ -pm_init: - return pm_device_driver_init(port, gpio_nrfx_pm_hook); + return 0; } static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = { @@ -682,10 +635,8 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = { \ static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ \ - PM_DEVICE_DT_INST_DEFINE(id, gpio_nrfx_pm_hook); \ - \ DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, \ - PM_DEVICE_DT_INST_GET(id), \ + NULL, \ &gpio_nrfx_p##id##_data, \ &gpio_nrfx_p##id##_cfg, \ PRE_KERNEL_1, \ diff --git a/drivers/gpio/gpio_pca6416.c b/drivers/gpio/gpio_pca6416.c index 5591eb64ae57c..a0d9b083fffb5 100644 --- a/drivers/gpio/gpio_pca6416.c +++ b/drivers/gpio/gpio_pca6416.c @@ -472,7 +472,7 @@ static DEVICE_API(gpio, api_table) = { .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ }, \ .interrupt_enabled = DT_INST_NODE_HAS_PROP(n, interrupt_gpios), \ - .gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, interrupt_gpios, {0}), \ + .gpio_int = GPIO_DT_SPEC_INST_GET(n, interrupt_gpios), \ }; \ \ static struct pca6416_drv_data pca6416_drvdata_##n = { \ diff --git a/drivers/gpio/gpio_pca_series.c b/drivers/gpio/gpio_pca_series.c index e62fed5c8d870..87e13a3624425 100644 --- a/drivers/gpio/gpio_pca_series.c +++ b/drivers/gpio/gpio_pca_series.c @@ -521,7 +521,7 @@ static inline int gpio_pca_series_reg_cache_read(const struct device *dev, #endif /* GPIO_NXP_PCA_SERIES_DEBUG */ src = ((uint8_t *)data->cache) + offset; - LOG_DBG("cache read type %d len %d mem addr 0x%p", reg_type, size, (void *)src); + LOG_DBG("cache read type %d len %d mem addr 0x%p", reg_type, size, src); memcpy(buf, src, size); return ret; } @@ -560,7 +560,7 @@ static inline int gpio_pca_series_reg_cache_update(const struct device *dev, (buf ? "buffer" : "device")); dst = ((uint8_t *)data->cache) + offset; - LOG_DBG("cache write mem addr 0x%p len %d", (void *)dst, size); + LOG_DBG("cache write mem addr 0x%p len %d", dst, size); /** update cache from buf */ memcpy(dst, buf, size); @@ -587,7 +587,7 @@ static inline struct gpio_pca_series_reg_cache_mini *gpio_pca_series_reg_cache_m struct gpio_pca_series_data *data = dev->data; struct gpio_pca_series_reg_cache_mini *cache = (struct gpio_pca_series_reg_cache_mini *)(&data->cache); - LOG_DBG("mini cache addr 0x%p", (void *)cache); + LOG_DBG("mini cache addr 0x%p", cache); return cache; } @@ -725,10 +725,10 @@ void gpio_pca_series_debug_dump(const struct device *dev) LOG_WRN("**** debug dump ****"); LOG_WRN("device: %s", dev->name); #ifdef CONFIG_GPIO_PCA_SERIES_CACHE_ALL - LOG_WRN("cache base addr: 0x%p size: 0x%2.2x", (void *)data->cache, - cfg->part_cfg->cache_size); + LOG_WRN("cache base addr: 0x%p size: 0x%2.2x", + data->cache, cfg->part_cfg->cache_size); #else - LOG_WRN("cache base addr: 0x%p", (void *)data->cache); + LOG_WRN("cache base addr: 0x%p", data->cache); #endif /* CONFIG_GPIO_PCA_SERIES_CACHE_ALL */ LOG_WRN("register profile:"); @@ -1068,7 +1068,7 @@ static int gpio_pca_series_port_read_standard( if (ret) { LOG_ERR("port read error %d", ret); } else { - *value = (gpio_port_value_t)sys_le32_to_cpu(input_data); + value = sys_le32_to_cpu(input_data); } k_sem_give(&data->lock); #endif /* CONFIG_GPIO_PCA_SERIES_INTERRUPT */ @@ -1684,11 +1684,6 @@ static int gpio_pca_series_init(const struct device *dev) LOG_ERR("i2c bus device not found"); goto out_bus; } - - /** device reset */ - gpio_pca_series_reset(dev); - LOG_DBG("device reset done"); - #ifdef GPIO_NXP_PCA_SERIES_DEBUG # ifdef CONFIG_GPIO_PCA_SERIES_CACHE_ALL gpio_pca_series_cache_test(dev); @@ -1707,6 +1702,10 @@ static int gpio_pca_series_init(const struct device *dev) } LOG_DBG("cache init done"); + /** device reset */ + gpio_pca_series_reset(dev); + LOG_DBG("device reset done"); + /** configure interrupt */ #ifdef CONFIG_GPIO_PCA_SERIES_INTERRUPT /** save dev pointer */ diff --git a/drivers/gpio/gpio_renesas_rx.c b/drivers/gpio/gpio_renesas_rx.c deleted file mode 100644 index 3c0d7259565ec..0000000000000 --- a/drivers/gpio/gpio_renesas_rx.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_rx_gpio - -#include -#include -#include -#include -#include -#include -#include - -struct gpio_rx_config { - struct gpio_driver_config common; - uint8_t port_num; - volatile struct { - volatile uint8_t *pdr; - volatile uint8_t *podr; - volatile uint8_t *pidr; - volatile uint8_t *pmr; - volatile uint8_t *odr0; - volatile uint8_t *odr1; - volatile uint8_t *pcr; - volatile uint8_t *dscr; - volatile uint8_t *dscr2; - } reg; -}; - -struct gpio_rx_data { - struct gpio_driver_data common; -}; - -static int gpio_rx_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) -{ - const struct gpio_rx_config *cfg = dev->config; - struct rx_pinctrl_soc_pin pincfg; - - memset(&pincfg, 0, sizeof(pincfg)); - - if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) { - return -ENOTSUP; - } - - if ((flags & GPIO_PULL_DOWN) != 0U) { - return -ENOTSUP; - } - - if ((flags & GPIO_INT_ENABLE) != 0) { - return -ENOTSUP; - } - - pincfg.port_num = cfg->port_num; - pincfg.pin_num = pin; - - /* Set pull-up if requested */ - if ((flags & GPIO_PULL_UP) != 0) { - pincfg.cfg.bias_pull_up = 1; - } - - /* Open drain (pins 0-3: odr0, pins 4-8: odr1) */ - if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) { - pincfg.cfg.drive_open_drain = 1; - } - - /* Set to output */ - if ((flags & GPIO_OUTPUT) != 0U) { - if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { - pincfg.cfg.output_high = 1; - } - pincfg.cfg.pin_mode = 0; - pincfg.cfg.output_enable = 1; - } - - return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); -} - -static int gpio_rx_port_get_raw(const struct device *dev, uint32_t *value) -{ - const struct gpio_rx_config *cfg = dev->config; - - *value = *(cfg->reg.pidr); - return 0; -} - -static int gpio_rx_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) -{ - const struct gpio_rx_config *cfg = dev->config; - - *(cfg->reg.podr) = ((*cfg->reg.podr) & ~mask) | (mask & value); - return 0; -} - -static int gpio_rx_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) -{ - const struct gpio_rx_config *cfg = dev->config; - - *(cfg->reg.podr) |= pins; - return 0; -} - -static int gpio_rx_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) -{ - const struct gpio_rx_config *cfg = dev->config; - - *(cfg->reg.podr) &= ~pins; - return 0; -} - -static int gpio_rx_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) -{ - const struct gpio_rx_config *cfg = dev->config; - - *(cfg->reg.podr) = *(cfg->reg.podr) ^ pins; - return 0; -} - -static DEVICE_API(gpio, gpio_rx_drv_api_funcs) = { - .pin_configure = gpio_rx_pin_configure, - .port_get_raw = gpio_rx_port_get_raw, - .port_set_masked_raw = gpio_rx_port_set_masked_raw, - .port_set_bits_raw = gpio_rx_port_set_bits_raw, - .port_clear_bits_raw = gpio_rx_port_clear_bits_raw, - .port_toggle_bits = gpio_rx_port_toggle_bits, - .pin_interrupt_configure = NULL, - .manage_callback = NULL, -}; - -#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \ - static const struct gpio_rx_config gpio_rx_config_##suffix = { \ - .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(8U)}, \ - .port_num = port_number, \ - .reg = {.pdr = (uint8_t *)DT_REG_ADDR_BY_NAME(node, PDR), \ - .podr = (uint8_t *)DT_REG_ADDR_BY_NAME(node, PODR), \ - .pidr = (uint8_t *)DT_REG_ADDR_BY_NAME(node, PIDR), \ - .pmr = (uint8_t *)DT_REG_ADDR_BY_NAME(node, PMR), \ - .odr0 = (uint8_t *)DT_REG_ADDR_BY_NAME_OR(node, ODR0, NULL), \ - .odr1 = (uint8_t *)DT_REG_ADDR_BY_NAME_OR(node, ODR1, NULL), \ - .pcr = (uint8_t *)DT_REG_ADDR_BY_NAME(node, PCR)}}; \ - static struct gpio_rx_data gpio_rx_data_##suffix; \ - DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_rx_data_##suffix, &gpio_rx_config_##suffix, \ - PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_rx_drv_api_funcs) - -#define GPIO_DEVICE_INIT_RX(suffix) \ - GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \ - DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \ - DT_REG_ADDR(DT_NODELABEL(ioport##suffix))) - -#define GPIO_DEVICE_INIT_RX_IF_OKAY(suffix) \ - COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(ioport##suffix), okay), \ - (GPIO_DEVICE_INIT_RX(suffix)), ()) - -GPIO_DEVICE_INIT_RX_IF_OKAY(0); -GPIO_DEVICE_INIT_RX_IF_OKAY(1); -GPIO_DEVICE_INIT_RX_IF_OKAY(2); -GPIO_DEVICE_INIT_RX_IF_OKAY(3); -GPIO_DEVICE_INIT_RX_IF_OKAY(4); -GPIO_DEVICE_INIT_RX_IF_OKAY(5); -GPIO_DEVICE_INIT_RX_IF_OKAY(a); -GPIO_DEVICE_INIT_RX_IF_OKAY(b); -GPIO_DEVICE_INIT_RX_IF_OKAY(c); -GPIO_DEVICE_INIT_RX_IF_OKAY(d); -GPIO_DEVICE_INIT_RX_IF_OKAY(e); -GPIO_DEVICE_INIT_RX_IF_OKAY(h); -GPIO_DEVICE_INIT_RX_IF_OKAY(j); diff --git a/drivers/gpio/gpio_renesas_rz.c b/drivers/gpio/gpio_renesas_rz.c index 3cbe3d5338b89..fa0b525ef2023 100644 --- a/drivers/gpio/gpio_renesas_rz.c +++ b/drivers/gpio/gpio_renesas_rz.c @@ -31,10 +31,10 @@ struct gpio_rz_config { bsp_io_port_t fsp_port; const ioport_cfg_t *fsp_cfg; const ioport_api_t *fsp_api; - const struct device *gpio_int_dev; + const struct device *int_dev; uint8_t int_num[GPIO_RZ_MAX_INT_NUM]; #if defined(CONFIG_RENESAS_RZ_EXT_IRQ) - const struct device *ext_irq_dev[GPIO_RZ_MAX_INT_NUM]; + const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM]; void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg); #endif @@ -60,39 +60,39 @@ struct gpio_rz_int_data { uint32_t irq_set_edge; }; -struct gpio_rz_flags { - gpio_flags_t gpio_flags; +struct gpio_rz_hw_config { + gpio_flags_t p_pm; uint8_t pfc; }; -struct gpio_rz_int_config { +struct gpio_rz_tint_config { void (*gpio_int_init)(void); }; -static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_flags *rz_flags); +static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags); #ifdef CONFIG_GPIO_GET_CONFIG static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) { const struct gpio_rz_config *config = dev->config; bsp_io_port_pin_t port_pin = config->fsp_port | pin; - struct gpio_rz_flags rz_flags; + struct gpio_rz_hw_config hw_flags; - gpio_rz_pin_config_get_raw(port_pin, &rz_flags); - *flags = rz_flags.gpio_flags; + gpio_rz_pin_config_get_raw(port_pin, &hw_flags); + *flags = hw_flags.p_pm; return 0; } #endif /* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */ -static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_flags *rz_flags) +static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags) { bsp_io_port_t port = (port_pin >> 8U) & 0xFF; gpio_pin_t pin = port_pin & 0xFF; - volatile uint8_t *p_p = GPIO_RZ_P_REG_GET(port, pin); - volatile uint16_t *p_pm = GPIO_RZ_PM_REG_GET(port, pin); - volatile uint32_t *p_pfc = GPIO_RZ_PFC_REG_GET(port, pin); + volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_GET(port, pin); + volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_GET(port, pin); + volatile uint32_t *p_pfc = GPIO_RZ_IOPORT_PFC_REG_GET(port, pin); uint8_t p_value; uint16_t pm_value; @@ -102,15 +102,17 @@ static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin); pfc_value = GPIO_RZ_PFC_VALUE_GET(*p_pfc, pin); + flags->p_pm = 0; + flags->pfc = 0; + if (p_value) { - rz_flags->gpio_flags = GPIO_OUTPUT_INIT_HIGH; + flags->p_pm |= GPIO_OUTPUT_INIT_HIGH; } else { - rz_flags->gpio_flags = GPIO_OUTPUT_INIT_LOW; + flags->p_pm |= GPIO_OUTPUT_INIT_LOW; } - rz_flags->gpio_flags |= (pm_value << 16); - rz_flags->pfc = pfc_value; - + flags->p_pm |= (pm_value << 16); + flags->pfc |= pfc_value; return 0; } @@ -120,16 +122,17 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ struct gpio_rz_data *data = dev->data; bsp_io_port_pin_t port_pin = config->fsp_port | pin; uint32_t ioport_config_data = 0; - struct gpio_rz_flags rz_flags; + struct gpio_rz_hw_config pre_flags; fsp_err_t err; - gpio_rz_pin_config_get_raw(port_pin, &rz_flags); + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); if (!flags) { /* Disconnect mode */ GPIO_RZ_PIN_DISCONNECT(config->fsp_port, pin); } else if (!(flags & GPIO_OPEN_DRAIN)) { /* PM register */ + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET; if (flags & GPIO_INPUT) { if (flags & GPIO_OUTPUT) { ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT; @@ -137,12 +140,12 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_INPUT; } } else if (flags & GPIO_OUTPUT) { + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET; ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT; } /* P register */ if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) { - flags |= rz_flags.gpio_flags & - (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW); + flags |= pre_flags.p_pm & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW); } if (flags & GPIO_OUTPUT_INIT_HIGH) { @@ -159,31 +162,31 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ /* * Interrupt register - * RZ/A,G,V: ISEL - * RZ/T,N: PMC + * RZG: ISEL + * RZTN: PMC */ if (flags & GPIO_INT_ENABLE) { - ioport_config_data |= GPIO_RZ_INT_ENABLE; + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE; } else if (flags & GPIO_INT_DISABLE) { - ioport_config_data &= GPIO_RZ_INT_DISABLE; + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE; } /* * Drive ability register - * RZ/A,G,V: IOLH - * RZ/T,N: DRCTL + * RZG: IOLH + * RZTN: DRCTL */ - ioport_config_data |= GPIO_RZ_FLAG_GET_CONFIG(flags); + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET(flags); /* PFC register */ - ioport_config_data |= GPIO_RZ_FLAG_SET_PFC(rz_flags.pfc); + ioport_config_data |= GPIO_RZ_IOPORT_PFC_SET(pre_flags.pfc); /* * Specific register - * RZ/A,G,V: FILONOFF, FILNUM, FILCLKSEL - * RZ/T,N: RSELP + * RZG: FILONOFF, FILNUM, FILCLKSEL + * RZTN: RSELP */ - ioport_config_data |= GPIO_RZ_FLAG_GET_SPECIFIC(flags); + ioport_config_data |= GPIO_RZ_PIN_SPECIAL_FLAG_GET(flags); } else { return -ENOTSUP; } @@ -192,7 +195,6 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ if (err != FSP_SUCCESS) { return -EIO; } - return 0; } @@ -208,7 +210,6 @@ static int gpio_rz_port_get_raw(const struct device *dev, gpio_port_value_t *val return -EIO; } *value = (gpio_port_value_t)port_value; - return 0; } @@ -225,7 +226,6 @@ static int gpio_rz_port_set_masked_raw(const struct device *dev, gpio_port_pins_ if (err != FSP_SUCCESS) { return -EIO; } - return 0; } @@ -241,7 +241,6 @@ static int gpio_rz_port_set_bits_raw(const struct device *dev, gpio_port_pins_t if (err != FSP_SUCCESS) { return -EIO; } - return 0; } @@ -257,7 +256,6 @@ static int gpio_rz_port_clear_bits_raw(const struct device *dev, gpio_port_pins_ if (err != FSP_SUCCESS) { return -EIO; } - return 0; } @@ -266,17 +264,17 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p const struct gpio_rz_config *config = dev->config; struct gpio_rz_data *data = dev->data; bsp_io_port_pin_t port_pin; - struct gpio_rz_flags rz_flags; + struct gpio_rz_hw_config pre_flags; ioport_size_t value = 0; fsp_err_t err; for (uint8_t idx = 0; idx < config->ngpios; idx++) { if (pins & (1U << idx)) { port_pin = config->fsp_port | idx; - gpio_rz_pin_config_get_raw(port_pin, &rz_flags); - if (rz_flags.gpio_flags & GPIO_OUTPUT_INIT_HIGH) { + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + if (pre_flags.p_pm & GPIO_OUTPUT_INIT_HIGH) { value &= (1U << idx); - } else if (rz_flags.gpio_flags & GPIO_OUTPUT_INIT_LOW) { + } else if (pre_flags.p_pm & GPIO_OUTPUT_INIT_LOW) { value |= (1U << idx); } } @@ -286,7 +284,6 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p if (err != FSP_SUCCESS) { return -EIO; } - return 0; } @@ -320,17 +317,17 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp data->gpio_mapping[int_num].pin = UINT8_MAX; #elif defined(CONFIG_RENESAS_RZ_EXT_IRQ) const struct gpio_rz_config *gpio_config = gpio_dev->config; - const struct device *ext_irq_dev = gpio_config->ext_irq_dev[pin]; + const struct device *eirq_dev = gpio_config->eirq_dev[pin]; - if (device_is_ready(ext_irq_dev)) { - intc_rz_ext_irq_disable(ext_irq_dev); + if (device_is_ready(eirq_dev)) { + intc_rz_ext_irq_disable(eirq_dev); } #endif /* CONFIG_RENESAS_RZ_EXT_IRQ */ return 0; } -static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct device *gpio_dev, +static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev, uint8_t int_num, uint8_t irq_type, gpio_pin_t pin) { if (irq_type == GPIO_RZ_INT_UNSUPPORTED) { @@ -342,7 +339,7 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de #if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) volatile uint32_t *tssr = &R_INTC->TSSR0; volatile uint32_t *titsr = &R_INTC->TITSR0; - struct gpio_rz_int_data *gpio_int_data = gpio_int_dev->data; + struct gpio_rz_int_data *int_data = int_dev->data; tssr = &tssr[int_num / 4]; titsr = &titsr[int_num / 16]; @@ -353,22 +350,22 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num); if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) { - gpio_int_data->irq_set_edge |= BIT(int_num); + int_data->irq_set_edge |= BIT(int_num); /* Clear interrupt status. */ R_INTC->TSCR &= ~BIT(int_num); } irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num)); - gpio_int_data->gpio_mapping[int_num].gpio_dev = gpio_dev; - gpio_int_data->gpio_mapping[int_num].pin = pin; + int_data->gpio_mapping[int_num].gpio_dev = gpio_dev; + int_data->gpio_mapping[int_num].pin = pin; #elif defined(CONFIG_RENESAS_RZ_EXT_IRQ) - const struct device *ext_irq_dev = gpio_config->ext_irq_dev[pin]; + const struct device *eirq_dev = gpio_config->eirq_dev[pin]; struct gpio_rz_data *gpio_data = gpio_dev->data; gpio_data->pin[int_num] = pin; - if (device_is_ready(ext_irq_dev)) { - intc_rz_ext_irq_set_type(ext_irq_dev, irq_type); - intc_rz_ext_irq_enable(ext_irq_dev); - intc_rz_ext_irq_set_callback(ext_irq_dev, gpio_config->cb_list[int_num], + if (device_is_ready(eirq_dev)) { + intc_rz_ext_irq_set_type(eirq_dev, irq_type); + intc_rz_ext_irq_enable(eirq_dev); + intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num], (void *)gpio_dev); } #endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */ @@ -384,7 +381,7 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t bsp_io_port_pin_t port_pin = config->fsp_port | pin; uint8_t int_num = config->int_num[pin]; uint8_t irq_type = 0; - struct gpio_rz_flags rz_flags; + struct gpio_rz_hw_config pre_flags; k_spinlock_key_t key; int ret = 0; @@ -399,10 +396,10 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t key = k_spin_lock(&data->lock); if (mode == GPIO_INT_MODE_DISABLED) { - gpio_rz_pin_config_get_raw(port_pin, &rz_flags); - rz_flags.gpio_flags |= GPIO_INT_DISABLE; - gpio_rz_pin_configure(dev, pin, rz_flags.gpio_flags); - gpio_rz_int_disable(config->gpio_int_dev, dev, int_num, pin); + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + pre_flags.p_pm |= GPIO_INT_DISABLE; + gpio_rz_pin_configure(dev, pin, pre_flags.p_pm); + gpio_rz_int_disable(config->int_dev, dev, int_num, pin); goto exit_unlock; } @@ -422,16 +419,15 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t } } - ret = gpio_rz_int_enable(config->gpio_int_dev, dev, int_num, irq_type, pin); + ret = gpio_rz_int_enable(config->int_dev, dev, int_num, irq_type, pin); if (ret == 0) { - gpio_rz_pin_config_get_raw(port_pin, &rz_flags); - rz_flags.gpio_flags |= GPIO_INT_ENABLE; - gpio_rz_pin_configure(dev, pin, rz_flags.gpio_flags); + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + pre_flags.p_pm |= GPIO_INT_ENABLE; + gpio_rz_pin_configure(dev, pin, pre_flags.p_pm); } exit_unlock: k_spin_unlock(&data->lock, key); - return ret; } @@ -447,7 +443,7 @@ static void gpio_rz_isr(uint16_t irq, void *param) { #if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) const struct device *dev = param; - struct gpio_rz_int_data *gpio_int_data = dev->data; + struct gpio_rz_int_data *int_data = dev->data; volatile uint32_t *tscr = &R_INTC->TSCR; if (!(*tscr & BIT(irq))) { @@ -455,12 +451,12 @@ static void gpio_rz_isr(uint16_t irq, void *param) return; } - if (gpio_int_data->irq_set_edge & BIT(irq)) { + if (int_data->irq_set_edge & BIT(irq)) { *tscr &= ~BIT(irq); } - uint8_t pin = gpio_int_data->gpio_mapping[irq].pin; - const struct device *gpio_dev = gpio_int_data->gpio_mapping[irq].gpio_dev; + uint8_t pin = int_data->gpio_mapping[irq].pin; + const struct device *gpio_dev = int_data->gpio_mapping[irq].gpio_dev; struct gpio_rz_data *gpio_data = gpio_dev->data; gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin)); @@ -492,10 +488,10 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { }; /* Initialize GPIO interrupt device */ -#define GPIO_RZ_ISR_DEFINE(idx, _) \ - static void rz_gpio_isr##idx(void *param) \ +#define GPIO_RZ_ISR_DEFINE(irq_num, _) \ + static void rz_gpio_isr##irq_num(void *param) \ { \ - gpio_rz_isr(idx, param); \ + gpio_rz_isr(irq_num, param); \ } #define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ()) @@ -503,39 +499,38 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { #if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ) #if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) -#define GPIO_RZ_INT_DEFINE(inst) \ - .gpio_int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)) +#define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)) static int gpio_rz_int_init(const struct device *dev) { - const struct gpio_rz_int_config *config = dev->config; + const struct gpio_rz_tint_config *config = dev->config; config->gpio_int_init(); - return 0; } -#define GPIO_RZ_INT_CONNECT(idx, node_id) \ - IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), DT_IRQ_BY_IDX(node_id, idx, priority), \ - rz_gpio_isr##idx, DEVICE_DT_GET(node_id), 0); +#define GPIO_RZ_TINT_CONNECT(irq_num, node_id) \ + IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq), \ + DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr##irq_num, \ + DEVICE_DT_GET(node_id), 0); -#define GPIO_RZ_INT_CONNECT_FUNC(node_id) \ - static void rz_gpio_int_connect_func##node_id(void) \ +#define GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ + static void rz_gpio_tint_connect_func##node_id(void) \ { \ LISTIFY(DT_NUM_IRQS(node_id), \ - GPIO_RZ_INT_CONNECT, (;), \ + GPIO_RZ_TINT_CONNECT, (;), \ node_id) \ } /* Initialize GPIO device */ #define GPIO_RZ_INT_INIT(node_id) \ GPIO_RZ_ALL_ISR_DEFINE(DT_NUM_IRQS(node_id)) \ - GPIO_RZ_INT_CONNECT_FUNC(node_id) \ - static const struct gpio_rz_int_config rz_gpio_int_cfg_##node_id = { \ - .gpio_int_init = rz_gpio_int_connect_func##node_id, \ + GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ + static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = { \ + .gpio_int_init = rz_gpio_tint_connect_func##node_id, \ }; \ - static struct gpio_rz_int_data rz_gpio_int_data_##node_id = {}; \ - DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_int_data_##node_id, \ - &rz_gpio_int_cfg_##node_id, POST_KERNEL, \ + static struct gpio_rz_int_data rz_gpio_tint_data_##node_id = {}; \ + DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id, \ + &rz_gpio_tint_cfg_##node_id, POST_KERNEL, \ UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL); DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT) @@ -543,23 +538,23 @@ DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT) GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM) -#define EXT_IRQ_CB_GET(ext_irq, _) [ext_irq] = rz_gpio_isr##ext_irq +#define EIRQ_CB_GET(eirq_line, _) [eirq_line] = rz_gpio_isr##eirq_line -#define EXT_IRQ_DEV_LABEL_GET(inst, idx) CONCAT(irq, DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx))) +#define EIRQ_DEV_LABEL_GET(inst, idx) CONCAT(irq, DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx))) -#define EXT_IRQ_DEV_GET(idx, inst) \ +#define EIRQ_DEV_GET(idx, inst) \ COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \ ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \ - DEVICE_DT_GET_OR_NULL(DT_NODELABEL(EXT_IRQ_DEV_LABEL_GET(inst, idx))),), \ + DEVICE_DT_GET_OR_NULL(DT_NODELABEL(EIRQ_DEV_LABEL_GET(inst, idx))),), \ ()) -#define ALL_EXT_IRQ_DEV_GET(inst) \ - FOR_EACH_FIXED_ARG(EXT_IRQ_DEV_GET, (), inst, \ +#define ALL_EIRQ_DEV_GET(inst) \ + FOR_EACH_FIXED_ARG(EIRQ_DEV_GET, (), inst, \ LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,))) #define GPIO_RZ_INT_DEFINE(inst) \ - .ext_irq_dev = {ALL_EXT_IRQ_DEV_GET(inst)}, \ - .cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EXT_IRQ_CB_GET, (,))} + .eirq_dev = {ALL_EIRQ_DEV_GET(inst)}, \ + .cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))} #endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */ diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h index 253ae775945be..c9570ef9e8443 100644 --- a/drivers/gpio/gpio_renesas_rz.h +++ b/drivers/gpio/gpio_renesas_rz.h @@ -16,46 +16,48 @@ #include #if defined(CONFIG_SOC_SERIES_RZG3S) -#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P_20) -#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM_20) -#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC_20) -#define GPIO_RZ_MAX_PORT_NUM 19 -#define GPIO_RZ_TINT_IRQ_OFFSET 429 -#define R_INTC R_INTC_IM33 +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20) +#define GPIO_RZ_MAX_PORT_NUM 19 +#define GPIO_RZ_TINT_IRQ_OFFSET 429 +#define R_INTC R_INTC_IM33 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, 47, 52, 56, 58, 63, 66, 70, 72, 76}; #elif defined(CONFIG_SOC_SERIES_RZA3UL) -#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10) -#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10) -#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10) -#define GPIO_RZ_MAX_PORT_NUM 19 -#define GPIO_RZ_TINT_IRQ_OFFSET 476 -#define R_INTC R_INTC_IA55 +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P10) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM10) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10) +#define GPIO_RZ_MAX_PORT_NUM 19 +#define GPIO_RZ_TINT_IRQ_OFFSET 476 +#define R_INTC R_INTC_IA55 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, 47, 52, 56, 58, 63, 66, 70, 72, 76}; #elif defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) -#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10) -#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10) -#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10) -#define GPIO_RZ_MAX_PORT_NUM 49 -#define GPIO_RZ_TINT_IRQ_OFFSET 444 -#define R_INTC R_INTC_IM33 +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P10) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM10) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10) +#define GPIO_RZ_MAX_PORT_NUM 49 +#define GPIO_RZ_TINT_IRQ_OFFSET 444 +#define R_INTC R_INTC_IM33 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = { 0, 2, 4, 6, 8, 10, 13, 15, 18, 21, 24, 25, 27, 29, 32, 34, 36, 38, 41, 43, 45, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 83, 85, 88, 91, 93, 98, 102, 106, 110, 114, 118}; #endif -#define GPIO_RZ_P_REG_GET(port, pin) (&GPIO_RZ_P_REG_BASE_GET[port]) -#define GPIO_RZ_PM_REG_GET(port, pin) (&GPIO_RZ_PM_REG_BASE_GET[port]) -#define GPIO_RZ_PFC_REG_GET(port, pin) (&GPIO_RZ_PFC_REG_BASE_GET[port]) +#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port]) +#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port]) +#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PFC_REG_BASE_GET[port]) #define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) #define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) #define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF) +#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 24) + #define GPIO_RZ_PIN_DISCONNECT(port, pin) /* do nothing */ #define GPIO_RZ_MAX_INT_NUM 32 @@ -67,45 +69,48 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = { #define GPIO_RZ_INT_LEVEL_HIGH 0x2 #define GPIO_RZ_INT_LEVEL_LOW 0x3 #define GPIO_RZ_INT_BOTH_EDGE GPIO_RZ_INT_UNSUPPORTED -#define GPIO_RZ_INT_ENABLE IOPORT_CFG_TINT_ENABLE -#define GPIO_RZ_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE)) #define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) #define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8) #define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2) -#define GPIO_RZ_FLAG_GET_CONFIG(flag) (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U) -#define GPIO_RZ_FLAG_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U) -#define GPIO_RZ_FLAG_SET_PFC(value) (value << 24) -#define GPIO_RZ_FLAG_GET_SPECIFIC(flag) GPIO_RZ_FLAG_GET_FILTER(flag) +#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U) +#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U) + +#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE +#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE)) +#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) +#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) #elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) || \ defined(CONFIG_SOC_SERIES_RZT2M) #include -#define GPIO_RZ_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0) +#define GPIO_RZ_IOPORT_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0) -#define GPIO_RZ_P_REG_BASE_GET(port, pin) \ - (GPIO_RZ_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port] \ - : &R_PORT_SR->P[port]) +#define GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port] \ + : &R_PORT_SR->P[port]) -#define GPIO_RZ_PM_REG_BASE_GET(port, pin) \ - (GPIO_RZ_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port] \ - : &R_PORT_SR->PM[port]) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port] \ + : &R_PORT_SR->PM[port]) -#define GPIO_RZ_PFC_REG_BASE_GET(port, pin) \ - (GPIO_RZ_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PFC[port] \ - : &R_PORT_SR->PFC[port]) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PFC[port] \ + : &R_PORT_SR->PFC[port]) -#define GPIO_RZ_P_REG_GET(port, pin) (GPIO_RZ_P_REG_BASE_GET(port, pin)) -#define GPIO_RZ_PM_REG_GET(port, pin) (GPIO_RZ_PM_REG_BASE_GET(port, pin)) -#define GPIO_RZ_PFC_REG_GET(port, pin) (GPIO_RZ_PFC_REG_BASE_GET(port, pin)) +#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin)) +#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin)) +#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin)) #define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) #define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) #define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF) +#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 4) + #define GPIO_RZ_PIN_DISCONNECT(port, pin) \ - *GPIO_RZ_PM_REG_GET((port >> 8U), pin) &= ~(3U << (pin * 2)) + *GPIO_RZ_IOPORT_PM_REG_GET((port >> 8U), pin) &= ~(3U << (pin * 2)) #define GPIO_RZ_MAX_INT_NUM 16 @@ -114,12 +119,13 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = { #define GPIO_RZ_INT_BOTH_EDGE 0x2 #define GPIO_RZ_INT_LEVEL_LOW 0x3 #define GPIO_RZ_INT_LEVEL_HIGH GPIO_RZ_INT_UNSUPPORTED -#define GPIO_RZ_INT_ENABLE (1U << 3) -#define GPIO_RZ_INT_DISABLE (~(1U << 3)) -#define GPIO_RZ_FLAG_GET_CONFIG(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U) -#define GPIO_RZ_FLAG_SET_PFC(value) (value << 4) -#define GPIO_RZ_FLAG_GET_SPECIFIC(flag) IOPORT_CFG_REGION_NSAFETY +#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U) + +#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE (1U << 3) +#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(1U << 3)) +#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) +#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) IOPORT_CFG_REGION_NSAFETY #endif /* CONFIG_SOC_* */ diff --git a/drivers/gpio/gpio_rts5912.c b/drivers/gpio/gpio_rts5912.c index f2f33c29c8158..bda68ae39a54d 100644 --- a/drivers/gpio/gpio_rts5912.c +++ b/drivers/gpio/gpio_rts5912.c @@ -95,17 +95,9 @@ static int gpio_rts5912_configuration(const struct device *port, gpio_pin_t pin, if (flags & GPIO_INPUT) { cfg_val &= ~GPIO_GCR_DIR_Msk; cfg_val &= ~GPIO_GCR_OUTCTRL_Msk; - /* enable input detect */ cfg_val |= GPIO_GCR_INDETEN_Msk; } - if (flags & GPIO_DISCONNECTED) { - cfg_val &= ~GPIO_GCR_DIR_Msk; - cfg_val &= ~GPIO_GCR_OUTCTRL_Msk; - /* disable input detect */ - cfg_val &= ~GPIO_GCR_INDETEN_Msk; - } - if (flags & GPIO_OPEN_DRAIN) { cfg_val |= GPIO_GCR_OUTMD_Msk; } else { @@ -139,48 +131,12 @@ static int gpio_rts5912_configuration(const struct device *port, gpio_pin_t pin, break; } - if (flags & RTS5912_GPIO_OUTDRV) { - cfg_val |= GPIO_GCR_OUTDRV_Msk; - } else { - cfg_val &= ~GPIO_GCR_OUTDRV_Msk; - } - - if (flags & RTS5912_GPIO_SLEWRATE) { - cfg_val |= GPIO_GCR_SLEWRATE_Msk; - } else { - cfg_val &= ~GPIO_GCR_SLEWRATE_Msk; - } - - if (flags & RTS5912_GPIO_SCHEN) { - cfg_val |= GPIO_GCR_SCHEN_Msk; - } else { - cfg_val &= ~GPIO_GCR_SCHEN_Msk; - } - - cfg_val &= ~GPIO_GCR_MFCTRL_Msk; - switch (flags & RTS5912_GPIO_MFCTRL_MASK) { - case RTS5912_GPIO_MFCTRL_0: - cfg_val |= (0U << GPIO_GCR_MFCTRL_Pos); - break; - case RTS5912_GPIO_MFCTRL_1: - cfg_val |= (1U << GPIO_GCR_MFCTRL_Pos); - break; - case RTS5912_GPIO_MFCTRL_2: - cfg_val |= (2U << GPIO_GCR_MFCTRL_Pos); - break; - case RTS5912_GPIO_MFCTRL_3: - cfg_val |= (3U << GPIO_GCR_MFCTRL_Pos); - break; - default: - return -EINVAL; - } - *gcr = cfg_val; if (flags & GPIO_OUTPUT) { if (flags & GPIO_OUTPUT_INIT_HIGH) { pin_output_high(port, pin); - } else if (flags & GPIO_OUTPUT_INIT_LOW) { + } else { pin_output_low(port, pin); } } @@ -227,73 +183,6 @@ static int gpio_rts5912_get_configuration(const struct device *port, gpio_pin_t cfg_flag |= GPIO_PULL_DOWN; } - if (*gcr & GPIO_GCR_INDETEN_Msk) { - cfg_flag |= RTS5912_GPIO_INDETEN; - } else { - cfg_flag &= ~RTS5912_GPIO_INDETEN; - } - - if (*gcr & GPIO_GCR_OUTDRV_Msk) { - cfg_flag |= RTS5912_GPIO_OUTDRV; - } else { - cfg_flag &= ~RTS5912_GPIO_OUTDRV; - } - - if (*gcr & GPIO_GCR_SLEWRATE_Msk) { - cfg_flag |= RTS5912_GPIO_SLEWRATE; - } else { - cfg_flag &= ~RTS5912_GPIO_SLEWRATE; - } - - if (*gcr & GPIO_GCR_SCHEN_Msk) { - cfg_flag |= RTS5912_GPIO_SCHEN; - } else { - cfg_flag &= ~RTS5912_GPIO_SCHEN; - } - - switch ((*gcr & GPIO_GCR_MFCTRL_Msk) >> GPIO_GCR_MFCTRL_Pos) { - case 0: - cfg_flag |= RTS5912_GPIO_MFCTRL_0; - break; - case 1: - cfg_flag |= RTS5912_GPIO_MFCTRL_1; - break; - case 2: - cfg_flag |= RTS5912_GPIO_MFCTRL_2; - break; - case 3: - cfg_flag |= RTS5912_GPIO_MFCTRL_3; - break; - default: - cfg_flag |= RTS5912_GPIO_MFCTRL_0; - break; - } - - if (*gcr & GPIO_GCR_INTEN_Msk) { - switch (*gcr & GPIO_GCR_INTCTRL_Msk) { - case GPIO_GCR_INTCTRL_TRIG_EDGE_HIGH: - cfg_flag |= GPIO_INT_EDGE_RISING; - break; - case GPIO_GCR_INTCTRL_TRIG_EDGE_LOW: - cfg_flag |= GPIO_INT_EDGE_FALLING; - break; - case GPIO_GCR_INTCTRL_TRIG_EDGE_BOTH: - cfg_flag |= GPIO_INT_EDGE_BOTH; - break; - case GPIO_GCR_INTCTRL_TRIG_LEVEL_LOW: - cfg_flag |= GPIO_INT_LEVEL_LOW; - break; - case GPIO_GCR_INTCTRL_TRIG_LEVEL_HIGH: - cfg_flag |= GPIO_INT_LEVEL_HIGH; - break; - default: - cfg_flag |= GPIO_INT_LEVEL_LOW; - break; - } - } else { - cfg_flag |= GPIO_INT_DISABLE; - } - *flags = cfg_flag; return 0; @@ -468,11 +357,11 @@ static int gpio_rts5912_intr_config(const struct device *port, gpio_pin_t pin, switch (trig) { case GPIO_INT_TRIG_LOW: cfg_val &= ~GPIO_GCR_INTCTRL_Msk; - cfg_val |= GPIO_GCR_INTCTRL_TRIG_LEVEL_LOW; + cfg_val |= 0x03UL << GPIO_GCR_INTCTRL_Pos; break; case GPIO_INT_TRIG_HIGH: cfg_val &= ~GPIO_GCR_INTCTRL_Msk; - cfg_val |= GPIO_GCR_INTCTRL_TRIG_LEVEL_HIGH; + cfg_val |= 0x04UL << GPIO_GCR_INTCTRL_Pos; break; default: return -EINVAL; @@ -482,15 +371,15 @@ static int gpio_rts5912_intr_config(const struct device *port, gpio_pin_t pin, switch (trig) { case GPIO_INT_TRIG_LOW: cfg_val &= ~GPIO_GCR_INTCTRL_Msk; - cfg_val |= GPIO_GCR_INTCTRL_TRIG_EDGE_LOW; + cfg_val |= 0x01UL << GPIO_GCR_INTCTRL_Pos; break; case GPIO_INT_TRIG_HIGH: cfg_val &= ~GPIO_GCR_INTCTRL_Msk; - cfg_val |= GPIO_GCR_INTCTRL_TRIG_EDGE_HIGH; + cfg_val |= 0x00UL << GPIO_GCR_INTCTRL_Pos; break; case GPIO_INT_TRIG_BOTH: cfg_val &= ~GPIO_GCR_INTCTRL_Msk; - cfg_val |= GPIO_GCR_INTCTRL_TRIG_EDGE_BOTH; + cfg_val |= 0x2UL << GPIO_GCR_INTCTRL_Pos; break; default: return -EINVAL; @@ -500,9 +389,7 @@ static int gpio_rts5912_intr_config(const struct device *port, gpio_pin_t pin, return -EINVAL; } - /* enable interrupt */ cfg_val |= GPIO_GCR_INTEN_Msk; - /* set value to GPIO register */ *gcr = cfg_val; irq_enable(pin_index); diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index b5fa7aeec9433..09881a4dd01d4 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -679,6 +679,7 @@ static DEVICE_API(gpio, gpio_stm32_driver) = { .manage_callback = gpio_stm32_manage_callback, }; +#ifdef CONFIG_PM_DEVICE static int gpio_stm32_pm_action(const struct device *dev, enum pm_device_action action) { @@ -687,15 +688,13 @@ static int gpio_stm32_pm_action(const struct device *dev, return gpio_stm32_clock_request(dev, true); case PM_DEVICE_ACTION_SUSPEND: return gpio_stm32_clock_request(dev, false); - case PM_DEVICE_ACTION_TURN_OFF: - case PM_DEVICE_ACTION_TURN_ON: - break; default: return -ENOTSUP; } return 0; } +#endif /* CONFIG_PM_DEVICE */ /** @@ -711,6 +710,7 @@ static int gpio_stm32_pm_action(const struct device *dev, static int gpio_stm32_init(const struct device *dev) { struct gpio_stm32_data *data = dev->data; + int ret; data->dev = dev; @@ -726,8 +726,18 @@ static int gpio_stm32_init(const struct device *dev) LL_PWR_EnableVddIO2(); z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); #endif + /* enable port clock (if runtime PM is not enabled) */ + ret = gpio_stm32_clock_request(dev, !IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)); + if (ret < 0) { + return ret; + } + + if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)) { + pm_device_init_suspended(dev); + } + (void)pm_device_runtime_enable(dev); - return pm_device_driver_init(dev, gpio_stm32_pm_action); + return 0; } #define GPIO_DEVICE_INIT(__node, __suffix, __base_addr, __port, __cenr, __bus) \ diff --git a/drivers/gpio/gpio_xlnx_ps_bank.c b/drivers/gpio/gpio_xlnx_ps_bank.c index 263fa9aa90aea..8f62dc95da259 100644 --- a/drivers/gpio/gpio_xlnx_ps_bank.c +++ b/drivers/gpio/gpio_xlnx_ps_bank.c @@ -441,6 +441,9 @@ static int gpio_xlnx_ps_bank_init(const struct device *dev) sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_DIS_REG); /* Disable all interrupts */ sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_STAT_REG); /* Clear all interrupts */ + sys_write32(0x0, GPIO_XLNX_PS_BANK_OEN_REG); /* All outputs disabled */ + sys_write32(0x0, GPIO_XLNX_PS_BANK_DIRM_REG); /* All pins input */ + sys_write32(0x0, GPIO_XLNX_PS_BANK_DATA_REG); /* Zero data register */ return 0; } diff --git a/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c b/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c index 5cc1fd1449a10..f66af5b349ac3 100644 --- a/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c +++ b/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c @@ -58,7 +58,7 @@ static void hdlc_iface_init(struct net_if *iface) ctx->ot_context = net_if_l2_data(iface); - otPlatRadioGetIeeeEui64(openthread_get_default_instance(), eui64.m8); + otPlatRadioGetIeeeEui64(ctx->ot_context->instance, eui64.m8); net_if_set_link_addr(iface, eui64.m8, OT_EXT_ADDRESS_SIZE, NET_LINK_IEEE802154); } diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt index 534e539650869..a74850cfeedb9 100644 --- a/drivers/hwinfo/CMakeLists.txt +++ b/drivers/hwinfo/CMakeLists.txt @@ -12,7 +12,6 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_SHELL hwinfo_shell.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_AMBIQ hwinfo_ambiq.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_ANDES hwinfo_andes.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_CC13XX_CC26XX hwinfo_cc13xx_cc26xx.c) -zephyr_library_sources_ifdef(CONFIG_HWINFO_CC23X0 hwinfo_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_ESP32 hwinfo_esp32.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_GECKO hwinfo_gecko.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_IMXRT hwinfo_imxrt.c) diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 4a4abfac14b5c..5495eb1bb7dd5 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -62,14 +62,6 @@ endchoice endif # HWINFO_CC13XX_CC26XX -config HWINFO_CC23X0 - bool "TI CC23X0 hwinfo" - default y - depends on SOC_FAMILY_TI_SIMPLELINK && SOC_SERIES_CC23X0 - select HWINFO_HAS_DRIVER - help - Enable CC23X0 hwinfo driver. - config HWINFO_STM32 bool "STM32 hwinfo" default y @@ -255,7 +247,7 @@ config HWINFO_RW61X config HWINFO_AMBIQ bool "AMBIQ hwinfo" default y - depends on SOC_SERIES_APOLLO4X || SOC_SERIES_APOLLO5X + depends on SOC_SERIES_APOLLO4X select HWINFO_HAS_DRIVER select AMBIQ_HAL select AMBIQ_HAL_USE_HWINFO @@ -265,7 +257,7 @@ config HWINFO_AMBIQ config HWINFO_NUMAKER bool "NuMaker hwinfo" default y - depends on SOC_SERIES_M46X || SOC_SERIES_M55M1X + depends on SOC_SERIES_M46X select HWINFO_HAS_DRIVER select HAS_NUMAKER_FMC help diff --git a/drivers/hwinfo/hwinfo_ambiq.c b/drivers/hwinfo/hwinfo_ambiq.c index 928c84bf02b62..c8173e0f813fe 100644 --- a/drivers/hwinfo/hwinfo_ambiq.c +++ b/drivers/hwinfo/hwinfo_ambiq.c @@ -11,6 +11,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { + struct ambiq_hwinfo { /* Ambiq Chip ID0 */ uint32_t chip_id_0; @@ -26,12 +27,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) /* Contains the HAL hardware information about the device. */ am_hal_mcuctrl_device_t mcu_ctrl_device; -#if (CONFIG_SOC_SERIES_APOLLO5X) - am_hal_info1_read(AM_HAL_INFO_INFOSPACE_CURRENT_INFO1, AM_REG_OTP_INFO1_TRIM_REV_O / 4, 1, - &dev_hw_info.factory_trim_version); -#else am_hal_mram_info_read(1, AM_REG_INFO1_TRIM_REV_O / 4, 1, &dev_hw_info.factory_trim_version); -#endif am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &mcu_ctrl_device); dev_hw_info.chip_id_0 = mcu_ctrl_device.ui32ChipID0; @@ -65,15 +61,9 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) } /* POWER CYCLE */ -#if (CONFIG_SOC_SERIES_APOLLO5X) - if (reset_status & AM_HAL_RESET_STATUS_POA) { - flags |= RESET_POR; - } -#else if (reset_status & AM_HAL_RESET_STATUS_POR) { flags |= RESET_POR; } -#endif /* BROWNOUT DETECTOR */ if (reset_status & AM_HAL_RESET_STATUS_BOD) { @@ -120,13 +110,6 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) flags |= RESET_HARDWARE; } -#if (CONFIG_SOC_SERIES_APOLLO5X) - /* AIRCR */ - if (reset_status & AM_HAL_RESET_STATUS_AIRCR) { - flags |= RESET_SOFTWARE; - } -#endif - *cause = flags; return 0; } diff --git a/drivers/hwinfo/hwinfo_cc23x0.c b/drivers/hwinfo/hwinfo_cc23x0.c deleted file mode 100644 index 80b5b3234123f..0000000000000 --- a/drivers/hwinfo/hwinfo_cc23x0.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2025 Baylibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include - -int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) -{ - *supported = (RESET_PIN - | RESET_SOFTWARE - | RESET_BROWNOUT - | RESET_POR - | RESET_WATCHDOG - | RESET_DEBUG - | RESET_CPU_LOCKUP - | RESET_CLOCK - | RESET_TEMPERATURE); - - return 0; -} - -int z_impl_hwinfo_get_reset_cause(uint32_t *cause) -{ - uint32_t rststa = PMCTLGetResetReason(); - - switch (rststa) { - case PMCTL_RESET_PIN: - *cause = RESET_PIN; - break; - case PMCTL_RESET_SYSTEM: - *cause = RESET_SOFTWARE; - break; - case PMCTL_RESET_VDDR: - case PMCTL_RESET_VDDS: - *cause = RESET_BROWNOUT; - break; - case PMCTL_RESET_POR: - *cause = RESET_POR; - break; - case PMCTL_RESET_WATCHDOG: - *cause = RESET_WATCHDOG; - break; - case PMCTL_RESET_SWD: - case PMCTL_RESET_SHUTDOWN_SWD: - *cause = RESET_DEBUG; - break; - case PMCTL_RESET_LOCKUP: - *cause = RESET_CPU_LOCKUP; - break; - case PMCTL_RESET_LFXT: - *cause = RESET_CLOCK; - break; - case PMCTL_RESET_TSD: - *cause = RESET_TEMPERATURE; - break; - default: - *cause = 0; - break; - } - - return 0; -} diff --git a/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c b/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c index 455eb024616c3..d6415d79568b6 100644 --- a/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c +++ b/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c @@ -11,22 +11,6 @@ LOG_MODULE_REGISTER(hwinfo_cmc, CONFIG_HWINFO_LOG_LEVEL); -#ifndef CMC0 -#define CMC0 CMC -#endif - -#ifdef CMC_SRS_VBAT_MASK -#define CMC_RESET_MASK_POR (CMC_SRS_POR_MASK | CMC_SRS_VBAT_MASK) -#else -#define CMC_RESET_MASK_POR CMC_SRS_POR_MASK -#endif - -#ifdef CMC_SRS_WWDT1_MASK -#define CMC_RESET_MASK_WATCHDOG (CMC_SRS_WWDT0_MASK | CMC_SRS_WWDT1_MASK) -#else -#define CMC_RESET_MASK_WATCHDOG CMC_SRS_WWDT0_MASK -#endif - /** * @brief Translate from CMC reset source mask to Zephyr hwinfo sources mask. * @@ -45,7 +29,7 @@ static uint32_t hwinfo_mcux_cmc_xlate_reset_sources(uint32_t sources) mask |= RESET_LOW_POWER_WAKE; } - if (sources & CMC_RESET_MASK_POR) { + if (sources & (CMC_SRS_POR_MASK | CMC_SRS_VBAT_MASK)) { mask |= RESET_POR; } @@ -65,7 +49,7 @@ static uint32_t hwinfo_mcux_cmc_xlate_reset_sources(uint32_t sources) mask |= RESET_CLOCK; } - if (sources & CMC_RESET_MASK_WATCHDOG) { + if (sources & (CMC_SRS_WWDT0_MASK | CMC_SRS_WWDT1_MASK)) { mask |= RESET_WATCHDOG; } @@ -81,11 +65,9 @@ static uint32_t hwinfo_mcux_cmc_xlate_reset_sources(uint32_t sources) mask |= RESET_WATCHDOG; } -#ifdef CMC_SRS_SECVIO_MASK if (sources & CMC_SRS_SECVIO_MASK) { mask |= RESET_SECURITY; } -#endif return mask; } diff --git a/drivers/hwinfo/hwinfo_mcux_rcm.c b/drivers/hwinfo/hwinfo_mcux_rcm.c index ed8122ac73b5d..e7dfcd6c3382f 100644 --- a/drivers/hwinfo/hwinfo_mcux_rcm.c +++ b/drivers/hwinfo/hwinfo_mcux_rcm.c @@ -120,9 +120,12 @@ int z_impl_hwinfo_clear_reset_cause(void) #if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) { - *supported = hwinfo_mcux_rcm_xlate_reset_sources(UINT32_MAX); + uint32_t sources; + + sources = RCM_GetResetSourceImplementedStatus(RCM); + *supported = hwinfo_mcux_rcm_xlate_reset_sources(sources); - LOG_DBG("supported = 0x%08x", *supported); + LOG_DBG("sources = 0x%08x, supported = 0x%08x", sources, *supported); return 0; } diff --git a/drivers/hwinfo/hwinfo_smartbond.c b/drivers/hwinfo/hwinfo_smartbond.c index be77f8b4f277a..f19c7770d60b8 100644 --- a/drivers/hwinfo/hwinfo_smartbond.c +++ b/drivers/hwinfo/hwinfo_smartbond.c @@ -6,42 +6,7 @@ #include #include -#include #include -#include - -#define PRODUCT_INFO_GPOUP (12U) -#define CHIP_ID_GPOUP (13U) - -#define PRODUCT_INFO_LENGTH (3U) -#define CHIP_ID_LENGTH (1U) - -ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) -{ - size_t len; - uint32_t unique_id[4]; - uint8_t product_info_len; - uint8_t chip_id_len; - - product_info_len = da1469x_trimv_group_read(PRODUCT_INFO_GPOUP, &unique_id[0], - PRODUCT_INFO_LENGTH); - chip_id_len = da1469x_trimv_group_read(CHIP_ID_GPOUP, &unique_id[3], - CHIP_ID_LENGTH); - - if ((product_info_len != PRODUCT_INFO_LENGTH) || (chip_id_len != CHIP_ID_LENGTH)) { - return -ENODATA; - } - - for (uint8_t i = 0; i < (product_info_len + chip_id_len); i++) { - unique_id[i] = BSWAP_32(unique_id[i]); - } - - len = MIN(length, sizeof(unique_id)); - - memcpy(buffer, unique_id, len); - - return len; -} int z_impl_hwinfo_get_reset_cause(uint32_t *cause) { diff --git a/drivers/i2c/Kconfig.ambiq b/drivers/i2c/Kconfig.ambiq index c1fbfd22d6f71..727573310e773 100644 --- a/drivers/i2c/Kconfig.ambiq +++ b/drivers/i2c/Kconfig.ambiq @@ -16,12 +16,16 @@ menuconfig I2C_AMBIQ if I2C_AMBIQ -config I2C_AMBIQ_HANDLE_CACHE - bool "Turn on cache handling in i2c driver" - default y - depends on CACHE_MANAGEMENT && DCACHE +config I2C_AMBIQ_DMA + bool "AMBIQ APOLLO I2C DMA Support" + help + Enable DMA for Ambiq I2C. + +config I2C_DMA_TCB_BUFFER_SIZE + int "DMA Transfer Control Buffer size in words." + default 1024 help - Disable this if cache has been handled in upper layers. + DMA Transfer Control Buffer size in words config I2C_AMBIQ_BUS_RECOVERY bool "Bus recovery support" diff --git a/drivers/i2c/i2c_ambiq.c b/drivers/i2c/i2c_ambiq.c index cae3cbc27ba78..8d2be5eccc240 100644 --- a/drivers/i2c/i2c_ambiq.c +++ b/drivers/i2c/i2c_ambiq.c @@ -12,7 +12,26 @@ #include #include #include -#include + +#include + +#include + +#ifdef CONFIG_DCACHE +#include +#endif /* CONFIG_DCACHE */ + +#ifdef CONFIG_NOCACHE_MEMORY +#include +#elif defined(CONFIG_CACHE_MANAGEMENT) +#include +#endif /* CONFIG_NOCACHE_MEMORY */ + +#if defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY) +#define I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 1 +#else +#define I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 0 +#endif /* defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY) */ #ifdef CONFIG_I2C_AMBIQ_BUS_RECOVERY #include @@ -28,8 +47,6 @@ LOG_MODULE_REGISTER(ambiq_i2c, CONFIG_I2C_LOG_LEVEL); #include "i2c-priv.h" -#include - struct i2c_ambiq_config { #ifdef CONFIG_I2C_AMBIQ_BUS_RECOVERY struct gpio_dt_spec scl; @@ -54,7 +71,6 @@ struct i2c_ambiq_data { void *callback_data; uint32_t transfer_status; bool pm_policy_state_on; - bool dma_mode; }; static void i2c_ambiq_pm_policy_state_lock_get(const struct device *dev) @@ -83,6 +99,17 @@ static void i2c_ambiq_pm_policy_state_lock_put(const struct device *dev) } } +#ifdef CONFIG_I2C_AMBIQ_DMA +/* + * If Nocache Memory is supported, buffer will be placed in nocache region by + * the linker to avoid potential DMA cache-coherency problems. + * If Nocache Memory is not supported, cache coherency might need to be kept + * manually. See I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED. + */ +static __aligned(32) struct { + __aligned(32) uint32_t buf[CONFIG_I2C_DMA_TCB_BUFFER_SIZE]; +} i2c_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __nocache; + static void i2c_ambiq_callback(void *callback_ctxt, uint32_t status) { const struct device *dev = callback_ctxt; @@ -94,6 +121,40 @@ static void i2c_ambiq_callback(void *callback_ctxt, uint32_t status) data->transfer_status = status; } +#ifdef CONFIG_DCACHE +static bool buf_in_nocache(uintptr_t buf, size_t len_bytes) +{ + bool buf_within_nocache = false; + +#ifdef CONFIG_NOCACHE_MEMORY + /* Check if buffer is in nocache region defined by the linker */ + buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) && + ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end)); + if (buf_within_nocache) { + return true; + } +#endif /* CONFIG_NOCACHE_MEMORY */ + + /* Check if buffer is in nocache memory region defined in DT */ + buf_within_nocache = + mem_attr_check_buf((void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0; + + return buf_within_nocache; +} + +static bool i2c_buf_set_in_nocache(const struct i2c_msg *msgs, uint8_t num_msgs) +{ + for (int i = 0; i < num_msgs; i++) { + if (!buf_in_nocache((uintptr_t)msgs[i]->buf, msgs[i]->len)) { + return false; + } + } + return true; +} +#endif /* CONFIG_DCACHE */ + +#endif + static void i2c_ambiq_isr(const struct device *dev) { uint32_t ui32Status; @@ -124,39 +185,34 @@ static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *hdr_msg, return -E2BIG; } #if defined(CONFIG_SOC_SERIES_APOLLO3X) - trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) - & (0xFFFFFFFFUL >> (32 - (hdr_msg->len * 8))); + trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) & (0xFFFFFFFF >> (32 - (hdr_msg->len * 8))); #else - trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) - & (0xFFFFFFFFFFFFFFFFULL >> (64 - (hdr_msg->len * 8))); + trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) & (0xFFFFFFFFFFFFFFFF >> (64 - (hdr_msg->len * 8))); #endif trans.ui32InstrLen = hdr_msg->len; } - if (data->dma_mode) { - data->transfer_status = -EFAULT; - ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback, - (void *)dev); - if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) { - LOG_ERR("Timeout waiting for transfer complete"); - /* cancel timed out transaction */ - am_hal_iom_disable(data->iom_handler); - /* clean up for next xfer */ - k_sem_reset(&data->transfer_sem); - am_hal_iom_enable(data->iom_handler); - return -ETIMEDOUT; - } -#if CONFIG_I2C_AMBIQ_HANDLE_CACHE - if (!buf_in_nocache((uintptr_t)trans.pui32RxBuffer, trans.ui32NumBytes)) { - /* Invalidate Dcache after DMA read */ - sys_cache_data_invd_range((void *)trans.pui32RxBuffer, trans.ui32NumBytes); - } -#endif /* CONFIG_I2C_AMBIQ_HANDLE_CACHE */ - ret = data->transfer_status; - } else { - ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans); +#ifdef CONFIG_I2C_AMBIQ_DMA + data->transfer_status = -EFAULT; + ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback, + (void *)dev); + if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) { + LOG_ERR("Timeout waiting for transfer complete"); + /* cancel timed out transaction */ + am_hal_iom_disable(data->iom_handler); + /* clean up for next xfer */ + k_sem_reset(&data->transfer_sem); + am_hal_iom_enable(data->iom_handler); + return -ETIMEDOUT; } - +#if I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED + /* Invalidate Dcache after DMA read */ + sys_cache_data_invd_range((void *)trans.pui32RxBuffer, trans.ui32NumBytes); +#endif /* I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */ + ret = data->transfer_status; +#else + ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans); +#endif return (ret != AM_HAL_STATUS_SUCCESS) ? -EIO : 0; } @@ -179,39 +235,35 @@ static int i2c_ambiq_write(const struct device *dev, struct i2c_msg *hdr_msg, return -E2BIG; } #if defined(CONFIG_SOC_SERIES_APOLLO3X) - trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) - & (0xFFFFFFFFUL >> (32 - (hdr_msg->len * 8))); + trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) & (0xFFFFFFFF >> (32 - (hdr_msg->len * 8))); #else - trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) - & (0xFFFFFFFFFFFFFFFFULL >> (64 - (hdr_msg->len * 8))); + trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) & (0xFFFFFFFFFFFFFFFF >> (64 - (hdr_msg->len * 8))); #endif trans.ui32InstrLen = hdr_msg->len; } - if (data->dma_mode) { - data->transfer_status = -EFAULT; -#if CONFIG_I2C_AMBIQ_HANDLE_CACHE - if (!buf_in_nocache((uintptr_t)trans.pui32TxBuffer, trans.ui32NumBytes)) { - /* Clean Dcache before DMA write */ - sys_cache_data_flush_range((void *)trans.pui32TxBuffer, trans.ui32NumBytes); - } -#endif /* CONFIG_I2C_AMBIQ_HANDLE_CACHE */ - ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback, - (void *)dev); - - if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) { - LOG_ERR("Timeout waiting for transfer complete"); - /* cancel timed out transaction */ - am_hal_iom_disable(data->iom_handler); - /* clean up for next xfer */ - k_sem_reset(&data->transfer_sem); - am_hal_iom_enable(data->iom_handler); - return -ETIMEDOUT; - } - ret = data->transfer_status; - } else { - ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans); +#ifdef CONFIG_I2C_AMBIQ_DMA + data->transfer_status = -EFAULT; +#if I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED + /* Clean Dcache before DMA write */ + sys_cache_data_flush_range((void *)trans.pui32TxBuffer, trans.ui32NumBytes); +#endif /* I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */ + ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback, + (void *)dev); + + if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) { + LOG_ERR("Timeout waiting for transfer complete"); + /* cancel timed out transaction */ + am_hal_iom_disable(data->iom_handler); + /* clean up for next xfer */ + k_sem_reset(&data->transfer_sem); + am_hal_iom_enable(data->iom_handler); + return -ETIMEDOUT; } + ret = data->transfer_status; +#else + ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans); +#endif return (ret != AM_HAL_STATUS_SUCCESS) ? -EIO : 0; } @@ -238,6 +290,13 @@ static int i2c_ambiq_configure(const struct device *dev, uint32_t dev_config) return -EINVAL; } +#ifdef CONFIG_I2C_AMBIQ_DMA + const struct i2c_ambiq_config *cfg = dev->config; + + data->iom_cfg.pNBTxnBuf = i2c_dma_tcb_buf[cfg->inst_idx].buf; + data->iom_cfg.ui32NBTxnBufLength = CONFIG_I2C_DMA_TCB_BUFFER_SIZE; +#endif + am_hal_iom_configure(data->iom_handler, &data->iom_cfg); return 0; @@ -253,6 +312,12 @@ static int i2c_ambiq_transfer(const struct device *dev, struct i2c_msg *msgs, ui return 0; } +#if defined(CONFIG_I2C_AMBIQ_DMA) && defined(CONFIG_DCACHE) + if (!i2c_buf_set_in_nocache(msgs, num_msgs)) { + return -EFAULT; + } +#endif /* CONFIG_DCACHE */ + i2c_ambiq_pm_policy_state_lock_get(dev); /* Send out messages */ @@ -376,6 +441,8 @@ static int i2c_ambiq_init(const struct device *dev) uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate); int ret = 0; + data->iom_cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE; + if (AM_HAL_STATUS_SUCCESS != am_hal_iom_initialize(config->inst_idx, &data->iom_handler)) { LOG_ERR("Fail to initialize I2C\n"); return -ENXIO; @@ -395,13 +462,11 @@ static int i2c_ambiq_init(const struct device *dev) goto end; } - if (data->dma_mode) { - am_hal_iom_interrupt_clear(data->iom_handler, - AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); - am_hal_iom_interrupt_enable(data->iom_handler, - AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); - config->irq_config_func(); - } +#ifdef CONFIG_I2C_AMBIQ_DMA + am_hal_iom_interrupt_clear(data->iom_handler, AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); + am_hal_iom_interrupt_enable(data->iom_handler, AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); + config->irq_config_func(); +#endif if (AM_HAL_STATUS_SUCCESS != am_hal_iom_enable(data->iom_handler)) { LOG_ERR("Fail to enable I2C\n"); @@ -453,17 +518,7 @@ static int i2c_ambiq_pm_action(const struct device *dev, enum pm_device_action a } #endif /* CONFIG_PM_DEVICE */ -#define IOM_HAL_CFG(n, cmdq, cmdq_size) \ - { \ - .eInterfaceMode = AM_HAL_IOM_I2C_MODE, \ - .ui32ClockFreq = AM_HAL_IOM_100KHZ, \ - .pNBTxnBuf = cmdq, \ - .ui32NBTxnBufLength = cmdq_size, \ - } - #define AMBIQ_I2C_DEFINE(n) \ - BUILD_ASSERT(DT_CHILD_NUM_STATUS_OKAY(DT_INST_PARENT(n)) == 1, \ - "Too many children for IOM, either SPI or I2C should be enabled!"); \ PINCTRL_DT_INST_DEFINE(n); \ static void i2c_irq_config_func_##n(void) \ { \ @@ -471,21 +526,9 @@ static int i2c_ambiq_pm_action(const struct device *dev, enum pm_device_action a i2c_ambiq_isr, DEVICE_DT_INST_GET(n), 0); \ irq_enable(DT_IRQN(DT_INST_PARENT(n))); \ }; \ - IF_ENABLED(DT_PROP(DT_INST_PARENT(n), dma_mode), \ - (static uint32_t i2c_ambiq_cmdq##n[DT_PROP_OR(DT_INST_PARENT(n), cmdq_buffer_size, 1024)] \ - __attribute__((section(DT_PROP_OR(DT_INST_PARENT(n), \ - cmdq_buffer_location, ".nocache"))));) \ - ) \ static struct i2c_ambiq_data i2c_ambiq_data##n = { \ - .iom_cfg = IOM_HAL_CFG( \ - n, COND_CODE_1(DT_PROP(DT_INST_PARENT(n), dma_mode), (i2c_ambiq_cmdq##n), \ - (NULL)), \ - COND_CODE_1(DT_PROP(DT_INST_PARENT(n), dma_mode), \ - (DT_INST_PROP_OR(n, cmdq_buffer_size, 1024)), (0))), \ - .dma_mode = DT_PROP(DT_INST_PARENT(n), dma_mode), \ .bus_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.bus_sem, 1, 1), \ - .transfer_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.transfer_sem, 0, 1), \ - }; \ + .transfer_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.transfer_sem, 0, 1)}; \ static const struct i2c_ambiq_config i2c_ambiq_config##n = { \ .base = DT_REG_ADDR(DT_INST_PARENT(n)), \ .size = DT_REG_SIZE(DT_INST_PARENT(n)), \ diff --git a/drivers/i2c/i2c_max32.c b/drivers/i2c/i2c_max32.c index adae37cdc4a78..d23910b416c1b 100644 --- a/drivers/i2c/i2c_max32.c +++ b/drivers/i2c/i2c_max32.c @@ -21,6 +21,8 @@ #define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF #define ADI_MAX32_I2C_INT_FL1_MASK 0x7 +#define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5) + #define I2C_RECOVER_MAX_RETRIES 3 #ifdef CONFIG_I2C_MAX32_DMA @@ -538,7 +540,8 @@ static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, ui /* Wait for busy flag to be cleared for clock stetching * use-cases */ - Wrap_MXC_I2C_WaitForBusyClear(i2c); + while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) { + } MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); } @@ -647,7 +650,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c) uint32_t int_en0; uint32_t int_en1; - Wrap_MXC_I2C_GetCtrl(i2c, &ctrl); + ctrl = i2c->ctrl; Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); @@ -707,7 +710,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c) if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) { if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) { /* Address match occurred, prepare for transaction */ - if (Wrap_MXC_I2C_GetReadWriteBitStatus(i2c)) { + if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { /* Read request received from the master */ i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD); int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD | diff --git a/drivers/i2s/CMakeLists.txt b/drivers/i2s/CMakeLists.txt index af5b38987cc4e..7857b6e863b5a 100644 --- a/drivers/i2s/CMakeLists.txt +++ b/drivers/i2s/CMakeLists.txt @@ -13,5 +13,4 @@ zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_FLEXCOMM i2s_mcux_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_I2S_NRFX i2s_nrfx.c) zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_SAI i2s_mcux_sai.c) zephyr_library_sources_ifdef(CONFIG_I2S_ESP32 i2s_esp32.c) -zephyr_library_sources_ifdef(CONFIG_I2S_SILABS_SIWX91X i2s_silabs_siwx91x.c) zephyr_library_sources_ifdef(CONFIG_I2S_TEST i2s_test.c) diff --git a/drivers/i2s/Kconfig.siwx91x b/drivers/i2s/Kconfig.siwx91x deleted file mode 100644 index 9825efefb4c44..0000000000000 --- a/drivers/i2s/Kconfig.siwx91x +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2025 Silicon Laboratories Inc. -# SPDX-License-Identifier: Apache-2.0 - -menuconfig I2S_SILABS_SIWX91X - bool "Silabs Siwx91x MCU I2S controller driver" - default y - depends on DT_HAS_SILABS_SIWX91X_I2S_ENABLED - select CACHE_MANAGEMENT if CPU_HAS_DCACHE - select DMA - select PINCTRL - select GPIO - help - Enable I2S support on the Siwx91x family. - -if I2S_SILABS_SIWX91X - -config I2S_SILABS_SIWX91X_RX_BLOCK_COUNT - int "RX queue length" - default 4 - -config I2S_SILABS_SIWX91X_TX_BLOCK_COUNT - int "TX queue length" - default 4 - -config I2S_SILABS_SIWX91X_DMA_MAX_BLOCKS - int "Maximum DMA transfer block per channel for a transaction." - default 16 - help - One block is needed for every 1024 bytes - -endif # I2S_SILABS_SIWX91X diff --git a/drivers/i2s/i2s_ll_stm32.c b/drivers/i2s/i2s_ll_stm32.c index 5c66323bd33dc..bbf7e60de62f0 100644 --- a/drivers/i2s/i2s_ll_stm32.c +++ b/drivers/i2s/i2s_ll_stm32.c @@ -274,11 +274,10 @@ static int i2s_stm32_configure(const struct device *dev, enum i2s_dir dir, } /* set I2S clock polarity */ - if ((i2s_cfg->format & I2S_FMT_CLK_FORMAT_MASK) == I2S_FMT_BIT_CLK_INV) { + if ((i2s_cfg->format & I2S_FMT_CLK_FORMAT_MASK) == I2S_FMT_BIT_CLK_INV) LL_I2S_SetClockPolarity(cfg->i2s, LL_I2S_POLARITY_HIGH); - } else { + else LL_I2S_SetClockPolarity(cfg->i2s, LL_I2S_POLARITY_LOW); - } stream->state = I2S_STATE_READY; return 0; diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c index 4449897b53373..2cfd9da8fbb96 100644 --- a/drivers/i2s/i2s_mcux_sai.c +++ b/drivers/i2s/i2s_mcux_sai.c @@ -1124,8 +1124,6 @@ static int i2s_mcux_initialize(const struct device *dev) /*clock configuration*/ audio_clock_settings(dev); - enable_mclk_direction(dev, dev_cfg->mclk_output); - SAI_Init(base); dev_data->tx.state = I2S_STATE_NOT_READY; diff --git a/drivers/i2s/i2s_silabs_siwx91x.c b/drivers/i2s/i2s_silabs_siwx91x.c deleted file mode 100644 index 1ef207ba65f98..0000000000000 --- a/drivers/i2s/i2s_silabs_siwx91x.c +++ /dev/null @@ -1,910 +0,0 @@ -/* - * Copyright (c) 2025 Silicon Laboratories Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT silabs_siwx91x_i2s - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "clock_update.h" - -#include "rsi_rom_clks.h" -#include "rsi_rom_ulpss_clk.h" -#include "rsi_power_save.h" -#include "rsi_pll.h" -#include "rsi_ulpss_clk.h" -#include "clock_update.h" - -#define DMA_MAX_TRANSFER_COUNT 1024 -#define I2S_SIWX91X_UNSUPPORTED_OPTIONS \ - (I2S_OPT_BIT_CLK_SLAVE | I2S_OPT_FRAME_CLK_SLAVE | I2S_OPT_LOOPBACK | I2S_OPT_PINGPONG | \ - I2S_OPT_BIT_CLK_GATED) - -struct i2s_siwx91x_config { - I2S0_Type *reg; - const struct device *clock_dev; - clock_control_subsys_t clock_subsys_peripheral; - clock_control_subsys_t clock_subsys_static; - const struct pinctrl_dev_config *pcfg; - uint8_t channel_group; -}; - -struct i2s_siwx91x_queue_item { - void *mem_block; - size_t size; -}; - -struct i2s_siwx91x_ring_buffer { - struct i2s_siwx91x_queue_item *buf; - uint16_t len; - uint16_t head; - uint16_t tail; -}; - -struct i2s_siwx91x_stream { - int32_t state; - struct k_sem sem; - const struct device *dma_dev; - uint32_t dma_channel; - bool last_block; - struct i2s_config cfg; - struct i2s_siwx91x_ring_buffer mem_block_queue; - void *mem_block; - bool reload_en; - struct dma_block_config dma_descriptors[CONFIG_I2S_SILABS_SIWX91X_DMA_MAX_BLOCKS]; - int (*stream_start)(struct i2s_siwx91x_stream *stream, const struct device *dev); - void (*queue_drop)(struct i2s_siwx91x_stream *stream); -}; - -struct i2s_siwx91x_data { - struct i2s_siwx91x_stream rx; - struct i2s_siwx91x_stream tx; - uint8_t current_resolution; -}; - -static void i2s_siwx91x_dma_rx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status); -static void i2s_siwx91x_dma_tx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status); - -static bool i2s_siwx91x_validate_word_size(uint8_t word_size) -{ - switch (word_size) { - case 16: - case 24: - case 32: - return true; - default: - return false; - } -} - -static bool i2s_siwx91x_validate_frequency(uint32_t sampling_freq) -{ - switch (sampling_freq) { - case 8000: - case 11025: - case 16000: - case 22050: - case 24000: - case 32000: - case 44100: - case 48000: - case 88200: - case 96000: - case 192000: - return true; - default: - return false; - } -} - -static int i2s_siwx91x_convert_to_resolution(uint8_t word_size) -{ - switch (word_size) { - case 16: - return 2; - case 24: - return 4; - case 32: - return 5; - default: - return -EINVAL; - } -} - -static int i2s_siwx91x_queue_put(struct i2s_siwx91x_ring_buffer *rb, void *mem_block, size_t size) -{ - uint16_t head_next; - unsigned int key; - - key = irq_lock(); - - head_next = rb->head; - head_next = (head_next + 1) % rb->len; - - if (head_next == rb->tail) { - /* Ring buffer is full */ - irq_unlock(key); - return -ENOMEM; - } - - rb->buf[rb->head].mem_block = mem_block; - rb->buf[rb->head].size = size; - rb->head = head_next; - - irq_unlock(key); - - return 0; -} - -static int i2s_siwx91x_queue_get(struct i2s_siwx91x_ring_buffer *rb, void **mem_block, size_t *size) -{ - unsigned int key; - - key = irq_lock(); - - if (rb->tail == rb->head) { - /* Ring buffer is empty */ - irq_unlock(key); - return -ENOMEM; - } - - *mem_block = rb->buf[rb->tail].mem_block; - *size = rb->buf[rb->tail].size; - rb->tail = (rb->tail + 1) % rb->len; - - irq_unlock(key); - - return 0; -} - -static int i2s_siwx91x_dma_config(const struct device *dev, struct i2s_siwx91x_stream *stream, - uint32_t block_count, bool is_tx, uint8_t xfer_size) -{ - struct dma_config cfg = { - .channel_direction = is_tx ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY, - .complete_callback_en = 0, - .source_data_size = xfer_size, - .dest_data_size = xfer_size, - .source_burst_length = xfer_size, - .dest_burst_length = xfer_size, - .block_count = block_count, - .head_block = stream->dma_descriptors, - .dma_callback = is_tx ? &i2s_siwx91x_dma_tx_callback : &i2s_siwx91x_dma_rx_callback, - .user_data = (void *)dev, - }; - - return dma_config(stream->dma_dev, stream->dma_channel, &cfg); -} - -struct dma_block_config *i2s_siwx91x_fill_data_desc(const struct i2s_siwx91x_config *cfg, - struct dma_block_config *desc, void *buffer, - uint32_t size, bool is_tx, uint8_t xfer_size) -{ - uint32_t max_chunk_size = DMA_MAX_TRANSFER_COUNT * xfer_size; - uint8_t *current_buffer = buffer; - int num_descriptors = (size + max_chunk_size - 1) / max_chunk_size; - int i; - - if (num_descriptors > CONFIG_I2S_SILABS_SIWX91X_DMA_MAX_BLOCKS) { - return NULL; - } - - for (i = 0; i < num_descriptors; i++) { - if (is_tx) { - desc[i].source_address = (uint32_t)current_buffer; - desc[i].dest_address = (uint32_t)&cfg->reg->I2S_TXDMA; - desc[i].dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; - desc[i].source_addr_adj = DMA_ADDR_ADJ_INCREMENT; - } else { - desc[i].dest_address = (uint32_t)current_buffer; - desc[i].source_address = (uint32_t)&(cfg->reg->I2S_RXDMA); - desc[i].source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; - desc[i].dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; - } - - desc[i].block_size = MIN(size, max_chunk_size); - size -= max_chunk_size; - current_buffer += max_chunk_size; - } - - desc[i - 1].next_block = NULL; - - return &desc[i - 1]; -} - -static void i2s_siwx91x_reset_desc(struct i2s_siwx91x_stream *stream) -{ - int i; - - memset(stream->dma_descriptors, 0, sizeof(stream->dma_descriptors)); - - for (i = 0; i < ARRAY_SIZE(stream->dma_descriptors) - 1; i++) { - stream->dma_descriptors[i].next_block = &stream->dma_descriptors[i + 1]; - } -} - -static int i2s_siwx91x_prepare_dma_channel(const struct device *i2s_dev, void *buffer, - uint32_t blk_size, uint32_t dma_channel, bool is_tx) -{ - const struct i2s_siwx91x_config *cfg = i2s_dev->config; - struct i2s_siwx91x_data *data = i2s_dev->data; - struct i2s_siwx91x_stream *stream; - struct dma_block_config *desc; - uint8_t xfer_size; - int ret; - - if (is_tx) { - stream = &data->tx; - } else { - stream = &data->rx; - } - - if (stream->cfg.word_size != 24) { - xfer_size = stream->cfg.word_size / 8; - } else { - /* 24-bit resolution also uses 32-bit (4 bytes) data size */ - xfer_size = 4; - } - - i2s_siwx91x_reset_desc(stream); - - desc = i2s_siwx91x_fill_data_desc(cfg, stream->dma_descriptors, buffer, blk_size, is_tx, - xfer_size); - if (!desc) { - return -ENOMEM; - } - - ret = i2s_siwx91x_dma_config(i2s_dev, stream, - ARRAY_INDEX(stream->dma_descriptors, desc) + 1, - is_tx, xfer_size); - if (ret) { - return ret; - } - - if (ARRAY_INDEX(stream->dma_descriptors, desc) == 0) { - /* Transfer size <= 1024*xfer_size */ - stream->reload_en = true; - } - - return ret; -} - -static int i2s_siwx91x_tx_stream_start(struct i2s_siwx91x_stream *stream, const struct device *dev) -{ - size_t mem_block_size; - int ret; - - ret = i2s_siwx91x_queue_get(&stream->mem_block_queue, &stream->mem_block, &mem_block_size); - if (ret < 0) { - return ret; - } - - k_sem_give(&stream->sem); - - ret = i2s_siwx91x_prepare_dma_channel(dev, stream->mem_block, mem_block_size, - stream->dma_channel, true); - if (ret < 0) { - return ret; - } - - ret = dma_start(stream->dma_dev, stream->dma_channel); - if (ret < 0) { - return ret; - } - - return 0; -} - -static int i2s_siwx91x_rx_stream_start(struct i2s_siwx91x_stream *stream, const struct device *dev) -{ - int ret; - - ret = k_mem_slab_alloc(stream->cfg.mem_slab, &stream->mem_block, K_NO_WAIT); - if (ret < 0) { - return ret; - } - - ret = i2s_siwx91x_prepare_dma_channel(dev, stream->mem_block, stream->cfg.block_size, - stream->dma_channel, false); - - if (ret < 0) { - return ret; - } - - ret = dma_start(stream->dma_dev, stream->dma_channel); - if (ret < 0) { - return ret; - } - - return 0; -} - -static void i2s_siwx91x_stream_disable(struct i2s_siwx91x_stream *stream, - const struct device *dma_dev) -{ - dma_stop(dma_dev, stream->dma_channel); - - dma_release_channel(dma_dev, stream->dma_channel); - - if (stream->mem_block != NULL) { - k_mem_slab_free(stream->cfg.mem_slab, stream->mem_block); - stream->mem_block = NULL; - } -} - -static void i2s_siwx91x_rx_queue_drop(struct i2s_siwx91x_stream *stream) -{ - size_t size; - void *mem_block; - - while (i2s_siwx91x_queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) { - k_mem_slab_free(stream->cfg.mem_slab, mem_block); - } - - k_sem_reset(&stream->sem); -} - -static void i2s_siwx91x_tx_queue_drop(struct i2s_siwx91x_stream *stream) -{ - size_t size; - void *mem_block; - uint32_t n = 0U; - - while (i2s_siwx91x_queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) { - k_mem_slab_free(stream->cfg.mem_slab, mem_block); - n++; - } - - for (; n > 0; n--) { - k_sem_give(&stream->sem); - } -} - -static void i2s_siwx91x_dma_rx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status) -{ - const struct device *i2s_dev = user_data; - const struct i2s_siwx91x_config *cfg = i2s_dev->config; - struct i2s_siwx91x_data *data = i2s_dev->data; - struct i2s_siwx91x_stream *stream = &data->rx; - uint8_t data_size; /* data size in bytes */ - int ret; - - __ASSERT_NO_MSG(stream->mem_block != NULL); - - if (stream->state == I2S_STATE_ERROR) { - goto rx_disable; - } - - ret = i2s_siwx91x_queue_put(&stream->mem_block_queue, stream->mem_block, - stream->cfg.block_size); - if (ret < 0) { - stream->state = I2S_STATE_ERROR; - goto rx_disable; - } - - stream->mem_block = NULL; - k_sem_give(&stream->sem); - - if (stream->state == I2S_STATE_STOPPING) { - stream->state = I2S_STATE_READY; - goto rx_disable; - } - - ret = k_mem_slab_alloc(stream->cfg.mem_slab, &stream->mem_block, K_NO_WAIT); - if (ret < 0) { - stream->state = I2S_STATE_ERROR; - goto rx_disable; - } - - if (stream->cfg.word_size == 24) { - /* 24-bit resolution also uses 32-bit (4 bytes) data size */ - data_size = 4; - } else { - data_size = stream->cfg.word_size / 8; - } - - if ((stream->cfg.block_size <= DMA_MAX_TRANSFER_COUNT * data_size) && stream->reload_en) { - ret = dma_reload(dma_dev, stream->dma_channel, (uint32_t)&cfg->reg->I2S_RXDMA, - (uint32_t)stream->mem_block, stream->cfg.block_size); - } else { - ret = i2s_siwx91x_prepare_dma_channel(i2s_dev, stream->mem_block, - stream->cfg.block_size, stream->dma_channel, - false); - stream->reload_en = false; - } - - if (ret < 0) { - goto rx_disable; - } - - ret = dma_start(dma_dev, stream->dma_channel); - if (ret < 0) { - goto rx_disable; - } - - return; - -rx_disable: - i2s_siwx91x_stream_disable(stream, dma_dev); -} - -static void i2s_siwx91x_dma_tx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status) -{ - const struct device *i2s_dev = user_data; - const struct i2s_siwx91x_config *cfg = i2s_dev->config; - struct i2s_siwx91x_data *data = i2s_dev->data; - struct i2s_siwx91x_stream *stream = &data->tx; - size_t mem_block_size; - uint8_t data_size; /* data size in bytes */ - int ret; - - __ASSERT_NO_MSG(stream->mem_block != NULL); - - k_mem_slab_free(stream->cfg.mem_slab, stream->mem_block); - stream->mem_block = NULL; - - if (stream->state == I2S_STATE_ERROR) { - goto tx_disable; - } - - if (stream->last_block) { - stream->state = I2S_STATE_READY; - goto tx_disable; - } - - ret = i2s_siwx91x_queue_get(&stream->mem_block_queue, &stream->mem_block, &mem_block_size); - if (ret < 0) { - if (stream->state == I2S_STATE_STOPPING) { - stream->state = I2S_STATE_READY; - } else { - stream->state = I2S_STATE_ERROR; - } - goto tx_disable; - } - - k_sem_give(&stream->sem); - - if (stream->cfg.word_size == 24) { - data_size = 4; - } else { - data_size = stream->cfg.word_size / 8; - } - - if ((mem_block_size <= DMA_MAX_TRANSFER_COUNT * data_size) && stream->reload_en) { - ret = dma_reload(dma_dev, stream->dma_channel, (uint32_t)stream->mem_block, - (uint32_t)&cfg->reg->I2S_TXDMA, mem_block_size); - } else { - ret = i2s_siwx91x_prepare_dma_channel(i2s_dev, stream->mem_block, mem_block_size, - stream->dma_channel, true); - stream->reload_en = false; - } - if (ret < 0) { - goto tx_disable; - } - - ret = dma_start(dma_dev, stream->dma_channel); - if (ret < 0) { - goto tx_disable; - } - - return; - -tx_disable: - i2s_siwx91x_stream_disable(stream, dma_dev); -} - -static int i2s_siwx91x_param_config(const struct device *dev, enum i2s_dir dir) -{ - const struct i2s_siwx91x_config *cfg = dev->config; - struct i2s_siwx91x_data *data = dev->data; - struct i2s_siwx91x_stream *stream; - uint32_t bit_freq; - int resolution; - int ret; - - if (dir == I2S_DIR_RX) { - stream = &data->rx; - } else { - stream = &data->tx; - } - - resolution = i2s_siwx91x_convert_to_resolution(stream->cfg.word_size); - if (resolution < 0) { - return -EINVAL; - } - - if (resolution != data->current_resolution) { - ret = clock_control_off(cfg->clock_dev, cfg->clock_subsys_static); - if (ret) { - return ret; - } - - /* Configure primary mode and bit clock frequency */ - bit_freq = 2 * stream->cfg.frame_clk_freq * stream->cfg.word_size; - - ret = clock_control_set_rate(cfg->clock_dev, cfg->clock_subsys_peripheral, - &bit_freq); - if (ret) { - return ret; - } - - cfg->reg->I2S_CCR_b.WSS = (resolution - 1) / 2; - cfg->reg->I2S_CCR_b.SCLKG = resolution; - data->current_resolution = resolution; - } - - if (dir == I2S_DIR_RX) { - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_RCR_b.WLEN = resolution; - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_RFCR_b.RXCHDT = 1; - } else { - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_TCR_b.WLEN = resolution; - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_TXFCR_b.TXCHET = 0; - } - - ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys_static); - if (ret) { - return ret; - } - - return 0; -} - -static int i2s_siwx91x_dma_channel_alloc(const struct device *dev, enum i2s_dir dir) -{ - struct i2s_siwx91x_data *data = dev->data; - struct i2s_siwx91x_stream *stream; - int channel_filter; - - if (dir == I2S_DIR_RX) { - stream = &data->rx; - } else { - stream = &data->tx; - } - - dma_release_channel(stream->dma_dev, stream->dma_channel); - - channel_filter = stream->dma_channel; - stream->dma_channel = dma_request_channel(stream->dma_dev, &channel_filter); - if (stream->dma_channel != channel_filter) { - stream->dma_channel = channel_filter; - return -EAGAIN; - } - - return 0; -} - -static void i2s_siwx91x_start_tx(const struct device *dev) -{ - const struct i2s_siwx91x_config *cfg = dev->config; - - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_IMR &= ~F_TXFEM; - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_TER_b.TXCHEN = 1; - cfg->reg->CHANNEL_CONFIG[1 - cfg->channel_group].I2S_TER_b.TXCHEN = 0; -} - -static void i2s_siwx91x_start_rx(const struct device *dev) -{ - const struct i2s_siwx91x_config *cfg = dev->config; - - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_RER_b.RXCHEN = 1; - cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_IMR &= ~F_RXDAM; - cfg->reg->CHANNEL_CONFIG[1 - cfg->channel_group].I2S_RER_b.RXCHEN = 0; -} - -static int i2s_siwx91x_configure(const struct device *dev, enum i2s_dir dir, - const struct i2s_config *i2s_cfg) -{ - struct i2s_siwx91x_data *data = dev->data; - struct i2s_siwx91x_stream *stream; - - if (dir != I2S_DIR_RX && dir != I2S_DIR_TX) { - return -ENOTSUP; - } - - if (dir == I2S_DIR_RX) { - stream = &data->rx; - } else { - stream = &data->tx; - } - - if (stream->state != I2S_STATE_NOT_READY && stream->state != I2S_STATE_READY) { - return -EINVAL; - } - - if (!i2s_siwx91x_validate_word_size(i2s_cfg->word_size)) { - return -EINVAL; - } - - if (i2s_cfg->channels != 2) { - return -EINVAL; - } - - if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) != I2S_FMT_DATA_FORMAT_I2S) { - return -EINVAL; - } - - if (i2s_cfg->options & I2S_SIWX91X_UNSUPPORTED_OPTIONS) { - return -ENOTSUP; - } - - if (!i2s_siwx91x_validate_frequency(i2s_cfg->frame_clk_freq)) { - return -EINVAL; - } - - if (i2s_cfg->word_size == 24) { - if (i2s_cfg->block_size % 4 != 0) { - return -EINVAL; - } - } else { - if (i2s_cfg->block_size % 2 != 0) { - return -EINVAL; - } - } - - memcpy(&stream->cfg, i2s_cfg, sizeof(struct i2s_config)); - - stream->state = I2S_STATE_READY; - - return 0; -} - -static const struct i2s_config *i2s_siwx91x_config_get(const struct device *dev, enum i2s_dir dir) -{ - struct i2s_siwx91x_data *data = dev->data; - struct i2s_siwx91x_stream *stream; - - if (dir == I2S_DIR_RX) { - stream = &data->rx; - } else if (dir == I2S_DIR_TX) { - stream = &data->tx; - } else { - return NULL; - } - - if (stream->state == I2S_STATE_NOT_READY) { - return NULL; - } - - return &stream->cfg; -} - -static int i2s_siwx91x_write(const struct device *dev, void *mem_block, size_t size) -{ - struct i2s_siwx91x_data *data = dev->data; - int ret; - - if (data->tx.state != I2S_STATE_RUNNING && data->tx.state != I2S_STATE_READY) { - return -EIO; - } - - ret = k_sem_take(&data->tx.sem, SYS_TIMEOUT_MS(data->tx.cfg.timeout)); - if (ret < 0) { - return ret; - } - - /* Add data to the end of the TX queue */ - i2s_siwx91x_queue_put(&data->tx.mem_block_queue, mem_block, size); - - return 0; -} - -static int i2s_siwx91x_read(const struct device *dev, void **mem_block, size_t *size) -{ - struct i2s_siwx91x_data *data = dev->data; - int ret; - - if (data->rx.state == I2S_STATE_NOT_READY) { - return -EIO; - } - - if (data->rx.state != I2S_STATE_ERROR) { - ret = k_sem_take(&data->rx.sem, SYS_TIMEOUT_MS(data->rx.cfg.timeout)); - if (ret < 0) { - return ret; - } - } - - /* Get data from the beginning of RX queue */ - ret = i2s_siwx91x_queue_get(&data->rx.mem_block_queue, mem_block, size); - if (ret < 0) { - return -EIO; - } - - return 0; -} - -static int i2s_siwx91x_trigger(const struct device *dev, enum i2s_dir dir, enum i2s_trigger_cmd cmd) -{ - const struct i2s_siwx91x_config *cfg = dev->config; - struct i2s_siwx91x_data *data = dev->data; - struct i2s_siwx91x_stream *stream; - unsigned int key; - int ret; - - if (dir == I2S_DIR_RX) { - stream = &data->rx; - } else if (dir == I2S_DIR_TX) { - stream = &data->tx; - } else { - return -ENOTSUP; - } - - switch (cmd) { - case I2S_TRIGGER_START: - if (stream->state != I2S_STATE_READY) { - return -EIO; - } - - __ASSERT_NO_MSG(stream->mem_block == NULL); - - ret = i2s_siwx91x_param_config(dev, dir); - if (ret < 0) { - return ret; - } - - ret = i2s_siwx91x_dma_channel_alloc(dev, dir); - if (ret < 0) { - return ret; - } - - if (dir == I2S_DIR_RX) { - i2s_siwx91x_start_rx(dev); - } else { - i2s_siwx91x_start_tx(dev); - } - - ret = stream->stream_start(stream, dev); - if (ret < 0) { - return ret; - } - - cfg->reg->I2S_CER_b.CLKEN = ENABLE; - if (dir == I2S_DIR_TX) { - cfg->reg->I2S_ITER_b.TXEN = ENABLE; - } else { - cfg->reg->I2S_IRER_b.RXEN = ENABLE; - } - - stream->state = I2S_STATE_RUNNING; - stream->last_block = false; - break; - - case I2S_TRIGGER_STOP: - key = irq_lock(); - if (stream->state != I2S_STATE_RUNNING) { - irq_unlock(key); - return -EIO; - } - - stream->state = I2S_STATE_STOPPING; - irq_unlock(key); - stream->last_block = true; - break; - - case I2S_TRIGGER_DRAIN: - key = irq_lock(); - if (stream->state != I2S_STATE_RUNNING) { - irq_unlock(key); - return -EIO; - } - - stream->state = I2S_STATE_STOPPING; - irq_unlock(key); - break; - - case I2S_TRIGGER_DROP: - if (stream->state == I2S_STATE_NOT_READY) { - return -EIO; - } - - i2s_siwx91x_stream_disable(stream, stream->dma_dev); - stream->queue_drop(stream); - stream->state = I2S_STATE_READY; - break; - - case I2S_TRIGGER_PREPARE: - if (stream->state != I2S_STATE_ERROR) { - return -EIO; - } - - stream->state = I2S_STATE_READY; - stream->queue_drop(stream); - break; - - default: - return -EINVAL; - } - - return 0; -} - -static int i2s_siwx91x_init(const struct device *dev) -{ - const struct i2s_siwx91x_config *cfg = dev->config; - struct i2s_siwx91x_data *data = dev->data; - int ret; - - ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys_peripheral); - if (ret) { - return ret; - } - - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret) { - return ret; - } - - cfg->reg->I2S_IER_b.IEN = 1; - cfg->reg->I2S_IRER_b.RXEN = 0; - cfg->reg->I2S_ITER_b.TXEN = 0; - - k_sem_init(&data->rx.sem, 0, CONFIG_I2S_SILABS_SIWX91X_RX_BLOCK_COUNT); - k_sem_init(&data->tx.sem, CONFIG_I2S_SILABS_SIWX91X_TX_BLOCK_COUNT, - CONFIG_I2S_SILABS_SIWX91X_TX_BLOCK_COUNT); - - return ret; -} - -static DEVICE_API(i2s, i2s_siwx91x_driver_api) = { - .configure = i2s_siwx91x_configure, - .config_get = i2s_siwx91x_config_get, - .read = i2s_siwx91x_read, - .write = i2s_siwx91x_write, - .trigger = i2s_siwx91x_trigger, -}; - -#define SIWX91X_I2S_INIT(inst) \ - PINCTRL_DT_INST_DEFINE(inst); \ - struct i2s_siwx91x_queue_item \ - rx_ring_buf_##inst[CONFIG_I2S_SILABS_SIWX91X_RX_BLOCK_COUNT + 1]; \ - struct i2s_siwx91x_queue_item \ - tx_ring_buf_##inst[CONFIG_I2S_SILABS_SIWX91X_TX_BLOCK_COUNT + 1]; \ - \ - BUILD_ASSERT((DT_INST_PROP(inst, silabs_channel_group) < \ - DT_INST_PROP(inst, silabs_max_channel_count)), \ - "Invalid channel group!"); \ - \ - static struct i2s_siwx91x_data i2s_data_##inst = { \ - .rx.dma_channel = DT_INST_DMAS_CELL_BY_NAME(inst, rx, channel), \ - .rx.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(inst, rx)), \ - .rx.mem_block_queue.buf = rx_ring_buf_##inst, \ - .rx.mem_block_queue.len = ARRAY_SIZE(rx_ring_buf_##inst), \ - .rx.stream_start = i2s_siwx91x_rx_stream_start, \ - .rx.queue_drop = i2s_siwx91x_rx_queue_drop, \ - .tx.dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, tx, channel), \ - .tx.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(inst, tx)), \ - .tx.mem_block_queue.buf = tx_ring_buf_##inst, \ - .tx.mem_block_queue.len = ARRAY_SIZE(tx_ring_buf_##inst), \ - .tx.stream_start = i2s_siwx91x_tx_stream_start, \ - .tx.queue_drop = i2s_siwx91x_tx_queue_drop, \ - }; \ - static const struct i2s_siwx91x_config i2s_config_##inst = { \ - .reg = (I2S0_Type *)DT_INST_REG_ADDR(inst), \ - .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \ - .clock_subsys_peripheral = \ - (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(inst, 0, clkid), \ - .clock_subsys_static = \ - (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(inst, 1, clkid), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ - .channel_group = DT_INST_PROP(inst, silabs_channel_group), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(inst, &i2s_siwx91x_init, NULL, &i2s_data_##inst, &i2s_config_##inst, \ - POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_siwx91x_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(SIWX91X_I2S_INIT) diff --git a/drivers/i3c/CMakeLists.txt b/drivers/i3c/CMakeLists.txt index 73a8ae4a661fe..39419267933c9 100644 --- a/drivers/i3c/CMakeLists.txt +++ b/drivers/i3c/CMakeLists.txt @@ -56,16 +56,6 @@ zephyr_library_sources_ifdef( i3c_dw.c ) -zephyr_library_sources_ifdef( - CONFIG_I3CM_IT51XXX - i3cm_it51xxx.c -) - -zephyr_library_sources_ifdef( - CONFIG_I3CS_IT51XXX - i3cs_it51xxx.c -) - zephyr_library_sources_ifdef( CONFIG_I3C_TEST i3c_test.c diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig index 0d5122ef7f25c..31f79b78f18b9 100644 --- a/drivers/i3c/Kconfig +++ b/drivers/i3c/Kconfig @@ -213,6 +213,5 @@ rsource "Kconfig.npcx" rsource "Kconfig.dw" rsource "Kconfig.test" rsource "Kconfig.stm32" -rsource "Kconfig.it51xxx" endif # I3C diff --git a/drivers/i3c/Kconfig.it51xxx b/drivers/i3c/Kconfig.it51xxx deleted file mode 100644 index 6ebded9837a32..0000000000000 --- a/drivers/i3c/Kconfig.it51xxx +++ /dev/null @@ -1,111 +0,0 @@ -# Copyright (c) 2025 ITE Corporation. -# SPDX-License-Identifier: Apache-2.0 - -module = I3C_IT51XXX -module-str = i3c-it51xxx -source "subsys/logging/Kconfig.template.log_config" - -config I3CM_IT51XXX - bool "it51xxx i3cm driver" - depends on DT_HAS_ITE_IT51XXX_I3CM_ENABLED - select PINCTRL - select I3C_IBI_WORKQUEUE if I3C_USE_IBI - select SOC_IT51XXX_CPU_IDLE_GATING - default y - help - Enable it51xxx i3c controller driver. - -if I3CM_IT51XXX - -config I3CM_IT51XXX_TRANSFER_TIMEOUT_MS - int "Set the transfer timeout in milliseconds" - default 1000 - -config I3CM_IT51XXX_DLM_SIZE - int "it51xxx i3cm dlm data size" - depends on I3CM_IT51XXX - default 256 - help - Set i3cm data-local-memory(DLM) size. - -endif # I3CM_IT51XXX - -config I3CS_IT51XXX - bool "it51xxx i3cs driver" - depends on DT_HAS_ITE_IT51XXX_I3CS_ENABLED - select PINCTRL - select I3C_TARGET_BUFFER_MODE - select SOC_IT51XXX_CPU_IDLE_GATING - default y - help - Enable it51xxx i3c target driver. - -if I3CS_IT51XXX - -config I3CS_IT51XXX_IBI_TIMEOUT_MS - int "Set the IBI timeout in milliseconds" - default 1000 - -choice - bool "choose i3cs tx fifo size" - default I3CS_TX_FIFO_16_BYTE - -config I3CS_TX_FIFO_16_BYTE - bool "16" - -config I3CS_TX_FIFO_32_BYTE - bool "32" - -config I3CS_TX_FIFO_64_BYTE - bool "64" - -config I3CS_TX_FIFO_128_BYTE - bool "128" - -config I3CS_TX_FIFO_4096_BYTE - bool "4096" -endchoice - -config I3CS_IT51XXX_TX_FIFO_SIZE - int "it51xxx i3cs tx fifo size" - default 16 if I3CS_TX_FIFO_16_BYTE - default 32 if I3CS_TX_FIFO_32_BYTE - default 64 if I3CS_TX_FIFO_64_BYTE - default 128 if I3CS_TX_FIFO_128_BYTE - default 4096 if I3CS_TX_FIFO_4096_BYTE - default 16 - help - Set i3cs tx fifo size size. - -choice - bool "choose i3cs rx fifo size" - default I3CS_RX_FIFO_16_BYTE - -config I3CS_RX_FIFO_16_BYTE - bool "16" - -config I3CS_RX_FIFO_32_BYTE - bool "32" - -config I3CS_RX_FIFO_64_BYTE - bool "64" - -config I3CS_RX_FIFO_128_BYTE - bool "128" - -config I3CS_RX_FIFO_4096_BYTE - bool "4096" -endchoice - -config I3CS_IT51XXX_RX_FIFO_SIZE - int "it51xxx i3cs rx fifo size" - default 16 if I3CS_RX_FIFO_16_BYTE - default 32 if I3CS_RX_FIFO_32_BYTE - default 64 if I3CS_RX_FIFO_64_BYTE - default 128 if I3CS_RX_FIFO_128_BYTE - default 4096 if I3CS_RX_FIFO_4096_BYTE - default 16 - help - Set i3cs rx fifo size size. - -endif # I3CS_IT51XXX diff --git a/drivers/i3c/i3c_mcux.c b/drivers/i3c/i3c_mcux.c index b541835149e79..581c1d2d1c3bd 100644 --- a/drivers/i3c/i3c_mcux.c +++ b/drivers/i3c/i3c_mcux.c @@ -198,7 +198,7 @@ static inline bool reg32_test(volatile uint32_t *reg, uint32_t mask) } /** - * @brief Disable all interrupts. + * @breif Disable all interrupts. * * @param base Pointer to controller registers. * diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index bc4e94ef7ce50..7a37919016c02 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -82,8 +82,6 @@ struct i3c_ctrl { /* zephyr-keep-sorted-start */ DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_FN) -DT_FOREACH_STATUS_OKAY(ite_it51xxx_i3cm, I3C_CTRL_FN) -DT_FOREACH_STATUS_OKAY(ite_it51xxx_i3cs, I3C_CTRL_FN) DT_FOREACH_STATUS_OKAY(nuvoton_npcx_i3c, I3C_CTRL_FN) DT_FOREACH_STATUS_OKAY(nxp_mcux_i3c, I3C_CTRL_FN) DT_FOREACH_STATUS_OKAY(snps_designware_i3c, I3C_CTRL_FN) @@ -101,8 +99,6 @@ DT_FOREACH_STATUS_OKAY(st_stm32_i3c, I3C_CTRL_FN) const struct i3c_ctrl i3c_list[] = { /* zephyr-keep-sorted-start */ DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_LIST_ENTRY) - DT_FOREACH_STATUS_OKAY(ite_it51xxx_i3cm, I3C_CTRL_LIST_ENTRY) - DT_FOREACH_STATUS_OKAY(ite_it51xxx_i3cs, I3C_CTRL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(nuvoton_npcx_i3c, I3C_CTRL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(nxp_mcux_i3c, I3C_CTRL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(snps_designware_i3c, I3C_CTRL_LIST_ENTRY) diff --git a/drivers/i3c/i3cm_it51xxx.c b/drivers/i3c/i3cm_it51xxx.c deleted file mode 100644 index a532a54e4079a..0000000000000 --- a/drivers/i3c/i3cm_it51xxx.c +++ /dev/null @@ -1,1714 +0,0 @@ -/* - * Copyright (c) 2025 ITE Technology Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ite_it51xxx_i3cm - -#include -#include -LOG_MODULE_REGISTER(i3cm_it51xxx); - -#include -#include -#include -#include -#include -#include - -#include - -#define BYTE_0(x) FIELD_GET(GENMASK(7, 0), x) -#define BYTE_1(x) FIELD_GET(GENMASK(15, 8), x) - -#define CALC_FREQUENCY(t_low, t_hddat, t_high) \ - (NSEC_PER_SEC / (t_high + t_low + t_hddat + 3) / 208 * 10) - -/* it51xxx i3cm registers definition */ -#define I3CM00_CYCLE_TYPE 0x00 -#define MORE_I3CM_TRANSFER BIT(6) -#define I3CM_PRIV_TRANS_WITHOUT_7EH_ADDR BIT(5) -#define I3CM_CYCLE_TYPE_SELECT(n) FIELD_PREP(GENMASK(3, 0), n) - -#define I3CM01_STATUS 0x01 -#define START_TRANSFER BIT(7) -#define PARITY_ERROR BIT(5) -#define CRC5_ERROR BIT(4) -#define IBI_INTERRUPT BIT(3) -#define TARGET_NACK BIT(2) -#define TRANSFER_END BIT(1) -#define NEXT_TRANSFER BIT(0) - -#define I3CM02_TARGET_ADDRESS 0x02 -#define I3CM_TARGET_ADDRESS(n) FIELD_PREP(GENMASK(7, 1), n) - -#define I3CM03_COMMON_COMMAND_CODE 0x03 -#define I3CM04_WRITE_LENGTH_LB 0x04 -#define I3CM05_WRITE_LENGTH_HB 0x05 -#define I3CM06_READ_LENGTH_LB 0x06 -#define I3CM07_READ_LENGTH_HB 0x07 -#define I3CM0E_DATA_COUNT_LB 0x0E -#define I3CM0F_IBI_ADDRESS 0x0F -#define I3CM_IBI_ADDR_MASK GENMASK(7, 1) -#define I3CM_IBI_RNW BIT(0) - -#define I3CM10_CONTROL 0x10 -#define I3CM_INTERRUPT_ENABLE BIT(7) -#define I3CM_REFUSE_IBI BIT(0) - -#define I3CM15_CONTROL_2 0x15 -#define I3CM_CCC_WITH_DEFINING_BYTE BIT(0) - -#define I3CM16_CCC_DEFINING_BYTE 0x16 -#define I3CM1E_DATA_COUNT_HB 0x1E -#define I3CM20_TCAS 0x20 /* i3c: clock after start condition */ -#define I3CM21_TCBP 0x21 /* i3c: clock before stop condition */ -#define I3CM22_TCBSR 0x22 /* i3c: clock before repeated start condition */ -#define I3CM23_TCASR 0x23 /* i3c: clock after repeated start condition */ -#define I3CM24_THDDAT_LB 0x24 /* i3c: low byte of data hold time */ -#define I3CM26_TLOW_LB 0x26 /* i3c: low byte of scl clock low period */ -#define I3CM27_TLOW_HB 0x27 /* i3c: high byte of scl clock low period */ -#define I3CM28_THIGH_LB 0x28 /* i3c: low byte of scl clock high period */ -#define I3CM29_THIGH_HB 0x29 /* i3c: high byte of scl clock high period */ -#define I3CM2A_TLOW_OD_LB 0x2A /* i3c: low byte of open drain scl clock low period */ -#define I3CM2B_TLOW_OD_HB 0x2B /* i3c: high byte of open drain scl clock low period */ -#define I3CM2F_I2C_CONTROL 0x2F -#define I3CM_USE_I2C_TIMING_SETTING BIT(1) - -#define I3CM30_I2C_THDSTA_SUSTO_LB \ - 0x30 /* i2c: low byte of "hold time for a (repeated) start"/"setup time for stop" */ -#define I3CM31_I2C_THDSTA_SUSTO_HB \ - 0x31 /* i2c: high byte of "hold time for a (repeated) start"/"setup time for stop" */ -#define I3CM34_I2C_THDDAT_LB 0x34 /* i2c: low byte of data hold time */ -#define I3CM35_I2C_THDDAT_HB 0x35 /* i2c: high byte of data hold time */ -#define I3CM36_I2C_TLOW_LB 0x36 /* i2c: low byte of scl clock low period */ -#define I3CM37_I2C_TLOW_HB 0x37 /* i2c: high byte of scl clock low period */ -#define I3CM38_I2C_THIGH_LB 0x38 /* i2c: low byte of scl clock high period */ -#define I3CM39_I2C_THIGH_HB 0x39 /* i2c: high byte of scl clock high period */ - -#define I3CM50_CONTROL_3 0x50 -#define I3CM_DLM_SIZE_MASK GENMASK(5, 4) -#define I3CM_CHANNEL_SELECT_MASK GENMASK(3, 2) -#define I3CM_PULL_UP_RESISTOR BIT(1) -#define I3CM_ENABLE BIT(0) - -#define I3CM52_DLM_BASE_ADDRESS_LB 0x52 /* dlm base address[15:8] */ -#define I3CM53_DLM_BASE_ADDRESS_HB 0x53 /* dlm base address[17:16] */ - -#define I3C_IBI_HJ_ADDR 0x02 - -#define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */ -#define I3C_BUS_THIGH_PP_MIN_NS 24 /* T_HIGH period in push-pull mode */ -#define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */ - -enum it51xxx_cycle_types { - PRIVATE_WRITE_TRANSFER = 0, - PRIVATE_READ_TRANSFER, - PRIVATE_WRITE_READ_TRANSFER, - LEGACY_I2C_WRITE_TRANSFER, - LEGACY_I2C_READ_TRANSFER, - LEGACY_I2C_WRITE_READ_TRANSFER, - BROADCAST_CCC_WRITE_TRANSFER, - DIRECT_CCC_WRITE_TRANSFER, - DIRECT_CCC_READ_TRANSFER, - DAA_TRANSFER, - IBI_READ_TRANSFER, - HDR_TRANSFER, -}; - -enum it51xxx_message_state { - IT51XXX_I3CM_MSG_IDLE = 0, - IT51XXX_I3CM_MSG_BROADCAST_CCC, - IT51XXX_I3CM_MSG_DIRECT_CCC, - IT51XXX_I3CM_MSG_DAA, - IT51XXX_I3CM_MSG_PRIVATE_XFER, - IT51XXX_I3CM_MSG_IBI, - IT51XXX_I3CM_MSG_ABORT, - IT51XXX_I3CM_MSG_ERROR, -}; - -struct it51xxx_i3cm_data { - /* common i3c driver data */ - struct i3c_driver_data common; - - enum it51xxx_message_state msg_state; - - struct { - struct i3c_ccc_payload *payload; - size_t target_idx; - } ccc_msgs; - - struct { - uint8_t target_addr; - - uint8_t num_msgs; - uint8_t curr_idx; - struct i3c_msg *i3c_msgs; - struct i2c_msg *i2c_msgs; - } curr_msg; - -#ifdef CONFIG_I3C_USE_IBI - bool ibi_hj_response; - uint8_t ibi_target_addr; - - struct { - uint8_t addr[4]; - uint8_t num_addr; - } ibi; -#endif /* CONFIG_I3C_USE_IBI */ - - struct k_sem msg_sem; - struct k_mutex lock; - - bool is_initialized; - bool error_is_detected; - bool transfer_is_aborted; /* record that the transfer was aborted due to ibi transaction. */ - - struct { - uint8_t tx_data[CONFIG_I3CM_IT51XXX_DLM_SIZE / 2]; - uint8_t rx_data[CONFIG_I3CM_IT51XXX_DLM_SIZE / 2]; - } dlm_data __aligned(CONFIG_I3CM_IT51XXX_DLM_SIZE); -}; - -struct it51xxx_i3cm_config { - /* common i3c driver config */ - struct i3c_driver_config common; - - const struct pinctrl_dev_config *pcfg; - mm_reg_t base; - uint8_t io_channel; - uint8_t irq_num; - - struct { - uint8_t i3c_pp_duty_cycle; - uint32_t i3c_od_scl_hz; - uint32_t i3c_scl_hddat; - uint32_t i3c_scl_tcas; - uint32_t i3c_scl_tcbs; - uint32_t i3c_scl_tcasr; - uint32_t i3c_scl_tcbsr; - uint32_t i2c_scl_hddat; - } clocks; - - void (*irq_config_func)(const struct device *dev); - - LOG_INSTANCE_PTR_DECLARE(log); -}; - -static inline bool bus_is_idle(const struct device *dev) -{ - struct it51xxx_i3cm_data *data = dev->data; - - return (data->msg_state == IT51XXX_I3CM_MSG_IDLE); -} - -static int it51xxx_curr_msg_init(const struct device *dev, struct i3c_msg *i3c_msgs, - struct i2c_msg *i2c_msgs, uint8_t num_msgs, uint8_t tgt_addr) -{ - struct it51xxx_i3cm_data *data = dev->data; - - __ASSERT(!(i3c_msgs == NULL && i2c_msgs == NULL), "both i3c_msgs and i2c_msgs are null"); - __ASSERT(!(i3c_msgs != NULL && i2c_msgs != NULL), - "both i3c_msgs and i2c_msgs are not null"); - - data->curr_msg.target_addr = tgt_addr; - data->curr_msg.num_msgs = num_msgs; - data->curr_msg.curr_idx = 0; - data->curr_msg.i3c_msgs = i3c_msgs; - data->curr_msg.i2c_msgs = i2c_msgs; - - return 0; -} - -static void it51xxx_enable_standby_state(const struct device *dev, const bool enable) -{ - ARG_UNUSED(dev); - - if (enable) { - chip_permit_idle(); - pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); - } else { - chip_block_idle(); - pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); - } -} - -static inline int it51xxx_set_tx_rx_length(const struct device *dev, const size_t tx_len, - const size_t rx_len) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - - if (tx_len > (CONFIG_I3CM_IT51XXX_DLM_SIZE / 2) || - rx_len > (CONFIG_I3CM_IT51XXX_DLM_SIZE / 2)) { - LOG_INST_ERR(cfg->log, "invalid tx(%d) or rx(%d) length", tx_len, rx_len); - return -EINVAL; - } - - sys_write8(BYTE_0(rx_len), cfg->base + I3CM06_READ_LENGTH_LB); - sys_write8(BYTE_1(rx_len), cfg->base + I3CM07_READ_LENGTH_HB); - sys_write8(BYTE_0(tx_len), cfg->base + I3CM04_WRITE_LENGTH_LB); - sys_write8(BYTE_1(tx_len), cfg->base + I3CM05_WRITE_LENGTH_HB); - - return 0; -} - -static inline size_t it51xxx_get_received_data_count(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - - return sys_read8(cfg->base + I3CM0E_DATA_COUNT_LB) + - ((sys_read8(cfg->base + I3CM1E_DATA_COUNT_HB) & 0x03) << 8); -} - -static void it51xxx_set_op_type(const struct device *dev, const uint8_t cycle_type, - const bool more_transfer, const bool broadcast_address) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - uint8_t reg_val = 0x0; - - if (more_transfer) { - reg_val |= MORE_I3CM_TRANSFER; - } - if (!broadcast_address) { - reg_val |= I3CM_PRIV_TRANS_WITHOUT_7EH_ADDR; - } - reg_val |= I3CM_CYCLE_TYPE_SELECT(cycle_type); - sys_write8(reg_val, cfg->base + I3CM00_CYCLE_TYPE); - LOG_INST_DBG(cfg->log, "set cycle type(%d) %s broadcast address %s", cycle_type, - broadcast_address ? "with" : "without", - more_transfer ? "and more transfer flag" : ""); -} - -static int it51xxx_wait_to_complete(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret = 0; - - if (k_sem_take(&data->msg_sem, K_MSEC(CONFIG_I3CM_IT51XXX_TRANSFER_TIMEOUT_MS)) != 0) { - LOG_INST_ERR(cfg->log, "timeout: message status(%d)", data->msg_state); - ret = -ETIMEDOUT; - } - - irq_disable(cfg->irq_num); - if (data->transfer_is_aborted) { - data->transfer_is_aborted = false; - ret = -EBUSY; - } - if (data->error_is_detected) { - data->error_is_detected = false; - ret = -EIO; - } - irq_enable(cfg->irq_num); - - return ret; -} - -static bool it51xxx_curr_msg_is_i3c(const struct device *dev) -{ - struct it51xxx_i3cm_data *data = dev->data; - - return (data->curr_msg.i3c_msgs != NULL); -} - -static int it51xxx_start_i3c_i2c_private_xfer(const struct device *dev, const uint8_t cycle_type, - const uint8_t dynamic_addr, const bool more_transfer, - const bool broadcast_address) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i2c_msg *i2c_msgs = data->curr_msg.i2c_msgs; - struct i3c_msg *i3c_msgs = data->curr_msg.i3c_msgs; - size_t tx_length = 0, rx_length = 0; - int ret; - - switch (cycle_type) { - case LEGACY_I2C_WRITE_TRANSFER: - __fallthrough; - case PRIVATE_WRITE_TRANSFER: - rx_length = 0; - tx_length = it51xxx_curr_msg_is_i3c(dev) ? i3c_msgs[data->curr_msg.curr_idx].len - : i2c_msgs[data->curr_msg.curr_idx].len; - break; - case LEGACY_I2C_READ_TRANSFER: - __fallthrough; - case PRIVATE_READ_TRANSFER: - rx_length = it51xxx_curr_msg_is_i3c(dev) ? i3c_msgs[data->curr_msg.curr_idx].len - : i2c_msgs[data->curr_msg.curr_idx].len; - tx_length = 0; - break; - case LEGACY_I2C_WRITE_READ_TRANSFER: - __fallthrough; - case PRIVATE_WRITE_READ_TRANSFER: - tx_length = it51xxx_curr_msg_is_i3c(dev) ? i3c_msgs[data->curr_msg.curr_idx].len - : i2c_msgs[data->curr_msg.curr_idx].len; - rx_length = it51xxx_curr_msg_is_i3c(dev) - ? i3c_msgs[data->curr_msg.curr_idx + 1].len - : i2c_msgs[data->curr_msg.curr_idx + 1].len; - break; - default: - LOG_INST_ERR(cfg->log, "unsupported cycle type(0x%x)", cycle_type); - return -ENOTSUP; - } - - ret = it51xxx_set_tx_rx_length(dev, tx_length, rx_length); - if (ret) { - return ret; - } - - if (tx_length) { - if (it51xxx_curr_msg_is_i3c(dev)) { - memcpy(data->dlm_data.tx_data, i3c_msgs[data->curr_msg.curr_idx].buf, - tx_length); - } else { - memcpy(data->dlm_data.tx_data, i2c_msgs[data->curr_msg.curr_idx].buf, - tx_length); - } - } - - sys_write8(I3CM_TARGET_ADDRESS(dynamic_addr), cfg->base + I3CM02_TARGET_ADDRESS); - - /* set cycle type register */ - it51xxx_set_op_type(dev, cycle_type, more_transfer, broadcast_address); - data->msg_state = IT51XXX_I3CM_MSG_PRIVATE_XFER; - - return 0; -} - -static inline int it51xxx_set_i2c_clock(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_config_controller *config_cntlr = &data->common.ctrl_config; - uint32_t t_high_period_ns, t_low_period_ns; - uint32_t t_high, t_low; - uint16_t t_hddat = - (cfg->clocks.i2c_scl_hddat > 0xFFFF) ? 0xFFFF : cfg->clocks.i2c_scl_hddat; - - /* high_period_ns = ns_per_sec / config_cntlr->scl.i2c / 2; - * high_period_ns = (t_high + 1) * 20.8 - * t_high = ((ns_per_sec / config_cntlr->scl.i2c / 2) / 20.8) - 1 - */ - t_high_period_ns = NSEC_PER_SEC / config_cntlr->scl.i2c / 2; - t_high = DIV_ROUND_UP(t_high_period_ns * 10, 208) - 1; - - /* t_low_period_ns = (ns_per_sec / config_cntlr->scl.i2c) - high_period_ns - * t_low_period_ns = (t_low + 1 + t_hddat + 1) * 20.8 - * t_low = (t_low_period_ns / 20.8) - t_hddat - 2 - */ - t_low_period_ns = (NSEC_PER_SEC / config_cntlr->scl.i2c) - t_high_period_ns; - t_low = DIV_ROUND_UP(t_low_period_ns * 10, 208) - t_hddat - 2; - - if (t_high > 0xFFFF || t_low > 0xFFFF) { - LOG_INST_ERR(cfg->log, "invalid t_high(0x%x) or t_low(0x%x) setting", t_high, - t_low); - } - - sys_write8(BYTE_0(t_high), cfg->base + I3CM30_I2C_THDSTA_SUSTO_LB); - sys_write8(BYTE_1(t_high), cfg->base + I3CM31_I2C_THDSTA_SUSTO_HB); - sys_write8(BYTE_0(t_hddat), cfg->base + I3CM34_I2C_THDDAT_LB); - sys_write8(BYTE_1(t_hddat), cfg->base + I3CM35_I2C_THDDAT_HB); - sys_write8(BYTE_0(t_low), cfg->base + I3CM36_I2C_TLOW_LB); - sys_write8(BYTE_1(t_low), cfg->base + I3CM37_I2C_TLOW_HB); - sys_write8(BYTE_0(t_high), cfg->base + I3CM38_I2C_THIGH_LB); - sys_write8(BYTE_1(t_high), cfg->base + I3CM39_I2C_THIGH_HB); - - LOG_INST_DBG(cfg->log, "i2c: t_high 0x%x, t_low 0x%x t_hddat 0x%x", t_high, t_low, t_hddat); - LOG_INST_DBG(cfg->log, "i2c: high period: %dns, low period: %dns", t_high_period_ns, - t_low_period_ns); - LOG_INST_INF(cfg->log, "i2c: freq: %dHz -> %dHz", config_cntlr->scl.i2c, - CALC_FREQUENCY(t_low, t_hddat, t_high)); - - return 0; -} - -static inline int it51xxx_set_i3c_clock(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_config_controller *config_cntlr = &data->common.ctrl_config; - uint32_t pp_freq, od_freq; - uint32_t odlow_ns, odhigh_ns, pplow_ns, pphigh_ns; - uint16_t pphigh, pplow, odhigh, odlow; - uint8_t pp_duty_cycle = - (cfg->clocks.i3c_pp_duty_cycle > 100) ? 100 : cfg->clocks.i3c_pp_duty_cycle; - uint8_t hddat = (cfg->clocks.i3c_scl_hddat > 63) ? 63 : cfg->clocks.i3c_scl_hddat; - uint8_t tcas = (cfg->clocks.i3c_scl_tcas > 0xff) ? 0xff : cfg->clocks.i3c_scl_tcas; - uint8_t tcbs = (cfg->clocks.i3c_scl_tcbs > 0xff) ? 0xff : cfg->clocks.i3c_scl_tcbs; - uint8_t tcasr = (cfg->clocks.i3c_scl_tcasr > 0xff) ? 0xff : cfg->clocks.i3c_scl_tcasr; - uint8_t tcbsr = (cfg->clocks.i3c_scl_tcbsr > 0xff) ? 0xff : cfg->clocks.i3c_scl_tcbsr; - - pp_freq = config_cntlr->scl.i3c; - od_freq = cfg->clocks.i3c_od_scl_hz; - if (pp_freq == 0 || od_freq == 0) { - LOG_INST_ERR(cfg->log, "invalid freq pp(%dHz) or od(%dHz)", pp_freq, od_freq); - return -EINVAL; - } - - /* use i3c timing setting */ - sys_write8(sys_read8(cfg->base + I3CM2F_I2C_CONTROL) & ~I3CM_USE_I2C_TIMING_SETTING, - cfg->base + I3CM2F_I2C_CONTROL); - - /* pphigh_ns = odhigh_ns = (ns_per_sec / pp_freq) * duty_cycle - * pplow_ns = (ns_per_sec / pp_freq) - pphigh_ns - * odlow_ns = (ns_per_sec / od_freq) - odhigh_ns - */ - pphigh_ns = DIV_ROUND_UP(DIV_ROUND_UP(NSEC_PER_SEC, pp_freq) * pp_duty_cycle, 100); - pplow_ns = DIV_ROUND_UP(NSEC_PER_SEC, pp_freq) - pphigh_ns; - odhigh_ns = pphigh_ns; - odlow_ns = DIV_ROUND_UP(NSEC_PER_SEC, od_freq) - odhigh_ns; - if (odlow_ns < I3C_BUS_TLOW_OD_MIN_NS) { - LOG_INST_ERR(cfg->log, "od low period(%dns) is out of spec", odlow_ns); - return -EINVAL; - } - if (pphigh_ns < I3C_BUS_THIGH_PP_MIN_NS) { - LOG_INST_ERR(cfg->log, "pp high period(%dns) is out of spec", pphigh_ns); - return -EINVAL; - } - if (pplow_ns < I3C_BUS_TLOW_PP_MIN_NS) { - LOG_INST_ERR(cfg->log, "pp low period(%dns) is out of spec", pplow_ns); - return -EINVAL; - } - - /* odlow_ns = (odlow + 1) * 20.8 + (hddat + 1) * 20.8 - * odlow = (odlow_ns / 20.8) - hddat - 2 - */ - odlow = DIV_ROUND_UP(odlow_ns * 10, 208) - hddat - 2; - odlow = (odlow > 0x1ff) ? 0x1ff : odlow; - sys_write8(BYTE_0(odlow), cfg->base + I3CM2A_TLOW_OD_LB); - sys_write8(BYTE_1(odlow), cfg->base + I3CM2B_TLOW_OD_HB); - - /* pphigh_ns = (pphigh + 1) * 20.8 - * pphigh = (pphigh_ns / 20.8) - 1 - * odhigh = pphigh - */ - pphigh = DIV_ROUND_UP(pphigh_ns * 10, 208) - 1; - pphigh = (pphigh > 0x1ff) ? 0x1ff : pphigh; - odhigh = pphigh; - sys_write8(BYTE_0(pphigh), cfg->base + I3CM28_THIGH_LB); - sys_write8(BYTE_1(pphigh), cfg->base + I3CM29_THIGH_HB); - - /* pplow_ns = (pplow + 1) * 20.8 + (hddat + 1) * 20.8 - * pplow = (pplow_ns / 20.8) - hddat - 2 - */ - pplow = DIV_ROUND_UP(pplow_ns * 10, 208) - hddat - 2; - pplow = (pplow > 0x1ff) ? 0x1ff : pplow; - sys_write8(BYTE_0(pplow), cfg->base + I3CM26_TLOW_LB); - sys_write8(BYTE_1(pplow), cfg->base + I3CM27_TLOW_HB); - - sys_write8(hddat, cfg->base + I3CM24_THDDAT_LB); - sys_write8(tcas, cfg->base + I3CM20_TCAS); - sys_write8(tcbs, cfg->base + I3CM21_TCBP); - sys_write8(tcasr, cfg->base + I3CM23_TCASR); - sys_write8(tcbsr, cfg->base + I3CM22_TCBSR); - - LOG_INST_DBG(cfg->log, "i3c: pphigh_ns: %dns, pplow_ns %dns", pphigh_ns, pplow_ns); - LOG_INST_DBG(cfg->log, "i3c: odhigh_ns: %dns, odlow_ns %dns", odhigh_ns, odlow_ns); - LOG_INST_DBG(cfg->log, "i3c: pphigh: %d, pplow %d, odhigh: %d, odlow %d, hddat %d", pphigh, - pplow, odhigh, odlow, hddat); - LOG_INST_INF(cfg->log, "i3c: pp_freq: %dHz -> %dHz, od_freq %dHz -> %dHz", pp_freq, - CALC_FREQUENCY(pplow, hddat, pphigh), od_freq, - CALC_FREQUENCY(odlow, hddat, odhigh)); - - return 0; -} - -static int it51xxx_set_frequency(const struct device *dev) -{ - int ret; - - ret = it51xxx_set_i3c_clock(dev); - if (ret) { - goto out; - } - - ret = it51xxx_set_i2c_clock(dev); - if (ret) { - goto out; - } - -out: - return ret; -} - -static int it51xxx_prepare_priv_xfer(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_msg *i3c_msgs = data->curr_msg.i3c_msgs; - struct i2c_msg *i2c_msgs = data->curr_msg.i2c_msgs; - bool more_transfer = false, send_broadcast = false, emit_stop, is_read; - int ret = 0; - uint8_t cycle_type; - - if (it51xxx_curr_msg_is_i3c(dev)) { - emit_stop = i3c_msgs[data->curr_msg.curr_idx].flags & I3C_MSG_STOP; - is_read = - (i3c_msgs[data->curr_msg.curr_idx].flags & I3C_MSG_RW_MASK) == I3C_MSG_READ; - } else { - emit_stop = i2c_msgs[data->curr_msg.curr_idx].flags & I2C_MSG_STOP; - is_read = - (i2c_msgs[data->curr_msg.curr_idx].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ; - } - - if (emit_stop) { - if ((data->curr_msg.curr_idx + 1) != data->curr_msg.num_msgs) { - LOG_INST_ERR(cfg->log, "invalid message: too much messages"); - return -EINVAL; - } - if (it51xxx_curr_msg_is_i3c(dev)) { - cycle_type = is_read ? PRIVATE_READ_TRANSFER : PRIVATE_WRITE_TRANSFER; - } else { - cycle_type = is_read ? LEGACY_I2C_READ_TRANSFER : LEGACY_I2C_WRITE_TRANSFER; - } - } else { - bool next_is_read; - bool next_is_restart; - - if ((data->curr_msg.curr_idx + 1) > data->curr_msg.num_msgs) { - LOG_INST_ERR(cfg->log, "invalid message: too few messages"); - return -EINVAL; - } - - if (is_read) { - LOG_INST_ERR(cfg->log, - "invalid message: multiple msgs initiated from the read flag"); - return -EINVAL; - } - - if (it51xxx_curr_msg_is_i3c(dev)) { - next_is_read = (i3c_msgs[data->curr_msg.curr_idx + 1].flags & - I3C_MSG_RW_MASK) == I3C_MSG_READ; - next_is_restart = ((i3c_msgs[data->curr_msg.curr_idx + 1].flags & - I3C_MSG_RESTART) == I3C_MSG_RESTART); - } else { - next_is_read = (i2c_msgs[data->curr_msg.curr_idx + 1].flags & - I2C_MSG_RW_MASK) == I2C_MSG_READ; - next_is_restart = ((i2c_msgs[data->curr_msg.curr_idx + 1].flags & - I2C_MSG_RESTART) == I2C_MSG_RESTART); - } - - if (!next_is_read && !next_is_restart) { - /* burst write */ - if (!it51xxx_curr_msg_is_i3c(dev)) { - /* legacy i2c transfer doesn't support burst write */ - return -ENOTSUP; - } - cycle_type = PRIVATE_WRITE_TRANSFER; - more_transfer = true; - } else if (next_is_read) { - /* write then read */ - cycle_type = it51xxx_curr_msg_is_i3c(dev) ? PRIVATE_WRITE_READ_TRANSFER - : LEGACY_I2C_WRITE_READ_TRANSFER; - } else { - LOG_INST_ERR(cfg->log, "invalid message"); - return -EINVAL; - } - } - - if (it51xxx_curr_msg_is_i3c(dev) && data->curr_msg.curr_idx == 0 && - !(i3c_msgs[data->curr_msg.curr_idx].flags & I3C_MSG_NBCH)) { - send_broadcast = true; - } - - ret = it51xxx_start_i3c_i2c_private_xfer(dev, cycle_type, data->curr_msg.target_addr, - more_transfer, send_broadcast); - if (ret) { - return ret; - } - - return 0; -} - -static int it51xxx_i3cm_i2c_api_transfer(const struct device *dev, struct i2c_msg *msgs, - uint8_t num_msgs, uint16_t addr) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret; - - if (!msgs) { - return -EINVAL; - } - - if (num_msgs == 0) { - return 0; - } - - for (uint8_t i = 0; i < num_msgs; i++) { - if (!msgs[i].buf) { - return -EINVAL; - } - if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) { - LOG_INST_ERR(cfg->log, "unsupported i2c extended address"); - return -ENOTSUP; - } - } - - irq_disable(cfg->irq_num); - if (!bus_is_idle(dev)) { - irq_enable(cfg->irq_num); - return -EBUSY; - } - - k_mutex_lock(&data->lock, K_FOREVER); - - it51xxx_enable_standby_state(dev, false); - - it51xxx_curr_msg_init(dev, NULL, msgs, num_msgs, addr); - ret = it51xxx_prepare_priv_xfer(dev); - if (ret) { - irq_enable(cfg->irq_num); - goto out; - } - - /* start transfer */ - sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS); - irq_enable(cfg->irq_num); - - ret = it51xxx_wait_to_complete(dev); - -out: - data->curr_msg.curr_idx = 0; - it51xxx_enable_standby_state(dev, true); - k_mutex_unlock(&data->lock); - - return ret; -} - -static int it51xxx_i3cm_configure(const struct device *dev, enum i3c_config_type type, void *config) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_config_controller *cntlr_cfg = config; - int ret; - - if (type != I3C_CONFIG_CONTROLLER) { - LOG_INST_ERR(cfg->log, "support controller mode only"); - return -ENOTSUP; - } - - if (cntlr_cfg->is_secondary || cntlr_cfg->scl.i3c == 0U || cntlr_cfg->scl.i2c == 0U) { - return -EINVAL; - } - - (void)memcpy(&data->common.ctrl_config, cntlr_cfg, sizeof(*cntlr_cfg)); - k_mutex_lock(&data->lock, K_FOREVER); - ret = it51xxx_set_frequency(dev); - k_mutex_unlock(&data->lock); - - return ret; -} - -static int it51xxx_i3cm_config_get(const struct device *dev, enum i3c_config_type type, - void *config) -{ - struct it51xxx_i3cm_data *data = dev->data; - - if (type != I3C_CONFIG_CONTROLLER) { - return -ENOTSUP; - } - - if (!config) { - return -EINVAL; - } - - (void)memcpy(config, &data->common.ctrl_config, sizeof(data->common.ctrl_config)); - - return 0; -} - -static int it51xxx_i3cm_do_daa(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret = 0; - - LOG_INST_DBG(cfg->log, "start daa"); - - irq_disable(cfg->irq_num); - if (!bus_is_idle(dev)) { - irq_enable(cfg->irq_num); - return -EBUSY; - } - - k_mutex_lock(&data->lock, K_FOREVER); - - data->msg_state = IT51XXX_I3CM_MSG_DAA; - - it51xxx_enable_standby_state(dev, false); - it51xxx_set_op_type(dev, DAA_TRANSFER, false, true); - sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS); - irq_enable(cfg->irq_num); - - ret = it51xxx_wait_to_complete(dev); - - it51xxx_enable_standby_state(dev, true); - k_mutex_unlock(&data->lock); - - return ret; -} - -static int it51xxx_broadcast_ccc_xfer(const struct device *dev, struct i3c_ccc_payload *payload) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret; - - irq_disable(cfg->irq_num); - if (!bus_is_idle(dev)) { - irq_enable(cfg->irq_num); - return -EBUSY; - } - - ret = it51xxx_set_tx_rx_length(dev, payload->ccc.data_len, 0); - if (ret) { - irq_enable(cfg->irq_num); - return ret; - } - - if (payload->ccc.data_len > 0) { - memcpy(data->dlm_data.tx_data, payload->ccc.data, payload->ccc.data_len); - } - - data->ccc_msgs.payload = payload; - data->msg_state = IT51XXX_I3CM_MSG_BROADCAST_CCC; - it51xxx_set_op_type(dev, BROADCAST_CCC_WRITE_TRANSFER, false, true); - sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS); - irq_enable(cfg->irq_num); - - return it51xxx_wait_to_complete(dev); -} - -static void it51xxx_direct_ccc_xfer_end(const struct device *dev) -{ - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_ccc_target_payload *tgt_payload = data->ccc_msgs.payload->targets.payloads; - size_t target_idx = data->ccc_msgs.target_idx; - bool is_read = tgt_payload[target_idx].rnw == 1U; - size_t data_count; - - if (is_read) { - data_count = it51xxx_get_received_data_count(dev); - memcpy(tgt_payload[target_idx].data, data->dlm_data.rx_data, - MIN(tgt_payload[target_idx].data_len, data_count)); - LOG_HEXDUMP_DBG(tgt_payload[target_idx].data, tgt_payload[target_idx].data_len, - "direct ccc rx:"); - } - tgt_payload[target_idx].num_xfer = is_read ? data_count : tgt_payload[target_idx].data_len; -} - -static int it51xxx_start_direct_ccc_xfer(const struct device *dev, struct i3c_ccc_payload *payload) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_ccc_target_payload *tgt_payload = &payload->targets.payloads[0]; - bool is_read = tgt_payload->rnw == 1U; - bool more_transfer; - uint8_t cycle_type; - int ret; - - irq_disable(cfg->irq_num); - if (!bus_is_idle(dev)) { - irq_enable(cfg->irq_num); - return -EBUSY; - } - - if (is_read) { - ret = it51xxx_set_tx_rx_length(dev, 0, tgt_payload->data_len); - if (ret) { - irq_enable(cfg->irq_num); - return ret; - } - cycle_type = DIRECT_CCC_READ_TRANSFER; - } else { - ret = it51xxx_set_tx_rx_length(dev, tgt_payload->data_len, 0); - if (ret) { - irq_enable(cfg->irq_num); - return ret; - } - - memcpy(data->dlm_data.tx_data, tgt_payload->data, tgt_payload->data_len); - cycle_type = DIRECT_CCC_WRITE_TRANSFER; - } - - data->ccc_msgs.payload = payload; - data->msg_state = IT51XXX_I3CM_MSG_DIRECT_CCC; - more_transfer = (payload->targets.num_targets > 1) ? true : false; - it51xxx_set_op_type(dev, cycle_type, more_transfer, true); - sys_write8(I3CM_TARGET_ADDRESS(tgt_payload->addr), cfg->base + I3CM02_TARGET_ADDRESS); - sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS); - irq_enable(cfg->irq_num); - - return it51xxx_wait_to_complete(dev); -} - -static int it51xxx_i3cm_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret = 0; - - if (!payload) { - return -EINVAL; - } - - LOG_INST_DBG(cfg->log, "send %s ccc(0x%x)", - i3c_ccc_is_payload_broadcast(payload) ? "broadcast" : "direct", - payload->ccc.id); - - k_mutex_lock(&data->lock, K_FOREVER); - - /* disable ccc defining byte */ - sys_write8(sys_read8(cfg->base + I3CM15_CONTROL_2) & ~I3CM_CCC_WITH_DEFINING_BYTE, - cfg->base + I3CM15_CONTROL_2); - - if (!i3c_ccc_is_payload_broadcast(payload)) { - if (payload->ccc.data_len > 1) { - LOG_INST_ERR(cfg->log, "only support 1 ccc defining byte"); - ret = -ENOTSUP; - goto out; - } - if (payload->ccc.data_len > 0 && payload->ccc.data == NULL) { - ret = -EINVAL; - goto out; - } - if (payload->targets.payloads == NULL || payload->targets.num_targets == 0) { - ret = -EINVAL; - goto out; - } - if (payload->ccc.data_len) { - /* set ccc defining byte */ - sys_write8(sys_read8(cfg->base + I3CM15_CONTROL_2) | - I3CM_CCC_WITH_DEFINING_BYTE, - cfg->base + I3CM15_CONTROL_2); - sys_write8(payload->ccc.data[0], cfg->base + I3CM16_CCC_DEFINING_BYTE); - } - } else { - if (payload->ccc.data_len > 0 && payload->ccc.data == NULL) { - ret = -EINVAL; - goto out; - } - } - - it51xxx_enable_standby_state(dev, false); - - sys_write8(payload->ccc.id, cfg->base + I3CM03_COMMON_COMMAND_CODE); - - if (i3c_ccc_is_payload_broadcast(payload)) { - ret = it51xxx_broadcast_ccc_xfer(dev, payload); - } else { - ret = it51xxx_start_direct_ccc_xfer(dev, payload); - } - - it51xxx_enable_standby_state(dev, true); - -out: - k_mutex_unlock(&data->lock); - - return ret; -} - -static struct i3c_device_desc *it51xxx_i3cm_device_find(const struct device *dev, - const struct i3c_device_id *id) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - - return i3c_dev_list_find(&cfg->common.dev_list, id); -} - -static int it51xxx_i3cm_transfer(const struct device *dev, struct i3c_device_desc *target, - struct i3c_msg *msgs, uint8_t num_msgs) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - int ret; - - if (!msgs || target->dynamic_addr == 0U) { - return -EINVAL; - } - - if (num_msgs == 0) { - return 0; - } - - for (uint8_t i = 0; i < num_msgs; i++) { - if (!msgs[i].buf) { - return -EINVAL; - } - if ((msgs[i].flags & I3C_MSG_HDR) && (msgs[i].hdr_mode != 0)) { - LOG_INST_ERR(cfg->log, "unsupported hdr mode"); - return -ENOTSUP; - } - } - - irq_disable(cfg->irq_num); - if (!bus_is_idle(dev)) { - irq_enable(cfg->irq_num); - return -EBUSY; - } - - k_mutex_lock(&data->lock, K_FOREVER); - - it51xxx_enable_standby_state(dev, false); - - it51xxx_curr_msg_init(dev, msgs, NULL, num_msgs, target->dynamic_addr); - ret = it51xxx_prepare_priv_xfer(dev); - if (ret) { - irq_enable(cfg->irq_num); - goto out; - } - - /* start transfer */ - sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS); - irq_enable(cfg->irq_num); - - ret = it51xxx_wait_to_complete(dev); - -out: - it51xxx_enable_standby_state(dev, true); - data->curr_msg.curr_idx = 0; - k_mutex_unlock(&data->lock); - - return ret; -} - -static inline void it51xxx_accept_ibi(const struct device *dev, bool accept) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - - if (accept) { - sys_write8(sys_read8(cfg->base + I3CM10_CONTROL) & ~I3CM_REFUSE_IBI, - cfg->base + I3CM10_CONTROL); - } else { - sys_write8(sys_read8(cfg->base + I3CM10_CONTROL) | I3CM_REFUSE_IBI, - cfg->base + I3CM10_CONTROL); - } -} - -#ifdef CONFIG_I3C_USE_IBI -static int it51xxx_i3cm_ibi_hj_response(const struct device *dev, bool ack) -{ - struct it51xxx_i3cm_data *data = dev->data; - - data->ibi_hj_response = ack; - - return 0; -} - -static int it51xxx_i3cm_ibi_enable(const struct device *dev, struct i3c_device_desc *target) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_ccc_events i3c_events; - int ret; - uint8_t idx; - - if (!i3c_ibi_has_payload(target)) { - LOG_INST_ERR(cfg->log, "i3cm only supports ibi with payload"); - return -ENOTSUP; - } - - if (!i3c_device_is_ibi_capable(target)) { - return -EINVAL; - } - - if (data->ibi.num_addr >= ARRAY_SIZE(data->ibi.addr)) { - LOG_INST_ERR(cfg->log, "no more free space in the ibi list"); - return -ENOMEM; - } - - for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { - if (data->ibi.addr[idx] == target->dynamic_addr) { - LOG_INST_ERR(cfg->log, "selected target is already in the ibi list"); - return -EINVAL; - } - } - - if (data->ibi.num_addr > 0) { - for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { - if (data->ibi.addr[idx] == 0U) { - break; - } - } - - if (idx >= ARRAY_SIZE(data->ibi.addr)) { - LOG_INST_ERR(cfg->log, "cannot support more ibis"); - return -ENOTSUP; - } - } else { - idx = 0; - } - - LOG_INST_DBG(cfg->log, "ibi enabling for 0x%x (bcr 0x%x)", target->dynamic_addr, - target->bcr); - - /* enable target ibi event by enec command */ - i3c_events.events = I3C_CCC_EVT_INTR; - ret = i3c_ccc_do_events_set(target, true, &i3c_events); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "failed to send ibi enec for 0x%x(%d)", target->dynamic_addr, - ret); - return ret; - } - - data->ibi.addr[idx] = target->dynamic_addr; - data->ibi.num_addr += 1U; - - if (data->ibi.num_addr == 1U) { - it51xxx_enable_standby_state(dev, false); - } - - return 0; -} - -static int it51xxx_i3cm_ibi_disable(const struct device *dev, struct i3c_device_desc *target) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_ccc_events i3c_events; - int ret; - uint8_t idx; - - if (!i3c_device_is_ibi_capable(target)) { - return -EINVAL; - } - - for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { - if (target->dynamic_addr == data->ibi.addr[idx]) { - break; - } - } - - if (idx == ARRAY_SIZE(data->ibi.addr)) { - LOG_INST_ERR(cfg->log, "selected target is not in ibi list"); - return -ENODEV; - } - - data->ibi.addr[idx] = 0U; - data->ibi.num_addr -= 1U; - - if (data->ibi.num_addr == 0U) { - it51xxx_enable_standby_state(dev, true); - } - - LOG_INST_DBG(cfg->log, "ibi disabling for 0x%x (bcr 0x%x)", target->dynamic_addr, - target->bcr); - - /* disable target ibi event by disec command */ - i3c_events.events = I3C_CCC_EVT_INTR; - ret = i3c_ccc_do_events_set(target, false, &i3c_events); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "failed to send ibi disec for 0x%x(%d)", - target->dynamic_addr, ret); - } - - return ret; -} -#endif /* CONFIG_I3C_USE_IBI */ - -static enum i3c_bus_mode i3c_bus_mode(const struct i3c_dev_list *dev_list) -{ - enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; - - for (int i = 0; i < dev_list->num_i2c; i++) { - switch (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) { - case I3C_LVR_I2C_DEV_IDX_0: - if (mode < I3C_BUS_MODE_MIXED_FAST) { - mode = I3C_BUS_MODE_MIXED_FAST; - } - break; - case I3C_LVR_I2C_DEV_IDX_1: - if (mode < I3C_BUS_MODE_MIXED_LIMITED) { - mode = I3C_BUS_MODE_MIXED_LIMITED; - } - break; - case I3C_LVR_I2C_DEV_IDX_2: - if (mode < I3C_BUS_MODE_MIXED_SLOW) { - mode = I3C_BUS_MODE_MIXED_SLOW; - } - break; - default: - mode = I3C_BUS_MODE_INVALID; - break; - } - } - - return mode; -} - -static int it51xxx_i3cm_init(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_config_controller *ctrl_config = &data->common.ctrl_config; - uint8_t reg_val; - int ret; - - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "failed to apply pinctrl, ret %d", ret); - return ret; - } - - ctrl_config->is_secondary = false; - ctrl_config->supported_hdr = 0x0; - - k_sem_init(&data->msg_sem, 0, 1); - k_mutex_init(&data->lock); - - if (i3c_bus_mode(&cfg->common.dev_list) != I3C_BUS_MODE_PURE) { - LOG_INST_ERR(cfg->log, "only support pure mode currently"); - return -ENOTSUP; - } - - ret = i3c_addr_slots_init(dev); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "failed to init slots, ret %d", ret); - return ret; - } - - /* clear status, enable the interrupt and refuse ibi bits */ - sys_write8(sys_read8(cfg->base + I3CM01_STATUS) & ~START_TRANSFER, - cfg->base + I3CM01_STATUS); - sys_write8(sys_read8(cfg->base + I3CM10_CONTROL) | - (I3CM_REFUSE_IBI | I3CM_INTERRUPT_ENABLE), - cfg->base + I3CM10_CONTROL); - cfg->irq_config_func(dev); - - reg_val = sys_read8(cfg->base + I3CM50_CONTROL_3); - reg_val &= ~I3CM_DLM_SIZE_MASK; - switch (CONFIG_I3CM_IT51XXX_DLM_SIZE) { - case 256: - reg_val |= FIELD_PREP(I3CM_DLM_SIZE_MASK, 0); - break; - case 512: - reg_val |= FIELD_PREP(I3CM_DLM_SIZE_MASK, 1); - break; - case 1024: - reg_val |= FIELD_PREP(I3CM_DLM_SIZE_MASK, 2); - break; - default: - LOG_INST_ERR(cfg->log, "invalid dlm size(%d)", CONFIG_I3CM_IT51XXX_DLM_SIZE); - return -EINVAL; - }; - - /* set i3cm channel selection */ - reg_val &= ~I3CM_CHANNEL_SELECT_MASK; - LOG_INST_DBG(cfg->log, "channel %d is selected", cfg->io_channel); - reg_val |= FIELD_PREP(I3CM_CHANNEL_SELECT_MASK, cfg->io_channel); - - /* select 4k pull-up resistor and enable i3c engine*/ - reg_val |= (I3CM_PULL_UP_RESISTOR | I3CM_ENABLE); - sys_write8(reg_val, cfg->base + I3CM50_CONTROL_3); - - LOG_INST_DBG(cfg->log, "dlm base address 0x%x", (uint32_t)&data->dlm_data); - sys_write8(FIELD_GET(GENMASK(17, 16), (uint32_t)&data->dlm_data), - cfg->base + I3CM53_DLM_BASE_ADDRESS_HB); - sys_write8(BYTE_1((uint32_t)&data->dlm_data), cfg->base + I3CM52_DLM_BASE_ADDRESS_LB); - - ret = it51xxx_set_frequency(dev); - if (ret) { - return ret; - } - - data->is_initialized = true; - -#ifdef CONFIG_I3C_USE_IBI - data->ibi_hj_response = true; -#endif - - if (cfg->common.dev_list.num_i3c > 0) { - ret = i3c_bus_init(dev, &cfg->common.dev_list); - if (ret != 0) { - /* Perhaps the target device is offline. Avoid returning - * an error code to allow the application layer to - * reinitialize by sending ccc. - */ - LOG_INST_ERR(cfg->log, "failed to init i3c bus, ret %d", ret); - } - } - - return 0; -} - -static int it51xxx_daa_next_xfer(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_device_desc *target; - int ret; - uint64_t pid; - uint32_t part_no; - uint16_t vendor_id; - uint8_t dyn_addr = 0; - size_t rx_count; - - rx_count = it51xxx_get_received_data_count(dev); - if (rx_count != 8) { - LOG_INST_ERR(cfg->log, "daa: rx count (%d) not as expected", rx_count); - return -EINVAL; - } - - LOG_HEXDUMP_DBG(data->dlm_data.rx_data, rx_count, "6pid/1bcr/1dcr:"); - vendor_id = (((uint16_t)data->dlm_data.rx_data[0] << 8U) | - (uint16_t)data->dlm_data.rx_data[1]) & - 0xFFFEU; - part_no = (uint32_t)data->dlm_data.rx_data[2] << 24U | - (uint32_t)data->dlm_data.rx_data[3] << 16U | - (uint32_t)data->dlm_data.rx_data[4] << 8U | (uint32_t)data->dlm_data.rx_data[5]; - pid = (uint64_t)vendor_id << 32U | (uint64_t)part_no; - - /* find the device in the device list */ - ret = i3c_dev_list_daa_addr_helper(&data->common.attached_dev.addr_slots, - &cfg->common.dev_list, pid, false, false, &target, - &dyn_addr); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "no dynamic address could be assigned to target"); - return -EINVAL; - } - - sys_write8(I3CM_TARGET_ADDRESS(dyn_addr), cfg->base + I3CM02_TARGET_ADDRESS); - - if (target != NULL) { - target->dynamic_addr = dyn_addr; - target->bcr = data->dlm_data.rx_data[6]; - target->dcr = data->dlm_data.rx_data[7]; - } else { - LOG_INST_INF( - cfg->log, - "pid 0x%04x%08x is not in registered device list, given dynamic address " - "0x%x", - vendor_id, part_no, dyn_addr); - } - - /* mark the address as used */ - i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots, dyn_addr); - - /* mark the static address as free */ - if ((target != NULL) && (target->static_addr != 0) && (dyn_addr != target->static_addr)) { - i3c_addr_slots_mark_free(&data->common.attached_dev.addr_slots, - target->static_addr); - } - - return 0; -} - -static int it51xxx_direct_ccc_next_xfer(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_ccc_target_payload *tgt_payload = data->ccc_msgs.payload->targets.payloads; - uint8_t cycle_type; - bool more_transfer; - bool is_read = tgt_payload[data->ccc_msgs.target_idx].rnw == 1U; - int ret; - - it51xxx_direct_ccc_xfer_end(dev); - - /* start next transfer */ - data->ccc_msgs.target_idx++; - if (is_read) { - ret = it51xxx_set_tx_rx_length(dev, 0, - tgt_payload[data->ccc_msgs.target_idx].data_len); - if (ret) { - return ret; - } - cycle_type = PRIVATE_READ_TRANSFER; - } else { - ret = it51xxx_set_tx_rx_length(dev, tgt_payload[data->ccc_msgs.target_idx].data_len, - 0); - if (ret) { - return ret; - } - memcpy(data->dlm_data.tx_data, tgt_payload[data->ccc_msgs.target_idx].data, - tgt_payload[data->ccc_msgs.target_idx].data_len); - cycle_type = PRIVATE_WRITE_TRANSFER; - } - more_transfer = - (data->ccc_msgs.target_idx == data->ccc_msgs.payload->targets.num_targets - 1) - ? false - : true; - it51xxx_set_op_type(dev, cycle_type, more_transfer, false); - sys_write8(I3CM_TARGET_ADDRESS(tgt_payload[data->ccc_msgs.target_idx].addr), - cfg->base + I3CM02_TARGET_ADDRESS); - - return 0; -} - -static int it51xxx_private_next_xfer(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_msg *i3c_msgs = data->curr_msg.i3c_msgs; - struct i2c_msg *i2c_msgs = data->curr_msg.i2c_msgs; - bool is_write, next_is_write, next_is_restart; - int ret; - - if (it51xxx_curr_msg_is_i3c(dev)) { - is_write = ((i3c_msgs[data->curr_msg.curr_idx].flags & I3C_MSG_RW_MASK) == - I3C_MSG_WRITE); - next_is_write = ((i3c_msgs[data->curr_msg.curr_idx + 1].flags & I3C_MSG_RW_MASK) == - I3C_MSG_WRITE); - next_is_restart = ((i3c_msgs[data->curr_msg.curr_idx + 1].flags & - I3C_MSG_RESTART) == I3C_MSG_RESTART); - } else { - is_write = ((i2c_msgs[data->curr_msg.curr_idx].flags & I2C_MSG_RW_MASK) == - I2C_MSG_WRITE); - next_is_write = ((i2c_msgs[data->curr_msg.curr_idx + 1].flags & I2C_MSG_RW_MASK) == - I2C_MSG_WRITE); - next_is_restart = ((i2c_msgs[data->curr_msg.curr_idx + 1].flags & - I2C_MSG_RESTART) == I2C_MSG_RESTART); - } - - if (is_write && next_is_write && !next_is_restart) { - data->curr_msg.curr_idx++; - } else { - LOG_INST_ERR(cfg->log, "unknown next private xfer message"); - return -EINVAL; - } - - /* prepare the next transfer */ - ret = it51xxx_prepare_priv_xfer(dev); - if (ret) { - return ret; - } - - return 0; -} - -static void it51xxx_private_xfer_end(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - struct i3c_msg *i3c_msgs = data->curr_msg.i3c_msgs; - struct i2c_msg *i2c_msgs = data->curr_msg.i2c_msgs; - size_t data_count; - uint8_t curr_msg_idx = data->curr_msg.curr_idx; - - if (it51xxx_curr_msg_is_i3c(dev)) { - if ((i3c_msgs[curr_msg_idx].flags & I3C_MSG_RW_MASK) == I3C_MSG_WRITE) { - i3c_msgs[curr_msg_idx].num_xfer = i3c_msgs[curr_msg_idx].len; - } - - if ((i3c_msgs[curr_msg_idx].flags & I3C_MSG_RW_MASK) == I3C_MSG_READ) { - data_count = it51xxx_get_received_data_count(dev); - i3c_msgs[curr_msg_idx].num_xfer = data_count; - memcpy(i3c_msgs[curr_msg_idx].buf, data->dlm_data.rx_data, - MIN(i3c_msgs[curr_msg_idx].len, data_count)); - LOG_INST_DBG(cfg->log, "i3c: private rx %d bytes", data_count); - LOG_HEXDUMP_DBG(i3c_msgs[curr_msg_idx].buf, i3c_msgs[curr_msg_idx].len, - "i3c: private xfer rx:"); - } - - if (curr_msg_idx != data->curr_msg.num_msgs - 1) { - if ((i3c_msgs[curr_msg_idx].flags & I3C_MSG_RW_MASK) == I3C_MSG_WRITE && - i3c_msgs[curr_msg_idx + 1].flags & I3C_MSG_READ) { - data_count = it51xxx_get_received_data_count(dev); - i3c_msgs[curr_msg_idx + 1].num_xfer = data_count; - memcpy(i3c_msgs[curr_msg_idx + 1].buf, data->dlm_data.rx_data, - MIN(i3c_msgs[curr_msg_idx + 1].len, data_count)); - LOG_INST_DBG(cfg->log, "i3c: private tx-then-rx %d bytes", - data_count); - LOG_HEXDUMP_DBG(i3c_msgs[curr_msg_idx + 1].buf, - i3c_msgs[curr_msg_idx + 1].len, - "i3c: private xfer tx-then-rx:"); - } - } - } else { - if ((i2c_msgs[curr_msg_idx].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) { - data_count = it51xxx_get_received_data_count(dev); - memcpy(i2c_msgs[curr_msg_idx].buf, data->dlm_data.rx_data, - MIN(i2c_msgs[curr_msg_idx].len, data_count)); - LOG_INST_DBG(cfg->log, "i2c: private rx %d bytes", data_count); - LOG_HEXDUMP_DBG(i2c_msgs[curr_msg_idx].buf, i2c_msgs[curr_msg_idx].len, - "i2c: private xfer rx:"); - } - - if (curr_msg_idx != data->curr_msg.num_msgs - 1) { - if ((i2c_msgs[curr_msg_idx].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE && - i2c_msgs[curr_msg_idx + 1].flags & I2C_MSG_READ) { - data_count = it51xxx_get_received_data_count(dev); - memcpy(i2c_msgs[curr_msg_idx + 1].buf, data->dlm_data.rx_data, - MIN(i2c_msgs[curr_msg_idx + 1].len, data_count)); - LOG_INST_DBG(cfg->log, "i2c: private tx-then-rx %d bytes", - data_count); - LOG_HEXDUMP_DBG(i2c_msgs[curr_msg_idx + 1].buf, - i2c_msgs[curr_msg_idx + 1].len, - "i2c: private xfer tx-then-rx:"); - } - } - } -} - -#ifdef CONFIG_I3C_USE_IBI -static void it51xxx_process_ibi_payload(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - size_t payload_sz = 0; - struct i3c_device_desc *target = i3c_dev_list_i3c_addr_find(dev, data->ibi_target_addr); - - if (i3c_ibi_has_payload(target)) { - payload_sz = it51xxx_get_received_data_count(dev); - if (payload_sz == 0) { - /* wrong ibi transaction due to missing payload. - * a 100us timeout on the targe side may cause this - * situation. - */ - return; - } - - if (payload_sz > CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE) { - LOG_INST_WRN(cfg->log, "ibi payloads(%d) is too much", payload_sz); - } - } - - if (i3c_ibi_work_enqueue_target_irq(target, data->dlm_data.rx_data, - MIN(payload_sz, CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE)) != - 0) { - LOG_INST_ERR(cfg->log, "failed to enqueue tir work"); - } -} -#endif /* CONFIG_I3C_USE_IBI */ - -static inline void it51xxx_check_error(const struct device *dev, const uint8_t int_status) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - - if (int_status & PARITY_ERROR) { - LOG_INST_ERR(cfg->log, "isr: transaction(%d) parity error", data->msg_state); - data->msg_state = IT51XXX_I3CM_MSG_ERROR; - sys_write8(PARITY_ERROR, cfg->base + I3CM01_STATUS); - } - - if (int_status & CRC5_ERROR) { - LOG_INST_ERR(cfg->log, "isr: transaction(%d) crc5 error", data->msg_state); - data->msg_state = IT51XXX_I3CM_MSG_ERROR; - sys_write8(CRC5_ERROR, cfg->base + I3CM01_STATUS); - } -} - -static void it51xxx_i3cm_isr(const struct device *dev) -{ - const struct it51xxx_i3cm_config *cfg = dev->config; - struct it51xxx_i3cm_data *data = dev->data; - uint8_t int_status; - - int_status = sys_read8(cfg->base + I3CM01_STATUS); - int_status &= ~START_TRANSFER; - - if (!data->is_initialized) { - LOG_INST_DBG(cfg->log, - "i3cm interrupt(0x%x) occurs before initialization was complete", - int_status); - } - - it51xxx_check_error(dev, int_status); - - if (int_status & IBI_INTERRUPT) { - LOG_INST_DBG(cfg->log, "isr: ibi interrupt is detected"); - - data->msg_state = bus_is_idle(dev) ? IT51XXX_I3CM_MSG_IBI : IT51XXX_I3CM_MSG_ABORT; -#ifdef CONFIG_I3C_USE_IBI - uint8_t ibi_value, ibi_address; - - ibi_value = sys_read8(cfg->base + I3CM0F_IBI_ADDRESS); - ibi_address = FIELD_GET(I3CM_IBI_ADDR_MASK, ibi_value); - if (ibi_value & I3CM_IBI_RNW) { - struct i3c_device_desc *target = NULL; - - target = i3c_dev_list_i3c_addr_find(dev, ibi_address); - if (target != NULL) { - data->ibi_target_addr = ibi_address; - if (i3c_ibi_has_payload(target)) { - it51xxx_set_tx_rx_length(dev, 0, - CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE); - it51xxx_set_op_type(dev, IBI_READ_TRANSFER, false, true); - } - it51xxx_accept_ibi(dev, true); - } else { - it51xxx_accept_ibi(dev, false); - } - sys_write8(IBI_INTERRUPT, cfg->base + I3CM01_STATUS); - } else if (ibi_address == I3C_IBI_HJ_ADDR) { - it51xxx_accept_ibi(dev, data->ibi_hj_response); - sys_write8(IBI_INTERRUPT, cfg->base + I3CM01_STATUS); - if (data->ibi_hj_response) { - if (i3c_ibi_work_enqueue_hotjoin(dev) != 0) { - LOG_INST_ERR(cfg->log, "failed to enqueue hot-join work"); - } - } - } else { - it51xxx_accept_ibi(dev, false); - sys_write8(IBI_INTERRUPT, cfg->base + I3CM01_STATUS); - LOG_INST_ERR(cfg->log, "unsupported controller role request"); - } -#else - LOG_INST_ERR(cfg->log, "isr: Kconfig I3C_USE_IBI is disabled"); - it51xxx_accept_ibi(dev, false); - sys_write8(IBI_INTERRUPT, cfg->base + I3CM01_STATUS); -#endif /* CONFIG_I3C_USE_IBI */ - } - - if (int_status & TRANSFER_END) { - LOG_INST_DBG(cfg->log, "isr: end transfer is detected"); - /* clear tx and rx length */ - it51xxx_set_tx_rx_length(dev, 0, 0); - if (int_status & TARGET_NACK) { - LOG_INST_DBG(cfg->log, "isr: target nack is detected"); - if (data->msg_state == IT51XXX_I3CM_MSG_DAA) { - LOG_INST_DBG(cfg->log, "isr: no target should be assigned address"); - } else { - LOG_INST_ERR(cfg->log, "isr: no target responses"); - data->msg_state = IT51XXX_I3CM_MSG_ERROR; - } - } - - switch (data->msg_state) { - case IT51XXX_I3CM_MSG_ABORT: - LOG_INST_INF(cfg->log, "isr: transfer was aborted due to ibi transaction"); - data->transfer_is_aborted = true; - __fallthrough; - case IT51XXX_I3CM_MSG_IBI: -#ifdef CONFIG_I3C_USE_IBI - if (data->ibi_target_addr) { - it51xxx_process_ibi_payload(dev); - data->ibi_target_addr = 0x0; - } -#endif /* CONFIG_I3C_USE_IBI */ - break; - case IT51XXX_I3CM_MSG_BROADCAST_CCC: - if (data->ccc_msgs.payload->ccc.data_len > 0) { - data->ccc_msgs.payload->ccc.num_xfer = - data->ccc_msgs.payload->ccc.data_len; - } - break; - case IT51XXX_I3CM_MSG_PRIVATE_XFER: - it51xxx_private_xfer_end(dev); - break; - case IT51XXX_I3CM_MSG_DIRECT_CCC: - data->ccc_msgs.payload->ccc.num_xfer = data->ccc_msgs.payload->ccc.data_len; - it51xxx_direct_ccc_xfer_end(dev); - data->ccc_msgs.target_idx = 0; - break; - case IT51XXX_I3CM_MSG_ERROR: - LOG_INST_ERR(cfg->log, "isr: message status error"); - data->error_is_detected = true; - break; - case IT51XXX_I3CM_MSG_DAA: - LOG_INST_DBG(cfg->log, "isr: daa finished"); - break; - case IT51XXX_I3CM_MSG_IDLE: - LOG_INST_WRN(cfg->log, "isr: end transfer occurs but bus is in idle"); - break; - default: - LOG_INST_ERR(cfg->log, "isr: unknown message status(%d)", data->msg_state); - break; - } - - if (data->msg_state != IT51XXX_I3CM_MSG_IBI) { - k_sem_give(&data->msg_sem); - } - - data->msg_state = IT51XXX_I3CM_MSG_IDLE; - sys_write8(TARGET_NACK | TRANSFER_END, cfg->base + I3CM01_STATUS); - } - - if (int_status & NEXT_TRANSFER) { - int ret = 0; - - LOG_INST_DBG(cfg->log, "isr: next transfer is detected"); - switch (data->msg_state) { - case IT51XXX_I3CM_MSG_DAA: - ret = it51xxx_daa_next_xfer(dev); - break; - case IT51XXX_I3CM_MSG_DIRECT_CCC: - ret = it51xxx_direct_ccc_next_xfer(dev); - break; - case IT51XXX_I3CM_MSG_PRIVATE_XFER: - ret = it51xxx_private_next_xfer(dev); - break; - default: - ret = -EINVAL; - LOG_INST_ERR(cfg->log, "isr: next transfer, unknown msg status(0x%x)", - data->msg_state); - break; - }; - - if (ret) { - data->msg_state = IT51XXX_I3CM_MSG_ERROR; - } - sys_write8(NEXT_TRANSFER, cfg->base + I3CM01_STATUS); - } -} - -static DEVICE_API(i3c, it51xxx_i3cm_api) = { - .i2c_api.transfer = it51xxx_i3cm_i2c_api_transfer, -#ifdef CONFIG_I2C_RTIO - .i2c_api.iodev_submit = i2c_iodev_submit_fallback, -#endif /* CONFIG_I2C_RTIO */ - - .configure = it51xxx_i3cm_configure, - .config_get = it51xxx_i3cm_config_get, - - .do_daa = it51xxx_i3cm_do_daa, - .do_ccc = it51xxx_i3cm_do_ccc, - - .i3c_device_find = it51xxx_i3cm_device_find, - - .i3c_xfers = it51xxx_i3cm_transfer, - -#ifdef CONFIG_I3C_USE_IBI - .ibi_hj_response = it51xxx_i3cm_ibi_hj_response, - .ibi_enable = it51xxx_i3cm_ibi_enable, - .ibi_disable = it51xxx_i3cm_ibi_disable, -#endif /* CONFIG_I3C_USE_IBI */ -#ifdef CONFIG_I3C_RTIO - .iodev_submit = i3c_iodev_submit_fallback, -#endif /* CONFIG_I3C_RTIO */ -}; - -#define IT51XXX_I3CM_INIT(n) \ - LOG_INSTANCE_REGISTER(DT_NODE_FULL_NAME_TOKEN(DT_DRV_INST(n)), n, \ - CONFIG_I3C_IT51XXX_LOG_LEVEL); \ - PINCTRL_DT_INST_DEFINE(n); \ - static struct i3c_device_desc it51xxx_i3cm_device_array_##n[] = \ - I3C_DEVICE_ARRAY_DT_INST(n); \ - static struct i3c_i2c_device_desc it51xxx_i3cm_i2c_device_array_##n[] = \ - I3C_I2C_DEVICE_ARRAY_DT_INST(n); \ - static void it51xxx_i3cm_config_func_##n(const struct device *dev) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), 0, it51xxx_i3cm_isr, DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - }; \ - static const struct it51xxx_i3cm_config i3c_config_##n = { \ - .base = DT_INST_REG_ADDR(n), \ - .irq_config_func = it51xxx_i3cm_config_func_##n, \ - .irq_num = DT_INST_IRQN(n), \ - .common.dev_list.i3c = it51xxx_i3cm_device_array_##n, \ - .common.dev_list.num_i3c = ARRAY_SIZE(it51xxx_i3cm_device_array_##n), \ - .common.dev_list.i2c = it51xxx_i3cm_i2c_device_array_##n, \ - .common.dev_list.num_i2c = ARRAY_SIZE(it51xxx_i3cm_i2c_device_array_##n), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .io_channel = DT_INST_PROP(n, io_channel), \ - .clocks.i3c_pp_duty_cycle = DT_INST_PROP_OR(n, i3c_pp_duty_cycle, 0), \ - .clocks.i3c_od_scl_hz = DT_INST_PROP_OR(n, i3c_od_scl_hz, 0), \ - .clocks.i3c_scl_hddat = DT_INST_PROP_OR(n, i3c_scl_hddat, 0), \ - .clocks.i3c_scl_tcas = DT_INST_PROP_OR(n, i3c_scl_tcas, 1), \ - .clocks.i3c_scl_tcbs = DT_INST_PROP_OR(n, i3c_scl_tcbs, 0), \ - .clocks.i3c_scl_tcasr = DT_INST_PROP_OR(n, i3c_scl_tcasr, 1), \ - .clocks.i3c_scl_tcbsr = DT_INST_PROP_OR(n, i3c_scl_tcbsr, 0), \ - .clocks.i2c_scl_hddat = DT_INST_PROP_OR(n, i2c_scl_hddat, 0), \ - LOG_INSTANCE_PTR_INIT(log, DT_NODE_FULL_NAME_TOKEN(DT_DRV_INST(n)), n)}; \ - static struct it51xxx_i3cm_data i3c_data_##n = { \ - .common.ctrl_config.scl.i3c = DT_INST_PROP_OR(n, i3c_scl_hz, 0), \ - .common.ctrl_config.scl.i2c = DT_INST_PROP_OR(n, i2c_scl_hz, 0), \ - }; \ - DEVICE_DT_INST_DEFINE(n, it51xxx_i3cm_init, NULL, &i3c_data_##n, &i3c_config_##n, \ - POST_KERNEL, CONFIG_I3C_CONTROLLER_INIT_PRIORITY, \ - &it51xxx_i3cm_api); - -DT_INST_FOREACH_STATUS_OKAY(IT51XXX_I3CM_INIT) diff --git a/drivers/i3c/i3cs_it51xxx.c b/drivers/i3c/i3cs_it51xxx.c deleted file mode 100644 index 04b4a6a1f446b..0000000000000 --- a/drivers/i3c/i3cs_it51xxx.c +++ /dev/null @@ -1,883 +0,0 @@ -/* - * Copyright (c) 2025 ITE Technology Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ite_it51xxx_i3cs - -#include -#include -LOG_MODULE_REGISTER(i3cs_it51xxx); - -#include -#include -#include -#include -#include -#include - -#include - -#define BYTE_0(x) FIELD_GET(GENMASK(7, 0), x) -#define BYTE_1(x) FIELD_GET(GENMASK(15, 8), x) -#define BYTE_2(x) FIELD_GET(GENMASK(23, 16), x) -#define BYTE_3(x) FIELD_GET(GENMASK(31, 24), x) - -/* used for tx/rx fifo base address setting */ -#define FIFO_ADDR_LB(x) FIELD_GET(GENMASK(10, 3), x) -#define FIFO_ADDR_HB(x) FIELD_GET(GENMASK(18, 11), x) - -#define I3CS05_CONFIG_1 0x05 -#define ID_RANDOM BIT(0) - -#define I3CS07_CONFIG_2 0x07 -#define I3CS_TARGET_ADDRESS(n) FIELD_PREP(GENMASK(7, 1), n) - -#define I3CS08_STATUS_0 0x08 -#define BUS_IS_BUSY BIT(0) - -#define I3CS09_STATUS_1 0x09 -#define INT_ERROR_WARNING BIT(7) -#define INT_CCC BIT(6) -#define INT_DYN_ADDR_CHANGE BIT(5) -#define INT_RX_PENDING BIT(3) -#define INT_STOP BIT(2) -#define INT_ADDR_MATCHED BIT(1) - -#define I3CS0A_STATUS_2 0x0A -#define EVENT_DETECT_MASK GENMASK(5, 4) -#define INT_TARGET_RST BIT(3) -#define INT_EVENT BIT(2) - -#define I3CS0B_STATUS_3 0x0B -#define HJ_DISABLED BIT(3) -#define IBI_DISABLED BIT(0) - -#define I3CS0C_CONTROL_0 0x0C -#define EXTENDED_IBI_DATA BIT(3) -#define I3CS_EVENT_SELECT(n) FIELD_PREP(GENMASK(1, 0), n) - -#define I3CS0D_CONTROL_1 0x0D -#define I3CS0F_CONTROL_3 0x0F -#define I3CS11_INTERRUPT_ENABLE_CTRL_0 0x11 - -#define I3CS14_DIRECT_TX_FIFO_BASE_ADDR_LB 0x14 -#define I3CS15_DIRECT_TX_FIFO_BASE_ADDR_HB 0x15 -#define I3CS16_DIRECT_RX_FIFO_BASE_ADDR_LB 0x16 -#define I3CS17_DIRECT_RX_FIFO_BASE_ADDR_HB 0x17 -#define I3CS1A_DIRECT_TX_LENGTH_LB 0x1A -#define I3CS1B_DIRECT_TX_LENGTH_HB 0x1B - -#define I3CS1C_ERROR_WARNING_REG_0 0x1C -#define INVALID_START BIT(4) -#define CONTROLLER_TERMINATED BIT(3) -#define TX_FIFO_UNDERRUN (BIT(2) | BIT(1)) -#define RX_FIFO_OVERRUN BIT(0) - -#define I3CS1D_ERROR_WARNING_REG_1 0x1D -#define S0_OR_S1_ERROR BIT(3) -#define SDR_PARITY_ERROR BIT(0) - -#define I3CS2C_DATA_CTRL_0 0x2C -#define FLUSH_TX_FIFO BIT(0) - -#define I3CS41_TX_RX_FIFO_BASE_ADDR_HB 0x41 -#define I3CS42_TX_FIFO_BASE_ADDR_LB 0x42 -#define I3CS43_RX_FIFO_BASE_ADDR_LB 0x43 -#define I3CS45_RX_FIFO_READ_PTR 0x45 -#define I3CS4A_TX_FIFO_SIZE 0x4A -#define I3CS_TX_FIFO_SIZE_MASK GENMASK(3, 0) - -#define I3CS4D_CONTROL_REG_4 0x4D -#define I3CS_DIRECT_MODE_AUTO_CLR_TX_CNT BIT(6) -#define I3CS_DIRECT_MODE_ENABLE BIT(5) | BIT(4) - -#define I3CS4E_DIRECT_FIFO_STATUS 0x4E -#define I3CS_DIRECT_TX_DONE BIT(1) -#define I3CS_DIRECT_RX_DONE BIT(0) - -#define I3CS58_TX_FIFO_BYTE_COUNT_LB 0x58 -#define I3CS59_TX_FIFO_BYTE_COUNT_HB 0x59 -#define I3CS5A_RX_FIFO_BYTE_COUNT_LB 0x5A -#define I3CS5B_RX_FIFO_BYTE_COUNT_HB 0x5B -#define I3CS64_DYNAMIC_ADDRESS 0x64 -#define DYNAMIC_ADDRESS(x) FIELD_GET(GENMASK(7, 1), x) -#define DYNAMIC_ADDRESS_VALID BIT(0) - -#define I3CS68_MRL_SET_BY_CTRL_LB 0x68 -#define I3CS69_MRL_SET_BY_CTRL_HB 0x69 -#define I3CS6A_MWL_SET_BY_CTRL_LB 0x6A -#define I3CS6B_MWL_SET_BY_CTRL_HB 0x6B -#define I3CS6C_PRAT_NUMBER_0 0x6C -#define I3CS6D_PRAT_NUMBER_1 0x6D -#define I3CS6E_PRAT_NUMBER_2 0x6E -#define I3CS6F_PRAT_NUMBER_3 0x6F -#define I3CS71_DCR 0x71 -#define I3CS72_BCR 0x72 -#define I3CS76_TX_FIFO_READ_PTR 0x76 -#define I3CS7A_RX_FIFO_SIZE 0x7A -#define I3CS_RX_FIFO_SIZE_MASK GENMASK(3, 0) - -#define IBI_MDB_GROUP_MASK GENMASK(7, 5) -#define IBI_MDB_GROUP_PENDING_READ_NOTI 5 - -#define IT51XXX_DIRECT_MODE_FIFO_SIZE 4096 -#define IT51XXX_I3CS_MAX_MRL_MWL 0xFFF /* 4095 bytes */ - -enum it51xxx_i3cs_event_type { - EVT_NORMAL_MODE = 0, - EVT_IBI, - EVT_CONTROL_REQUEST, - EVT_HOT_JOIN, -}; - -enum it51xxx_i3cs_request_event { - NONE = 0, - REQUEST_NOT_SENT, - REQUEST_NACK_EVT, - REQUEST_ACK_EVT, -}; - -static const struct fifo_size_mapping_t { - uint16_t fifo_size; - uint8_t value; -} fifo_size_table[5] = {[0] = {.fifo_size = 16, .value = 0x0}, - [1] = {.fifo_size = 32, .value = 0x5}, - [2] = {.fifo_size = 64, .value = 0x6}, - [3] = {.fifo_size = 128, .value = 0x7}, - [4] = {.fifo_size = 4096, .value = 0xC}}; - -struct it51xxx_i3cs_data { - struct i3c_driver_data common; - struct i3c_target_config *target_config; - - /* configuration parameters for I3C hardware to act as target device */ - struct i3c_config_target config_target; - -#ifdef CONFIG_I3C_USE_IBI - struct k_sem ibi_sync_sem; -#endif /* CONFIG_I3C_USE_IBI */ - - struct k_mutex lock; - - struct { - uint8_t tx_data[CONFIG_I3CS_IT51XXX_TX_FIFO_SIZE]; - uint8_t rx_data[CONFIG_I3CS_IT51XXX_RX_FIFO_SIZE]; - } fifo __aligned(IT51XXX_DIRECT_MODE_FIFO_SIZE); -}; - -struct it51xxx_i3cs_config { - /* common i3c driver config */ - struct i3c_driver_config common; - - const struct pinctrl_dev_config *pcfg; - mm_reg_t base; - uint8_t io_channel; - uint8_t vendor_info; - - struct { - mm_reg_t addr; - uint8_t bit_mask; - } extern_enable; - - void (*irq_config_func)(const struct device *dev); - - LOG_INSTANCE_PTR_DECLARE(log); -}; - -static inline bool rx_direct_mode_is_enabled(const struct device *dev) -{ - struct it51xxx_i3cs_data *data = dev->data; - - return sizeof(data->fifo.rx_data) == IT51XXX_DIRECT_MODE_FIFO_SIZE; -} - -static inline bool tx_direct_mode_is_enabled(const struct device *dev) -{ - struct it51xxx_i3cs_data *data = dev->data; - - return sizeof(data->fifo.tx_data) == IT51XXX_DIRECT_MODE_FIFO_SIZE; -} - -static inline uint16_t rx_byte_cnt_in_fifo(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - - return (sys_read8(cfg->base + I3CS5B_RX_FIFO_BYTE_COUNT_HB) << 8) + - sys_read8(cfg->base + I3CS5A_RX_FIFO_BYTE_COUNT_LB); -} - -static inline uint16_t tx_byte_cnt_in_fifo(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - - return (sys_read8(cfg->base + I3CS59_TX_FIFO_BYTE_COUNT_HB) << 8) + - sys_read8(cfg->base + I3CS58_TX_FIFO_BYTE_COUNT_LB); -} - -static inline void set_mrl_value(const struct device *dev, const uint16_t value) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - uint16_t mrl; - - mrl = (value > IT51XXX_I3CS_MAX_MRL_MWL) ? IT51XXX_I3CS_MAX_MRL_MWL : value; - - sys_write8(BYTE_0(mrl), cfg->base + I3CS68_MRL_SET_BY_CTRL_LB); - sys_write8(BYTE_1(mrl), cfg->base + I3CS69_MRL_SET_BY_CTRL_HB); -} - -static inline void set_mwl_value(const struct device *dev, const uint16_t value) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - uint16_t mwl; - - mwl = (value > IT51XXX_I3CS_MAX_MRL_MWL) ? IT51XXX_I3CS_MAX_MRL_MWL : value; - - sys_write8(BYTE_0(mwl), cfg->base + I3CS6A_MWL_SET_BY_CTRL_LB); - sys_write8(BYTE_1(mwl), cfg->base + I3CS6B_MWL_SET_BY_CTRL_HB); -} - -static int it51xxx_i3cs_prepare_tx_fifo(const struct device *dev, uint8_t *buf, uint16_t len) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - uint16_t tx_count; - - if (len > sizeof(data->fifo.tx_data)) { - return -ENOSPC; - } - - tx_count = tx_byte_cnt_in_fifo(dev); - if (tx_count) { - LOG_INST_WRN(cfg->log, "dropped the remaining %d bytes in the tx fifo", tx_count); - } - - /* flush tx fifo */ - sys_write8(sys_read8(cfg->base + I3CS2C_DATA_CTRL_0) | FLUSH_TX_FIFO, - cfg->base + I3CS2C_DATA_CTRL_0); - - /* set tx length */ - if (tx_direct_mode_is_enabled(dev)) { - sys_write8(BYTE_0(len), cfg->base + I3CS1A_DIRECT_TX_LENGTH_LB); - sys_write8(BYTE_1(len), cfg->base + I3CS1B_DIRECT_TX_LENGTH_HB); - } else { - sys_write8(len, cfg->base + I3CS76_TX_FIFO_READ_PTR); - } - - /* fill tx fifo with data */ - memcpy(data->fifo.tx_data, buf, len); - - return 0; -} - -static int it51xxx_i3cs_target_register(const struct device *dev, struct i3c_target_config *tgt_cfg) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - - if (!data->target_config) { - data->target_config = tgt_cfg; - - chip_block_idle(); - pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); - } else { - LOG_INST_WRN(cfg->log, "the target has already been registered"); - } - - return 0; -} - -static int it51xxx_i3cs_target_unregister(const struct device *dev, - struct i3c_target_config *tgt_cfg) -{ - ARG_UNUSED(tgt_cfg); - - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - - if (data->target_config) { - data->target_config = NULL; - - /* Permit to enter power policy and idle mode. */ - pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); - chip_permit_idle(); - } else { - LOG_INST_WRN(cfg->log, "the target has not been registered"); - } - - return 0; -} - -static int it51xxx_i3cs_target_tx_write(const struct device *dev, uint8_t *buf, uint16_t len, - uint8_t hdr_mode) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - int ret; - - if (!buf || len == 0) { - LOG_INST_ERR(cfg->log, "null buffer or zero length"); - return -EINVAL; - } - - if (hdr_mode != 0) { - LOG_INST_ERR(cfg->log, "unsupported hdr mode"); - return -ENOTSUP; - } - - if (len > sizeof(data->fifo.tx_data)) { - LOG_INST_ERR(cfg->log, "invalid tx length(%d)", len); - return -ENOSPC; - } - - k_mutex_lock(&data->lock, K_FOREVER); - ret = it51xxx_i3cs_prepare_tx_fifo(dev, buf, len); - k_mutex_unlock(&data->lock); - - return ret ? ret : len; -} - -static inline bool it51xxx_i3cs_dynamic_addr_valid(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - - return ((sys_read8(cfg->base + I3CS64_DYNAMIC_ADDRESS) & DYNAMIC_ADDRESS_VALID) == - DYNAMIC_ADDRESS_VALID); -} - -#ifdef CONFIG_I3C_USE_IBI -static inline bool it51xxx_i3cs_is_ibi_disable(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - - return ((sys_read8(cfg->base + I3CS0B_STATUS_3) & IBI_DISABLED) == IBI_DISABLED); -} - -static inline bool it51xxx_i3cs_is_hj_disable(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - - return ((sys_read8(cfg->base + I3CS0B_STATUS_3) & HJ_DISABLED) == HJ_DISABLED); -} - -static int it51xxx_i3cs_wait_to_complete(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - - if (k_sem_take(&data->ibi_sync_sem, K_MSEC(CONFIG_I3CS_IT51XXX_IBI_TIMEOUT_MS)) != 0) { - LOG_INST_ERR(cfg->log, "ibi event transmission timed out"); - return -ETIMEDOUT; - } - - return 0; -} - -static int it51xxx_i3cs_target_ibi_raise(const struct device *dev, struct i3c_ibi *request) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - struct i3c_config_target *config_target = &data->config_target; - int ret = 0; - uint8_t reg_val; - - if (!request) { - LOG_INST_ERR(cfg->log, "ibi request is null"); - return -EINVAL; - } - - k_mutex_lock(&data->lock, K_FOREVER); - - reg_val = sys_read8(cfg->base + I3CS08_STATUS_0); - if (reg_val & BUS_IS_BUSY) { - LOG_INST_ERR(cfg->log, "bus is busy"); - ret = -EBUSY; - goto out; - } - - switch (request->ibi_type) { - case I3C_IBI_TARGET_INTR: - if (it51xxx_i3cs_is_ibi_disable(dev) || !it51xxx_i3cs_dynamic_addr_valid(dev)) { - LOG_INST_ERR(cfg->log, "ibi is disabled or dynamic address is invalid"); - ret = -EINVAL; - goto out; - } - if (request->payload_len > sizeof(data->fifo.tx_data) + 1) { - LOG_INST_ERR(cfg->log, "payload too large for ibi tir"); - ret = -ENOMEM; - goto out; - } - if (config_target->bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE && - request->payload_len == 0) { - LOG_INST_ERR(cfg->log, "ibi should be with payload"); - ret = -EINVAL; - goto out; - } - if (!(config_target->bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE) && - request->payload_len != 0) { - LOG_INST_ERR(cfg->log, "ibi should not be with payload"); - ret = -EINVAL; - goto out; - } - - if (request->payload_len == 0) { - LOG_INST_DBG(cfg->log, "send ibi without payload"); - sys_write8(I3CS_EVENT_SELECT(EVT_IBI), cfg->base + I3CS0C_CONTROL_0); - } else { - /* set mandatory data byte */ - sys_write8(request->payload[0], cfg->base + I3CS0D_CONTROL_1); - - if (request->payload_len > 1) { - if (FIELD_GET(IBI_MDB_GROUP_MASK, request->payload[0]) == - IBI_MDB_GROUP_PENDING_READ_NOTI) { - /* since the fifo for ibi payload and pending data is - * shared, the i3cs controller cannot issue an ibi with - * pending data notification if the ibi payload size - * exceeds 1. - */ - LOG_INST_ERR(cfg->log, "unsupported multiple payloads with " - "pending read noti. group"); - ret = -ENOTSUP; - goto out; - } - - ret = it51xxx_i3cs_prepare_tx_fifo(dev, &request->payload[1], - request->payload_len - 1); - if (ret) { - goto out; - } - - sys_write8(EXTENDED_IBI_DATA | I3CS_EVENT_SELECT(EVT_IBI), - cfg->base + I3CS0C_CONTROL_0); - } else { - sys_write8(I3CS_EVENT_SELECT(EVT_IBI), - cfg->base + I3CS0C_CONTROL_0); - } - } - break; - case I3C_IBI_HOTJOIN: - if (it51xxx_i3cs_is_hj_disable(dev) || it51xxx_i3cs_dynamic_addr_valid(dev)) { - LOG_INST_ERR(cfg->log, - "hj is disabled or dynamic address is already assigned"); - ret = -EINVAL; - goto out; - } - sys_write8(I3CS_EVENT_SELECT(EVT_HOT_JOIN), cfg->base + I3CS0C_CONTROL_0); - break; - case I3C_IBI_CONTROLLER_ROLE_REQUEST: - LOG_INST_ERR(cfg->log, "unsupported controller role request"); - ret = -ENOTSUP; - goto out; - default: - LOG_INST_ERR(cfg->log, "invalid ibi type(0x%x)", request->ibi_type); - ret = -EINVAL; - goto out; - } - - if (it51xxx_i3cs_wait_to_complete(dev) != 0) { - LOG_INST_WRN(cfg->log, "failed to issue ibi. maybe the controller is offline"); - sys_write8(I3CS_EVENT_SELECT(EVT_NORMAL_MODE), cfg->base + I3CS0C_CONTROL_0); - } -out: - k_mutex_unlock(&data->lock); - - return ret; -} -#endif /* CONFIG_I3C_USE_IBI */ - -static int it51xxx_i3cs_set_fifo_address(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - - if (sizeof(data->fifo.rx_data) <= 128 && sizeof(data->fifo.tx_data) <= 128) { - if (FIFO_ADDR_HB(((uint32_t)&data->fifo.tx_data)) != - FIFO_ADDR_HB(((uint32_t)&data->fifo.rx_data))) { - LOG_INST_ERR(cfg->log, - "the msb of tx and rx fifo address should be the same"); - return -EINVAL; - } - sys_write8(FIFO_ADDR_LB((uint32_t)&data->fifo.rx_data), - cfg->base + I3CS43_RX_FIFO_BASE_ADDR_LB); - sys_write8(FIFO_ADDR_LB((uint32_t)&data->fifo.tx_data), - cfg->base + I3CS42_TX_FIFO_BASE_ADDR_LB); - sys_write8(FIFO_ADDR_HB((uint32_t)&data->fifo.tx_data), - cfg->base + I3CS41_TX_RX_FIFO_BASE_ADDR_HB); - return 0; - } - - if (!rx_direct_mode_is_enabled(dev) || !tx_direct_mode_is_enabled(dev)) { - /* The tx and rx direct modes must be enabled simultaneously. */ - LOG_INST_ERR(cfg->log, "tx or rx fifo size is invalid for direct mode"); - return -EINVAL; - } - - LOG_INST_DBG(cfg->log, "direct mode is enabled"); - sys_write8(sys_read8(cfg->base + I3CS4D_CONTROL_REG_4) | I3CS_DIRECT_MODE_ENABLE, - cfg->base + I3CS4D_CONTROL_REG_4); - sys_write8(FIFO_ADDR_LB((uint32_t)&data->fifo.rx_data), - cfg->base + I3CS16_DIRECT_RX_FIFO_BASE_ADDR_LB); - sys_write8(FIFO_ADDR_HB((uint32_t)&data->fifo.rx_data), - cfg->base + I3CS17_DIRECT_RX_FIFO_BASE_ADDR_HB); - sys_write8(FIFO_ADDR_LB((uint32_t)&data->fifo.tx_data), - cfg->base + I3CS14_DIRECT_TX_FIFO_BASE_ADDR_LB); - sys_write8(FIFO_ADDR_HB((uint32_t)&data->fifo.tx_data), - cfg->base + I3CS15_DIRECT_TX_FIFO_BASE_ADDR_HB); - - return 0; -} - -static int it51xxx_i3cs_init(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - struct i3c_config_target *config_target = &data->config_target; - uint8_t reg_val; - int ret; - - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret != 0) { - LOG_INST_ERR(cfg->log, "failed to apply pinctrl, ret %d", ret); - return ret; - } - - /* set i3cs channel selection */ - sys_write8(cfg->io_channel, cfg->base + I3CS4D_CONTROL_REG_4); - LOG_INST_DBG(cfg->log, "select io channel %d", cfg->io_channel); - - /* set extern enable bit */ - if (cfg->extern_enable.bit_mask > 7) { - LOG_INST_ERR(cfg->log, "invalid bit mask %d for extern enable setting", - cfg->extern_enable.bit_mask); - return -EINVAL; - } - sys_write8(sys_read8(cfg->extern_enable.addr) | BIT(cfg->extern_enable.bit_mask), - cfg->extern_enable.addr); - - /* set static address */ - sys_write8(I3CS_TARGET_ADDRESS(config_target->static_addr), cfg->base + I3CS07_CONFIG_2); - - /* set msb(vendor info) of get device status ccc */ - sys_write8(cfg->vendor_info, cfg->base + I3CS0F_CONTROL_3); - - /* set pid, bcr and dcr */ - if (config_target->pid_random) { - sys_write8(sys_read8(cfg->base + I3CS05_CONFIG_1) | ID_RANDOM, - cfg->base + I3CS05_CONFIG_1); - sys_write8(BYTE_0(config_target->pid), cfg->base + I3CS6C_PRAT_NUMBER_0); - sys_write8(BYTE_1(config_target->pid), cfg->base + I3CS6D_PRAT_NUMBER_1); - sys_write8(BYTE_2(config_target->pid), cfg->base + I3CS6E_PRAT_NUMBER_2); - sys_write8(BYTE_3(config_target->pid), cfg->base + I3CS6F_PRAT_NUMBER_3); - LOG_INST_INF(cfg->log, "set pid random value: %#llx", config_target->pid); - } - if (I3C_BCR_DEVICE_ROLE(config_target->bcr) == I3C_BCR_DEVICE_ROLE_I3C_CONTROLLER_CAPABLE) { - LOG_INST_ERR(cfg->log, "i3cs doesn't support controller capability"); - return -ENOTSUP; - } - sys_write8(config_target->bcr, cfg->base + I3CS72_BCR); - sys_write8(config_target->dcr, cfg->base + I3CS71_DCR); - - LOG_INST_INF(cfg->log, "tx fifo size(%d), address(0x%x)", sizeof(data->fifo.tx_data), - (uint32_t)&data->fifo.tx_data); - LOG_INST_INF(cfg->log, "rx fifo size(%d), address(0x%x)", sizeof(data->fifo.rx_data), - (uint32_t)&data->fifo.rx_data); - - /* set tx and rx fifo size */ - for (uint8_t i = 0; i <= ARRAY_SIZE(fifo_size_table); i++) { - if (i == ARRAY_SIZE(fifo_size_table)) { - LOG_INST_ERR(cfg->log, "unknown rx fifo size %d", - sizeof(data->fifo.rx_data)); - return -ENOTSUP; - } - if (sizeof(data->fifo.rx_data) == fifo_size_table[i].fifo_size) { - sys_write8(FIELD_PREP(I3CS_RX_FIFO_SIZE_MASK, fifo_size_table[i].value), - cfg->base + I3CS7A_RX_FIFO_SIZE); - set_mwl_value(dev, sizeof(data->fifo.rx_data)); - break; - } - } - for (uint8_t i = 0; i <= ARRAY_SIZE(fifo_size_table); i++) { - if (i == ARRAY_SIZE(fifo_size_table)) { - LOG_INST_ERR(cfg->log, "unknown tx fifo size %d", - sizeof(data->fifo.tx_data)); - return -ENOTSUP; - } - if (sizeof(data->fifo.tx_data) == fifo_size_table[i].fifo_size) { - sys_write8(FIELD_PREP(I3CS_TX_FIFO_SIZE_MASK, fifo_size_table[i].value), - cfg->base + I3CS4A_TX_FIFO_SIZE); - set_mrl_value(dev, sizeof(data->fifo.tx_data)); - break; - } - } - - ret = it51xxx_i3cs_set_fifo_address(dev); - if (ret) { - return ret; - } - - if (tx_direct_mode_is_enabled(dev)) { - sys_write8(sys_read8(cfg->base + I3CS4D_CONTROL_REG_4) | - I3CS_DIRECT_MODE_AUTO_CLR_TX_CNT, - cfg->base + I3CS4D_CONTROL_REG_4); - } - -#ifdef CONFIG_I3C_USE_IBI - k_sem_init(&data->ibi_sync_sem, 0, 1); -#endif /*CONFIG_I3C_USE_IBI */ - - k_mutex_init(&data->lock); - - /* clear interrupt/errwarn status and enable interrupt */ - sys_write8(sys_read8(cfg->base + I3CS1C_ERROR_WARNING_REG_0), - cfg->base + I3CS1C_ERROR_WARNING_REG_0); - sys_write8(sys_read8(cfg->base + I3CS1D_ERROR_WARNING_REG_1), - cfg->base + I3CS1D_ERROR_WARNING_REG_1); - sys_write8(sys_read8(cfg->base + I3CS09_STATUS_1), cfg->base + I3CS09_STATUS_1); - reg_val = INT_STOP | INT_ERROR_WARNING; - sys_write8(reg_val, cfg->base + I3CS11_INTERRUPT_ENABLE_CTRL_0); - - cfg->irq_config_func(dev); - - return 0; -} - -static DEVICE_API(i3c, it51xxx_i3cs_api) = { - .target_tx_write = it51xxx_i3cs_target_tx_write, - .target_register = it51xxx_i3cs_target_register, - .target_unregister = it51xxx_i3cs_target_unregister, - -#ifdef CONFIG_I3C_USE_IBI - .ibi_raise = it51xxx_i3cs_target_ibi_raise, -#endif /* CONFIG_I3C_USE_IBI */ -}; - -static void it51xxx_i3cs_check_errwarn(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - uint8_t errwarn0_val, errwarn1_val; - - errwarn0_val = sys_read8(cfg->base + I3CS1C_ERROR_WARNING_REG_0); - errwarn1_val = sys_read8(cfg->base + I3CS1D_ERROR_WARNING_REG_1); - if (errwarn0_val & INVALID_START) { - LOG_INST_ERR(cfg->log, "isr: invalid start"); - } - if (errwarn0_val & CONTROLLER_TERMINATED) { - LOG_INST_WRN(cfg->log, - "isr: terminated by controller, flush the remaining %d bytes", - tx_byte_cnt_in_fifo(dev)); - sys_write8(sys_read8(cfg->base + I3CS2C_DATA_CTRL_0) | FLUSH_TX_FIFO, - cfg->base + I3CS2C_DATA_CTRL_0); - } - if (errwarn0_val & TX_FIFO_UNDERRUN) { - LOG_INST_ERR(cfg->log, "isr: the tx fifo is underrun"); - } - if (errwarn0_val & RX_FIFO_OVERRUN) { - LOG_INST_ERR(cfg->log, "isr: the rx fifo is overrun"); - } - if (errwarn1_val & S0_OR_S1_ERROR) { - LOG_INST_ERR(cfg->log, "isr: s0 or s1 error is detected"); - } - if (errwarn1_val & SDR_PARITY_ERROR) { - LOG_INST_ERR(cfg->log, "isr: sdr parity error"); - } - LOG_INST_DBG(cfg->log, "isr: error/warning is detected(0x%x, 0x%x)", errwarn0_val, - errwarn1_val); - - /* write 1 to clear the error and warning registers */ - sys_write8(errwarn0_val, cfg->base + I3CS1C_ERROR_WARNING_REG_0); - sys_write8(errwarn1_val, cfg->base + I3CS1D_ERROR_WARNING_REG_1); -} - -static inline void invoke_rx_cb(const struct device *dev, const bool ccc, uint8_t *buf, - const size_t buf_len) -{ - struct it51xxx_i3cs_data *data = dev->data; - const struct i3c_target_callbacks *target_cb = - data->target_config ? data->target_config->callbacks : NULL; - - if (!ccc) { - LOG_HEXDUMP_DBG(buf, buf_len, "isr: rx:"); -#ifdef CONFIG_I3C_TARGET_BUFFER_MODE - if (target_cb && target_cb->buf_write_received_cb) { - target_cb->buf_write_received_cb(data->target_config, buf, buf_len); - } -#endif /* CONFIG_I3C_TARGET_BUFFER_MODE */ - } else { - LOG_HEXDUMP_WRN(buf, buf_len, "isr: unhandled ccc:"); - } -} - -static void it51xxx_i3cs_process_rx_fifo(const struct device *dev, const bool ccc) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - uint16_t byte_count = rx_byte_cnt_in_fifo(dev); - - if (rx_direct_mode_is_enabled(dev)) { - uint8_t dfifo_status = sys_read8(cfg->base + I3CS4E_DIRECT_FIFO_STATUS); - - if (dfifo_status & I3CS_DIRECT_RX_DONE) { - sys_write8(I3CS_DIRECT_RX_DONE, cfg->base + I3CS4E_DIRECT_FIFO_STATUS); - } else { - LOG_INST_WRN(cfg->log, "isr: rx pending, but rx not completed"); - return; - } - invoke_rx_cb(dev, ccc, data->fifo.rx_data, byte_count); - } else { - uint8_t read_ptr, idx; - uint8_t rx_buf[sizeof(data->fifo.rx_data)]; - const size_t rx_fifo_sz = sizeof(data->fifo.rx_data); - - read_ptr = sys_read8(cfg->base + I3CS45_RX_FIFO_READ_PTR); - idx = read_ptr % rx_fifo_sz; - for (size_t i = 0; i < byte_count; i++) { - rx_buf[i] = - data->fifo.rx_data[(idx + i) >= rx_fifo_sz ? (idx + i) - rx_fifo_sz - : (idx + i)]; - } - sys_write8(read_ptr + byte_count, cfg->base + I3CS45_RX_FIFO_READ_PTR); - invoke_rx_cb(dev, ccc, rx_buf, byte_count); - } -} - -static void it51xxx_i3cs_process_tx_fifo(const struct device *dev, const bool ccc) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - const struct i3c_target_callbacks *target_cb = - data->target_config ? data->target_config->callbacks : NULL; - - if (tx_direct_mode_is_enabled(dev)) { - uint8_t dfifo_status = sys_read8(cfg->base + I3CS4E_DIRECT_FIFO_STATUS); - - if (dfifo_status & I3CS_DIRECT_TX_DONE) { - sys_write8(I3CS_DIRECT_TX_DONE, cfg->base + I3CS4E_DIRECT_FIFO_STATUS); - } else { - return; - } - } - - if (!ccc) { -#ifdef CONFIG_I3C_TARGET_BUFFER_MODE - if (target_cb && target_cb->buf_read_requested_cb) { - target_cb->buf_read_requested_cb(data->target_config, NULL, NULL, NULL); - } -#endif /* CONFIG_I3C_TARGET_BUFFER_MODE */ - } -} - -static void it51xxx_i3cs_isr(const struct device *dev) -{ - const struct it51xxx_i3cs_config *cfg = dev->config; - struct it51xxx_i3cs_data *data = dev->data; - const struct i3c_target_callbacks *target_cb = - data->target_config ? data->target_config->callbacks : NULL; - uint8_t int_status_1, int_status_2; - - int_status_1 = sys_read8(cfg->base + I3CS09_STATUS_1); - int_status_2 = sys_read8(cfg->base + I3CS0A_STATUS_2); - LOG_INST_DBG(cfg->log, "isr: interrupt status 0x%x 0x%x", int_status_1, int_status_2); - - if (int_status_1 & INT_DYN_ADDR_CHANGE) { - if (it51xxx_i3cs_dynamic_addr_valid(dev)) { - if (data->target_config) { - data->target_config->address = DYNAMIC_ADDRESS( - sys_read8(cfg->base + I3CS64_DYNAMIC_ADDRESS)); - } - LOG_INST_DBG(cfg->log, "dynamic address is assigned"); - } else { - if (data->target_config) { - data->target_config->address = 0; - } - LOG_INST_DBG(cfg->log, "dynamic address is reset"); - } - } - - if (int_status_1 & INT_ERROR_WARNING) { - it51xxx_i3cs_check_errwarn(dev); - } - - if (int_status_1 & INT_STOP) { - bool is_unhandled_ccc = - (!(int_status_1 & INT_ADDR_MATCHED) || (int_status_1 & INT_CCC)); - - if (int_status_1 & INT_RX_PENDING) { - it51xxx_i3cs_process_rx_fifo(dev, is_unhandled_ccc); - } else { - it51xxx_i3cs_process_tx_fifo(dev, is_unhandled_ccc); - } - - if (!is_unhandled_ccc) { - if (target_cb != NULL && target_cb->stop_cb) { - target_cb->stop_cb(data->target_config); - } - } - } - - switch (int_status_2 & EVENT_DETECT_MASK) { - case FIELD_PREP(EVENT_DETECT_MASK, REQUEST_NACK_EVT): - LOG_INST_ERR(cfg->log, "isr: nack is detected"); - break; - case FIELD_PREP(EVENT_DETECT_MASK, REQUEST_NOT_SENT): - LOG_INST_ERR(cfg->log, "isr: request is not sent yet"); - break; - case FIELD_PREP(EVENT_DETECT_MASK, REQUEST_ACK_EVT): - if (int_status_2 & INT_EVENT) { - LOG_INST_DBG(cfg->log, "isr: tir/hj is completed"); - } - break; - default: - break; - }; - - if (int_status_2 & EVENT_DETECT_MASK) { -#ifdef CONFIG_I3C_USE_IBI - k_sem_give(&data->ibi_sync_sem); -#endif /* CONFIG_I3C_USE_IBI */ - } - - if (int_status_2 & INT_TARGET_RST) { - LOG_INST_INF(cfg->log, "isr: target reset pattern is detected"); - } - - sys_write8(int_status_1, cfg->base + I3CS09_STATUS_1); - sys_write8(int_status_2, cfg->base + I3CS0A_STATUS_2); -} - -#define IT51XXX_I3CS_EXTERN_ENABLE(n) \ - { \ - .addr = DT_INST_PROP_BY_IDX(n, extern_enable, 0), \ - .bit_mask = DT_INST_PROP_BY_IDX(n, extern_enable, 1), \ - } - -#define IT51XXX_I3CS_INIT(n) \ - LOG_INSTANCE_REGISTER(DT_NODE_FULL_NAME_TOKEN(DT_DRV_INST(n)), n, \ - CONFIG_I3C_IT51XXX_LOG_LEVEL); \ - PINCTRL_DT_INST_DEFINE(n); \ - static void it51xxx_i3cs_config_func_##n(const struct device *dev) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), 0, it51xxx_i3cs_isr, DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - }; \ - static const struct it51xxx_i3cs_config i3c_config_##n = { \ - .base = DT_INST_REG_ADDR(n), \ - .irq_config_func = it51xxx_i3cs_config_func_##n, \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .io_channel = DT_INST_PROP(n, io_channel), \ - .extern_enable = IT51XXX_I3CS_EXTERN_ENABLE(n), \ - .vendor_info = DT_INST_PROP_OR(n, vendor_info_fields, 0x0), \ - LOG_INSTANCE_PTR_INIT(log, DT_NODE_FULL_NAME_TOKEN(DT_DRV_INST(n)), n)}; \ - static struct it51xxx_i3cs_data i3c_data_##n = { \ - .config_target.static_addr = DT_INST_PROP_OR(n, static_address, 0), \ - .config_target.pid = DT_INST_PROP_OR(n, pid_random_value, 0), \ - .config_target.pid_random = DT_INST_NODE_HAS_PROP(n, pid_random_value), \ - .config_target.bcr = DT_INST_PROP_OR(n, bcr, 0x0F), \ - .config_target.dcr = DT_INST_PROP_OR(n, dcr, 0), \ - .config_target.supported_hdr = false, \ - }; \ - DEVICE_DT_INST_DEFINE(n, it51xxx_i3cs_init, NULL, &i3c_data_##n, &i3c_config_##n, \ - POST_KERNEL, CONFIG_I3C_CONTROLLER_INIT_PRIORITY, \ - &it51xxx_i3cs_api); - -DT_INST_FOREACH_STATUS_OKAY(IT51XXX_I3CS_INIT) diff --git a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c index d5ab993593af1..a355bb9787877 100644 --- a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c +++ b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c @@ -738,11 +738,7 @@ static struct ieee802154_cc13xx_cc26xx_data ieee802154_cc13xx_cc26xx_data = { .bStrictLenFilter = 1 }, .frameTypes = { -#if defined(CONFIG_NET_L2_OPENTHREAD) - .bAcceptFt0Beacon = 1, -#else .bAcceptFt0Beacon = 0, -#endif .bAcceptFt1Data = 1, .bAcceptFt2Ack = 0, .bAcceptFt3MacCmd = 1, diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index 054c04ff60cd7..cab9dcd3cacee 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -23,7 +23,6 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT51XXX_KBD input_ite_it51xxx_kbd. zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8801_KBD input_ite_it8801_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8XXX2_KBD input_ite_it8xxx2_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_KBD_MATRIX input_kbd_matrix.c) -zephyr_library_sources_ifdef(CONFIG_INPUT_MODULINO_BUTTONS input_modulino_buttons.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NPCX_KBD input_npcx_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NUNCHUK input_nunchuk.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PAT912X input_pat912x.c) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index b8dc0890b5678..d23b1db9beddb 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -25,7 +25,6 @@ source "drivers/input/Kconfig.it51xxx" source "drivers/input/Kconfig.it8801" source "drivers/input/Kconfig.it8xxx2" source "drivers/input/Kconfig.kbd_matrix" -source "drivers/input/Kconfig.modulino" source "drivers/input/Kconfig.npcx" source "drivers/input/Kconfig.nunchuk" source "drivers/input/Kconfig.pat912x" diff --git a/drivers/input/Kconfig.modulino b/drivers/input/Kconfig.modulino deleted file mode 100644 index 95ae6fe4dfd2c..0000000000000 --- a/drivers/input/Kconfig.modulino +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config INPUT_MODULINO_BUTTONS - bool "Arduino Modulino buttons" - default y - depends on DT_HAS_ARDUINO_MODULINO_BUTTONS_ENABLED - select I2C - help - Enable driver Arduino Modulino Buttons. diff --git a/drivers/input/input_adc_keys.c b/drivers/input/input_adc_keys.c index be6cc714a8a78..d37d79bf0987c 100644 --- a/drivers/input/input_adc_keys.c +++ b/drivers/input/input_adc_keys.c @@ -23,7 +23,6 @@ struct adc_keys_code_config { }; struct adc_keys_key_state { - bool orig_state; bool last_state; bool curr_state; }; @@ -100,18 +99,7 @@ static inline void adc_keys_process(const struct device *dev) LOG_DBG("sample=%d mV, closest=%d mV, diff=%d mV", sample_mv, closest_mv, closest_diff); /* - * Update cached key states and init current states with false - */ - - for (uint8_t i = 0; i < cfg->key_cnt; i++) { - key_state = &cfg->key_state[i]; - - key_state->last_state = key_state->curr_state; - key_state->curr_state = false; - } - - /* - * Update current key states according to the closest key press threshold. + * Update cached key states according to the closest key press threshold. * * Note that multiple keys may have the same press threshold, which is * the mixed voltage that these keys are simultaneously pressed. @@ -131,20 +119,25 @@ static inline void adc_keys_process(const struct device *dev) } /* - * Report the key event if the key state changed for at least two continuous cycles. + * Report the key event if the key state has changed. */ for (uint8_t i = 0; i < cfg->key_cnt; i++) { key_state = &cfg->key_state[i]; key_code = cfg->key_code[i]; - if (key_state->orig_state != key_state->curr_state && - key_state->last_state == key_state->curr_state) { + if (key_state->last_state != key_state->curr_state) { LOG_DBG("Report event %s %d, code=%d", dev->name, key_state->curr_state, key_code); input_report_key(dev, key_code, key_state->curr_state, true, K_FOREVER); - key_state->orig_state = key_state->curr_state; + key_state->last_state = key_state->curr_state; } + + /* + * Reset the state so that it can be updated in the next + * iteration. + */ + key_state->curr_state = false; } } diff --git a/drivers/input/input_cap12xx.c b/drivers/input/input_cap12xx.c index b2a2003af719f..8b0a23130915f 100644 --- a/drivers/input/input_cap12xx.c +++ b/drivers/input/input_cap12xx.c @@ -10,23 +10,13 @@ #include #include #include -#include LOG_MODULE_REGISTER(cap12xx, CONFIG_INPUT_LOG_LEVEL); -#define REG_MAIN_CONTROL 0x00 -#define MAIN_CONTROL_GAIN_MASK GENMASK(7, 6) -#define MAIN_CONTROL_GAIN_SHIFT 6 - -#define CONTROL_INT 0x01 +#define REG_MAIN_CONTROL 0x00 +#define CONTROL_INT 0x01 #define REG_INPUT_STATUS 0x03 -#define REG_SENSITIVITY_CONTROL 0x1F -#define DELTA_SENSE_BITS 3 -#define DELTA_SENSE_SHIFT 4 -#define DELTA_SENSE_MASK GENMASK(6, 4) -#define DELTA_SENSE_MAX GENMASK(DELTA_SENSE_BITS - 1, 0) - #define REG_INTERRUPT_ENABLE 0x27 #define INTERRUPT_ENABLE 0xFF #define INTERRUPT_DISABLE 0x00 @@ -35,13 +25,6 @@ LOG_MODULE_REGISTER(cap12xx, CONFIG_INPUT_LOG_LEVEL); #define REPEAT_ENABLE 0xFF #define REPEAT_DISABLE 0x00 -#define REG_SIGNAL_GUARD_ENABLE 0x29 - -#define REG_CALIB_SENSITIVITY_CONFIG1 0x80 -#define REG_CALIB_SENSITIVITY_CONFIG2 0x81 -#define CALSENS_BITS 2 -#define NUM_CALSENS_PER_REG 4 - struct cap12xx_config { struct i2c_dt_spec i2c; const uint8_t input_channels; @@ -49,10 +32,6 @@ struct cap12xx_config { struct gpio_dt_spec *int_gpio; bool repeat; const uint16_t poll_interval_ms; - const uint8_t sensor_gain; - const uint8_t sensitivity_delta_sense; - const uint8_t *signal_guard; - const uint8_t *calib_sensitivity; }; struct cap12xx_data { @@ -66,11 +45,11 @@ struct cap12xx_data { static int cap12xx_clear_interrupt(const struct i2c_dt_spec *i2c) { uint8_t ctrl; - int ret; + int r; - ret = i2c_reg_read_byte_dt(i2c, REG_MAIN_CONTROL, &ctrl); - if (ret < 0) { - return ret; + r = i2c_reg_read_byte_dt(i2c, REG_MAIN_CONTROL, &ctrl); + if (r < 0) { + return r; } ctrl = ctrl & ~CONTROL_INT; @@ -84,65 +63,25 @@ static int cap12xx_enable_interrupt(const struct i2c_dt_spec *i2c, bool enable) return i2c_reg_write_byte_dt(i2c, REG_INTERRUPT_ENABLE, intr); } -static int cap12xx_set_sensor_gain(const struct i2c_dt_spec *i2c, uint8_t gain) -{ - uint8_t regval = gain << MAIN_CONTROL_GAIN_SHIFT; - - return i2c_reg_update_byte_dt(i2c, REG_MAIN_CONTROL, MAIN_CONTROL_GAIN_MASK, regval); -} - -static int cap12xx_set_sensitivity(const struct i2c_dt_spec *i2c, uint8_t sensitivity) -{ - uint8_t regval = sensitivity << DELTA_SENSE_SHIFT; - - return i2c_reg_update_byte_dt(i2c, REG_SENSITIVITY_CONTROL, DELTA_SENSE_MASK, regval); -} - -static int cap12xx_set_calsens(const struct i2c_dt_spec *i2c, const uint8_t *calsens, - uint8_t channels) -{ - int ret; - uint8_t regval; - - for (uint8_t i = 0; i < channels; i += NUM_CALSENS_PER_REG) { - regval = 0; - for (uint8_t j = 0; j < NUM_CALSENS_PER_REG && i + j < channels; j++) { - /* Convert the enumerated sensitivity to the corresponding register value */ - regval |= (ilog2(calsens[i + j]) << (CALSENS_BITS * j)); - } - if (i == 0) { - ret = i2c_reg_write_byte_dt(i2c, REG_CALIB_SENSITIVITY_CONFIG1, regval); - } else { - ret = i2c_reg_write_byte_dt(i2c, REG_CALIB_SENSITIVITY_CONFIG2, regval); - } - - if (ret) { - return ret; - } - } - - return 0; -} - static int cap12xx_process(const struct device *dev) { const struct cap12xx_config *config = dev->config; struct cap12xx_data *data = dev->data; - int ret; + int r; uint8_t input_state; /* * Clear INT bit to clear SENSOR INPUT STATUS bits. * Note that this is also required in polling mode. */ - ret = cap12xx_clear_interrupt(&config->i2c); + r = cap12xx_clear_interrupt(&config->i2c); - if (ret < 0) { - return ret; + if (r < 0) { + return r; } - ret = i2c_reg_read_byte_dt(&config->i2c, REG_INPUT_STATUS, &input_state); - if (ret < 0) { - return ret; + r = i2c_reg_read_byte_dt(&config->i2c, REG_INPUT_STATUS, &input_state); + if (r < 0) { + return r; } if (config->int_gpio == NULL) { @@ -190,8 +129,7 @@ static int cap12xx_init(const struct device *dev) { const struct cap12xx_config *config = dev->config; struct cap12xx_data *data = dev->data; - uint8_t guarded_channels = 0; - int ret; + int r; if (!device_is_ready(config->i2c.bus)) { LOG_ERR("I2C controller device not ready"); @@ -202,43 +140,13 @@ static int cap12xx_init(const struct device *dev) k_work_init(&data->work, cap12xx_work_handler); - for (uint8_t i = 0; i < config->input_channels; i++) { - if (config->signal_guard[i]) { - guarded_channels |= BIT(i); - } - } - ret = i2c_reg_write_byte_dt(&config->i2c, REG_SIGNAL_GUARD_ENABLE, guarded_channels); - if (ret < 0) { - LOG_ERR("Could not set guarded channels"); - return ret; - } - ret = cap12xx_set_calsens(&config->i2c, config->calib_sensitivity, config->input_channels); - if (ret < 0) { - LOG_ERR("Could not set calibration sensitivities"); - return ret; - } - /* Convert the enumerated gain to the corresponding register value */ - ret = cap12xx_set_sensor_gain(&config->i2c, ilog2(config->sensor_gain)); - if (ret < 0) { - LOG_ERR("Could not set analog gain"); - return ret; - } - /* Convert the enumerated sensitivity to the corresponding register value, - * which is in reverse order - */ - ret = cap12xx_set_sensitivity(&config->i2c, - DELTA_SENSE_MAX - ilog2(config->sensitivity_delta_sense)); - if (ret < 0) { - LOG_ERR("Could not set sensitivity"); - return ret; - } if (config->int_gpio == NULL) { LOG_DBG("cap12xx driver in polling mode"); k_timer_init(&data->poll_timer, cap12xx_timer_handler, NULL); - ret = cap12xx_enable_interrupt(&config->i2c, true); - if (ret < 0) { + r = cap12xx_enable_interrupt(&config->i2c, true); + if (r < 0) { LOG_ERR("Could not configure interrupt"); - return ret; + return r; } k_timer_start(&data->poll_timer, K_MSEC(config->poll_interval_ms), K_MSEC(config->poll_interval_ms)); @@ -250,50 +158,49 @@ static int cap12xx_init(const struct device *dev) return -ENODEV; } - ret = gpio_pin_configure_dt(config->int_gpio, GPIO_INPUT); - if (ret < 0) { + r = gpio_pin_configure_dt(config->int_gpio, GPIO_INPUT); + if (r < 0) { LOG_ERR("Could not configure interrupt GPIO pin"); - return ret; + return r; } - ret = gpio_pin_interrupt_configure_dt(config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); - if (ret < 0) { + r = gpio_pin_interrupt_configure_dt(config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); + if (r < 0) { LOG_ERR("Could not configure interrupt GPIO interrupt"); - return ret; + return r; } gpio_init_callback(&data->int_gpio_cb, cap12xx_isr_handler, BIT(config->int_gpio->pin)); - ret = gpio_add_callback_dt(config->int_gpio, &data->int_gpio_cb); - if (ret < 0) { + r = gpio_add_callback_dt(config->int_gpio, &data->int_gpio_cb); + if (r < 0) { LOG_ERR("Could not set gpio callback"); - return ret; + return r; } - ret = cap12xx_clear_interrupt(&config->i2c); - if (ret < 0) { + r = cap12xx_clear_interrupt(&config->i2c); + if (r < 0) { LOG_ERR("Could not clear interrupt"); - return ret; + return r; } - ret = cap12xx_enable_interrupt(&config->i2c, true); - if (ret < 0) { + r = cap12xx_enable_interrupt(&config->i2c, true); + if (r < 0) { LOG_ERR("Could not configure interrupt"); - return ret; + return r; } if (config->repeat) { - ret = i2c_reg_write_byte_dt(&config->i2c, REG_REPEAT_ENABLE, REPEAT_ENABLE); - if (ret < 0) { + r = i2c_reg_write_byte_dt(&config->i2c, REG_REPEAT_ENABLE, REPEAT_ENABLE); + if (r < 0) { LOG_ERR("Could not disable repeated interrupts"); - return ret; + return r; } LOG_DBG("cap12xx enabled repeated interrupts"); } else { - ret = i2c_reg_write_byte_dt(&config->i2c, REG_REPEAT_ENABLE, - REPEAT_DISABLE); - if (ret < 0) { + r = i2c_reg_write_byte_dt(&config->i2c, REG_REPEAT_ENABLE, REPEAT_DISABLE); + if (r < 0) { LOG_ERR("Could not enable repeated interrupts"); - return ret; + return r; } LOG_DBG("cap12xx disabled repeated interrupts"); } @@ -307,10 +214,6 @@ static int cap12xx_init(const struct device *dev) static struct gpio_dt_spec cap12xx_int_gpio_##index = \ GPIO_DT_SPEC_INST_GET(index, int_gpios);)) \ static const uint16_t cap12xx_input_codes_##index[] = DT_INST_PROP(index, input_codes); \ - static const uint8_t cap12xx_signal_guard_##index[] = \ - DT_INST_PROP(index, signal_guard); \ - static const uint8_t cap12xx_calib_sensitivity_##index[] = \ - DT_INST_PROP(index, calib_sensitivity); \ static const struct cap12xx_config cap12xx_config_##index = { \ .i2c = I2C_DT_SPEC_INST_GET(index), \ .input_channels = DT_INST_PROP_LEN(index, input_codes), \ @@ -318,11 +221,7 @@ static int cap12xx_init(const struct device *dev) IF_ENABLED(DT_INST_NODE_HAS_PROP(index, int_gpios), ( \ .int_gpio = &cap12xx_int_gpio_##index,)) \ .repeat = DT_INST_PROP(index, repeat), \ - .poll_interval_ms = DT_INST_PROP(index, poll_interval_ms), \ - .sensor_gain = DT_INST_PROP(index, sensor_gain), \ - .sensitivity_delta_sense = DT_INST_PROP(index, sensitivity_delta_sense), \ - .signal_guard = cap12xx_signal_guard_##index, \ - .calib_sensitivity = cap12xx_calib_sensitivity_##index}; \ + .poll_interval_ms = DT_INST_PROP_OR(index, poll_interval_ms, 10)}; \ static struct cap12xx_data cap12xx_data_##index; \ DEVICE_DT_INST_DEFINE(index, cap12xx_init, NULL, &cap12xx_data_##index, \ &cap12xx_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \ diff --git a/drivers/input/input_gt911.c b/drivers/input/input_gt911.c index 5c0a537c16fed..3b021032cf73e 100644 --- a/drivers/input/input_gt911.c +++ b/drivers/input/input_gt911.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, 2025 NXP + * Copyright (c) 2020 NXP * Copyright (c) 2020 Mark Olsson * Copyright (c) 2020 Teslabs Engineering S.L. * @@ -12,7 +12,6 @@ #include #include #include -#include #include LOG_MODULE_REGISTER(gt911, CONFIG_INPUT_LOG_LEVEL); @@ -65,9 +64,6 @@ struct gt911_data { /** Timer (polling mode). */ struct k_timer timer; #endif -#ifdef CONFIG_PM - struct pm_notifier pm_notifier_handle; -#endif }; /** gt911 point reg */ @@ -241,37 +237,6 @@ static bool gt911_verify_firmware(const uint8_t *firmware) (gt911_get_firmware_checksum(firmware) == firmware[REG_CONFIG_SIZE - 2U])); } -#if CONFIG_PM -static void gt911_pm_state_exit(const struct device *dev, enum pm_state state) -{ - switch (state) { - case PM_STATE_STANDBY: - /* Reconfigure the GPIO interrupt pin on exit from - * certain low power states as we might lose the GPIO state. - */ - const struct gt911_config *config = dev->config; - int r; - - r = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT); - if (r < 0) { - LOG_ERR("Could not configure interrupt GPIO pin"); - return; - } - -#ifdef CONFIG_INPUT_GT911_INTERRUPT - r = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); - if (r < 0) { - LOG_ERR("Could not configure interrupt GPIO interrupt."); - return; - } -#endif /* CONFIG_INPUT_GT911_INTERRUPT */ - break; - default: - break; - } -} -#endif /* CONFIG_PM */ - static int gt911_init(const struct device *dev) { const struct gt911_config *config = dev->config; @@ -425,31 +390,9 @@ static int gt911_init(const struct device *dev) K_MSEC(CONFIG_INPUT_GT911_PERIOD_MS)); #endif -#if CONFIG_PM - /* We need to reconfigure the interrupt GPIO when waking up from - * certain low power modes. - */ - pm_notifier_register(&data->pm_notifier_handle); -#endif return 0; } -#if CONFIG_PM -#define GT911_PM_NOTIFIER_FUNCS(n) \ -static void gt911_##n##_pm_state_exit(enum pm_state state) \ -{ \ - gt911_pm_state_exit(DEVICE_DT_INST_GET(n), state); \ -} - -#define GT911_PM_NOTIFIER(n) \ - .pm_notifier_handle = { \ - .state_exit = gt911_##n##_pm_state_exit, \ - }, -#else -#define GT911_PM_NOTIFIER_FUNCS(n) -#define GT911_PM_NOTIFIER(n) -#endif /* CONFIG_PM */ - #define GT911_INIT(index) \ static const struct gt911_config gt911_config_##index = { \ .bus = I2C_DT_SPEC_INST_GET(index), \ @@ -457,10 +400,7 @@ static void gt911_##n##_pm_state_exit(enum pm_state state) .int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \ .alt_addr = DT_INST_PROP_OR(index, alt_addr, 0), \ }; \ - GT911_PM_NOTIFIER_FUNCS(index) \ - static struct gt911_data gt911_data_##index = { \ - GT911_PM_NOTIFIER(index) \ - }; \ + static struct gt911_data gt911_data_##index; \ DEVICE_DT_INST_DEFINE(index, gt911_init, NULL, >911_data_##index, >911_config_##index, \ POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL); diff --git a/drivers/input/input_modulino_buttons.c b/drivers/input/input_modulino_buttons.c deleted file mode 100644 index d88aeff9c9cbb..0000000000000 --- a/drivers/input/input_modulino_buttons.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT arduino_modulino_buttons - -#include -#include -#include -#include -#include - -LOG_MODULE_REGISTER(modulino_buttons, CONFIG_INPUT_LOG_LEVEL); - -#define MODULINO_NUM_BUTTONS 3 - -struct modulino_buttons_config { - struct i2c_dt_spec bus; - uint32_t poll_period_ms; - uint32_t zephyr_code[MODULINO_NUM_BUTTONS]; -}; - -struct modulino_buttons_data { - const struct device *dev; - struct k_work_delayable poll_work; - uint8_t prev_state[MODULINO_NUM_BUTTONS]; -}; - -static void modulino_buttons_handler(struct k_work *work) -{ - struct k_work_delayable *dwork = k_work_delayable_from_work(work); - struct modulino_buttons_data *data = CONTAINER_OF( - dwork, struct modulino_buttons_data, poll_work); - const struct device *dev = data->dev; - const struct modulino_buttons_config *cfg = dev->config; - int ret; - uint8_t buf[MODULINO_NUM_BUTTONS + 1]; - - ret = i2c_read_dt(&cfg->bus, buf, sizeof(buf)); - if (ret < 0) { - LOG_ERR("i2c read error: %d", ret); - goto out; - } - - for (uint8_t i = 0; i < MODULINO_NUM_BUTTONS; i++) { - uint8_t state = buf[i + 1]; - - if (data->prev_state[i] != state) { - input_report_key(dev, cfg->zephyr_code[i], state, true, K_FOREVER); - } - } - - memcpy(data->prev_state, &buf[1], sizeof(data->prev_state)); - -out: - k_work_reschedule(dwork, K_MSEC(cfg->poll_period_ms)); -} - -static int modulino_buttons_init(const struct device *dev) -{ - const struct modulino_buttons_config *cfg = dev->config; - struct modulino_buttons_data *data = dev->data; - - data->dev = dev; - - if (!i2c_is_ready_dt(&cfg->bus)) { - LOG_ERR("Bus device is not ready"); - return -ENODEV; - } - - k_work_init_delayable(&data->poll_work, modulino_buttons_handler); - k_work_reschedule(&data->poll_work, K_MSEC(cfg->poll_period_ms)); - - return 0; -} - -#define MODULINO_BUTTONS_INIT(inst) \ - BUILD_ASSERT(DT_INST_PROP_LEN(inst, zephyr_codes) == MODULINO_NUM_BUTTONS, \ - "zephyr,codes must specify three key codes"); \ - \ - static const struct modulino_buttons_config modulino_buttons_cfg_##inst = { \ - .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ - .poll_period_ms = DT_INST_PROP(inst, poll_period_ms), \ - .zephyr_code = DT_INST_PROP(inst, zephyr_codes), \ - }; \ - \ - static struct modulino_buttons_data modulino_buttons_data_##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, modulino_buttons_init, NULL, \ - &modulino_buttons_data_##inst, \ - &modulino_buttons_cfg_##inst, \ - POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL); - - -DT_INST_FOREACH_STATUS_OKAY(MODULINO_BUTTONS_INIT) diff --git a/drivers/input/input_realtek_rts5912_kbd.c b/drivers/input/input_realtek_rts5912_kbd.c index b4065de7c33c1..ba8314a2932c1 100644 --- a/drivers/input/input_realtek_rts5912_kbd.c +++ b/drivers/input/input_realtek_rts5912_kbd.c @@ -173,8 +173,6 @@ static int rts5912_kbd_init(const struct device *dev) /* W/C interrupt status of KSI pins */ rts5912_intc_isr_clear(dev); - NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); - /* Interrupts are enabled in the thread function */ IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rts5912_kbd_isr, DEVICE_DT_INST_GET(0), 0); diff --git a/drivers/interrupt_controller/intc_ite_it8xxx2.c b/drivers/interrupt_controller/intc_ite_it8xxx2.c index f31cd7533c465..62e7d87275d4c 100644 --- a/drivers/interrupt_controller/intc_ite_it8xxx2.c +++ b/drivers/interrupt_controller/intc_ite_it8xxx2.c @@ -266,8 +266,8 @@ void soc_interrupt_init(void) wdt_regs->EWDKEYR = 0; /* Spin and wait for reboot */ - while (1) { - } + while (1) + ; } else { /* Disable ETWD hardware reset */ gctrl_regs->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN; diff --git a/drivers/interrupt_controller/intc_nxp_pint.c b/drivers/interrupt_controller/intc_nxp_pint.c index 72b6916e01b26..2a11fd7ad4584 100644 --- a/drivers/interrupt_controller/intc_nxp_pint.c +++ b/drivers/interrupt_controller/intc_nxp_pint.c @@ -10,11 +10,9 @@ #include #include #include -#include #include - -#include "intc_nxp_pint/power.h" +#include #define DT_DRV_COMPAT nxp_pint @@ -96,8 +94,14 @@ int nxp_pint_pin_enable(uint8_t pin, enum nxp_pint_trigger trigger, bool wake) * driver handles the IRQ */ PINT_PinInterruptConfig(pint_base, slot, trigger, NULL); - nxp_pint_pin_deep_sleep_irq(pint_irq_cfg[slot].irq, wake); - +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + if (wake) { + EnableDeepSleepIRQ(pint_irq_cfg[slot].irq); + } else { + DisableDeepSleepIRQ(pint_irq_cfg[slot].irq); + irq_enable(pint_irq_cfg[slot].irq); + } +#endif return 0; } @@ -181,24 +185,6 @@ static void nxp_pint_isr(uint8_t *slot) } } -static int intc_nxp_pm_action(const struct device *dev, enum pm_device_action action) -{ - switch (action) { - case PM_DEVICE_ACTION_RESUME: - break; - case PM_DEVICE_ACTION_SUSPEND: - break; - case PM_DEVICE_ACTION_TURN_OFF: - break; - case PM_DEVICE_ACTION_TURN_ON: - PINT_Init(pint_base); - break; - default: - return -ENOTSUP; - } - - return 0; -} /* Defines PINT IRQ handler for a given irq index */ #define NXP_PINT_IRQ(idx, node_id) \ @@ -219,12 +205,10 @@ static int intc_nxp_pint_init(const struct device *dev) * parameter. */ LISTIFY(8, NXP_PINT_IRQ, (;), DT_INST(0, DT_DRV_COMPAT)); + PINT_Init(pint_base); memset(pin_pint_id, NO_PINT_ID, ARRAY_SIZE(pin_pint_id)); - - return pm_device_driver_init(dev, intc_nxp_pm_action); + return 0; } -PM_DEVICE_DT_INST_DEFINE(0, intc_nxp_pm_action); - -DEVICE_DT_INST_DEFINE(0, intc_nxp_pint_init, PM_DEVICE_DT_INST_GET(0), NULL, NULL, +DEVICE_DT_INST_DEFINE(0, intc_nxp_pint_init, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL); diff --git a/drivers/interrupt_controller/intc_nxp_pint/power.h b/drivers/interrupt_controller/intc_nxp_pint/power.h deleted file mode 100644 index 0be24a5c6d070..0000000000000 --- a/drivers/interrupt_controller/intc_nxp_pint/power.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * This file abstracts operations exposed by fsl_power.h from NXP HAL, - * for cases when that driver can't be compiled (DSP targets). - */ - -#ifndef __ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_NXP_PINT_POWER_H__ -#define __ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_NXP_PINT_POWER_H__ - -#include -#include -#include - -#if defined(FSL_FEATURE_SOC_PMC_COUNT) && FSL_FEATURE_SOC_PMC_COUNT > 0 -#include -#endif - -static inline void nxp_pint_pin_deep_sleep_irq(uint8_t irq, bool wake) -{ -#if (defined(FSL_FEATURE_SOC_PMC_COUNT) && FSL_FEATURE_SOC_PMC_COUNT > 0) && \ - !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - if (wake) { - EnableDeepSleepIRQ(irq); - } else { - DisableDeepSleepIRQ(irq); - irq_enable(irq); - } -#else - ARG_UNUSED(irq); - ARG_UNUSED(wake); -#endif -} - -#endif diff --git a/drivers/led/CMakeLists.txt b/drivers/led/CMakeLists.txt index 73a808d7d5a2a..14a26c601aa64 100644 --- a/drivers/led/CMakeLists.txt +++ b/drivers/led/CMakeLists.txt @@ -19,7 +19,6 @@ zephyr_library_sources_ifdef(CONFIG_LP3943 lp3943.c) zephyr_library_sources_ifdef(CONFIG_LP50XX lp50xx.c) zephyr_library_sources_ifdef(CONFIG_LP5562 lp5562.c) zephyr_library_sources_ifdef(CONFIG_LP5569 lp5569.c) -zephyr_library_sources_ifdef(CONFIG_MODULINO_BUTTONS_LEDS modulino_buttons_leds.c) zephyr_library_sources_ifdef(CONFIG_NCP5623 ncp5623.c) zephyr_library_sources_ifdef(CONFIG_PCA9633 pca9633.c) zephyr_library_sources_ifdef(CONFIG_TLC59108 tlc59108.c) diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index bac815242c390..720106576af7c 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -38,7 +38,6 @@ source "drivers/led/Kconfig.lp3943" source "drivers/led/Kconfig.lp50xx" source "drivers/led/Kconfig.lp5562" source "drivers/led/Kconfig.lp5569" -source "drivers/led/Kconfig.modulino" source "drivers/led/Kconfig.ncp5623" source "drivers/led/Kconfig.npm1300" source "drivers/led/Kconfig.pca9633" diff --git a/drivers/led/Kconfig.modulino b/drivers/led/Kconfig.modulino deleted file mode 100644 index c496e85c7d7e9..0000000000000 --- a/drivers/led/Kconfig.modulino +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config MODULINO_BUTTONS_LEDS - bool "Arduino Modulino buttons LEDs" - default y - depends on DT_HAS_ARDUINO_MODULINO_BUTTONS_LEDS_ENABLED - select I2C - help - Enable driver Arduino Modulino Buttons LEDs. diff --git a/drivers/led/ht16k33.c b/drivers/led/ht16k33.c index 788b46900d04e..af33651ae5931 100644 --- a/drivers/led/ht16k33.c +++ b/drivers/led/ht16k33.c @@ -21,6 +21,8 @@ LOG_MODULE_REGISTER(ht16k33, CONFIG_LED_LOG_LEVEL); +#include "led_context.h" + /* HT16K33 commands and options */ #define HT16K33_CMD_DISP_DATA_ADDR 0x00 @@ -59,8 +61,6 @@ LOG_MODULE_REGISTER(ht16k33, CONFIG_LED_LOG_LEVEL); #define HT16K33_KEYSCAN_COLS 13 #define HT16K33_KEYSCAN_DATA_SIZE 6 -#define HT16K33_MAX_PERIOD 2000U - struct ht16k33_cfg { struct i2c_dt_spec i2c; bool irq_enabled; @@ -71,6 +71,7 @@ struct ht16k33_cfg { struct ht16k33_data { const struct device *dev; + struct led_data dev_data; /* Shadow buffer for the display data RAM */ uint8_t buffer[HT16K33_DISP_DATA_SIZE]; #ifdef CONFIG_HT16K33_KEYSCAN @@ -94,11 +95,13 @@ static int ht16k33_led_blink(const struct device *dev, uint32_t led, ARG_UNUSED(led); const struct ht16k33_cfg *config = dev->config; + struct ht16k33_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint32_t period; uint8_t cmd; period = delay_on + delay_off; - if (period > HT16K33_MAX_PERIOD) { + if (period < dev_data->min_period || period > dev_data->max_period) { return -EINVAL; } @@ -127,10 +130,17 @@ static int ht16k33_led_set_brightness(const struct device *dev, uint32_t led, ARG_UNUSED(led); const struct ht16k33_cfg *config = dev->config; + struct ht16k33_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t dim; uint8_t cmd; - dim = (value * (HT16K33_DIMMING_LEVELS - 1)) / LED_BRIGTHNESS_MAX; + if (value < dev_data->min_brightness || + value > dev_data->max_brightness) { + return -EINVAL; + } + + dim = (value * (HT16K33_DIMMING_LEVELS - 1)) / dev_data->max_brightness; cmd = HT16K33_CMD_DIMMING_SET | dim; if (i2c_write_dt(&config->i2c, &cmd, sizeof(cmd))) { @@ -278,6 +288,7 @@ static int ht16k33_init(const struct device *dev) { const struct ht16k33_cfg *config = dev->config; struct ht16k33_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t cmd[1 + HT16K33_DISP_DATA_SIZE]; /* 1 byte command + data */ int err; @@ -290,6 +301,12 @@ static int ht16k33_init(const struct device *dev) memset(&data->buffer, 0, sizeof(data->buffer)); + /* Hardware specific limits */ + dev_data->min_period = 0U; + dev_data->max_period = 2000U; + dev_data->min_brightness = 0U; + dev_data->max_brightness = 100U; + /* System oscillator on */ cmd[0] = HT16K33_CMD_SYSTEM_SETUP | HT16K33_OPT_S; err = i2c_write_dt(&config->i2c, cmd, 1); diff --git a/drivers/led/is31fl3194.c b/drivers/led/is31fl3194.c index 5e9466ca13f67..649afa5556ac2 100644 --- a/drivers/led/is31fl3194.c +++ b/drivers/led/is31fl3194.c @@ -145,8 +145,12 @@ static int is31fl3194_set_brightness(const struct device *dev, uint32_t led, uin return -ENOTSUP; } + if (value > 100) { + return -EINVAL; + } + /* Rescale 0..100 to 0..255 */ - value = value * 255 / LED_BRIGTHNESS_MAX; + value = value * 255 / 100; ret = i2c_reg_write_byte_dt(&config->bus, led_channels[led], value); if (ret == 0) { @@ -162,6 +166,16 @@ static int is31fl3194_set_brightness(const struct device *dev, uint32_t led, uin return ret; } +static inline int is31fl3194_led_on(const struct device *dev, uint32_t led) +{ + return is31fl3194_set_brightness(dev, led, 100); +} + +static inline int is31fl3194_led_off(const struct device *dev, uint32_t led) +{ + return is31fl3194_set_brightness(dev, led, 0); +} + /* * Counts red, green, blue channels; returns true if color_id is valid * and no more than one channel maps to the same color @@ -301,6 +315,8 @@ static int is31fl3194_init(const struct device *dev) static DEVICE_API(led, is31fl3194_led_api) = { .set_brightness = is31fl3194_set_brightness, + .on = is31fl3194_led_on, + .off = is31fl3194_led_off, .get_info = is31fl3194_get_info, .set_color = is31fl3194_set_color, }; diff --git a/drivers/led/is31fl3216a.c b/drivers/led/is31fl3216a.c index cc391a6a48d8b..ff7a292af2b9b 100644 --- a/drivers/led/is31fl3216a.c +++ b/drivers/led/is31fl3216a.c @@ -62,7 +62,7 @@ static int is31fl3216a_update_pwm(const struct i2c_dt_spec *i2c) static uint8_t is31fl3216a_brightness_to_pwm(uint8_t brightness) { - return (0xFFU * brightness) / LED_BRIGTHNESS_MAX; + return (0xFFU * brightness) / 100; } static int is31fl3216a_led_write_channels(const struct device *dev, @@ -87,7 +87,7 @@ static int is31fl3216a_led_write_channels(const struct device *dev, i2c_buffer[0] = IS31FL3216A_REG_PWM_LAST - start_channel - (num_channels - 1); for (i = 0; i < num_channels; i++) { - if (buf[num_channels - i - 1] > LED_BRIGTHNESS_MAX) { + if (buf[num_channels - i - 1] > 100) { return -EINVAL; } i2c_buffer[i + 1] = is31fl3216a_brightness_to_pwm( @@ -111,7 +111,7 @@ static int is31fl3216a_led_set_brightness(const struct device *dev, int status; uint8_t pwm_value; - if (led > IS31FL3216A_MAX_LEDS - 1) { + if (led > IS31FL3216A_MAX_LEDS - 1 || value > 100) { return -EINVAL; } @@ -124,6 +124,16 @@ static int is31fl3216a_led_set_brightness(const struct device *dev, return is31fl3216a_update_pwm(&config->i2c); } +static int is31fl3216a_led_on(const struct device *dev, uint32_t led) +{ + return is31fl3216a_led_set_brightness(dev, led, 100); +} + +static int is31fl3216a_led_off(const struct device *dev, uint32_t led) +{ + return is31fl3216a_led_set_brightness(dev, led, 0); +} + static int is31fl3216a_init_registers(const struct i2c_dt_spec *i2c) { int i; @@ -214,6 +224,8 @@ static int is31fl3216a_init(const struct device *dev) static DEVICE_API(led, is31fl3216a_led_api) = { .set_brightness = is31fl3216a_led_set_brightness, + .on = is31fl3216a_led_on, + .off = is31fl3216a_led_off, .write_channels = is31fl3216a_led_write_channels }; diff --git a/drivers/led/is31fl3733.c b/drivers/led/is31fl3733.c index 82317e69dacfb..7d36af0867ef8 100644 --- a/drivers/led/is31fl3733.c +++ b/drivers/led/is31fl3733.c @@ -43,6 +43,8 @@ LOG_MODULE_REGISTER(is31fl3733, CONFIG_LED_LOG_LEVEL); #define IS31FL3733_MAX_LED (IS31FL3733_ROW_COUNT * IS31FL3733_COL_COUNT) /* Max brightness */ +#define IS31FL3733_MAX_BRIGHTNESS 100 + struct is31fl3733_config { struct i2c_dt_spec bus; struct gpio_dt_spec sdb; @@ -96,7 +98,7 @@ static int is31fl3733_led_set_brightness(const struct device *dev, uint32_t led, { const struct is31fl3733_config *config = dev->config; int ret; - uint8_t led_brightness = (uint8_t)(((uint32_t)value * 255) / LED_BRIGTHNESS_MAX); + uint8_t led_brightness = (uint8_t)(((uint32_t)value * 255) / 100); if (led >= IS31FL3733_MAX_LED) { return -EINVAL; @@ -111,6 +113,16 @@ static int is31fl3733_led_set_brightness(const struct device *dev, uint32_t led, return i2c_reg_write_byte_dt(&config->bus, led, led_brightness); } +static int is31fl3733_led_on(const struct device *dev, uint32_t led) +{ + return is31fl3733_led_set_brightness(dev, led, IS31FL3733_MAX_BRIGHTNESS); +} + +static int is31fl3733_led_off(const struct device *dev, uint32_t led) +{ + return is31fl3733_led_set_brightness(dev, led, 0); +} + static int is31fl3733_led_write_channels(const struct device *dev, uint32_t start_channel, uint32_t num_channels, const uint8_t *buf) { @@ -264,6 +276,8 @@ int is31fl3733_current_limit(const struct device *dev, uint8_t limit) } static DEVICE_API(led, is31fl3733_api) = { + .on = is31fl3733_led_on, + .off = is31fl3733_led_off, .set_brightness = is31fl3733_led_set_brightness, .write_channels = is31fl3733_led_write_channels, }; diff --git a/drivers/led/led_context.h b/drivers/led/led_context.h new file mode 100644 index 0000000000000..601d1c766a0be --- /dev/null +++ b/drivers/led/led_context.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Private LED driver APIs + */ + +#ifndef ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_ +#define ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Internal driver specific representation of an LED device + */ + +struct led_data { + /* Minimum acceptable LED blinking time period (in ms) */ + uint32_t min_period; + /* Maximum acceptable LED blinking time period (in ms) */ + uint32_t max_period; + /* Minimum acceptable LED brightness value */ + uint16_t min_brightness; + /* Maximum acceptable LED brightness value */ + uint16_t max_brightness; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_ */ diff --git a/drivers/led/led_dac.c b/drivers/led/led_dac.c index 54bc0e2d81e0c..e7fec3b5c4150 100644 --- a/drivers/led/led_dac.c +++ b/drivers/led/led_dac.c @@ -43,13 +43,37 @@ static int led_dac_set_brightness(const struct device *dev, uint32_t led, uint8_ value = pct > 0 ? config->leds[led].dac_min_brightness + (uint64_t)(config->leds[led].dac_max_brightness - config->leds[led].dac_min_brightness) * - pct / LED_BRIGTHNESS_MAX + pct / 100 : 0; return led_dac_set_raw(dev, led, value); } +static inline int led_dac_on(const struct device *dev, uint32_t led) +{ + const struct led_dac_config *config = dev->config; + + if (led >= config->num_leds) { + return -EINVAL; + } + + return led_dac_set_raw(dev, led, config->leds[led].dac_max_brightness); +} + +static inline int led_dac_off(const struct device *dev, uint32_t led) +{ + const struct led_dac_config *config = dev->config; + + if (led >= config->num_leds) { + return -EINVAL; + } + + return led_dac_set_raw(dev, led, 0); +} + static DEVICE_API(led, led_dac_api) = { + .on = led_dac_on, + .off = led_dac_off, .set_brightness = led_dac_set_brightness, }; diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c index 433dcca0dc51e..2243509c652c5 100644 --- a/drivers/led/led_gpio.c +++ b/drivers/led/led_gpio.c @@ -30,7 +30,7 @@ static int led_gpio_set_brightness(const struct device *dev, uint32_t led, uint8 const struct led_gpio_config *config = dev->config; const struct gpio_dt_spec *led_gpio; - if (led >= config->num_leds) { + if ((led >= config->num_leds) || (value > 100)) { return -EINVAL; } @@ -39,6 +39,16 @@ static int led_gpio_set_brightness(const struct device *dev, uint32_t led, uint8 return gpio_pin_set_dt(led_gpio, value > 0); } +static int led_gpio_on(const struct device *dev, uint32_t led) +{ + return led_gpio_set_brightness(dev, led, 100); +} + +static int led_gpio_off(const struct device *dev, uint32_t led) +{ + return led_gpio_set_brightness(dev, led, 0); +} + static int led_gpio_init(const struct device *dev) { const struct led_gpio_config *config = dev->config; @@ -68,6 +78,8 @@ static int led_gpio_init(const struct device *dev) } static DEVICE_API(led, led_gpio_api) = { + .on = led_gpio_on, + .off = led_gpio_off, .set_brightness = led_gpio_set_brightness, }; diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index b35e28a792872..6dd818d073f74 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -58,14 +58,24 @@ static int led_pwm_set_brightness(const struct device *dev, const struct led_pwm_config *config = dev->config; const struct pwm_dt_spec *dt_led; - if (led >= config->num_leds) { + if (led >= config->num_leds || value > 100) { return -EINVAL; } dt_led = &config->led[led]; return pwm_set_pulse_dt(&config->led[led], - (uint32_t) ((uint64_t) dt_led->period * value / LED_BRIGTHNESS_MAX)); + (uint32_t) ((uint64_t) dt_led->period * value / 100)); +} + +static int led_pwm_on(const struct device *dev, uint32_t led) +{ + return led_pwm_set_brightness(dev, led, 100); +} + +static int led_pwm_off(const struct device *dev, uint32_t led) +{ + return led_pwm_set_brightness(dev, led, 0); } static int led_pwm_init(const struct device *dev) @@ -115,6 +125,8 @@ static int led_pwm_pm_action(const struct device *dev, #endif /* CONFIG_PM_DEVICE */ static DEVICE_API(led, led_pwm_api) = { + .on = led_pwm_on, + .off = led_pwm_off, .blink = led_pwm_blink, .set_brightness = led_pwm_set_brightness, }; diff --git a/drivers/led/led_shell.c b/drivers/led/led_shell.c index 6d6c7dfc2147d..65db93c67562c 100644 --- a/drivers/led/led_shell.c +++ b/drivers/led/led_shell.c @@ -164,7 +164,7 @@ static int cmd_set_brightness(const struct shell *sh, argv[arg_idx_value]); return -EINVAL; } - if (value > LED_BRIGTHNESS_MAX) { + if (value > 100) { shell_error(sh, "Invalid LED brightness value %lu (max 100)", value); return -EINVAL; diff --git a/drivers/led/lp3943.c b/drivers/led/lp3943.c index c9959a9ab50a9..dae655e68e78e 100644 --- a/drivers/led/lp3943.c +++ b/drivers/led/lp3943.c @@ -28,6 +28,8 @@ #include LOG_MODULE_REGISTER(lp3943); +#include "led_context.h" + /* LP3943 Registers */ #define LP3943_INPUT_1 0x00 #define LP3943_INPUT_2 0x01 @@ -42,8 +44,6 @@ LOG_MODULE_REGISTER(lp3943); #define LP3943_MASK 0x03 -#define LP3943_MAX_PERIOD 1600U - enum lp3943_modes { LP3943_OFF, LP3943_ON, @@ -55,6 +55,10 @@ struct lp3943_config { struct i2c_dt_spec bus; }; +struct lp3943_data { + struct led_data dev_data; +}; + static int lp3943_get_led_reg(uint32_t *led, uint8_t *reg) { switch (*led) { @@ -122,12 +126,15 @@ static int lp3943_led_blink(const struct device *dev, uint32_t led, uint32_t delay_on, uint32_t delay_off) { const struct lp3943_config *config = dev->config; + struct lp3943_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; int ret; uint16_t period; uint8_t reg, val, mode; period = delay_on + delay_off; - if (period > LP3943_MAX_PERIOD) { + + if (period < dev_data->min_period || period > dev_data->max_period) { return -EINVAL; } @@ -144,7 +151,7 @@ static int lp3943_led_blink(const struct device *dev, uint32_t led, reg = LP3943_PSC1; } - val = period * 255U / LP3943_MAX_PERIOD; + val = (period * 255U) / dev_data->max_period; if (i2c_reg_write_byte_dt(&config->bus, reg, val)) { LOG_ERR("LED write failed"); return -EIO; @@ -162,9 +169,16 @@ static int lp3943_led_set_brightness(const struct device *dev, uint32_t led, uint8_t value) { const struct lp3943_config *config = dev->config; + struct lp3943_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; int ret; uint8_t reg, val, mode; + if (value < dev_data->min_brightness || + value > dev_data->max_brightness) { + return -EINVAL; + } + /* Use DIM0 for LEDs 0 to 7 and DIM1 for LEDs 8 to 15 */ if (led < 8) { mode = LP3943_DIM0; @@ -178,7 +192,7 @@ static int lp3943_led_set_brightness(const struct device *dev, uint32_t led, reg = LP3943_PWM1; } - val = (value * 255U) / LED_BRIGTHNESS_MAX; + val = (value * 255U) / dev_data->max_brightness; if (i2c_reg_write_byte_dt(&config->bus, reg, val)) { LOG_ERR("LED write failed"); return -EIO; @@ -238,15 +252,25 @@ static inline int lp3943_led_off(const struct device *dev, uint32_t led) static int lp3943_led_init(const struct device *dev) { const struct lp3943_config *config = dev->config; + struct lp3943_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; if (!device_is_ready(config->bus.bus)) { LOG_ERR("I2C device not ready"); return -ENODEV; } + /* Hardware specific limits */ + dev_data->min_period = 0U; + dev_data->max_period = 1600U; + dev_data->min_brightness = 0U; + dev_data->max_brightness = 100U; + return 0; } +static struct lp3943_data lp3943_led_data; + static const struct lp3943_config lp3943_led_config = { .bus = I2C_DT_SPEC_INST_GET(0), }; @@ -258,6 +282,6 @@ static DEVICE_API(led, lp3943_led_api) = { .off = lp3943_led_off, }; -DEVICE_DT_INST_DEFINE(0, &lp3943_led_init, NULL, NULL, +DEVICE_DT_INST_DEFINE(0, &lp3943_led_init, NULL, &lp3943_led_data, &lp3943_led_config, POST_KERNEL, CONFIG_LED_INIT_PRIORITY, &lp3943_led_api); diff --git a/drivers/led/lp50xx.c b/drivers/led/lp50xx.c index 2d6bb904b37d0..bd1fd11b529e7 100644 --- a/drivers/led/lp50xx.c +++ b/drivers/led/lp50xx.c @@ -23,6 +23,8 @@ #include LOG_MODULE_REGISTER(lp50xx, CONFIG_LED_LOG_LEVEL); +#define LP50XX_MAX_BRIGHTNESS 100U + /* * Number of supported RGB led modules per chipset. * @@ -124,12 +126,28 @@ static int lp50xx_set_brightness(const struct device *dev, return -ENODEV; } + if (value > LP50XX_MAX_BRIGHTNESS) { + LOG_ERR("%s: brightness value out of bounds: val=%d, max=%d", + dev->name, value, LP50XX_MAX_BRIGHTNESS); + return -EINVAL; + } + buf[0] = LP50XX_LED0_BRIGHTNESS(config->num_modules) + led_info->index; - buf[1] = (value * 0xff) / LED_BRIGTHNESS_MAX; + buf[1] = (value * 0xff) / 100; return i2c_write_dt(&config->bus, buf, sizeof(buf)); } +static int lp50xx_on(const struct device *dev, uint32_t led) +{ + return lp50xx_set_brightness(dev, led, 100); +} + +static int lp50xx_off(const struct device *dev, uint32_t led) +{ + return lp50xx_set_brightness(dev, led, 0); +} + static int lp50xx_set_color(const struct device *dev, uint32_t led, uint8_t num_colors, const uint8_t *color) { @@ -334,6 +352,8 @@ static int lp50xx_pm_action(const struct device *dev, #endif /* CONFIG_PM_DEVICE */ static DEVICE_API(led, lp50xx_led_api) = { + .on = lp50xx_on, + .off = lp50xx_off, .get_info = lp50xx_get_info, .set_brightness = lp50xx_set_brightness, .set_color = lp50xx_set_color, diff --git a/drivers/led/lp5562.c b/drivers/led/lp5562.c index ff75cf2e8fb00..773e6966ec9a9 100644 --- a/drivers/led/lp5562.c +++ b/drivers/led/lp5562.c @@ -41,6 +41,8 @@ #include LOG_MODULE_REGISTER(lp5562); +#include "led_context.h" + /* Registers */ #define LP5562_ENABLE 0x00 #define LP5562_OP_MODE 0x01 @@ -77,6 +79,10 @@ LOG_MODULE_REGISTER(lp5562); */ #define LP5562_MIN_BLINK_PERIOD 1 +/* Brightness limits in percent */ +#define LP5562_MIN_BRIGHTNESS 0 +#define LP5562_MAX_BRIGHTNESS 100 + /* Output current limits in 0.1 mA */ #define LP5562_MIN_CURRENT_SETTING 0 #define LP5562_MAX_CURRENT_SETTING 255 @@ -168,6 +174,10 @@ struct lp5562_config { struct gpio_dt_spec enable_gpio; }; +struct lp5562_data { + struct led_data dev_data; +}; + /* * @brief Get the register for the given LED channel used to directly write a * brightness value instead of using the execution engines. @@ -274,8 +284,8 @@ static int lp5562_get_engine_reg_shift(enum lp5562_led_sources engine, * @param prescale Pointer to the prescale value. * @param step_time Pointer to the step_time value. */ -static void lp5562_ms_to_prescale_and_step(uint32_t ms, uint8_t *prescale, - uint8_t *step_time) +static void lp5562_ms_to_prescale_and_step(struct led_data *data, uint32_t ms, + uint8_t *prescale, uint8_t *step_time) { /* * One step with the prescaler set to 0 takes 0.49ms. The max value for @@ -599,9 +609,16 @@ static int lp5562_program_set_brightness(const struct device *dev, uint8_t command_index, uint8_t brightness) { + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t val; - val = (brightness * 0xFF) / LED_BRIGTHNESS_MAX; + if ((brightness < dev_data->min_brightness) || + (brightness > dev_data->max_brightness)) { + return -EINVAL; + } + + val = (brightness * 0xFF) / dev_data->max_brightness; return lp5562_program_command(dev, engine, command_index, LP5562_PROG_COMMAND_SET_PWM, val); @@ -631,14 +648,17 @@ static int lp5562_program_ramp(const struct device *dev, uint8_t step_count, enum lp5562_engine_fade_dirs fade_dir) { + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t prescale, step_time; - if (time_per_step < LP5562_MIN_BLINK_PERIOD || - time_per_step > LP5562_MAX_BLINK_PERIOD) { + if ((time_per_step < dev_data->min_period) || + (time_per_step > dev_data->max_period)) { return -EINVAL; } - lp5562_ms_to_prescale_and_step(time_per_step, &prescale, &step_time); + lp5562_ms_to_prescale_and_step(dev_data, time_per_step, + &prescale, &step_time); return lp5562_program_command(dev, engine, command_index, LP5562_PROG_COMMAND_RAMP_TIME(prescale, step_time), @@ -748,6 +768,8 @@ static int lp5562_update_blinking_brightness(const struct device *dev, static int lp5562_led_blink(const struct device *dev, uint32_t led, uint32_t delay_on, uint32_t delay_off) { + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; int ret; enum lp5562_led_sources engine; uint8_t command_index = 0U; @@ -781,7 +803,7 @@ static int lp5562_led_blink(const struct device *dev, uint32_t led, } ret = lp5562_program_set_brightness(dev, engine, command_index, - LED_BRIGTHNESS_MAX); + dev_data->max_brightness); if (ret) { return ret; } @@ -792,7 +814,7 @@ static int lp5562_led_blink(const struct device *dev, uint32_t led, } ret = lp5562_program_set_brightness(dev, engine, ++command_index, - LED_BRIGTHNESS_MAX); + dev_data->min_brightness); if (ret) { return ret; } @@ -820,10 +842,17 @@ static int lp5562_led_set_brightness(const struct device *dev, uint32_t led, uint8_t value) { const struct lp5562_config *config = dev->config; + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; int ret; uint8_t val, reg; enum lp5562_led_sources current_source; + if ((value < dev_data->min_brightness) || + (value > dev_data->max_brightness)) { + return -EINVAL; + } + ret = lp5562_get_led_source(dev, led, ¤t_source); if (ret) { return ret; @@ -845,7 +874,7 @@ static int lp5562_led_set_brightness(const struct device *dev, uint32_t led, } } - val = (value * 0xFF) / LED_BRIGTHNESS_MAX; + val = (value * 0xFF) / dev_data->max_brightness; ret = lp5562_get_pwm_reg(led, ®); if (ret) { @@ -862,11 +891,17 @@ static int lp5562_led_set_brightness(const struct device *dev, uint32_t led, static inline int lp5562_led_on(const struct device *dev, uint32_t led) { - return lp5562_led_set_brightness(dev, led, LED_BRIGTHNESS_MAX); + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; + + return lp5562_led_set_brightness(dev, led, dev_data->max_brightness); } static inline int lp5562_led_off(const struct device *dev, uint32_t led) { + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; + int ret; enum lp5562_led_sources current_source; @@ -882,7 +917,7 @@ static inline int lp5562_led_off(const struct device *dev, uint32_t led) } } - return lp5562_led_set_brightness(dev, led, LED_BRIGTHNESS_MAX); + return lp5562_led_set_brightness(dev, led, dev_data->min_brightness); } static int lp5562_led_update_current(const struct device *dev) @@ -975,6 +1010,8 @@ static int lp5562_disable(const struct device *dev) static int lp5562_led_init(const struct device *dev) { const struct lp5562_config *config = dev->config; + struct lp5562_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; const struct gpio_dt_spec *enable_gpio = &config->enable_gpio; int ret; @@ -999,6 +1036,12 @@ static int lp5562_led_init(const struct device *dev) return ret; } + /* Hardware specific limits */ + dev_data->min_period = LP5562_MIN_BLINK_PERIOD; + dev_data->max_period = LP5562_MAX_BLINK_PERIOD; + dev_data->min_brightness = LP5562_MIN_BRIGHTNESS; + dev_data->max_brightness = LP5562_MAX_BRIGHTNESS; + ret = lp5562_led_update_current(dev); if (ret) { LOG_ERR("Setting current setting LP5562 LED chip failed."); @@ -1066,8 +1109,9 @@ static int lp5562_pm_action(const struct device *dev, enum pm_device_action acti \ PM_DEVICE_DT_INST_DEFINE(id, lp5562_pm_action); \ \ + struct lp5562_data lp5562_data_##id; \ DEVICE_DT_INST_DEFINE(id, &lp5562_led_init, PM_DEVICE_DT_INST_GET(id), \ - NULL, \ + &lp5562_data_##id, \ &lp5562_config_##id, POST_KERNEL, \ CONFIG_LED_INIT_PRIORITY, \ &lp5562_led_api); \ diff --git a/drivers/led/lp5569.c b/drivers/led/lp5569.c index ee115f8425c9c..d07f6452275e8 100644 --- a/drivers/led/lp5569.c +++ b/drivers/led/lp5569.c @@ -49,12 +49,12 @@ static int lp5569_led_set_brightness(const struct device *dev, uint32_t led, uin uint8_t val; int ret; - if (led >= LP5569_NUM_LEDS) { + if (led >= LP5569_NUM_LEDS || brightness > 100) { return -EINVAL; } /* Map 0-100 % to 0-255 pwm register value */ - val = brightness * 255 / LED_BRIGTHNESS_MAX; + val = brightness * 255 / 100; ret = i2c_reg_write_byte_dt(&config->bus, LP5569_LED0_PWM + led, val); if (ret < 0) { @@ -65,6 +65,18 @@ static int lp5569_led_set_brightness(const struct device *dev, uint32_t led, uin return 0; } +static inline int lp5569_led_on(const struct device *dev, uint32_t led) +{ + /* Set LED brightness to 100 % */ + return lp5569_led_set_brightness(dev, led, 100); +} + +static inline int lp5569_led_off(const struct device *dev, uint32_t led) +{ + /* Set LED brightness to 0 % */ + return lp5569_led_set_brightness(dev, led, 0); +} + static int lp5569_write_channels(const struct device *dev, uint32_t start_channel, uint32_t num_channels, const uint8_t *buf) { @@ -173,6 +185,8 @@ static int lp5569_pm_action(const struct device *dev, enum pm_device_action acti static DEVICE_API(led, lp5569_led_api) = { .set_brightness = lp5569_led_set_brightness, + .on = lp5569_led_on, + .off = lp5569_led_off, .write_channels = lp5569_write_channels, }; diff --git a/drivers/led/modulino_buttons_leds.c b/drivers/led/modulino_buttons_leds.c deleted file mode 100644 index 488443f507cef..0000000000000 --- a/drivers/led/modulino_buttons_leds.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT arduino_modulino_buttons_leds - -#include -#include -#include -#include -#include - -LOG_MODULE_REGISTER(modulino_buttons_leds, CONFIG_LED_LOG_LEVEL); - -#define MODULINO_BUTTONS_NUM_LEDS 3 - -struct modulino_buttons_leds_config { - struct i2c_dt_spec bus; -}; - -struct modulino_buttons_leds_data { - uint8_t buf[MODULINO_BUTTONS_NUM_LEDS]; -}; - -static int modulino_buttons_leds_set(const struct device *dev, - uint32_t led, bool value) -{ - const struct modulino_buttons_leds_config *cfg = dev->config; - struct modulino_buttons_leds_data *data = dev->data; - int ret; - - if (led >= MODULINO_BUTTONS_NUM_LEDS) { - return -EINVAL; - } - - data->buf[led] = value ? 1 : 0; - - ret = i2c_write_dt(&cfg->bus, data->buf, sizeof(data->buf)); - if (ret < 0) { - LOG_ERR("i2c write error: %d", ret); - return ret; - } - - return 0; -} - -static int modulino_buttons_leds_on(const struct device *dev, uint32_t led) -{ - return modulino_buttons_leds_set(dev, led, true); -} - -static int modulino_buttons_leds_off(const struct device *dev, uint32_t led) -{ - return modulino_buttons_leds_set(dev, led, false); -} - -static int modulino_buttons_leds_set_brightness(const struct device *dev, - uint32_t led, uint8_t value) -{ - return modulino_buttons_leds_set(dev, led, value > 0); -} - -static int modulino_buttons_leds_init(const struct device *dev) -{ - const struct modulino_buttons_leds_config *cfg = dev->config; - struct modulino_buttons_leds_data *data = dev->data; - int ret; - - if (!i2c_is_ready_dt(&cfg->bus)) { - LOG_ERR("Bus device is not ready"); - return -ENODEV; - } - - /* Reset to all LEDs off */ - ret = i2c_write_dt(&cfg->bus, data->buf, sizeof(data->buf)); - if (ret < 0) { - LOG_ERR("i2c write error: %d", ret); - return ret; - } - - return 0; -} - -static DEVICE_API(led, modulino_buttons_leds_api) = { - .on = modulino_buttons_leds_on, - .off = modulino_buttons_leds_off, - .set_brightness = modulino_buttons_leds_set_brightness, -}; - -#define MODULINO_BUTTONS_INIT(inst) \ - static const struct modulino_buttons_leds_config \ - modulino_buttons_leds_cfg_##inst = { \ - .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ - }; \ - \ - static struct modulino_buttons_leds_data modulino_buttons_leds_data_##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, modulino_buttons_leds_init, NULL, \ - &modulino_buttons_leds_data_##inst, \ - &modulino_buttons_leds_cfg_##inst, \ - POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \ - &modulino_buttons_leds_api); - - -DT_INST_FOREACH_STATUS_OKAY(MODULINO_BUTTONS_INIT) diff --git a/drivers/led/ncp5623.c b/drivers/led/ncp5623.c index 663ebacba2aef..996fad2fd121c 100644 --- a/drivers/led/ncp5623.c +++ b/drivers/led/ncp5623.c @@ -100,12 +100,16 @@ static int ncp5623_set_brightness(const struct device *dev, uint32_t led, uint8_ return -ENODEV; } + if (value > 100) { + return -EINVAL; + } + if (led_info->num_colors != 1) { return -ENOTSUP; } /* Rescale 0..100 to 0..31 */ - value = value * NCP5623_MAX_BRIGHTNESS / LED_BRIGTHNESS_MAX; + value = value * NCP5623_MAX_BRIGHTNESS / 100; ret = i2c_reg_write_byte_dt(&config->bus, led_channels[led] | value, 0x70); @@ -116,6 +120,16 @@ static int ncp5623_set_brightness(const struct device *dev, uint32_t led, uint8_ return ret; } +static inline int ncp5623_led_on(const struct device *dev, uint32_t led) +{ + return ncp5623_set_brightness(dev, led, 100); +} + +static inline int ncp5623_led_off(const struct device *dev, uint32_t led) +{ + return ncp5623_set_brightness(dev, led, 0); +} + static int ncp5623_led_init(const struct device *dev) { const struct ncp5623_config *config = dev->config; @@ -172,6 +186,8 @@ static int ncp5623_led_init(const struct device *dev) static DEVICE_API(led, ncp5623_led_api) = { .set_brightness = ncp5623_set_brightness, + .on = ncp5623_led_on, + .off = ncp5623_led_off, .get_info = ncp5623_get_info, .set_color = ncp5623_set_color, }; diff --git a/drivers/led/pca9633.c b/drivers/led/pca9633.c index 60f9f20fba158..45356f327da54 100644 --- a/drivers/led/pca9633.c +++ b/drivers/led/pca9633.c @@ -20,6 +20,8 @@ #include LOG_MODULE_REGISTER(pca9633); +#include "led_context.h" + /* PCA9633 select registers determine the source that drives LED outputs */ #define PCA9633_LED_OFF 0x0 /* LED driver off */ #define PCA9633_LED_ON 0x1 /* LED driver on */ @@ -42,24 +44,27 @@ LOG_MODULE_REGISTER(pca9633); #define PCA9633_MASK 0x03 -#define PCA9633_MIN_PERIOD 41U -#define PCA9633_MAX_PERIOD 10667U - struct pca9633_config { struct i2c_dt_spec i2c; bool disable_allcall; }; +struct pca9633_data { + struct led_data dev_data; +}; + static int pca9633_led_blink(const struct device *dev, uint32_t led, uint32_t delay_on, uint32_t delay_off) { + struct pca9633_data *data = dev->data; const struct pca9633_config *config = dev->config; + struct led_data *dev_data = &data->dev_data; uint8_t gdc, gfrq; uint32_t period; period = delay_on + delay_off; - if (period < PCA9633_MIN_PERIOD || period > PCA9633_MAX_PERIOD) { + if (period < dev_data->min_period || period > dev_data->max_period) { return -EINVAL; } @@ -116,10 +121,17 @@ static int pca9633_led_set_brightness(const struct device *dev, uint32_t led, uint8_t value) { const struct pca9633_config *config = dev->config; + struct pca9633_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t val; + if (value < dev_data->min_brightness || + value > dev_data->max_brightness) { + return -EINVAL; + } + /* Set the LED brightness value */ - val = (value * 255U) / LED_BRIGTHNESS_MAX; + val = (value * 255U) / dev_data->max_brightness; if (i2c_reg_write_byte_dt(&config->i2c, PCA9633_PWM_BASE + led, val)) { @@ -174,6 +186,8 @@ static inline int pca9633_led_off(const struct device *dev, uint32_t led) static int pca9633_led_init(const struct device *dev) { const struct pca9633_config *config = dev->config; + struct pca9633_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; if (!device_is_ready(config->i2c.bus)) { LOG_ERR("I2C bus is not ready"); @@ -193,6 +207,11 @@ static int pca9633_led_init(const struct device *dev) LOG_ERR("LED reg update failed"); return -EIO; } + /* Hardware specific limits */ + dev_data->min_period = 41U; + dev_data->max_period = 10667U; + dev_data->min_brightness = 0U; + dev_data->max_brightness = 100U; return 0; } @@ -209,9 +228,10 @@ static DEVICE_API(led, pca9633_led_api) = { .i2c = I2C_DT_SPEC_INST_GET(id), \ .disable_allcall = DT_INST_PROP(id, disable_allcall), \ }; \ + static struct pca9633_data pca9633_##id##_data; \ \ DEVICE_DT_INST_DEFINE(id, &pca9633_led_init, NULL, \ - NULL, \ + &pca9633_##id##_data, \ &pca9633_##id##_cfg, POST_KERNEL, \ CONFIG_LED_INIT_PRIORITY, \ &pca9633_led_api); diff --git a/drivers/led/tlc59108.c b/drivers/led/tlc59108.c index 1d6f72caccb32..59f96df141218 100644 --- a/drivers/led/tlc59108.c +++ b/drivers/led/tlc59108.c @@ -20,6 +20,8 @@ LOG_MODULE_REGISTER(tlc59108, CONFIG_LED_LOG_LEVEL); +#include "led_context.h" + /* TLC59108 max supported LED id */ #define TLC59108_MAX_LED 7 @@ -46,13 +48,15 @@ LOG_MODULE_REGISTER(tlc59108, CONFIG_LED_LOG_LEVEL); #define TLC59108_MASK 0x03 -#define TLC59108_MIN_PERIOD 41U -#define TLC59108_MAX_PERIOD 10730U struct tlc59108_cfg { struct i2c_dt_spec i2c; }; +struct tlc59108_data { + struct led_data dev_data; +}; + static int tlc59108_set_ledout(const struct device *dev, uint32_t led, uint8_t val) { @@ -80,6 +84,8 @@ static int tlc59108_led_blink(const struct device *dev, uint32_t led, uint32_t delay_on, uint32_t delay_off) { const struct tlc59108_cfg *config = dev->config; + struct tlc59108_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t gdc, gfrq; uint32_t period; @@ -89,7 +95,7 @@ static int tlc59108_led_blink(const struct device *dev, uint32_t led, return -EINVAL; } - if (period < TLC59108_MIN_PERIOD || period > TLC59108_MAX_PERIOD) { + if (period < dev_data->min_period || period > dev_data->max_period) { return -EINVAL; } @@ -132,14 +138,21 @@ static int tlc59108_led_set_brightness(const struct device *dev, uint32_t led, uint8_t value) { const struct tlc59108_cfg *config = dev->config; + struct tlc59108_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; uint8_t val; if (led > TLC59108_MAX_LED) { return -EINVAL; } + if (value < dev_data->min_brightness || + value > dev_data->max_brightness) { + return -EINVAL; + } + /* Set the LED brightness value */ - val = (value * 255U) / LED_BRIGTHNESS_MAX; + val = (value * 255U) / dev_data->max_brightness; if (i2c_reg_write_byte_dt(&config->i2c, TLC59108_PWM_BASE + led, val)) { LOG_ERR("LED 0x%x reg write failed", TLC59108_PWM_BASE + led); return -EIO; @@ -172,6 +185,8 @@ static inline int tlc59108_led_off(const struct device *dev, uint32_t led) static int tlc59108_led_init(const struct device *dev) { const struct tlc59108_cfg *config = dev->config; + struct tlc59108_data *data = dev->data; + struct led_data *dev_data = &data->dev_data; if (!device_is_ready(config->i2c.bus)) { LOG_ERR("I2C bus device %s is not ready", config->i2c.bus->name); @@ -184,6 +199,12 @@ static int tlc59108_led_init(const struct device *dev) return -EIO; } + /* Hardware specific limits */ + dev_data->min_period = 41U; + dev_data->max_period = 10730U; + dev_data->min_brightness = 0U; + dev_data->max_brightness = 100U; + return 0; } @@ -198,9 +219,10 @@ static DEVICE_API(led, tlc59108_led_api) = { static const struct tlc59108_cfg tlc59108_##id##_cfg = { \ .i2c = I2C_DT_SPEC_INST_GET(id), \ }; \ + static struct tlc59108_data tlc59108_##id##_data; \ \ DEVICE_DT_INST_DEFINE(id, &tlc59108_led_init, NULL, \ - NULL, \ + &tlc59108_##id##_data, \ &tlc59108_##id##_cfg, POST_KERNEL, \ CONFIG_LED_INIT_PRIORITY, \ &tlc59108_led_api); diff --git a/drivers/led_strip/CMakeLists.txt b/drivers/led_strip/CMakeLists.txt index 9d7bf6ffcbee4..b293782e620fb 100644 --- a/drivers/led_strip/CMakeLists.txt +++ b/drivers/led_strip/CMakeLists.txt @@ -10,4 +10,3 @@ zephyr_library_sources_ifdef(CONFIG_WS2812_STRIP_I2S ws2812_i2s.c) zephyr_library_sources_ifdef(CONFIG_WS2812_STRIP_RPI_PICO_PIO ws2812_rpi_pico_pio.c) zephyr_library_sources_ifdef(CONFIG_TLC5971_STRIP tlc5971.c) zephyr_library_sources_ifdef(CONFIG_TLC59731_STRIP tlc59731.c) -zephyr_library_sources_ifdef(CONFIG_MODULINO_SMARTLEDS modulino_smartleds.c) diff --git a/drivers/led_strip/Kconfig b/drivers/led_strip/Kconfig index 2e0c54b1d0bea..3be80de47298c 100644 --- a/drivers/led_strip/Kconfig +++ b/drivers/led_strip/Kconfig @@ -37,6 +37,4 @@ source "drivers/led_strip/Kconfig.tlc5971" source "drivers/led_strip/Kconfig.tlc59731" -source "drivers/led_strip/Kconfig.modulino" - endif # LED_STRIP diff --git a/drivers/led_strip/Kconfig.modulino b/drivers/led_strip/Kconfig.modulino deleted file mode 100644 index e60f2ac2493f5..0000000000000 --- a/drivers/led_strip/Kconfig.modulino +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config MODULINO_SMARTLEDS - bool "Arduino Modulino smart LEDs" - default y - depends on DT_HAS_ARDUINO_MODULINO_SMARTLEDS_ENABLED - select I2C - help - Enable driver Arduino Modulino smart LEDs. diff --git a/drivers/led_strip/modulino_smartleds.c b/drivers/led_strip/modulino_smartleds.c deleted file mode 100644 index 220a88799e596..0000000000000 --- a/drivers/led_strip/modulino_smartleds.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2025 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT arduino_modulino_smartleds - -#include -#include -#include -#include -#include -#include - -LOG_MODULE_REGISTER(modulino_smartleds, CONFIG_LED_STRIP_LOG_LEVEL); - -#define MODULINO_SMARTLEDS_NUM_LEDS 8 - -/* This is a strip of LC8822 driven by the microcontroller on the Modulino - * board, the start frame is sent automatically, the rest uses the LC8822 - * protocol: - * - 4x "1" marker bits - * - 5x brightness bits - * - 3x bytes for B, G, R - */ - -#define MODULINO_SMARTLEDS_MARKER (0xe0 << 24) -#define MODULINO_SMARTLEDS_FULL_BRIGHTNESS (0x1f << 24) - -struct modulino_smartleds_config { - struct i2c_dt_spec bus; -}; - -struct modulino_smartleds_data { - uint32_t buf[MODULINO_SMARTLEDS_NUM_LEDS]; -}; - -static int modulino_smartleds_update_rgb(const struct device *dev, - struct led_rgb *pixels, - size_t count) -{ - const struct modulino_smartleds_config *cfg = dev->config; - struct modulino_smartleds_data *data = dev->data; - int ret; - - if (count > MODULINO_SMARTLEDS_NUM_LEDS) { - return -EINVAL; - } - - for (uint8_t i = 0; i < count; i++) { - data->buf[i] = sys_cpu_to_be32( - MODULINO_SMARTLEDS_MARKER | - MODULINO_SMARTLEDS_FULL_BRIGHTNESS | - (pixels[i].b << 16) | - (pixels[i].g << 8) | - pixels[i].r); - } - - ret = i2c_write_dt(&cfg->bus, (uint8_t *)data->buf, sizeof(data->buf)); - if (ret < 0) { - LOG_ERR("i2c write error: %d", ret); - return ret; - } - - return 0; -} - -static size_t modulino_smartleds_length(const struct device *dev) -{ - return MODULINO_SMARTLEDS_NUM_LEDS; -} - -static int modulino_smartleds_init(const struct device *dev) -{ - const struct modulino_smartleds_config *cfg = dev->config; - struct modulino_smartleds_data *data = dev->data; - int ret; - - if (!i2c_is_ready_dt(&cfg->bus)) { - LOG_ERR("Bus device is not ready"); - return -ENODEV; - } - - for (uint8_t i = 0; i < ARRAY_SIZE(data->buf); i++) { - data->buf[i] = sys_cpu_to_be32(MODULINO_SMARTLEDS_MARKER); - } - - /* Reset to all LEDs off */ - ret = i2c_write_dt(&cfg->bus, (uint8_t *)data->buf, sizeof(data->buf)); - if (ret < 0) { - LOG_ERR("i2c write error: %d", ret); - return ret; - } - - return 0; -} - -static DEVICE_API(led_strip, modulino_smartleds_api) = { - .update_rgb = modulino_smartleds_update_rgb, - .length = modulino_smartleds_length, -}; - -#define MODULINO_SMARTLEDS_INIT(inst) \ - static const struct modulino_smartleds_config \ - modulino_smartleds_cfg_##inst = { \ - .bus = I2C_DT_SPEC_INST_GET(inst), \ - }; \ - \ - static struct modulino_smartleds_data modulino_smartleds_data_##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, modulino_smartleds_init, NULL, \ - &modulino_smartleds_data_##inst, \ - &modulino_smartleds_cfg_##inst, \ - POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY, \ - &modulino_smartleds_api); - - -DT_INST_FOREACH_STATUS_OKAY(MODULINO_SMARTLEDS_INIT) diff --git a/drivers/mbox/mbox_esp32.c b/drivers/mbox/mbox_esp32.c index bbdb64dd65900..39bb2c9fa3543 100644 --- a/drivers/mbox/mbox_esp32.c +++ b/drivers/mbox/mbox_esp32.c @@ -75,8 +75,8 @@ IRAM_ATTR static void esp32_mbox_isr(const struct device *dev) /* first of all take the ownership of the shared memory */ while (!atomic_cas(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL, - dev_data->this_core_id)) { - } + dev_data->this_core_id)) + ; if (dev_data->cb) { /* For ESP32 soft mbox driver, the message parameter of the callback holds @@ -224,8 +224,8 @@ static int esp32_mbox_init(const struct device *dev) LOG_DBG("Waiting CPU0 to sync"); while (!atomic_cas(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL, - data->this_core_id)) { - } + data->this_core_id)) + ; atomic_set(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL); diff --git a/drivers/mbox/mbox_nrf_vevif_task_tx.c b/drivers/mbox/mbox_nrf_vevif_task_tx.c index 76da4aa357f99..3d553d4b48415 100644 --- a/drivers/mbox/mbox_nrf_vevif_task_tx.c +++ b/drivers/mbox/mbox_nrf_vevif_task_tx.c @@ -5,14 +5,12 @@ #define DT_DRV_COMPAT nordic_nrf_vevif_task_tx -#include #include #include #include #define TASKS_IDX_MAX NRF_VPR_TASKS_TRIGGER_MAX -#define VEVIF_RETRIGGER_DELAY_USEC 12 struct mbox_vevif_task_tx_conf { NRF_VPR_Type *vpr; @@ -41,12 +39,6 @@ static int vevif_task_tx_send(const struct device *dev, uint32_t id, const struc nrfy_vpr_task_trigger(config->vpr, nrfy_vpr_trigger_task_get(id)); -#ifdef CONFIG_SOC_NRF54H20 - k_busy_wait(VEVIF_RETRIGGER_DELAY_USEC); - - nrfy_vpr_task_trigger(config->vpr, nrfy_vpr_trigger_task_get(id)); -#endif /* CONFIG_SOC_NRF54H20 */ - return 0; } diff --git a/drivers/mdio/mdio_esp32.c b/drivers/mdio/mdio_esp32.c index 7dd8995b65456..9079d49e7415d 100644 --- a/drivers/mdio/mdio_esp32.c +++ b/drivers/mdio/mdio_esp32.c @@ -147,10 +147,9 @@ static int mdio_esp32_initialize(const struct device *dev) #if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios) emac_hal_init(&dev_data->hal, NULL, NULL, NULL); emac_hal_iomux_init_rmii(); - BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 0 || - DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 || + BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 || DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17, - "Only GPIO0/16/17 are allowed as a GPIO REF_CLK source!"); + "Only GPIO16/17 are allowed as a GPIO REF_CLK source!"); int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios); emac_hal_iomux_rmii_clk_output(ref_clk_gpio); diff --git a/drivers/memc/CMakeLists.txt b/drivers/memc/CMakeLists.txt index c1ec964e42787..ab1702584bc82 100644 --- a/drivers/memc/CMakeLists.txt +++ b/drivers/memc/CMakeLists.txt @@ -2,30 +2,31 @@ zephyr_library() -zephyr_library_sources_ifdef(CONFIG_MEMC_HIFIVE_UNMATCHED_DRAM sifive_ddr.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MAX32_HPB memc_max32_hpb.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6404L memc_mcux_flexspi_aps6404l.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6408L memc_mcux_flexspi_aps6408l.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_IS66WVQ8M4 memc_mcux_flexspi_is66wvq8m4.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_S27KS0641 memc_mcux_flexspi_s27ks0641.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_STM32 memc_stm32.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c) +zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld) +zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_NOR_PSRAM memc_stm32_nor_psram.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM memc_stm32_xspi_psram.c) +zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM SECTIONS memc_stm32_xspi_psram.ld) + +zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c) zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_W956A8MBYA memc_mcux_flexspi_w956a8mbya.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_S27KS0641 memc_mcux_flexspi_s27ks0641.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6408L memc_mcux_flexspi_aps6408l.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6404L memc_mcux_flexspi_aps6404l.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_IS66WVQ8M4 memc_mcux_flexspi_is66wvq8m4.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_RENESAS_RA_SDRAM memc_renesas_ra_sdram.c) + +zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c) + +zephyr_library_sources_ifdef(CONFIG_MEMC_HIFIVE_UNMATCHED_DRAM sifive_ddr.c) + if((DEFINED CONFIG_FLASH_MCUX_FLEXSPI_XIP) AND (DEFINED CONFIG_FLASH)) zephyr_code_relocate(FILES memc_mcux_flexspi.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) endif() -zephyr_library_sources_ifdef(CONFIG_MEMC_MSPI_APS6404L memc_mspi_aps6404l.c) -zephyr_library_include_directories_ifdef(CONFIG_MEMC_MSPI_APS6404L ${ZEPHYR_BASE}/drivers/mspi) +zephyr_library_sources_ifdef(CONFIG_MEMC_NXP_S32_QSPI memc_nxp_s32_qspi.c) +zephyr_library_sources_ifdef(CONFIG_MEMC_SMARTBOND memc_smartbond_nor_psram.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_NXP_S32_QSPI memc_nxp_s32_qspi.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_RENESAS_RA_SDRAM memc_renesas_ra_sdram.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_SILABS_SIWX91X_QSPI memc_silabs_siwx91x_qspi.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_SMARTBOND memc_smartbond_nor_psram.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_STM32 memc_stm32.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_NOR_PSRAM memc_stm32_nor_psram.c) -zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c) -zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld) - -zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM memc_stm32_xspi_psram.c) -zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM SECTIONS memc_stm32_xspi_psram.ld) +zephyr_library_sources_ifdef(CONFIG_MEMC_MSPI_APS6404L memc_mspi_aps6404l.c) +zephyr_library_include_directories_ifdef(CONFIG_MEMC_MSPI_APS6404L ${ZEPHYR_BASE}/drivers/mspi) diff --git a/drivers/memc/Kconfig b/drivers/memc/Kconfig index 07eb8103420e8..ce0eac6043064 100644 --- a/drivers/memc/Kconfig +++ b/drivers/memc/Kconfig @@ -18,18 +18,21 @@ config MEMC_INIT_PRIORITY help Memory controllers initialization priority. -# zephyr-keep-sorted-start -source "drivers/memc/Kconfig.max32_hpb" +source "drivers/memc/Kconfig.stm32" + source "drivers/memc/Kconfig.mcux" -source "drivers/memc/Kconfig.mspi" -source "drivers/memc/Kconfig.nxp_s32" -source "drivers/memc/Kconfig.renesas_ra" + source "drivers/memc/Kconfig.sam" + source "drivers/memc/Kconfig.sifive" -source "drivers/memc/Kconfig.siwx91x_qspi" + +source "drivers/memc/Kconfig.nxp_s32" + source "drivers/memc/Kconfig.smartbond" -source "drivers/memc/Kconfig.stm32" -# zephyr-keep-sorted-stop + +source "drivers/memc/Kconfig.mspi" + +source "drivers/memc/Kconfig.renesas_ra" module = MEMC module-str = memc diff --git a/drivers/memc/Kconfig.max32_hpb b/drivers/memc/Kconfig.max32_hpb deleted file mode 100644 index b1976eb2439be..0000000000000 --- a/drivers/memc/Kconfig.max32_hpb +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 Analog Devices, Inc -# SPDX-License-Identifier: Apache-2.0 - -config MEMC_MAX32_HPB - bool "MAX32 HyperBus" - default y - depends on DT_HAS_ADI_MAX32_HPB_ENABLED - select PINCTRL - help - Enable ADI MAX32 HyperBus controller. diff --git a/drivers/memc/Kconfig.mspi b/drivers/memc/Kconfig.mspi index 5f2950076259a..1e9783bd4de56 100644 --- a/drivers/memc/Kconfig.mspi +++ b/drivers/memc/Kconfig.mspi @@ -14,6 +14,6 @@ config MEMC_MSPI_APS6404L default y depends on DT_HAS_MSPI_APS6404L_ENABLED select MEMC_MSPI - select MSPI_AMBIQ_CONTROLLER if SOC_FAMILY_AMBIQ + select MSPI_AMBIQ_AP3 if SOC_SERIES_APOLLO3X endmenu diff --git a/drivers/memc/Kconfig.siwx91x_qspi b/drivers/memc/Kconfig.siwx91x_qspi deleted file mode 100644 index ffecef247a35b..0000000000000 --- a/drivers/memc/Kconfig.siwx91x_qspi +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2025 Silicon Laboratories Inc. -# SPDX-License-Identifier: Apache-2.0 - -config MEMC_SILABS_SIWX91X_QSPI - bool "Silabs SiWx91x QSPI memory controller" - default y - depends on DT_HAS_SILABS_SIWX91X_QSPI_MEMORY_ENABLED - select PINCTRL - help - Enable Silabs SiWx91x QSPI (Quad Serial Peripheral Interface) memory - controller. - - If you want to rely on the linker to place symbols in this memory - (using`zephyr_code_relocate() or Z_GENERIC_SECTION()), you have to - ensure this driver in initialized before KERNEL_INIT_PRIORITY_OBJECTS - (=30). In addition, this driver may depends on a clock. Then, you have - to ensure the clock will be started before this driver (see - CLOCK_CONTROL_INIT_PRIORITY) diff --git a/drivers/memc/memc_max32_hpb.c b/drivers/memc/memc_max32_hpb.c deleted file mode 100644 index 5afc9e35e9a03..0000000000000 --- a/drivers/memc/memc_max32_hpb.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2025 Analog Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include -#include - -#include - -LOG_MODULE_REGISTER(memc_max32_hpb, CONFIG_MEMC_LOG_LEVEL); - -#include -#include - -#define DT_DRV_COMPAT adi_max32_hpb - -struct memc_max32_hpb_config { - const struct device *clock; - const struct pinctrl_dev_config *pcfg; -}; - -struct memc_max32_hpb_mem_config { - uint8_t reg; - - mxc_hpb_mem_config_t config; -}; - -/* clang-format off */ - -#define MEM_CONFIG(n) \ - { \ - .reg = DT_REG_ADDR(n), \ - .config = {.device_type = DT_PROP(n, device_type), \ - .base_addr = DT_PROP(n, base_address), \ - .latency_cycle = DT_PROP_OR(n, latency_cycles, 1), \ - .write_cs_high = DT_PROP_OR(n, write_cs_high, 0), \ - .read_cs_high = DT_PROP_OR(n, read_cs_high, 0), \ - .write_cs_hold = DT_PROP_OR(n, write_cs_hold, 0), \ - .read_cs_hold = DT_PROP_OR(n, read_cs_hold, 0), \ - .write_cs_setup = DT_PROP_OR(n, write_cs_setup, 0), \ - .read_cs_setup = DT_PROP_OR(n, read_cs_setup, 0), \ - .fixed_latency = DT_PROP_OR(n, fixed_read_latency, 0), \ - COND_CODE_1(DT_NODE_HAS_PROP(n, config_regs), \ - (.cfg_reg_val = config_regs_##n, \ - .cfg_reg_val_len = ARRAY_SIZE(config_regs_##n)), ()) }, \ - } - -/* clang-format on */ - -#define CR_ENTRY(idx, n) \ - { \ - .addr = DT_PROP_BY_IDX(n, config_regs, idx), \ - .val = DT_PROP_BY_IDX(n, config_reg_vals, idx), \ - } - -#define MEM_CR_ENTRIES(n) \ - COND_CODE_1(DT_NODE_HAS_PROP(n, config_regs), ( \ - BUILD_ASSERT(DT_PROP_LEN(n, config_regs) == DT_PROP_LEN(n, config_reg_vals), \ - "The config-regs and config-reg-vals properties of adi,max32-hpb memory device" \ - " child nodes must be the same length"); \ - static const mxc_hpb_cfg_reg_val_t config_regs_##n[] = \ - { LISTIFY(DT_PROP_LEN(n, config_regs), CR_ENTRY, (,), n) }; \ - ), ()) - -/** memory device configuration(s). */ -DT_INST_FOREACH_CHILD(0, MEM_CR_ENTRIES) - -/* clang-format off */ - -static const struct memc_max32_hpb_mem_config mem_configs[] = { - DT_INST_FOREACH_CHILD_SEP(0, MEM_CONFIG, (,))}; - -#define CLOCK_CFG(node_id, prop, idx) \ - {.bus = DT_CLOCKS_CELL_BY_IDX(node_id, idx, offset), \ - .bit = DT_CLOCKS_CELL_BY_IDX(node_id, idx, bit)} - -static const struct max32_perclk perclks[] = { - DT_INST_FOREACH_PROP_ELEM_SEP(0, clocks, CLOCK_CFG, (,))}; - -/* clang-format on */ -static int memc_max32_hpb_init(const struct device *dev) -{ - const struct memc_max32_hpb_config *config = dev->config; - - int r; - const mxc_hpb_mem_config_t *mem0 = NULL, *mem1 = NULL; - - if (!device_is_ready(config->clock)) { - LOG_ERR("clock control device not ready"); - return -ENODEV; - } - - for (size_t i = 0; i < ARRAY_SIZE(perclks); i++) { - r = clock_control_on(config->clock, (clock_control_subsys_t)&perclks[i]); - if (r < 0) { - LOG_ERR("Could not initialize HPB clock (%d)", r); - return r; - } - } - - for (size_t i = 0; i < ARRAY_SIZE(mem_configs); i++) { - if (mem_configs[i].reg == 0) { - mem0 = &mem_configs[i].config; - } else if (mem_configs[i].reg == 1) { - mem1 = &mem_configs[i].config; - } - } - - /* configure pinmux */ - r = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (r < 0) { - LOG_ERR("HPB pinctrl setup failed (%d)", r); - return r; - } - - r = MXC_HPB_Init(mem0, mem1); - if (r < 0) { - LOG_ERR("HPB init failed (%d)", r); - return r; - } - - COND_CODE_1(DT_INST_PROP(0, enable_emcc), (MXC_EMCC_Enable()), (MXC_EMCC_Disable())); - - return 0; -} - -PINCTRL_DT_INST_DEFINE(0); - -static const struct memc_max32_hpb_config config = { - .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)), - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), -}; - -DEVICE_DT_INST_DEFINE(0, memc_max32_hpb_init, NULL, NULL, &config, POST_KERNEL, - CONFIG_MEMC_INIT_PRIORITY, NULL); diff --git a/drivers/memc/memc_mspi_aps6404l.c b/drivers/memc/memc_mspi_aps6404l.c index b3db096fa4f9e..a3bf64cb45006 100644 --- a/drivers/memc/memc_mspi_aps6404l.c +++ b/drivers/memc/memc_mspi_aps6404l.c @@ -82,7 +82,6 @@ static int memc_mspi_aps6404l_command_write(const struct device *psram, uint8_t data->trans.async = false; data->trans.xfer_mode = MSPI_PIO; data->trans.tx_dummy = 0; - data->trans.rx_dummy = data->dev_cfg.rx_dummy; data->trans.cmd_length = 1; data->trans.addr_length = 0; data->trans.hold_ce = false; @@ -119,7 +118,6 @@ static int memc_mspi_aps6404l_command_read(const struct device *psram, uint8_t c data->trans.async = false; data->trans.xfer_mode = MSPI_PIO; - data->trans.tx_dummy = data->dev_cfg.tx_dummy; data->trans.rx_dummy = 0; data->trans.cmd_length = 1; data->trans.addr_length = 3; @@ -395,8 +393,8 @@ static int memc_mspi_aps6404l_init(const struct device *psram) .write_cmd = APS6404L_WRITE, \ .cmd_length = 1, \ .addr_length = 3, \ - .mem_boundary = 1024, \ - .time_to_break = 8, \ + .mem_boundary = 1024, \ + .time_to_break = 8, \ } #define MSPI_DEVICE_CONFIG_QUAD(n) \ @@ -415,21 +413,28 @@ static int memc_mspi_aps6404l_init(const struct device *psram) .write_cmd = APS6404L_QUAD_WRITE, \ .cmd_length = 1, \ .addr_length = 3, \ - .mem_boundary = 1024, \ - .time_to_break = 4, \ + .mem_boundary = 1024, \ + .time_to_break = 4, \ } +#if CONFIG_SOC_FAMILY_AMBIQ #define MSPI_TIMING_CONFIG(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_TIMING_CONFIG(n)), ({})) \ - -#define MSPI_TIMING_CONFIG_MASK(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_TIMING_CONFIG_MASK(n)), (MSPI_TIMING_PARAM_DUMMY)) \ - -#define MSPI_PORT(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \ - (MSPI_AMBIQ_PORT(n)), (0)) \ + { \ + .ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \ + .ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \ + .bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \ + .bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \ + .bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \ + .ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \ + .ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \ + .ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \ + } +#define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask) +#else +#define MSPI_TIMING_CONFIG(n) {} +#define MSPI_TIMING_CONFIG_MASK(n) MSPI_TIMING_PARAM_DUMMY +#define MSPI_PORT(n) 0 +#endif #define MEMC_MSPI_APS6404L(n) \ static const struct memc_mspi_aps6404l_config \ diff --git a/drivers/memc/memc_silabs_siwx91x_qspi.c b/drivers/memc/memc_silabs_siwx91x_qspi.c deleted file mode 100644 index b3aa6e99ffbd8..0000000000000 --- a/drivers/memc/memc_silabs_siwx91x_qspi.c +++ /dev/null @@ -1,122 +0,0 @@ -/* Copyright (c) 2025 Silicon Laboratories Inc. - * SPDX-License-Identifier: Apache-2.0 - */ -#define DT_DRV_COMPAT silabs_siwx91x_qspi_memory -#include -#include -#include - -#include -#include -#include - -#include "rsi_qspi_proto.h" -#include "sl_si91x_psram_handle.h" - -LOG_MODULE_REGISTER(siwx91x_memc, CONFIG_MEMC_LOG_LEVEL); - -struct siwx91x_memc_config { - qspi_reg_t *reg; - const struct device *clock_dev; - clock_control_subsys_t clock_subsys; - const struct pinctrl_dev_config *pincfg; -}; - -static int siwx91x_memc_init(const struct device *dev) -{ - const struct siwx91x_memc_config *config = dev->config; - int ret; - - /* Memory controller is automatically setup by the siwx91x bootloader, - * so we have to uninitialize it before to change the configuration - */ - ret = sl_si91x_psram_uninit(); - if (ret) { - return -EIO; - } - - ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); - if (ret) { - return -EIO; - } - if (config->clock_dev) { - ret = device_is_ready(config->clock_dev); - if (!ret) { - return -EINVAL; - } - ret = clock_control_on(config->clock_dev, config->clock_subsys); - if (ret && ret != -EALREADY && ret != -ENOSYS) { - return ret; - } - } - - ret = sl_si91x_psram_init(); - if (ret) { - LOG_ERR("sl_si91x_psram_init() returned %d", ret); - return -EIO; - } - - return 0; -} - -PINCTRL_DT_INST_DEFINE(0); -static const struct siwx91x_memc_config siwx91x_memc_config = { - .reg = (void *)DT_INST_REG_ADDR(0), - .clock_dev = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR(0)), - .clock_subsys = (void *)DT_INST_PHA_OR(0, clocks, clkid, NULL), - .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), -}; -/* Required to properly initialize ,deviceID */ -static const uint8_t devid[] = DT_INST_PROP(0, device_id); - -/* PSRAM_Device is directly referenced by sl_si91x_psram_init() */ -struct sl_psram_info_type_t PSRAM_Device = { - .deviceID.MFID = devid[0], - .deviceID.KGD = devid[1], - .deviceID.EID = { devid[2], devid[3], devid[4], devid[5], devid[6], devid[7] }, - /* FIXME: Currently, the Chip Select (.cs_no property) and the RAM start - * address are hard coded. The hardware also support Chip Select == 1, - * then RAM start address will be 0xb000000. - */ - .devDensity = DT_REG_SIZE(DT_INST_CHILD(0, psram_a000000)), - .normalReadMAXFrequency = DT_INST_PROP(0, normal_freq), - .fastReadMAXFrequency = DT_INST_PROP(0, fast_freq), - .rwType = QUAD_RW, - .defaultBurstWrapSize = 1024, - .toggleBurstWrapSize = 0, - .spi_config.spi_config_2.auto_mode = 1, - /* FIXME: user may want to customize these values */ - .spi_config.spi_config_1.read_cmd = 0xEB, - .spi_config.spi_config_3.wr_cmd = 0x38, - .spi_config.spi_config_1.extra_byte_mode = QUAD_MODE, - .spi_config.spi_config_1.dummy_mode = QUAD_MODE, - .spi_config.spi_config_1.addr_mode = QUAD_MODE, - .spi_config.spi_config_1.data_mode = QUAD_MODE, - .spi_config.spi_config_1.inst_mode = QUAD_MODE, - .spi_config.spi_config_3.wr_addr_mode = QUAD_MODE, - .spi_config.spi_config_3.wr_data_mode = QUAD_MODE, - .spi_config.spi_config_3.wr_inst_mode = QUAD_MODE, - .spi_config.spi_config_2.wrap_len_in_bytes = NO_WRAP, - .spi_config.spi_config_2.swap_en = 1, - .spi_config.spi_config_2.addr_width = 3, /* 24 bits */ - .spi_config.spi_config_2.cs_no = 0, - .spi_config.spi_config_4.secondary_csn = 1, - .spi_config.spi_config_2.neg_edge_sampling = 1, - .spi_config.spi_config_1.no_of_dummy_bytes = 3, - .spi_config.spi_config_1.dummy_W_or_R = DUMMY_READS, - .spi_config.spi_config_2.full_duplex = IGNORE_FULL_DUPLEX, - .spi_config.spi_config_2.qspi_clk_en = QSPI_FULL_TIME_CLK, - .spi_config.spi_config_1.flash_type = 0xf, - .spi_config.spi_config_3.dummys_4_jump = 1, - .spi_config.spi_config_4.valid_prot_bits = 4, - .spi_config.spi_config_1.d3d2_data = 0x03, - .spi_config.spi_config_5.d7_d4_data = 0x0f, -}; -/* PSRAMSecureSegments is directly referenced by sl_si91x_psram_init() */ -struct PSRAMSecureSegmentType PSRAMSecureSegments[MAX_SEC_SEGMENTS] = { - [0].segmentEnable = 1, - [0].lowerBoundary = 0x00000, - [0].higherBoundary = 0x0ffff, -}; -DEVICE_DT_INST_DEFINE(0, siwx91x_memc_init, NULL, NULL, &siwx91x_memc_config, - PRE_KERNEL_1, CONFIG_MEMC_INIT_PRIORITY, NULL); diff --git a/drivers/memc/memc_stm32_xspi_psram.c b/drivers/memc/memc_stm32_xspi_psram.c index a688610c7b8c1..676ec8c7f27fc 100644 --- a/drivers/memc/memc_stm32_xspi_psram.c +++ b/drivers/memc/memc_stm32_xspi_psram.c @@ -40,17 +40,12 @@ LOG_MODULE_REGISTER(memc_stm32_xspi_psram, CONFIG_MEMC_LOG_LEVEL); #define DUMMY_CLK_CYCLES_READ 6U #define DUMMY_CLK_CYCLES_WRITE 6U -#define STM32_XSPI_CLOCK_PRESCALER_MIN 0U -#define STM32_XSPI_CLOCK_PRESCALER_MAX 255U -#define STM32_XSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U)) - struct memc_stm32_xspi_psram_config { const struct pinctrl_dev_config *pcfg; const struct stm32_pclken pclken; const struct stm32_pclken pclken_ker; const struct stm32_pclken pclken_mgr; size_t memory_size; - uint32_t max_frequency; }; struct memc_stm32_xspi_psram_data { @@ -206,11 +201,11 @@ static int memc_stm32_xspi_psram_init(const struct device *dev) const struct memc_stm32_xspi_psram_config *dev_cfg = dev->config; struct memc_stm32_xspi_psram_data *dev_data = dev->data; XSPI_HandleTypeDef hxspi = dev_data->hxspi; + XSPI_TypeDef *xspi = hxspi.Instance; uint32_t ahb_clock_freq; XSPIM_CfgTypeDef cfg = {0}; XSPI_RegularCmdTypeDef cmd = {0}; XSPI_MemoryMappedTypeDef mem_mapped_cfg = {0}; - uint32_t prescaler = STM32_XSPI_CLOCK_PRESCALER_MIN; int ret; /* Signals configuration */ @@ -264,20 +259,6 @@ static int memc_stm32_xspi_psram_init(const struct device *dev) } #endif - for (; prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX; prescaler++) { - uint32_t clk = STM32_XSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler); - - if (clk <= dev_cfg->max_frequency) { - break; - } - } - - if (prescaler > STM32_XSPI_CLOCK_PRESCALER_MAX) { - LOG_ERR("XSPI could not find valid prescaler value"); - return -EINVAL; - } - - hxspi.Init.ClockPrescaler = prescaler; hxspi.Init.MemorySize = find_msb_set(dev_cfg->memory_size) - 2; if (HAL_XSPI_Init(&hxspi) != HAL_OK) { @@ -331,21 +312,14 @@ static int memc_stm32_xspi_psram_init(const struct device *dev) } mem_mapped_cfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE; - -#if defined(XSPI_CR_NOPREF) mem_mapped_cfg.NoPrefetchData = HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE; -#endif -#if defined(XSPI_CR_NOPREF_AXI) mem_mapped_cfg.NoPrefetchAXI = HAL_XSPI_AXI_PREFETCH_DISABLE; -#endif if (HAL_XSPI_MemoryMapped(&hxspi, &mem_mapped_cfg) != HAL_OK) { return -EIO; } -#if defined(XSPI_CR_NOPREF) - MODIFY_REG(hxspi.Instance->CR, XSPI_CR_NOPREF, HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE); -#endif + MODIFY_REG(xspi->CR, XSPI_CR_NOPREF, HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE); return 0; } @@ -364,8 +338,7 @@ static const struct memc_stm32_xspi_psram_config memc_stm32_xspi_cfg = { .pclken_mgr = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus), .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits)}, #endif - .memory_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ - .max_frequency = DT_INST_PROP(0, max_frequency), + .memory_size = DT_INST_REG_ADDR_BY_IDX(0, 1), }; static struct memc_stm32_xspi_psram_data memc_stm32_xspi_data = { @@ -381,6 +354,7 @@ static struct memc_stm32_xspi_psram_data memc_stm32_xspi_data = { .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE, .ClockMode = HAL_XSPI_CLOCK_MODE_0, .WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED, + .ClockPrescaler = 3U, .SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE, .DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE, .ChipSelectBoundary = HAL_XSPI_BONDARYOF_16KB, diff --git a/drivers/misc/CMakeLists.txt b/drivers/misc/CMakeLists.txt index 54ed29d934956..4b1e29a4901be 100644 --- a/drivers/misc/CMakeLists.txt +++ b/drivers/misc/CMakeLists.txt @@ -11,6 +11,4 @@ add_subdirectory_ifdef(CONFIG_DEVMUX devmux) add_subdirectory_ifdef(CONFIG_NORDIC_VPR_LAUNCHER nordic_vpr_launcher) add_subdirectory_ifdef(CONFIG_MCUX_FLEXIO mcux_flexio) add_subdirectory_ifdef(CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT renesas_ra_external_interrupt) -add_subdirectory_ifdef(CONFIG_NXP_RTXXX_DSP_CTRL nxp_rtxxx_dsp_ctrl) - add_subdirectory(coresight) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 5668434c43e65..e80b1650ccd31 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -16,6 +16,5 @@ source "drivers/misc/nordic_vpr_launcher/Kconfig" source "drivers/misc/mcux_flexio/Kconfig" source "drivers/misc/coresight/Kconfig" source "drivers/misc/renesas_ra_external_interrupt/Kconfig" -source "drivers/misc/nxp_rtxxx_dsp_ctrl/Kconfig" endmenu diff --git a/drivers/misc/nxp_rtxxx_dsp_ctrl/CMakeLists.txt b/drivers/misc/nxp_rtxxx_dsp_ctrl/CMakeLists.txt deleted file mode 100644 index 9b4e1a1ef4383..0000000000000 --- a/drivers/misc/nxp_rtxxx_dsp_ctrl/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2025 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/misc/nxp_rtxxx_dsp_ctrl/nxp_rtxxx_dsp_ctrl.h) - -zephyr_library() - -zephyr_library_sources_ifdef(CONFIG_NXP_RTXXX_DSP_CTRL - nxp_rtxxx_dsp_ctrl.c -) diff --git a/drivers/misc/nxp_rtxxx_dsp_ctrl/Kconfig b/drivers/misc/nxp_rtxxx_dsp_ctrl/Kconfig deleted file mode 100644 index 5eb7ee980d9fe..0000000000000 --- a/drivers/misc/nxp_rtxxx_dsp_ctrl/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2025 NXP -# SPDX-License-Identifier: Apache-2.0 - -config NXP_RTXXX_DSP_CTRL - bool "NXP i.MX RTxxx DSP control" - depends on DT_HAS_NXP_RTXXX_DSP_CTRL_ENABLED - default y - help - Enables a DSP control driver for NXP i.MX RTxxx devices. diff --git a/drivers/misc/nxp_rtxxx_dsp_ctrl/nxp_rtxxx_dsp_ctrl.c b/drivers/misc/nxp_rtxxx_dsp_ctrl/nxp_rtxxx_dsp_ctrl.c deleted file mode 100644 index 0ab59540bb32d..0000000000000 --- a/drivers/misc/nxp_rtxxx_dsp_ctrl/nxp_rtxxx_dsp_ctrl.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nxp_rtxxx_dsp_ctrl - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -struct nxp_rtxxx_dsp_ctrl_region { - void *base; - int32_t length; -}; - -struct nxp_rtxxx_dsp_ctrl_config { - SYSCTL0_Type *sysctl; - struct nxp_rtxxx_dsp_ctrl_region regions[NXP_RTXXX_DSP_REGION_MAX]; -}; - -static void dsp_ctrl_enable(const struct device *dev) -{ - SYSCTL0_Type *sysctl = ((struct nxp_rtxxx_dsp_ctrl_config *)dev->config)->sysctl; - - sysctl->DSPSTALL = 0; -} - -static void dsp_ctrl_disable(const struct device *dev) -{ - SYSCTL0_Type *sysctl = ((struct nxp_rtxxx_dsp_ctrl_config *)dev->config)->sysctl; - - sysctl->DSPSTALL = 1; -} - -static int dsp_ctrl_load_section(const struct device *dev, const void *base, size_t length, - enum nxp_rtxxx_dsp_ctrl_section_type section) -{ - if (section >= NXP_RTXXX_DSP_REGION_MAX) { - return -EINVAL; - } - - const struct nxp_rtxxx_dsp_ctrl_config *cfg = - (const struct nxp_rtxxx_dsp_ctrl_config *)dev->config; - - if (cfg->regions[section].base == NULL) { - return -EINVAL; - } - - if (length > cfg->regions[section].length) { - return -ENOMEM; - } - - /* - * Custom memcpy implementation is needed because the DSP TCMs can be accessed - * only by 32 bits. - */ - const uint32_t *src = (const uint32_t *)base; - uint32_t *dst = cfg->regions[section].base; - - for (size_t remaining = length; remaining > 0; remaining -= sizeof(uint32_t)) { - *dst++ = *src++; - - if (remaining < sizeof(uint32_t)) { - break; - } - } - - return 0; -} - -static int nxp_rtxxx_dsp_ctrl_init(const struct device *dev) -{ - /* - * Initialize clocks associated with the DSP. - * Taken from DSP examples for the MIMXRT685-EVK in the MCUXpresso SDK. - */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - CLOCK_AttachClk(kDSP_PLL_to_DSP_MAIN_CLK); - CLOCK_SetClkDiv(kCLOCK_DivDspCpuClk, 1); - CLOCK_SetClkDiv(kCLOCK_DivDspRamClk, 2); - - DSP_Init(); - - return 0; -} - -static struct nxp_rtxxx_dsp_ctrl_api nxp_rtxxx_dsp_ctrl_api = { - .load_section = dsp_ctrl_load_section, - .enable = dsp_ctrl_enable, - .disable = dsp_ctrl_disable -}; - -#define NXP_RTXXX_DSP_SECTION(child_node_id, n) \ - [DT_PROP(child_node_id, type)] = { \ - .base = (void *)DT_REG_ADDR(child_node_id), \ - .length = DT_REG_SIZE(child_node_id) \ - }, - -#define NXP_RTXXX_DSP_CTRL(n) \ - static const struct nxp_rtxxx_dsp_ctrl_config nxp_rtxxx_dsp_ctrl_##n##_config = { \ - .sysctl = (SYSCTL0_Type *)DT_REG_ADDR(DT_INST_PHANDLE(n, sysctl)), \ - .regions = {DT_INST_FOREACH_CHILD_VARGS(n, NXP_RTXXX_DSP_SECTION, n)}}; \ - \ - DEVICE_DT_INST_DEFINE(n, nxp_rtxxx_dsp_ctrl_init, NULL, NULL, \ - &nxp_rtxxx_dsp_ctrl_##n##_config, PRE_KERNEL_1, \ - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &nxp_rtxxx_dsp_ctrl_api); - -DT_INST_FOREACH_STATUS_OKAY(NXP_RTXXX_DSP_CTRL); diff --git a/drivers/modem/Kconfig.cellular b/drivers/modem/Kconfig.cellular index 1d15350b48e03..adc66f574b7d3 100644 --- a/drivers/modem/Kconfig.cellular +++ b/drivers/modem/Kconfig.cellular @@ -13,7 +13,6 @@ config MODEM_CELLULAR select RING_BUFFER select NET_L2_PPP_OPTION_MRU select NET_L2_PPP_PAP - select NET_L2_PPP_MGMT depends on (DT_HAS_QUECTEL_BG95_ENABLED || \ DT_HAS_SIMCOM_SIM7080_ENABLED || DT_HAS_U_BLOX_SARA_R4_ENABLED || \ DT_HAS_U_BLOX_SARA_R5_ENABLED || DT_HAS_SWIR_HL7800_ENABLED || \ diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 7ca2001697fff..2af67a01c7a76 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -60,7 +60,6 @@ enum modem_cellular_state { MODEM_CELLULAR_STATE_RUN_DIAL_SCRIPT, MODEM_CELLULAR_STATE_AWAIT_REGISTERED, MODEM_CELLULAR_STATE_CARRIER_ON, - MODEM_CELLULAR_STATE_DORMANT, MODEM_CELLULAR_STATE_INIT_POWER_OFF, MODEM_CELLULAR_STATE_RUN_SHUTDOWN_SCRIPT, MODEM_CELLULAR_STATE_POWER_OFF_PULSE, @@ -80,7 +79,6 @@ enum modem_cellular_event { MODEM_CELLULAR_EVENT_DEREGISTERED, MODEM_CELLULAR_EVENT_BUS_OPENED, MODEM_CELLULAR_EVENT_BUS_CLOSED, - MODEM_CELLULAR_EVENT_PPP_DEAD, }; struct modem_cellular_data { @@ -128,7 +126,6 @@ struct modem_cellular_data { /* PPP */ struct modem_ppp *ppp; - struct net_mgmt_event_callback net_mgmt_event_callback; enum modem_cellular_state state; const struct device *dev; @@ -199,8 +196,6 @@ static const char *modem_cellular_state_str(enum modem_cellular_state state) return "run dial script"; case MODEM_CELLULAR_STATE_CARRIER_ON: return "carrier on"; - case MODEM_CELLULAR_STATE_DORMANT: - return "dormant"; case MODEM_CELLULAR_STATE_INIT_POWER_OFF: return "init power off"; case MODEM_CELLULAR_STATE_RUN_SHUTDOWN_SCRIPT: @@ -241,8 +236,6 @@ static const char *modem_cellular_event_str(enum modem_cellular_event event) return "bus opened"; case MODEM_CELLULAR_EVENT_BUS_CLOSED: return "bus closed"; - case MODEM_CELLULAR_EVENT_PPP_DEAD: - return "ppp dead"; } return ""; @@ -1028,9 +1021,7 @@ static void modem_cellular_run_dial_script_event_handler(struct modem_cellular_d modem_chat_attach(&data->chat, data->dlci1_pipe); modem_chat_run_script_async(&data->chat, config->dial_chat_script); break; - case MODEM_CELLULAR_EVENT_SCRIPT_FAILED: - modem_cellular_start_timer(data, MODEM_CELLULAR_PERIODIC_SCRIPT_TIMEOUT); - break; + case MODEM_CELLULAR_EVENT_SCRIPT_SUCCESS: modem_cellular_enter_state(data, MODEM_CELLULAR_STATE_AWAIT_REGISTERED); break; @@ -1119,7 +1110,7 @@ static void modem_cellular_carrier_on_event_handler(struct modem_cellular_data * break; case MODEM_CELLULAR_EVENT_DEREGISTERED: - modem_cellular_enter_state(data, MODEM_CELLULAR_STATE_DORMANT); + modem_cellular_enter_state(data, MODEM_CELLULAR_STATE_RUN_DIAL_SCRIPT); break; case MODEM_CELLULAR_EVENT_SUSPEND: @@ -1134,37 +1125,9 @@ static void modem_cellular_carrier_on_event_handler(struct modem_cellular_data * static int modem_cellular_on_carrier_on_state_leave(struct modem_cellular_data *data) { modem_cellular_stop_timer(data); - - return 0; -} - -static int modem_cellular_on_dormant_state_enter(struct modem_cellular_data *data) -{ - net_if_dormant_on(modem_ppp_get_iface(data->ppp)); - - return 0; -} - -static void modem_cellular_dormant_event_handler(struct modem_cellular_data *data, - enum modem_cellular_event evt) -{ - switch (evt) { - case MODEM_CELLULAR_EVENT_PPP_DEAD: - modem_cellular_enter_state(data, MODEM_CELLULAR_STATE_RUN_DIAL_SCRIPT); - break; - - default: - break; - } -} - -static int modem_cellular_on_dormant_state_leave(struct modem_cellular_data *data) -{ net_if_carrier_off(modem_ppp_get_iface(data->ppp)); modem_chat_release(&data->chat); modem_ppp_release(data->ppp); - net_if_dormant_off(modem_ppp_get_iface(data->ppp)); - return 0; } @@ -1353,10 +1316,6 @@ static int modem_cellular_on_state_enter(struct modem_cellular_data *data) ret = modem_cellular_on_carrier_on_state_enter(data); break; - case MODEM_CELLULAR_STATE_DORMANT: - ret = modem_cellular_on_dormant_state_enter(data); - break; - case MODEM_CELLULAR_STATE_INIT_POWER_OFF: ret = modem_cellular_on_init_power_off_state_enter(data); break; @@ -1418,10 +1377,6 @@ static int modem_cellular_on_state_leave(struct modem_cellular_data *data) ret = modem_cellular_on_carrier_on_state_leave(data); break; - case MODEM_CELLULAR_STATE_DORMANT: - ret = modem_cellular_on_dormant_state_leave(data); - break; - case MODEM_CELLULAR_STATE_INIT_POWER_OFF: ret = modem_cellular_on_init_power_off_state_leave(data); break; @@ -1521,10 +1476,6 @@ static void modem_cellular_event_handler(struct modem_cellular_data *data, modem_cellular_carrier_on_event_handler(data, evt); break; - case MODEM_CELLULAR_STATE_DORMANT: - modem_cellular_dormant_event_handler(data, evt); - break; - case MODEM_CELLULAR_STATE_INIT_POWER_OFF: modem_cellular_init_power_off_event_handler(data, evt); break; @@ -1768,22 +1719,6 @@ static int modem_cellular_pm_action(const struct device *dev, enum pm_device_act } #endif /* CONFIG_PM_DEVICE */ -static void net_mgmt_event_handler(struct net_mgmt_event_callback *cb, uint32_t mgmt_event, - struct net_if *iface) -{ - struct modem_cellular_data *data = - CONTAINER_OF(cb, struct modem_cellular_data, net_mgmt_event_callback); - - switch (mgmt_event) { - case NET_EVENT_PPP_PHASE_DEAD: - modem_cellular_delegate_event(data, MODEM_CELLULAR_EVENT_PPP_DEAD); - break; - - default: - break; - } -} - static int modem_cellular_init(const struct device *dev) { struct modem_cellular_data *data = (struct modem_cellular_data *)dev->data; @@ -1892,13 +1827,6 @@ static int modem_cellular_init(const struct device *dev) modem_chat_init(&data->chat, &chat_config); } - { - net_mgmt_init_event_callback(&data->net_mgmt_event_callback, net_mgmt_event_handler, - NET_EVENT_PPP_PHASE_DEAD); - net_mgmt_add_event_callback(&data->net_mgmt_event_callback); - } - - #ifndef CONFIG_PM_DEVICE modem_cellular_delegate_event(data, MODEM_CELLULAR_EVENT_RESUME); #else diff --git a/drivers/modem/modem_cmd_handler.c b/drivers/modem/modem_cmd_handler.c index 2893f73694738..99b1548051585 100644 --- a/drivers/modem/modem_cmd_handler.c +++ b/drivers/modem/modem_cmd_handler.c @@ -486,34 +486,6 @@ int modem_cmd_handler_update_cmds(struct modem_cmd_handler_data *data, return 0; } -int modem_cmd_handler_await(struct modem_cmd_handler_data *data, - struct k_sem *sem, k_timeout_t timeout) -{ - int ret = k_sem_take(sem, timeout); - - if (ret == 0) { - ret = modem_cmd_handler_get_error(data); - } else if (ret == -EAGAIN) { - ret = -ETIMEDOUT; - } - - return ret; -} - -int modem_cmd_send_data_nolock(struct modem_iface *iface, - const uint8_t *buf, size_t len) -{ -#if defined(CONFIG_MODEM_CONTEXT_VERBOSE_DEBUG) - if (len > 256) { - /* Truncate the message, since too long log messages gets dropped somewhere. */ - LOG_HEXDUMP_DBG(buf, 256, "SENT DIRECT DATA (truncated)"); - } else { - LOG_HEXDUMP_DBG(buf, len, "SENT DIRECT DATA"); - } -#endif - return iface->write(iface, buf, len); -} - int modem_cmd_send_ext(struct modem_iface *iface, struct modem_cmd_handler *handler, const struct modem_cmd *handler_cmds, @@ -570,7 +542,13 @@ int modem_cmd_send_ext(struct modem_iface *iface, iface->write(iface, data->eol, data->eol_len); if (sem) { - ret = modem_cmd_handler_await(data, sem, timeout); + ret = k_sem_take(sem, timeout); + + if (ret == 0) { + ret = data->last_error; + } else if (ret == -EAGAIN) { + ret = -ETIMEDOUT; + } } if (!(flags & MODEM_NO_UNSET_CMDS)) { diff --git a/drivers/modem/modem_cmd_handler.h b/drivers/modem/modem_cmd_handler.h index 0acde55d9a866..017097b2346c8 100644 --- a/drivers/modem/modem_cmd_handler.h +++ b/drivers/modem/modem_cmd_handler.h @@ -158,33 +158,6 @@ int modem_cmd_handler_update_cmds(struct modem_cmd_handler_data *data, size_t handler_cmds_len, bool reset_error_flag); -/** - * @brief Wait until semaphore is given - * - * This function does the same wait behavior as @ref modem_cmd_send, but can wait without sending - * any command first. Useful for waiting for asynchronous responses. - * - * @param data: handler data to use - * @param sem: wait for semaphore. - * @param timeout: wait timeout. - * - * @retval 0 if ok, < 0 if error. - */ -int modem_cmd_handler_await(struct modem_cmd_handler_data *data, - struct k_sem *sem, k_timeout_t timeout); - -/** - * @brief send data directly to interface w/o TX lock. - * - * This function just writes directly to the modem interface. - * Recommended to use to get verbose logging for all data sent to the interface. - * @param iface: interface to use - * @param buf: send buffer (not NULL terminated) - * @param len: length of send buffer. - */ -int modem_cmd_send_data_nolock(struct modem_iface *iface, - const uint8_t *buf, size_t len); - /** * @brief send AT command to interface with behavior defined by flags * diff --git a/drivers/modem/modem_shell.c b/drivers/modem/modem_shell.c index ad12dbe669e04..191a486d7cfcf 100644 --- a/drivers/modem/modem_shell.c +++ b/drivers/modem/modem_shell.c @@ -30,7 +30,7 @@ struct modem_shell_user_data { #define ms_context modem_context #define ms_max_context CONFIG_MODEM_CONTEXT_MAX_NUM #define ms_send(ctx_, buf_, size_) \ - (modem_cmd_send_data_nolock(&ctx_->iface, buf_, size_)) + (ctx_->iface.write(&ctx_->iface, buf_, size_)) #define ms_context_from_id modem_context_from_id #define UART_DEV_NAME(ctx) (ctx->iface.dev->name) #elif defined(CONFIG_MODEM_RECEIVER) diff --git a/drivers/modem/quectel-bg9x.c b/drivers/modem/quectel-bg9x.c index 234bbca743b71..a89257275f81f 100644 --- a/drivers/modem/quectel-bg9x.c +++ b/drivers/modem/quectel-bg9x.c @@ -484,8 +484,8 @@ static ssize_t send_socket_data(struct modem_socket *sock, } /* Write all data on the console and send CTRL+Z. */ - modem_cmd_send_data_nolock(&mctx.iface, buf, buf_len); - modem_cmd_send_data_nolock(&mctx.iface, &ctrlz, 1); + mctx.iface.write(&mctx.iface, buf, buf_len); + mctx.iface.write(&mctx.iface, &ctrlz, 1); /* Wait for 'SEND OK' or 'SEND FAIL' */ k_sem_reset(&mdata.sem_response); diff --git a/drivers/modem/simcom-sim7080.c b/drivers/modem/simcom-sim7080.c index 06dda64ff5485..cc3955f96f63e 100644 --- a/drivers/modem/simcom-sim7080.c +++ b/drivers/modem/simcom-sim7080.c @@ -273,8 +273,8 @@ static ssize_t offload_sendto(void *obj, const void *buf, size_t len, int flags, } /* Send data */ - modem_cmd_send_data_nolock(&mctx.iface, buf, len); - modem_cmd_send_data_nolock(&mctx.iface, &ctrlz, 1); + mctx.iface.write(&mctx.iface, buf, len); + mctx.iface.write(&mctx.iface, &ctrlz, 1); /* Wait for the OK */ k_sem_reset(&mdata.sem_response); diff --git a/drivers/modem/ublox-sara-r4.c b/drivers/modem/ublox-sara-r4.c index 46e6bc28bba41..734ccac2eb98e 100644 --- a/drivers/modem/ublox-sara-r4.c +++ b/drivers/modem/ublox-sara-r4.c @@ -415,7 +415,7 @@ static ssize_t send_socket_data(void *obj, if (len == 0) { break; } - modem_cmd_send_data_nolock(&mctx.iface, msg->msg_iov[i].iov_base, len); + mctx.iface.write(&mctx.iface, msg->msg_iov[i].iov_base, len); buf_len -= len; } @@ -423,8 +423,13 @@ static ssize_t send_socket_data(void *obj, ret = 0; goto exit; } + ret = k_sem_take(&mdata.sem_response, timeout); - ret = modem_cmd_handler_await(&mdata.cmd_handler_data, &mdata.sem_response, timeout); + if (ret == 0) { + ret = modem_cmd_handler_get_error(&mdata.cmd_handler_data); + } else if (ret == -EAGAIN) { + ret = -ETIMEDOUT; + } exit: /* unset handler commands and ignore any errors */ @@ -481,17 +486,18 @@ static ssize_t send_cert(struct modem_socket *sock, goto exit; } - /* Reset response semaphore before sending data - * So that we are sure that we won't use a previously pending one - * And we won't miss the one that is going to be freed - */ - k_sem_reset(&mdata.sem_response); - /* slight pause per spec so that @ prompt is received */ k_sleep(MDM_PROMPT_CMD_DELAY); - modem_cmd_send_data_nolock(&mctx.iface, cert_data, cert_len); + mctx.iface.write(&mctx.iface, cert_data, cert_len); + + k_sem_reset(&mdata.sem_response); + ret = k_sem_take(&mdata.sem_response, K_MSEC(1000)); - ret = modem_cmd_handler_await(&mdata.cmd_handler_data, &mdata.sem_response, K_MSEC(1000)); + if (ret == 0) { + ret = modem_cmd_handler_get_error(&mdata.cmd_handler_data); + } else if (ret == -EAGAIN) { + ret = -ETIMEDOUT; + } exit: /* unset handler commands and ignore any errors */ diff --git a/drivers/mspi/CMakeLists.txt b/drivers/mspi/CMakeLists.txt index 7f0a98ddb3b4d..78f704393f428 100644 --- a/drivers/mspi/CMakeLists.txt +++ b/drivers/mspi/CMakeLists.txt @@ -4,6 +4,5 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/mspi.h) zephyr_library() zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_AP3 mspi_ambiq_ap3.c) -zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_AP5 mspi_ambiq_ap5.c) zephyr_library_sources_ifdef(CONFIG_MSPI_DW mspi_dw.c) zephyr_library_sources_ifdef(CONFIG_MSPI_EMUL mspi_emul.c) diff --git a/drivers/mspi/Kconfig.ambiq b/drivers/mspi/Kconfig.ambiq index 2ca136d04ef8d..64d155596b4b4 100644 --- a/drivers/mspi/Kconfig.ambiq +++ b/drivers/mspi/Kconfig.ambiq @@ -1,49 +1,28 @@ -# Copyright (c) 2025, Ambiq Micro Inc. +# Copyright (c) 2024, Ambiq Micro Inc. # SPDX-License-Identifier: Apache-2.0 -config MSPI_AMBIQ_CONTROLLER - bool "Ambiq MSPI Controller driver" +config MSPI_AMBIQ_AP3 + bool "Ambiq Apollo3 series MSPI driver" + default y depends on DT_HAS_AMBIQ_MSPI_CONTROLLER_ENABLED select AMBIQ_HAL select AMBIQ_HAL_USE_MSPI + select MSPI_XIP + select MSPI_SCRAMBLE + select MSPI_TIMING select GPIO - help - Ambiq MSPI controller driver is enabled. - -if MSPI_AMBIQ_CONTROLLER - -config MSPI_AMBIQ_AP3 - bool "Ambiq Apollo3 series MSPI Controller driver" - default y - depends on SOC_SERIES_APOLLO3X - imply MSPI_XIP - imply MSPI_SCRAMBLE - imply MSPI_TIMING - help - Enable driver for Ambiq MSPI. - -config MSPI_AMBIQ_AP5 - bool "Ambiq Apollo5 series MSPI Controller driver" - default y - depends on SOC_SERIES_APOLLO5X - imply MSPI_XIP - imply MSPI_SCRAMBLE - imply MSPI_TIMING help Enable driver for Ambiq MSPI. config MSPI_AMBIQ_BUFF_RAM_LOCATION - hex "Byte offset to SRAM_BASE_ADDRESS" - default SOC_AMBIQ_DMA_BUFF_LOCATION if SOC_SERIES_APOLLO5X + hex "byte offset to SRAM_BASE_ADDRESS" default 0x50000 help This option specifies the mspi buffer/heap start address config MSPI_AMBIQ_BUFF_ALIGNMENT - int "Byte alignment of the MSPI buffer" + int "byte alignment of the MSPI buffer" default 8 if MSPI_AMBIQ_AP3 - default SOC_AMBIQ_DMA_BUFF_ALIGNMENT if SOC_SERIES_APOLLO5X + default 4 help This option specifies the mspi buffer alignment - -endif # MSPI_AMBIQ_CONTROLLER diff --git a/drivers/mspi/mspi_ambiq.h b/drivers/mspi/mspi_ambiq.h index 8aabf0a1f6dc5..f8ca6789ae4ba 100644 --- a/drivers/mspi/mspi_ambiq.h +++ b/drivers/mspi/mspi_ambiq.h @@ -25,38 +25,6 @@ }, \ } -#define MSPI_CQ_MAX_ENTRY MSPI0_CQCURIDX_CQCURIDX_Msk - -#define TIMING_CFG_GET_RX_DUMMY(cfg) \ - { \ - mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \ - timing->ui8TurnAround; \ - } - -#define TIMING_CFG_SET_RX_DUMMY(cfg, num) \ - { \ - mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \ - timing->ui8TurnAround = num; \ - } - -#define MSPI_AMBIQ_TIMING_CONFIG(n) \ - { \ - .ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \ - .ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \ - .bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \ - .bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \ - .bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \ - .ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \ - .ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \ - .ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \ - } - -#define MSPI_AMBIQ_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask) - -#define MSPI_AMBIQ_PORT(n) ((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / \ - (MSPI1_BASE - MSPI0_BASE)) - - struct mspi_ambiq_timing_cfg { uint8_t ui8WriteLatency; uint8_t ui8TurnAround; @@ -79,6 +47,9 @@ enum mspi_ambiq_timing_param { MSPI_AMBIQ_SET_RXDQSDLYEXT = BIT(7), }; +#define MSPI_PORT(n) ((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / \ + (DT_REG_SIZE(DT_INST_BUS(n)) * 4)) + #define TIMING_CFG_GET_RX_DUMMY(cfg) \ { \ mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \ diff --git a/drivers/mspi/mspi_ambiq_ap5.c b/drivers/mspi/mspi_ambiq_ap5.c deleted file mode 100644 index 2fade01fbb395..0000000000000 --- a/drivers/mspi/mspi_ambiq_ap5.c +++ /dev/null @@ -1,2009 +0,0 @@ -/* - * Copyright (c) 2025, Ambiq Micro Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT ambiq_mspi_controller - -#include -#include -LOG_LEVEL_SET(CONFIG_MSPI_LOG_LEVEL); -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include <../dts/common/mem.h> - -#include "mspi_ambiq.h" - -#define MSPI_MAX_FREQ 125000000 -#define MSPI_MAX_DEVICE 2 -#define MSPI_TIMEOUT_US 1000000 - -#define MSPI_BUSY BIT(2) - -typedef int (*mspi_ambiq_pwr_func_t)(void); -typedef void (*irq_config_func_t)(void); - -struct mspi_context { - const struct mspi_dev_id *owner; - - struct mspi_xfer xfer; - - int packets_left; - int packets_done; - - mspi_callback_handler_t callback; - struct mspi_callback_context *callback_ctx; - bool asynchronous; - - struct k_sem lock; -}; - -struct mspi_ambiq_config { - uint32_t reg_base; - uint32_t reg_size; - uint32_t xip_base; - uint32_t xip_size; - - bool apmemory_supp; - bool hyperbus_supp; - - struct mspi_cfg mspicfg; - - const struct pinctrl_dev_config *pcfg; - irq_config_func_t irq_cfg_func; - - bool pm_dev_runtime_auto; - - LOG_INSTANCE_PTR_DECLARE(log); -}; - -struct mspi_ambiq_data { - void *mspiHandle; - am_hal_mspi_config_t hal_cfg; - am_hal_mspi_dev_config_t hal_dev_cfg; - am_hal_mspi_rxcfg_t hal_rx_cfg; - am_hal_mspi_xip_config_t hal_xip_cfg; - am_hal_mspi_xip_misc_t hal_xip_misc_cfg; - am_hal_mspi_dqs_t hal_dqs_cfg; - am_hal_mspi_timing_scan_t hal_timing; - - struct mspi_dev_id *dev_id; - struct k_mutex lock; - - struct mspi_dev_cfg dev_cfg; - struct mspi_xip_cfg xip_cfg; - struct mspi_scramble_cfg scramble_cfg; - - mspi_callback_handler_t cbs[MSPI_BUS_EVENT_MAX]; - struct mspi_callback_context *cb_ctxs[MSPI_BUS_EVENT_MAX]; - - struct mspi_context ctx; -}; - -static int mspi_set_freq(enum mspi_data_rate data_rate, uint32_t freq) -{ - if (freq > MSPI_MAX_FREQ) { - return AM_HAL_MSPI_CLK_INVALID; - } - - switch (freq) { - case 125000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_250MHZ; - } else { - return AM_HAL_MSPI_CLK_INVALID; - } - case 96000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_192MHZ; - } else { - return AM_HAL_MSPI_CLK_96MHZ; - } - case 62500000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_125MHZ; - } else { - return AM_HAL_MSPI_CLK_62P5MHZ; - } - case 48000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_96MHZ; - } else { - return AM_HAL_MSPI_CLK_48MHZ; - } - case 31250000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_62P5MHZ; - } else { - return AM_HAL_MSPI_CLK_31P25MHZ; - } - case 24000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_48MHZ; - } else { - return AM_HAL_MSPI_CLK_24MHZ; - } - case 20830000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_41P67MHZ; - } else { - return AM_HAL_MSPI_CLK_20P83MHZ; - } - case 16000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_INVALID; - } else { - return AM_HAL_MSPI_CLK_16MHZ; - } - case 15625000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_31P25MHZ; - } else { - return AM_HAL_MSPI_CLK_15P63MHZ; - } - case 12000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_24MHZ; - } else { - return AM_HAL_MSPI_CLK_12MHZ; - } - case 8000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_16MHZ; - } else { - return AM_HAL_MSPI_CLK_8MHZ; - } - case 6000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_12MHZ; - } else { - return AM_HAL_MSPI_CLK_6MHZ; - } - case 5210000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_10P42MHZ; - } else { - return AM_HAL_MSPI_CLK_5P21MHZ; - } - case 4000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_8MHZ; - } else { - return AM_HAL_MSPI_CLK_4MHZ; - } - case 3000000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_6MHZ; - } else { - return AM_HAL_MSPI_CLK_3MHZ; - } - case 1500000: - if (data_rate == MSPI_DATA_RATE_S_D_D || - data_rate == MSPI_DATA_RATE_DUAL) { - return AM_HAL_MSPI_CLK_3MHZ; - } else { - return AM_HAL_MSPI_CLK_1P5MHZ; - } - default: - return AM_HAL_MSPI_CLK_INVALID; - } -} - -static am_hal_mspi_device_e mspi_set_line(enum mspi_io_mode io_mode, - enum mspi_data_rate data_rate, - uint8_t ce_num) -{ - if (ce_num == 0) { - switch (data_rate) { - case MSPI_DATA_RATE_SINGLE: - switch (io_mode) { - case MSPI_IO_MODE_SINGLE: - return AM_HAL_MSPI_FLASH_SERIAL_CE0; - case MSPI_IO_MODE_DUAL: - return AM_HAL_MSPI_FLASH_DUAL_CE0; - case MSPI_IO_MODE_DUAL_1_1_2: - return AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2; - case MSPI_IO_MODE_DUAL_1_2_2: - return AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2; - case MSPI_IO_MODE_QUAD: - return AM_HAL_MSPI_FLASH_QUAD_CE0; - case MSPI_IO_MODE_QUAD_1_1_4: - return AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4; - case MSPI_IO_MODE_QUAD_1_4_4: - return AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4; - case MSPI_IO_MODE_OCTAL: - return AM_HAL_MSPI_FLASH_OCTAL_CE0; - case MSPI_IO_MODE_OCTAL_1_1_8: - return AM_HAL_MSPI_FLASH_OCTAL_CE0_1_1_8; - case MSPI_IO_MODE_OCTAL_1_8_8: - return AM_HAL_MSPI_FLASH_OCTAL_CE0_1_8_8; - default: - return AM_HAL_MSPI_FLASH_MAX; - } - case MSPI_DATA_RATE_S_D_D: - case MSPI_DATA_RATE_DUAL: - switch (io_mode) { - case MSPI_IO_MODE_OCTAL: - return AM_HAL_MSPI_FLASH_OCTAL_DDR_CE0; - case MSPI_IO_MODE_HEX_8_8_16: - return AM_HAL_MSPI_FLASH_HEX_DDR_CE0; - default: - return AM_HAL_MSPI_FLASH_MAX; - } - default: - return AM_HAL_MSPI_FLASH_MAX; - } - - } else if (ce_num == 1) { - switch (data_rate) { - case MSPI_DATA_RATE_SINGLE: - switch (io_mode) { - case MSPI_IO_MODE_SINGLE: - return AM_HAL_MSPI_FLASH_SERIAL_CE1; - case MSPI_IO_MODE_DUAL: - return AM_HAL_MSPI_FLASH_DUAL_CE1; - case MSPI_IO_MODE_DUAL_1_1_2: - return AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2; - case MSPI_IO_MODE_DUAL_1_2_2: - return AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2; - case MSPI_IO_MODE_QUAD: - return AM_HAL_MSPI_FLASH_QUAD_CE1; - case MSPI_IO_MODE_QUAD_1_1_4: - return AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4; - case MSPI_IO_MODE_QUAD_1_4_4: - return AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4; - case MSPI_IO_MODE_OCTAL: - return AM_HAL_MSPI_FLASH_OCTAL_CE1; - case MSPI_IO_MODE_OCTAL_1_1_8: - return AM_HAL_MSPI_FLASH_OCTAL_CE1_1_1_8; - case MSPI_IO_MODE_OCTAL_1_8_8: - return AM_HAL_MSPI_FLASH_OCTAL_CE1_1_8_8; - default: - return AM_HAL_MSPI_FLASH_MAX; - } - case MSPI_DATA_RATE_S_D_D: - case MSPI_DATA_RATE_DUAL: - switch (io_mode) { - case MSPI_IO_MODE_OCTAL: - return AM_HAL_MSPI_FLASH_OCTAL_DDR_CE1; - case MSPI_IO_MODE_HEX_8_8_16: - return AM_HAL_MSPI_FLASH_HEX_DDR_CE1; - default: - return AM_HAL_MSPI_FLASH_MAX; - } - default: - return AM_HAL_MSPI_FLASH_MAX; - } - } else { - return AM_HAL_MSPI_FLASH_MAX; - } -} - -static am_hal_mspi_dma_boundary_e mspi_set_mem_boundary(uint32_t mem_boundary) -{ - switch (mem_boundary) { - case 0: - return AM_HAL_MSPI_BOUNDARY_NONE; - case 32: - return AM_HAL_MSPI_BOUNDARY_BREAK32; - case 64: - return AM_HAL_MSPI_BOUNDARY_BREAK64; - case 128: - return AM_HAL_MSPI_BOUNDARY_BREAK128; - case 256: - return AM_HAL_MSPI_BOUNDARY_BREAK256; - case 512: - return AM_HAL_MSPI_BOUNDARY_BREAK512; - case 1024: - return AM_HAL_MSPI_BOUNDARY_BREAK1K; - case 2048: - return AM_HAL_MSPI_BOUNDARY_BREAK2K; - case 4096: - return AM_HAL_MSPI_BOUNDARY_BREAK4K; - case 8192: - return AM_HAL_MSPI_BOUNDARY_BREAK8K; - case 16384: - return AM_HAL_MSPI_BOUNDARY_BREAK16K; - default: - return AM_HAL_MSPI_BOUNDARY_MAX; - } -} - -static uint32_t mspi_set_time_limit(am_hal_mspi_clock_e clock, uint32_t time_limit) -{ - /* TODO */ - switch (clock) { - /**case AM_HAL_MSPI_CLK_250MHZ: - * return time_limit * 26; - * case AM_HAL_MSPI_CLK_192MHZ: - * return time_limit * 20; - */ - default: - return time_limit * 10; - } -} - -static int mspi_get_mem_apsize(const struct mspi_ambiq_config *cfg, uint32_t mem_size) -{ - if (mem_size > cfg->xip_size) { - LOG_INST_ERR(cfg->log, "%u, xip size->%08X exceed maximum size->%08X.", - __LINE__, mem_size, cfg->xip_size); - return -ENOTSUP; - } - - switch (mem_size) { - case DT_SIZE_K(64): - return AM_HAL_MSPI_AP_SIZE64K; - case DT_SIZE_K(128): - return AM_HAL_MSPI_AP_SIZE128K; - case DT_SIZE_K(256): - return AM_HAL_MSPI_AP_SIZE256K; - case DT_SIZE_K(512): - return AM_HAL_MSPI_AP_SIZE512K; - case DT_SIZE_M(1): - return AM_HAL_MSPI_AP_SIZE1M; - case DT_SIZE_M(2): - return AM_HAL_MSPI_AP_SIZE2M; - case DT_SIZE_M(4): - return AM_HAL_MSPI_AP_SIZE4M; - case DT_SIZE_M(8): - return AM_HAL_MSPI_AP_SIZE8M; - case DT_SIZE_M(16): - return AM_HAL_MSPI_AP_SIZE16M; - case DT_SIZE_M(32): - return AM_HAL_MSPI_AP_SIZE32M; - case DT_SIZE_M(64): - return AM_HAL_MSPI_AP_SIZE64M; - case DT_SIZE_M(128): - return AM_HAL_MSPI_AP_SIZE128M; - case DT_SIZE_M(256): - return AM_HAL_MSPI_AP_SIZE256M; - default: - return -ENOTSUP; - } -} - -static inline void mspi_context_ce_control(struct mspi_context *ctx, bool on) -{ - if (ctx->owner) { - if (ctx->xfer.hold_ce && - ctx->xfer.ce_sw_ctrl.gpio.port != NULL) { - if (on) { - gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 1); - k_busy_wait(ctx->xfer.ce_sw_ctrl.delay); - } else { - k_busy_wait(ctx->xfer.ce_sw_ctrl.delay); - gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 0); - } - } - } -} - -static inline void mspi_context_release(struct mspi_context *ctx) -{ - ctx->owner = NULL; - k_sem_give(&ctx->lock); -} - -static inline void mspi_context_unlock_unconditionally(struct mspi_context *ctx) -{ - mspi_context_ce_control(ctx, false); - - if (!k_sem_count_get(&ctx->lock)) { - ctx->owner = NULL; - k_sem_give(&ctx->lock); - } -} - -static inline int mspi_context_lock(struct mspi_context *ctx, - const struct mspi_dev_id *req, - const struct mspi_xfer *xfer, - mspi_callback_handler_t callback, - struct mspi_callback_context *callback_ctx, - bool lockon) -{ - int ret = 1; - - if ((k_sem_count_get(&ctx->lock) == 0) && !lockon && - (ctx->owner == req)) { - return 0; - } - - if (k_sem_take(&ctx->lock, K_MSEC(xfer->timeout))) { - return -EBUSY; - } - if (ctx->xfer.async) { - if ((xfer->tx_dummy == ctx->xfer.tx_dummy) && - (xfer->rx_dummy == ctx->xfer.rx_dummy) && - (xfer->cmd_length == ctx->xfer.cmd_length) && - (xfer->addr_length == ctx->xfer.addr_length)) { - ret = 0; - } else if (ctx->packets_left == 0) { - if (ctx->callback_ctx) { - volatile struct mspi_event_data *evt_data; - - evt_data = &ctx->callback_ctx->mspi_evt.evt_data; - while (evt_data->status != 0) { - } - ret = 1; - } else { - ret = 0; - } - } else { - return -EIO; - } - } - ctx->owner = req; - ctx->xfer = *xfer; - ctx->packets_done = 0; - ctx->packets_left = ctx->xfer.num_packet; - ctx->callback = callback; - ctx->callback_ctx = callback_ctx; - return ret; -} - -static inline bool mspi_is_inp(const struct device *controller) -{ - struct mspi_ambiq_data *data = controller->data; - - return (k_sem_count_get(&data->ctx.lock) == 0); -} - -static inline int mspi_verify_device(const struct device *controller, - const struct mspi_dev_id *dev_id) -{ - const struct mspi_ambiq_config *cfg = controller->config; - int device_index = cfg->mspicfg.num_periph; - int ret = 0; - - for (int i = 0; i < cfg->mspicfg.num_periph; i++) { - if (dev_id->ce.port == cfg->mspicfg.ce_group[i].port && - dev_id->ce.pin == cfg->mspicfg.ce_group[i].pin && - dev_id->ce.dt_flags == cfg->mspicfg.ce_group[i].dt_flags) { - device_index = i; - } - } - - if (device_index >= cfg->mspicfg.num_periph || - device_index != dev_id->dev_idx) { - LOG_INST_ERR(cfg->log, "%u, invalid device ID.", __LINE__); - return -ENODEV; - } - - return ret; -} - -static int mspi_ambiq_deinit(const struct device *controller) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - int ret = 0; - - if (!data->mspiHandle) { - LOG_INST_ERR(cfg->log, "%u, the mspi not yet initialized.", __LINE__); - return -ENODEV; - } - - if (k_mutex_lock(&data->lock, K_MSEC(CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE))) { - LOG_INST_ERR(cfg->log, "%u, fail to gain controller access.", __LINE__); - return -EBUSY; - } - - ret = pm_device_runtime_get(controller); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_get.", __LINE__); - goto e_deinit_return; - } - - ret = pm_device_runtime_disable(controller); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_disable.", __LINE__); - goto e_deinit_return; - } - - ret = am_hal_mspi_interrupt_disable(data->mspiHandle, 0xFFFFFFFF); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to disable interrupt, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_deinit_return; - } - - ret = am_hal_mspi_interrupt_clear(data->mspiHandle, 0xFFFFFFFF); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to clear interrupt, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_deinit_return; - } - - ret = am_hal_mspi_disable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to disable MSPI, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_deinit_return; - } - - ret = am_hal_mspi_power_control(data->mspiHandle, AM_HAL_SYSCTRL_DEEPSLEEP, false); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to power off MSPI, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_deinit_return; - } - - ret = am_hal_mspi_deinitialize(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to deinit MSPI.", __LINE__); - ret = -ENODEV; - goto e_deinit_return; - } - return ret; - -e_deinit_return: - k_mutex_unlock(&data->lock); - return ret; -} - -/** DMA specific config */ -static int mspi_xfer_config(const struct device *controller, - const struct mspi_xfer *xfer) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - am_hal_mspi_dev_config_t hal_dev_cfg = data->hal_dev_cfg; - am_hal_mspi_request_e eRequest; - int ret = 0; - - if (data->scramble_cfg.enable) { - eRequest = AM_HAL_MSPI_REQ_SCRAMB_EN; - } else { - eRequest = AM_HAL_MSPI_REQ_SCRAMB_DIS; - } - - ret = am_hal_mspi_disable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to disable MSPI, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_control(data->mspiHandle, eRequest, NULL); - if (ret) { - LOG_INST_ERR(cfg->log, "%u,Unable to complete scramble config:%d.", - __LINE__, data->scramble_cfg.enable); - return -EHOSTDOWN; - } - - uint8_t cmd_length = xfer->cmd_length; - - if (data->dev_cfg.data_rate == MSPI_DATA_RATE_S_D_D) { - cmd_length *= 2; - /* TODO - buggy, cmd can not be changed here */ - } - if (cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, cmd_length is too large.", __LINE__); - return -ENOTSUP; - } - if (cmd_length == 0) { - hal_dev_cfg.bSendInstr = false; - } else { - hal_dev_cfg.bSendInstr = true; - hal_dev_cfg.eInstrCfg = cmd_length - 1; - } - - if (xfer->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, addr_length is too large.", __LINE__); - return -ENOTSUP; - } - if (xfer->addr_length == 0) { - hal_dev_cfg.bSendAddr = false; - } else { - hal_dev_cfg.bSendAddr = true; - hal_dev_cfg.eAddrCfg = xfer->addr_length - 1; - } - - hal_dev_cfg.bTurnaround = (xfer->rx_dummy != 0); - hal_dev_cfg.ui8TurnAround = (uint8_t)(hal_dev_cfg.bEmulateDDR ? xfer->rx_dummy * 2 : - xfer->rx_dummy); - hal_dev_cfg.bEnWriteLatency = (xfer->tx_dummy != 0); - hal_dev_cfg.ui8WriteLatency = (uint8_t)(hal_dev_cfg.bEmulateDDR ? xfer->tx_dummy * 2 : - xfer->tx_dummy); - - ret = am_hal_mspi_device_configure(data->mspiHandle, &hal_dev_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure MSPI, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_enable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to enable MSPI, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - data->hal_dev_cfg = hal_dev_cfg; - return ret; -} - -static int mspi_ambiq_pm_action(const struct device *controller, enum pm_device_action action) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - int ret = 0; - - switch (action) { - case PM_DEVICE_ACTION_RESUME: - ret = am_hal_mspi_power_control(data->mspiHandle, AM_HAL_SYSCTRL_WAKE, true); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to resume MSPI, code:%d.", __LINE__, - ret); - return -EHOSTDOWN; - } - break; - - case PM_DEVICE_ACTION_SUSPEND: - ret = am_hal_mspi_power_control(data->mspiHandle, AM_HAL_SYSCTRL_DEEPSLEEP, true); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to suspend MSPI, code:%d.", __LINE__, - ret); - return -EHOSTDOWN; - } - break; - - default: - return -ENOTSUP; - } - - return ret; -} - -static int mspi_ambiq_config(const struct mspi_dt_spec *spec) -{ - const struct mspi_cfg *config = &spec->config; - const struct mspi_ambiq_config *cfg = spec->bus->config; - struct mspi_ambiq_data *data = spec->bus->data; - am_hal_mspi_config_t *hal_cfg = &data->hal_cfg; - am_hal_mspi_dqs_t dqs_cfg; - - int ret = 0; - - LOG_INST_DBG(cfg->log, "MSPI controller init."); - - if (config->op_mode != MSPI_OP_MODE_CONTROLLER) { - LOG_INST_ERR(cfg->log, "%u, only support MSPI controller mode.", __LINE__); - return -ENOTSUP; - } - - if (config->max_freq > MSPI_MAX_FREQ) { - LOG_INST_ERR(cfg->log, "%u, max_freq too large.", __LINE__); - return -ENOTSUP; - } - - if (config->duplex != MSPI_HALF_DUPLEX) { - LOG_INST_ERR(cfg->log, "%u, only support half duplex mode.", __LINE__); - return -ENOTSUP; - } - - if (cfg->apmemory_supp && cfg->hyperbus_supp) { - LOG_INST_ERR(cfg->log, "%u, only support one of APM or HyperBus at a time.", - __LINE__); - return -ENOTSUP; - } - - if (config->re_init) { - ret = mspi_ambiq_deinit(spec->bus); - if (ret) { - return ret; - } - } - - ret = am_hal_mspi_initialize(config->channel_num, &data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to initialize MSPI, code:%d.", - __LINE__, ret); - return -EPERM; - } - - ret = am_hal_mspi_power_control(data->mspiHandle, AM_HAL_SYSCTRL_WAKE, false); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to power on MSPI, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_configure(data->mspiHandle, hal_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to config MSPI, code:%d.", __LINE__, ret); - return -EHOSTDOWN; - } - - memset(&dqs_cfg, 0, sizeof(am_hal_mspi_dqs_t)); - dqs_cfg.ui8RxDQSDelay = 16; - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_DQS, &dqs_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure DQS.", __LINE__); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_enable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to Enable MSPI, code:%d.", __LINE__, ret); - return -EHOSTDOWN; - } - - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret) { - return ret; - } - - ret = am_hal_mspi_interrupt_clear(data->mspiHandle, AM_HAL_MSPI_INT_CQUPD | - AM_HAL_MSPI_INT_ERR); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to clear interrupt, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_interrupt_enable(data->mspiHandle, AM_HAL_MSPI_INT_CQUPD | - AM_HAL_MSPI_INT_ERR); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to turn on interrupt, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - cfg->irq_cfg_func(); - - if (cfg->pm_dev_runtime_auto) { - ret = pm_device_runtime_enable(spec->bus); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_enable.", __LINE__); - return ret; - } - } - - mspi_context_unlock_unconditionally(&data->ctx); - - if (config->re_init) { - k_mutex_unlock(&data->lock); - } - - return ret; -} - -static int mspi_ambiq_dev_config(const struct device *controller, - const struct mspi_dev_id *dev_id, - const enum mspi_dev_cfg_mask param_mask, - const struct mspi_dev_cfg *dev_cfg) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - am_hal_mspi_dev_config_t hal_dev_cfg = data->hal_dev_cfg; - am_hal_mspi_rxcfg_t hal_rx_cfg = data->hal_rx_cfg; - int ret = 0; - - if (data->dev_id != dev_id) { - if (k_mutex_lock(&data->lock, K_MSEC(CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE))) { - LOG_INST_ERR(cfg->log, "%u, fail to gain controller access.", __LINE__); - return -EBUSY; - } - - ret = mspi_verify_device(controller, dev_id); - if (ret) { - goto e_return; - } - - ret = pm_device_runtime_get(controller); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_get.", __LINE__); - goto e_return; - } - } - - if (mspi_is_inp(controller)) { - ret = -EBUSY; - goto e_return; - } - - if (param_mask == MSPI_DEVICE_CONFIG_NONE && - !cfg->mspicfg.sw_multi_periph) { - /* Do nothing except obtaining the controller lock */ - data->dev_id = (struct mspi_dev_id *)dev_id; - return ret; - - } else if (param_mask != MSPI_DEVICE_CONFIG_ALL) { - if (data->dev_id != dev_id) { - LOG_INST_ERR(cfg->log, "%u, config failed, must be the same device.", - __LINE__); - ret = -EACCES; - goto e_return; - } - - if ((param_mask & (~(MSPI_DEVICE_CONFIG_FREQUENCY | - MSPI_DEVICE_CONFIG_IO_MODE | - MSPI_DEVICE_CONFIG_CE_NUM | - MSPI_DEVICE_CONFIG_DATA_RATE | - MSPI_DEVICE_CONFIG_CMD_LEN | - MSPI_DEVICE_CONFIG_ADDR_LEN | - MSPI_DEVICE_CONFIG_DQS)))) { - LOG_INST_ERR(cfg->log, "%u, config type not supported.", __LINE__); - ret = -EINVAL; - goto e_return; - } - - if (param_mask & MSPI_DEVICE_CONFIG_FREQUENCY) { - hal_dev_cfg.eClockFreq = mspi_set_freq(data->dev_cfg.data_rate, - dev_cfg->freq); - if (hal_dev_cfg.eClockFreq == AM_HAL_MSPI_CLK_INVALID) { - LOG_INST_ERR(cfg->log, "%u,Frequency not supported!", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_CLOCK_CONFIG, - &hal_dev_cfg.eClockFreq); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure eClockFreq.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->dev_cfg.freq = dev_cfg->freq; - - if (hal_dev_cfg.eClockFreq >= AM_HAL_MSPI_CLK_96MHZ && - hal_dev_cfg.bEmulateDDR) { - hal_rx_cfg.ui8RxSmp = 2; - } else { - hal_rx_cfg.ui8RxSmp = 1; - } - - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_RXCFG, &hal_rx_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure RXCFG.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - /* Sync TxNeg RxNeg RxCap */ - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_TIMING_SCAN_GET, - &data->hal_timing); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to get timing.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - } - - if ((param_mask & MSPI_DEVICE_CONFIG_IO_MODE) || - (param_mask & MSPI_DEVICE_CONFIG_CE_NUM) || - (param_mask & MSPI_DEVICE_CONFIG_DATA_RATE)) { - enum mspi_io_mode io_mode; - enum mspi_data_rate data_rate; - uint8_t ce_num; - - if (param_mask & MSPI_DEVICE_CONFIG_IO_MODE) { - io_mode = dev_cfg->io_mode; - } else { - io_mode = data->dev_cfg.io_mode; - } - - if (param_mask & MSPI_DEVICE_CONFIG_CE_NUM) { - ce_num = dev_cfg->ce_num; - } else { - ce_num = data->dev_cfg.ce_num; - } - - if (param_mask & MSPI_DEVICE_CONFIG_DATA_RATE) { - data_rate = dev_cfg->data_rate; - } else { - data_rate = data->dev_cfg.data_rate; - } - - hal_dev_cfg.eDeviceConfig = mspi_set_line(io_mode, data_rate, ce_num); - if (hal_dev_cfg.eDeviceConfig == AM_HAL_MSPI_FLASH_MAX || - (data->hal_cfg.bClkonD4 && - io_mode > MSPI_IO_MODE_QUAD_1_4_4)) { - LOG_INST_ERR(cfg->log, "%u, not supported mode(s) detected.", - __LINE__); - ret = -ENOTSUP; - goto e_return; - } - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_DEVICE_CONFIG, - &hal_dev_cfg.eDeviceConfig); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure device.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->dev_cfg.freq = io_mode; - data->dev_cfg.data_rate = data_rate; - data->dev_cfg.ce_num = ce_num; - - if (cfg->apmemory_supp || cfg->hyperbus_supp) { - hal_rx_cfg.ui8Sfturn = data_rate ? 2 : 1; - hal_rx_cfg.ui8Sfturn |= 0x8; - hal_rx_cfg.bHyperIO = cfg->hyperbus_supp & - (io_mode == MSPI_IO_MODE_HEX_8_8_16); - } else if (io_mode == MSPI_IO_MODE_HEX_8_8_16) { - LOG_INST_ERR(cfg->log, "%u, io_mode not supported.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - - am_hal_mspi_request_e eRequest; - - hal_dev_cfg.bEmulateDDR = data_rate ? true : false; - if (hal_dev_cfg.bEmulateDDR) { - hal_rx_cfg.bTaForth = true; - if (!data->hal_dev_cfg.bEmulateDDR) { - hal_dev_cfg.ui8TurnAround *= 2; - hal_dev_cfg.ui8WriteLatency *= 2; - } - eRequest = AM_HAL_MSPI_REQ_DDR_EN; - } else { - hal_rx_cfg.bTaForth = false; - if (data->hal_dev_cfg.bEmulateDDR) { - hal_dev_cfg.ui8TurnAround /= 2; - hal_dev_cfg.ui8WriteLatency /= 2; - } - eRequest = AM_HAL_MSPI_REQ_DDR_DIS; - } - - ret = am_hal_mspi_control(data->mspiHandle, eRequest, NULL); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to enable DDR.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_RXCFG, - &hal_rx_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure RXCFG.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_SET_DATA_LATENCY, - &hal_dev_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to set data latency.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->hal_timing.ui8Turnaround = hal_dev_cfg.ui8TurnAround; - - } - - if (param_mask & MSPI_DEVICE_CONFIG_CMD_LEN) { - uint8_t cmd_length = dev_cfg->cmd_length; - - if (data->dev_cfg.data_rate == MSPI_DATA_RATE_S_D_D) { - cmd_length *= 2; - } - if (cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1 || - cmd_length == 0) { - LOG_INST_ERR(cfg->log, "%u, invalid cmd_length.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - hal_dev_cfg.eInstrCfg = cmd_length - 1; - } - - if (param_mask & MSPI_DEVICE_CONFIG_ADDR_LEN) { - if (dev_cfg->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1 || - dev_cfg->addr_length == 0) { - LOG_INST_ERR(cfg->log, "%u, invalid addr_length.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - hal_dev_cfg.eAddrCfg = dev_cfg->addr_length - 1; - } - - if ((param_mask & MSPI_DEVICE_CONFIG_CMD_LEN) || - (param_mask & MSPI_DEVICE_CONFIG_ADDR_LEN)) { - am_hal_mspi_instr_addr_t ia_cfg; - - ia_cfg.eAddrCfg = hal_dev_cfg.eAddrCfg; - ia_cfg.eInstrCfg = hal_dev_cfg.eInstrCfg; - - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_SET_INSTR_ADDR_LEN, &ia_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure device.", - __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->dev_cfg.cmd_length = ia_cfg.eInstrCfg + 1; - data->dev_cfg.addr_length = ia_cfg.eAddrCfg + 1; - } - - if (param_mask & MSPI_DEVICE_CONFIG_DQS) { - am_hal_mspi_dqs_t dqs_cfg = data->hal_dqs_cfg; - - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_TIMING_SCAN_GET, - &data->hal_timing); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to get timing.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - - dqs_cfg.bDQSEnable = dev_cfg->dqs_enable; - dqs_cfg.ui8RxDQSDelay = data->hal_timing.ui8RxDQSDelay; - dqs_cfg.ui8TxDQSDelay = data->hal_timing.ui8TxDQSDelay; - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_DQS, &dqs_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure DQS.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->hal_dqs_cfg.bDQSEnable = dev_cfg->dqs_enable; - } - - } else { - - if (data->dev_id != dev_id) { - ret = pinctrl_apply_state(cfg->pcfg, - PINCTRL_STATE_PRIV_START + dev_id->dev_idx); - if (ret) { - goto e_return; - } - } - - if (memcmp(&data->dev_cfg, dev_cfg, sizeof(struct mspi_dev_cfg)) == 0) { - /** Nothing to config */ - data->dev_id = (struct mspi_dev_id *)dev_id; - return ret; - } - - if (dev_cfg->endian != MSPI_XFER_LITTLE_ENDIAN) { - LOG_INST_ERR(cfg->log, "%u, only support MSB first.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - - hal_dev_cfg.bEmulateDDR = dev_cfg->data_rate ? true : false; - hal_dev_cfg.eSpiMode = dev_cfg->cpp; - hal_dev_cfg.bEnWriteLatency = (dev_cfg->tx_dummy != 0); - hal_dev_cfg.ui8WriteLatency = dev_cfg->tx_dummy; - hal_dev_cfg.bTurnaround = (dev_cfg->rx_dummy != 0); - hal_dev_cfg.ui8TurnAround = dev_cfg->rx_dummy; - - hal_dev_cfg.eClockFreq = mspi_set_freq(dev_cfg->data_rate, dev_cfg->freq); - if (hal_dev_cfg.eClockFreq == AM_HAL_MSPI_CLK_INVALID) { - LOG_INST_ERR(cfg->log, "%u,Frequency not supported!", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - - hal_dev_cfg.eDeviceConfig = mspi_set_line(dev_cfg->io_mode, - dev_cfg->data_rate, - dev_cfg->ce_num); - if (hal_dev_cfg.eDeviceConfig == AM_HAL_MSPI_FLASH_MAX || - (data->hal_cfg.bClkonD4 && - dev_cfg->io_mode > MSPI_IO_MODE_QUAD_1_4_4)) { - ret = -ENOTSUP; - goto e_return; - } - - uint8_t cmd_length = dev_cfg->cmd_length; - - if (dev_cfg->data_rate == MSPI_DATA_RATE_S_D_D) { - cmd_length *= 2; - } - if (cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, cmd_length too large.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - if (cmd_length == 0) { - hal_dev_cfg.bSendInstr = false; - } else { - hal_dev_cfg.bSendInstr = true; - hal_dev_cfg.eInstrCfg = cmd_length - 1; - } - - if (dev_cfg->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, addr_length too large.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - if (dev_cfg->addr_length == 0) { - hal_dev_cfg.bSendAddr = false; - } else { - hal_dev_cfg.bSendAddr = true; - hal_dev_cfg.eAddrCfg = dev_cfg->addr_length - 1; - } - if (dev_cfg->data_rate == MSPI_DATA_RATE_S_D_D) { - hal_dev_cfg.ui16ReadInstr = (uint16_t)(dev_cfg->read_cmd << 8 | - dev_cfg->read_cmd); - hal_dev_cfg.ui16WriteInstr = (uint16_t)(dev_cfg->write_cmd << 8 | - dev_cfg->write_cmd); - } else { - hal_dev_cfg.ui16ReadInstr = (uint16_t)dev_cfg->read_cmd; - hal_dev_cfg.ui16WriteInstr = (uint16_t)dev_cfg->write_cmd; - } - - hal_dev_cfg.eDMABoundary = mspi_set_mem_boundary(dev_cfg->mem_boundary); - if (hal_dev_cfg.eDMABoundary >= AM_HAL_MSPI_BOUNDARY_MAX) { - LOG_INST_ERR(cfg->log, "%u, mem_boundary too large.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - - hal_dev_cfg.ui16DMATimeLimit = mspi_set_time_limit(hal_dev_cfg.eClockFreq, - dev_cfg->time_to_break); - - if (hal_dev_cfg.eClockFreq >= AM_HAL_MSPI_CLK_96MHZ && - hal_dev_cfg.bEmulateDDR) { - hal_rx_cfg.ui8RxSmp = 2; - } else { - hal_rx_cfg.ui8RxSmp = 1; - } - - if (cfg->apmemory_supp || cfg->hyperbus_supp) { - hal_rx_cfg.ui8Sfturn = 10; - hal_rx_cfg.bHyperIO = cfg->hyperbus_supp & - (dev_cfg->io_mode == - MSPI_IO_MODE_HEX_8_8_16); - } else if (dev_cfg->io_mode == MSPI_IO_MODE_HEX_8_8_16) { - LOG_INST_ERR(cfg->log, "%u, io_mode not supported.", __LINE__); - ret = -ENOTSUP; - goto e_return; - } - - if (hal_dev_cfg.bEmulateDDR) { - hal_rx_cfg.bTaForth = true; - hal_dev_cfg.ui8TurnAround *= 2; - hal_dev_cfg.ui8WriteLatency *= 2; - } else { - hal_rx_cfg.bTaForth = false; - } - - ret = am_hal_mspi_disable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to disable MSPI, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_return; - } - - ret = am_hal_mspi_device_configure(data->mspiHandle, &hal_dev_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure MSPI, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_return; - } - /* Sync TxNeg RxNeg RxCap */ - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_TIMING_SCAN_GET, - &data->hal_timing); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to get timing.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - - if (dev_cfg->dqs_enable != data->hal_dqs_cfg.bDQSEnable) { - am_hal_mspi_dqs_t dqs_cfg = data->hal_dqs_cfg; - - dqs_cfg.bDQSEnable = dev_cfg->dqs_enable; - dqs_cfg.ui8RxDQSDelay = data->hal_timing.ui8RxDQSDelay; - dqs_cfg.ui8TxDQSDelay = data->hal_timing.ui8TxDQSDelay; - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_DQS, &dqs_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure DQS.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - data->hal_dqs_cfg.bDQSEnable = dev_cfg->dqs_enable; - } - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_RXCFG, &hal_rx_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure RXCFG.", __LINE__); - ret = -EHOSTDOWN; - goto e_return; - } - - ret = am_hal_mspi_enable(data->mspiHandle); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to enable MSPI, code:%d.", - __LINE__, ret); - ret = -EHOSTDOWN; - goto e_return; - } - data->dev_cfg = *dev_cfg; - data->dev_id = (struct mspi_dev_id *)dev_id; - } - data->hal_dev_cfg = hal_dev_cfg; - data->hal_rx_cfg = hal_rx_cfg; - - return ret; - -e_return: - if (pm_device_runtime_put(controller)) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_put.", __LINE__); - } - k_mutex_unlock(&data->lock); - return ret; -} - -static int mspi_ambiq_xip_config(const struct device *controller, - const struct mspi_dev_id *dev_id, - const struct mspi_xip_cfg *xip_cfg) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - am_hal_mspi_request_e eRequest; - am_hal_mspi_xip_config_t hal_xip_cfg = data->hal_xip_cfg; - int ret = 0; - - if (dev_id != data->dev_id) { - LOG_INST_ERR(cfg->log, "%u, dev_id don't match.", __LINE__); - return -ESTALE; - } - - if (xip_cfg->enable) { - eRequest = AM_HAL_MSPI_REQ_XIP_EN; - ret = mspi_get_mem_apsize(cfg, xip_cfg->size); - if (ret == -ENOTSUP) { - LOG_INST_ERR(cfg->log, "%u, incorrect XIP size.", __LINE__); - return ret; - } - hal_xip_cfg.eAPSize = (am_hal_mspi_ap_size_e)ret; - hal_xip_cfg.eAPMode = xip_cfg->permission; - } else { - eRequest = AM_HAL_MSPI_REQ_XIP_DIS; - } - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_XIP_CONFIG, &hal_xip_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure XIP REQ config, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - data->hal_xip_cfg = hal_xip_cfg; - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_XIP_MISC_CONFIG, - &data->hal_xip_misc_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure XIP MISC config, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_control(data->mspiHandle, eRequest, NULL); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to set XIP enable:%d.", - __LINE__, xip_cfg->enable); - return -EHOSTDOWN; - } - - data->xip_cfg = *xip_cfg; - return ret; -} - -static int mspi_ambiq_scramble_config(const struct device *controller, - const struct mspi_dev_id *dev_id, - const struct mspi_scramble_cfg *scramble_cfg) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - am_hal_mspi_xip_config_t hal_xip_cfg = data->hal_xip_cfg; - am_hal_mspi_request_e eRequest; - int ret = 0; - - if (mspi_is_inp(controller)) { - return -EBUSY; - } - - if (dev_id != data->dev_id) { - LOG_INST_ERR(cfg->log, "%u, dev_id don't match.", __LINE__); - return -ESTALE; - } - - if (scramble_cfg->enable) { - eRequest = AM_HAL_MSPI_REQ_SCRAMB_EN; - hal_xip_cfg.scramblingStartAddr = 0 + scramble_cfg->address_offset; - hal_xip_cfg.scramblingEndAddr = hal_xip_cfg.scramblingStartAddr + - scramble_cfg->size; - } else { - eRequest = AM_HAL_MSPI_REQ_SCRAMB_DIS; - } - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_SCRAMBLE_CONFIG, &hal_xip_cfg); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure scramble, code:%d.", - __LINE__, ret); - return -EHOSTDOWN; - } - - ret = am_hal_mspi_control(data->mspiHandle, eRequest, NULL); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to set scramble enable:%d.", - __LINE__, scramble_cfg->enable); - return -EHOSTDOWN; - } - - data->scramble_cfg = *scramble_cfg; - data->hal_xip_cfg = hal_xip_cfg; - return ret; -} - -static int mspi_ambiq_timing_config(const struct device *controller, - const struct mspi_dev_id *dev_id, - const uint32_t param_mask, - void *timing_cfg) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - am_hal_mspi_dev_config_t hal_dev_cfg = data->hal_dev_cfg; - struct mspi_ambiq_timing_cfg *time_cfg = timing_cfg; - am_hal_mspi_timing_scan_t hal_timing = data->hal_timing; - int ret = 0; - - if (mspi_is_inp(controller)) { - return -EBUSY; - } - - if (dev_id != data->dev_id) { - LOG_INST_ERR(cfg->log, "%u, dev_id don't match.", __LINE__); - return -ESTALE; - } - - if ((param_mask & (~(MSPI_AMBIQ_SET_RLC | - MSPI_AMBIQ_SET_TXDQSDLY | - MSPI_AMBIQ_SET_RXDQSDLY)))) { - LOG_INST_ERR(cfg->log, "%u, config type not supported.", __LINE__); - return -EINVAL; - } - - if (param_mask & MSPI_AMBIQ_SET_RLC) { - if (time_cfg->ui8TurnAround) { - hal_dev_cfg.bTurnaround = true; - } else { - hal_dev_cfg.bTurnaround = false; - } - hal_dev_cfg.ui8TurnAround = data->dev_cfg.data_rate ? - 2 * time_cfg->ui8TurnAround : - time_cfg->ui8TurnAround; - - hal_timing.ui8Turnaround = hal_dev_cfg.ui8TurnAround; - } - - if (param_mask & MSPI_AMBIQ_SET_TXDQSDLY) { - hal_timing.ui8TxDQSDelay = time_cfg->ui32TxDQSDelay; - } - - if (param_mask & MSPI_AMBIQ_SET_RXDQSDLY) { - hal_timing.ui8RxDQSDelay = time_cfg->ui32RxDQSDelay; - } - - ret = am_hal_mspi_control(data->mspiHandle, - AM_HAL_MSPI_REQ_TIMING_SCAN_SET, &hal_timing); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, fail to configure timing.", __LINE__); - return -EHOSTDOWN; - } - - data->hal_dev_cfg = hal_dev_cfg; - data->hal_timing = hal_timing; - return ret; -} - -static int mspi_ambiq_get_channel_status(const struct device *controller, uint8_t ch) -{ - ARG_UNUSED(ch); - - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - int ret = 0; - - if (sys_read32(cfg->reg_base) & MSPI_BUSY) { - ret = -EBUSY; - } - - if (mspi_is_inp(controller)) { - return -EBUSY; - } - - data->dev_id = NULL; - if (pm_device_runtime_put(controller)) { - LOG_INST_ERR(cfg->log, "%u, failed pm_device_runtime_put.", __LINE__); - } - k_mutex_unlock(&data->lock); - - return ret; -} - -static void mspi_ambiq_isr(const struct device *dev) -{ - struct mspi_ambiq_data *data = dev->data; - uint32_t ui32Status; - - am_hal_mspi_interrupt_status_get(data->mspiHandle, &ui32Status, false); - am_hal_mspi_interrupt_clear(data->mspiHandle, ui32Status); - am_hal_mspi_interrupt_service(data->mspiHandle, ui32Status); -} - -/** Manage sync dma transceive */ -static void hal_mspi_callback(void *pCallbackCtxt, uint32_t status) -{ - const struct device *controller = pCallbackCtxt; - struct mspi_ambiq_data *data = controller->data; - - data->ctx.packets_done++; -} - -static int mspi_pio_prepare(const struct device *controller, - am_hal_mspi_pio_transfer_t *trans) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - const struct mspi_xfer *xfer = &data->ctx.xfer; - am_hal_mspi_instr_e eInstrCfg = data->hal_dev_cfg.eInstrCfg; - am_hal_mspi_addr_e eAddrCfg = data->hal_dev_cfg.eAddrCfg; - uint8_t cmd_length = xfer->cmd_length; - int ret = 0; - - trans->bScrambling = false; - trans->bSendAddr = (xfer->addr_length != 0); - trans->bSendInstr = (cmd_length != 0); - trans->bTurnaround = (xfer->rx_dummy != 0); - trans->bEnWRLatency = (xfer->tx_dummy != 0); - trans->bDCX = false; - trans->bContinue = false; - - if (data->dev_cfg.data_rate == MSPI_DATA_RATE_S_D_D) { - cmd_length *= 2; - } - if (cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, invalid cmd_length.", __LINE__); - return -ENOTSUP; - } - - if (cmd_length != 0) { - eInstrCfg = cmd_length - 1; - } - - if (xfer->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1) { - LOG_INST_ERR(cfg->log, "%u, invalid addr_length.", __LINE__); - return -ENOTSUP; - } - - if (xfer->addr_length != 0) { - eAddrCfg = xfer->addr_length - 1; - } - - data->dev_cfg.addr_length = xfer->addr_length; - - if ((eInstrCfg != data->hal_dev_cfg.eInstrCfg) || - (eAddrCfg != data->hal_dev_cfg.eAddrCfg)) { - am_hal_mspi_instr_addr_t pConfig; - - pConfig.eAddrCfg = eAddrCfg; - pConfig.eInstrCfg = eInstrCfg; - - ret = am_hal_mspi_control(data->mspiHandle, AM_HAL_MSPI_REQ_SET_INSTR_ADDR_LEN, - &pConfig); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to configure device.", __LINE__); - ret = -EHOSTDOWN; - } - - data->dev_cfg.cmd_length = eInstrCfg + 1; - data->dev_cfg.addr_length = eAddrCfg + 1; - data->hal_dev_cfg.eInstrCfg = eInstrCfg; - data->hal_dev_cfg.eAddrCfg = eAddrCfg; - } - - return ret; -} - -static int mspi_pio_transceive(const struct device *controller, - const struct mspi_xfer *xfer, - mspi_callback_handler_t cb, - struct mspi_callback_context *cb_ctx) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - struct mspi_context *ctx = &data->ctx; - const struct mspi_xfer_packet *packet; - uint32_t packet_idx; - am_hal_mspi_pio_transfer_t trans; - int ret = 0; - int cfg_flag = 0; - - if (xfer->num_packet == 0 || - !xfer->packets || - xfer->timeout > CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE) { - return -EFAULT; - } - - cfg_flag = mspi_context_lock(ctx, data->dev_id, xfer, cb, cb_ctx, true); - /** For async, user must make sure when cfg_flag = 0 the dummy and instr addr length - * in mspi_xfer of the two calls are the same if the first one has not finished yet. - */ - if (cfg_flag) { - if (cfg_flag == 1) { - ret = mspi_pio_prepare(controller, &trans); - if (ret) { - goto pio_err; - } - } else { - ret = cfg_flag; - goto pio_err; - } - } - - if (!ctx->xfer.async) { - - while (ctx->packets_left > 0) { - packet_idx = ctx->xfer.num_packet - ctx->packets_left; - packet = &ctx->xfer.packets[packet_idx]; - trans.eDirection = packet->dir; - trans.ui32DeviceAddr = packet->address; - trans.ui32NumBytes = packet->num_bytes; - trans.pui32Buffer = (uint32_t *)packet->data_buf; - - if (data->dev_cfg.data_rate == MSPI_DATA_RATE_S_D_D) { - trans.ui16DeviceInstr = (uint16_t)(packet->cmd << 8 | - packet->cmd); - } else { - trans.ui16DeviceInstr = (uint16_t)packet->cmd; - } - - ret = am_hal_mspi_blocking_transfer(data->mspiHandle, &trans, - MSPI_TIMEOUT_US); - ctx->packets_left--; - if (ret) { - ret = -EIO; - goto pio_err; - } - } - - } else { - - ret = am_hal_mspi_interrupt_enable(data->mspiHandle, AM_HAL_MSPI_INT_DMACMP); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to enable interrupt.", __LINE__); - ret = -EHOSTDOWN; - goto pio_err; - } - - while (ctx->packets_left > 0) { - packet_idx = ctx->xfer.num_packet - ctx->packets_left; - packet = &ctx->xfer.packets[packet_idx]; - trans.eDirection = packet->dir; - trans.ui16DeviceInstr = (uint16_t)packet->cmd; - trans.ui32DeviceAddr = packet->address; - trans.ui32NumBytes = packet->num_bytes; - trans.pui32Buffer = (uint32_t *)packet->data_buf; - - if (ctx->callback && packet->cb_mask == MSPI_BUS_XFER_COMPLETE_CB) { - ctx->callback_ctx->mspi_evt.evt_type = MSPI_BUS_XFER_COMPLETE; - ctx->callback_ctx->mspi_evt.evt_data.controller = controller; - ctx->callback_ctx->mspi_evt.evt_data.dev_id = data->ctx.owner; - ctx->callback_ctx->mspi_evt.evt_data.packet = packet; - ctx->callback_ctx->mspi_evt.evt_data.packet_idx = packet_idx; - ctx->callback_ctx->mspi_evt.evt_data.status = ~0; - } - - am_hal_mspi_callback_t callback = NULL; - - if (packet->cb_mask == MSPI_BUS_XFER_COMPLETE_CB) { - callback = (am_hal_mspi_callback_t)ctx->callback; - } - - ret = am_hal_mspi_nonblocking_transfer(data->mspiHandle, &trans, MSPI_PIO, - callback, - (void *)ctx->callback_ctx); - ctx->packets_left--; - if (ret) { - if (ret == AM_HAL_STATUS_OUT_OF_RANGE) { - ret = -ENOMEM; - } else { - ret = -EIO; - } - goto pio_err; - } - } - } - -pio_err: - mspi_context_release(ctx); - return ret; -} - -static int mspi_dma_transceive(const struct device *controller, - const struct mspi_xfer *xfer, - mspi_callback_handler_t cb, - struct mspi_callback_context *cb_ctx) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - struct mspi_context *ctx = &data->ctx; - am_hal_mspi_dma_transfer_t trans; - int ret = 0; - int cfg_flag = 0; - - if (xfer->num_packet == 0 || - !xfer->packets || - xfer->timeout > CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE) { - return -EFAULT; - } - - cfg_flag = mspi_context_lock(ctx, data->dev_id, xfer, cb, cb_ctx, true); - /** For async, user must make sure when cfg_flag = 0 the dummy and instr addr length - * in mspi_xfer of the two calls are the same if the first one has not finished yet. - */ - if (cfg_flag) { - if (cfg_flag == 1) { - ret = mspi_xfer_config(controller, xfer); - if (ret) { - goto dma_err; - } - } else { - ret = cfg_flag; - goto dma_err; - } - } - - ret = am_hal_mspi_interrupt_enable(data->mspiHandle, AM_HAL_MSPI_INT_DMACMP); - if (ret) { - LOG_INST_ERR(cfg->log, "%u, failed to enable interrupt.", __LINE__); - ret = -EHOSTDOWN; - goto dma_err; - } - - while (ctx->packets_left > 0) { - uint32_t packet_idx = ctx->xfer.num_packet - ctx->packets_left; - const struct mspi_xfer_packet *packet; - - packet = &ctx->xfer.packets[packet_idx]; - trans.ui8Priority = ctx->xfer.priority; - trans.eDirection = packet->dir; - trans.ui32TransferCount = packet->num_bytes; - trans.ui32DeviceAddress = packet->address; - trans.ui32SRAMAddress = (uint32_t)packet->data_buf; - trans.ui32PauseCondition = 0; - trans.ui32StatusSetClr = 0; - - if (ctx->xfer.async) { - - if (ctx->callback && packet->cb_mask == MSPI_BUS_XFER_COMPLETE_CB) { - ctx->callback_ctx->mspi_evt.evt_type = MSPI_BUS_XFER_COMPLETE; - ctx->callback_ctx->mspi_evt.evt_data.controller = controller; - ctx->callback_ctx->mspi_evt.evt_data.dev_id = data->ctx.owner; - ctx->callback_ctx->mspi_evt.evt_data.packet = packet; - ctx->callback_ctx->mspi_evt.evt_data.packet_idx = packet_idx; - ctx->callback_ctx->mspi_evt.evt_data.status = ~0; - } - - am_hal_mspi_callback_t callback = NULL; - - if (packet->cb_mask == MSPI_BUS_XFER_COMPLETE_CB) { - callback = (am_hal_mspi_callback_t)ctx->callback; - } - - ret = am_hal_mspi_nonblocking_transfer(data->mspiHandle, &trans, MSPI_DMA, - callback, - (void *)ctx->callback_ctx); - } else { - ret = am_hal_mspi_nonblocking_transfer(data->mspiHandle, &trans, MSPI_DMA, - hal_mspi_callback, - (void *)controller); - } - ctx->packets_left--; - if (ret) { - if (ret == AM_HAL_STATUS_OUT_OF_RANGE) { - ret = -ENOMEM; - } else { - ret = -EIO; - } - goto dma_err; - } - } - - if (!ctx->xfer.async) { - while (ctx->packets_done < ctx->xfer.num_packet) { - k_busy_wait(10); - } - } - -dma_err: - mspi_context_release(ctx); - return ret; -} - -static int mspi_ambiq_transceive(const struct device *controller, - const struct mspi_dev_id *dev_id, - const struct mspi_xfer *xfer) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - mspi_callback_handler_t cb = NULL; - struct mspi_callback_context *cb_ctx = NULL; - - if (dev_id != data->dev_id) { - LOG_INST_ERR(cfg->log, "%u, dev_id don't match.", __LINE__); - return -ESTALE; - } - - if (xfer->async) { - cb = data->cbs[MSPI_BUS_XFER_COMPLETE]; - cb_ctx = data->cb_ctxs[MSPI_BUS_XFER_COMPLETE]; - } - - if (xfer->xfer_mode == MSPI_PIO) { - return mspi_pio_transceive(controller, xfer, cb, cb_ctx); - } else if (xfer->xfer_mode == MSPI_DMA) { - return mspi_dma_transceive(controller, xfer, cb, cb_ctx); - } else { - return -EIO; - } -} - -static int mspi_ambiq_register_callback(const struct device *controller, - const struct mspi_dev_id *dev_id, - const enum mspi_bus_event evt_type, - mspi_callback_handler_t cb, - struct mspi_callback_context *ctx) -{ - const struct mspi_ambiq_config *cfg = controller->config; - struct mspi_ambiq_data *data = controller->data; - - if (mspi_is_inp(controller)) { - return -EBUSY; - } - - if (dev_id != data->dev_id) { - LOG_INST_ERR(cfg->log, "%u, dev_id don't match.", __LINE__); - return -ESTALE; - } - - if (evt_type != MSPI_BUS_XFER_COMPLETE) { - LOG_INST_ERR(cfg->log, "%u, callback types not supported.", __LINE__); - return -ENOTSUP; - } - - data->cbs[evt_type] = cb; - data->cb_ctxs[evt_type] = ctx; - return 0; -} - -static int mspi_ambiq_init(const struct device *controller) -{ - const struct mspi_ambiq_config *cfg = controller->config; - const struct mspi_dt_spec spec = { - .bus = controller, - .config = cfg->mspicfg, - }; - - return mspi_ambiq_config(&spec); -} - -static DEVICE_API(mspi, mspi_ambiq_driver_api) = { - .config = mspi_ambiq_config, - .dev_config = mspi_ambiq_dev_config, - .xip_config = mspi_ambiq_xip_config, - .scramble_config = mspi_ambiq_scramble_config, - .timing_config = mspi_ambiq_timing_config, - .get_channel_status = mspi_ambiq_get_channel_status, - .register_callback = mspi_ambiq_register_callback, - .transceive = mspi_ambiq_transceive, -}; - -#define MSPI_PINCTRL_STATE_INIT(state_idx, node_id) \ - COND_CODE_1(Z_PINCTRL_SKIP_STATE(state_idx, node_id), (), \ - ({ \ - .id = state_idx, \ - .pins = Z_PINCTRL_STATE_PINS_NAME(state_idx, node_id), \ - .pin_cnt = ARRAY_SIZE(Z_PINCTRL_STATE_PINS_NAME(state_idx, node_id)) \ - })) - -#define MSPI_PINCTRL_STATES_DEFINE(node_id) \ - static const struct pinctrl_state \ - Z_PINCTRL_STATES_NAME(node_id)[] = { \ - LISTIFY(DT_NUM_PINCTRL_STATES(node_id), \ - MSPI_PINCTRL_STATE_INIT, (,), node_id) \ - }; - -#define MSPI_PINCTRL_DT_DEFINE(node_id) \ - LISTIFY(DT_NUM_PINCTRL_STATES(node_id), \ - Z_PINCTRL_STATE_PINS_DEFINE, (;), node_id); \ - MSPI_PINCTRL_STATES_DEFINE(node_id) \ - Z_PINCTRL_DEV_CONFIG_STATIC Z_PINCTRL_DEV_CONFIG_CONST \ - struct pinctrl_dev_config Z_PINCTRL_DEV_CONFIG_NAME(node_id) = \ - Z_PINCTRL_DEV_CONFIG_INIT(node_id) - -#define MSPI_CONFIG(n) \ - { \ - .channel_num = (DT_INST_REG_ADDR(n) - MSPI0_BASE) / \ - (MSPI1_BASE - MSPI0_BASE), \ - .op_mode = MSPI_OP_MODE_CONTROLLER, \ - .duplex = MSPI_HALF_DUPLEX, \ - .max_freq = MSPI_MAX_FREQ, \ - .dqs_support = false, \ - .num_periph = DT_INST_CHILD_NUM(n), \ - .sw_multi_periph = DT_INST_PROP(n, software_multiperipheral), \ - } - -#define MSPI_HAL_CONFIG(n, cmdq, cmdq_size) \ -{ \ - .ui32TCBSize = cmdq_size, \ - .pTCB = cmdq, \ - .bClkonD4 = DT_INST_PROP(n, ambiq_clkond4), \ -} - -#define MSPI_HAL_DEVICE_CONFIG(n) \ - { \ - .ui8WriteLatency = 0, \ - .ui8TurnAround = 0, \ - .eAddrCfg = 0, \ - .eInstrCfg = 0, \ - .ui16ReadInstr = 0, \ - .ui16WriteInstr = 0, \ - .eDeviceConfig = AM_HAL_MSPI_FLASH_SERIAL_CE0, \ - .eSpiMode = AM_HAL_MSPI_SPI_MODE_0, \ - .eClockFreq = MSPI_MAX_FREQ / DT_INST_PROP_OR(n, \ - clock_frequency, \ - MSPI_MAX_FREQ), \ - .bEnWriteLatency = false, \ - .bSendAddr = false, \ - .bSendInstr = false, \ - .bTurnaround = false, \ - .bEmulateDDR = false, \ - .eCeLatency = AM_HAL_MSPI_CE_LATENCY_NORMAL, \ - .ui16DMATimeLimit = 0, \ - .eDMABoundary = AM_HAL_MSPI_BOUNDARY_NONE, \ - } - -#define MSPI_HAL_XIP_CONFIG(n) \ - { \ - .scramblingStartAddr = 0, \ - .scramblingEndAddr = 0, \ - .ui32APBaseAddr = DT_INST_REG_ADDR_BY_IDX(n, 1), \ - .eAPMode = AM_HAL_MSPI_AP_READ_WRITE, \ - .eAPSize = AM_HAL_MSPI_AP_SIZE64K, \ - } - -#define MSPI_HAL_XIP_MISC_CONFIG(n) \ - { \ - .ui32CEBreak = 10, \ - .bXIPBoundary = true, \ - .bXIPOdd = true, \ - .bAppndOdd = false, \ - .bBEOn = false, \ - .eBEPolarity = AM_HAL_MSPI_BE_LOW_ENABLE, \ - } - -#define MSPI_HAL_RX_CFG(n) \ - { \ - .ui8DQSturn = 2, \ - .bRxHI = 0, \ - .bTaForth = 0, \ - .bHyperIO = 0, \ - .ui8RxSmp = 1, \ - .bRBX = DT_INST_PROP(n, ambiq_rbx), \ - .bWBX = DT_INST_PROP(n, ambiq_wbx), \ - .bSCLKRxHalt = 0, \ - .bRxCapEXT = 0, \ - .ui8Sfturn = 0, \ - } - -#define MSPI_HAL_DQS_CFG(n) \ - { \ - .bDQSEnable = 0, \ - .bDQSSyncNeg = 0, \ - .bEnableFineDelay = 0, \ - .ui8TxDQSDelay = 0, \ - .ui8RxDQSDelay = 16, \ - .ui8RxDQSDelayNeg = 0, \ - .bRxDQSDelayNegEN = 0, \ - .ui8RxDQSDelayHi = 0, \ - .ui8RxDQSDelayNegHi = 0, \ - .bRxDQSDelayHiEN = 0, \ - } - -#define AMBIQ_MSPI_DEFINE(n) \ - LOG_INSTANCE_REGISTER(DT_DRV_INST(n), mspi##n, CONFIG_MSPI_LOG_LEVEL); \ - MSPI_PINCTRL_DT_DEFINE(DT_DRV_INST(n)); \ - static void mspi_ambiq_irq_cfg_func_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ - mspi_ambiq_isr, DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - } \ - static uint32_t mspi_ambiq_cmdq##n[DT_INST_PROP_OR(n, cmdq_buffer_size, 1024)] \ - __attribute__((section(DT_INST_PROP_OR(n, cmdq_buffer_location, ".nocache")))); \ - static struct gpio_dt_spec ce_gpios##n[] = MSPI_CE_GPIOS_DT_SPEC_INST_GET(n); \ - static struct mspi_ambiq_data mspi_ambiq_data##n = { \ - .mspiHandle = NULL, \ - .hal_cfg = MSPI_HAL_CONFIG(n, mspi_ambiq_cmdq##n, \ - DT_INST_PROP_OR(n, cmdq_buffer_size, 1024)), \ - .hal_dev_cfg = MSPI_HAL_DEVICE_CONFIG(n), \ - .hal_xip_cfg = MSPI_HAL_XIP_CONFIG(n), \ - .hal_xip_misc_cfg = MSPI_HAL_XIP_MISC_CONFIG(n), \ - .hal_rx_cfg = MSPI_HAL_RX_CFG(n), \ - .hal_dqs_cfg = MSPI_HAL_DQS_CFG(n), \ - .dev_id = 0, \ - .lock = Z_MUTEX_INITIALIZER(mspi_ambiq_data##n.lock), \ - .dev_cfg = {0}, \ - .xip_cfg = {0}, \ - .scramble_cfg = {0}, \ - .cbs = {0}, \ - .cb_ctxs = {0}, \ - .ctx.lock = Z_SEM_INITIALIZER(mspi_ambiq_data##n.ctx.lock, 0, 1), \ - .ctx.callback = 0, \ - .ctx.callback_ctx = 0, \ - }; \ - static const struct mspi_ambiq_config mspi_ambiq_config##n = { \ - .reg_base = DT_INST_REG_ADDR(n), \ - .reg_size = DT_INST_REG_SIZE(n), \ - .xip_base = DT_INST_REG_ADDR_BY_IDX(n, 1), \ - .xip_size = DT_INST_REG_SIZE_BY_IDX(n, 1), \ - .apmemory_supp = DT_INST_PROP(n, ambiq_apmemory), \ - .hyperbus_supp = DT_INST_PROP(n, ambiq_hyperbus), \ - .mspicfg = MSPI_CONFIG(n), \ - .mspicfg.ce_group = (struct gpio_dt_spec *)ce_gpios##n, \ - .mspicfg.num_ce_gpios = ARRAY_SIZE(ce_gpios##n), \ - .mspicfg.re_init = false, \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .irq_cfg_func = mspi_ambiq_irq_cfg_func_##n, \ - .pm_dev_runtime_auto = DT_INST_PROP(n, zephyr_pm_device_runtime_auto), \ - LOG_INSTANCE_PTR_INIT(log, DT_DRV_INST(n), mspi##n) \ - }; \ - PM_DEVICE_DT_INST_DEFINE(n, mspi_ambiq_pm_action); \ - DEVICE_DT_INST_DEFINE(n, \ - mspi_ambiq_init, \ - PM_DEVICE_DT_INST_GET(n), \ - &mspi_ambiq_data##n, \ - &mspi_ambiq_config##n, \ - POST_KERNEL, \ - CONFIG_MSPI_INIT_PRIORITY, \ - &mspi_ambiq_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(AMBIQ_MSPI_DEFINE) diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 465cd1e1f88b0..7a47ab577d8c7 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -72,15 +72,6 @@ static void loopback_init(struct net_if *iface) LOG_ERR("Failed to register IPv6 loopback address"); } } - - if (IS_ENABLED(CONFIG_NET_INTERFACE_NAME)) { - int ret; - - ret = net_if_set_name(iface, "lo"); - if (ret < 0) { - LOG_ERR("Failed to set loopback interface name (%d)", ret); - } - } } #ifdef CONFIG_NET_LOOPBACK_SIMULATE_PACKET_DROP diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 5efe0bd6abca6..60e1741f2b7c7 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -16,7 +16,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NPCX pinctrl_npcx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMICRO pinctrl_numicro.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_MSPM0 pinctrl_mspm0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c) @@ -53,6 +52,5 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a47c4392a78ad..9cdbfd4244479 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -45,7 +45,6 @@ source "drivers/pinctrl/Kconfig.it8xxx2" source "drivers/pinctrl/Kconfig.npcx" source "drivers/pinctrl/Kconfig.numicro" source "drivers/pinctrl/Kconfig.nrf" -source "drivers/pinctrl/Kconfig.mspm0" source "drivers/pinctrl/Kconfig.rpi_pico" source "drivers/pinctrl/Kconfig.sam" source "drivers/pinctrl/Kconfig.sam0" @@ -80,7 +79,6 @@ source "drivers/pinctrl/Kconfig.wch_afio" source "drivers/pinctrl/Kconfig.sy1xx" source "drivers/pinctrl/Kconfig.realtek_rts5912" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" -source "drivers/pinctrl/Kconfig.wch_00x_afio" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.mspm0 b/drivers/pinctrl/Kconfig.mspm0 deleted file mode 100644 index 1bd21a1c60625..0000000000000 --- a/drivers/pinctrl/Kconfig.mspm0 +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2025 Texas Instruments - -config PINCTRL_MSPM0 - bool "TI pinctrl MSPM0 driver" - default y - depends on DT_HAS_TI_MSPM0_PINCTRL_ENABLED - help - Enable support for the PINCTRL on TI MSPM0 series. diff --git a/drivers/pinctrl/Kconfig.npcx b/drivers/pinctrl/Kconfig.npcx index 0e8106e411151..d6ea4e715335c 100644 --- a/drivers/pinctrl/Kconfig.npcx +++ b/drivers/pinctrl/Kconfig.npcx @@ -3,6 +3,7 @@ # Copyright (c) 2022 Nuvoton Technology Corporation. # SPDX-License-Identifier: Apache-2.0 + config PINCTRL_NPCX bool "Nuvoton NPCX embedded controller (EC) pin controller driver" default y @@ -10,9 +11,3 @@ config PINCTRL_NPCX help This option enables the pin controller driver for NPCX family of processors. - -config PINCTRL_NPCX_EX - bool "Extended NPCX driver support" - default y if DT_HAS_NUVOTON_NPCX_PINCTRL_NPCKN_ENABLED - help - This option enables the extended driver for NPCKN variant of processors. diff --git a/drivers/pinctrl/Kconfig.wch_00x_afio b/drivers/pinctrl/Kconfig.wch_00x_afio deleted file mode 100644 index c581abc7dcd57..0000000000000 --- a/drivers/pinctrl/Kconfig.wch_00x_afio +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2025 Michael Hope -# SPDX-License-Identifier: Apache-2.0 - -config PINCTRL_WCH_00X_AFIO - bool "WCH AFIO pin controller driver for CH32V00x" - default y - depends on DT_HAS_WCH_00X_AFIO_ENABLED - help - WCH CH32V00x AFIO pin controller driver, excluding the CH32V003. diff --git a/drivers/pinctrl/pinctrl_gd32_afio.c b/drivers/pinctrl/pinctrl_gd32_afio.c index 3698bcdeb073d..fe0cf67e09f31 100644 --- a/drivers/pinctrl/pinctrl_gd32_afio.c +++ b/drivers/pinctrl/pinctrl_gd32_afio.c @@ -74,8 +74,8 @@ static int afio_init(void) #ifdef AFIO_CPSCTL if (DT_PROP(AFIO_NODE, enable_cps)) { gpio_compensation_config(GPIO_COMPENSATION_ENABLE); - while (gpio_compensation_flag_get() == RESET) { - } + while (gpio_compensation_flag_get() == RESET) + ; } #endif /* AFIO_CPSCTL */ diff --git a/drivers/pinctrl/pinctrl_mspm0.c b/drivers/pinctrl/pinctrl_mspm0.c deleted file mode 100644 index fc8055c196e4b..0000000000000 --- a/drivers/pinctrl/pinctrl_mspm0.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2025 Texas Instruments - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#define DT_DRV_COMPAT ti_mspm0_pinctrl - -#define MSPM0_PINCM(pinmux) (pinmux >> 0x10) -#define MSPM0_PIN_FUNCTION(pinmux) (pinmux & 0x3F) - -int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, - uint8_t pin_cnt, - uintptr_t reg) -{ - ARG_UNUSED(reg); - - uint8_t pin_function; - uint32_t pin_cm; - uint32_t iomux; - - for (int i = 0; i < pin_cnt; i++) { - pin_cm = MSPM0_PINCM(pins[i].pinmux); - pin_function = MSPM0_PIN_FUNCTION(pins[i].pinmux); - iomux = pins[i].iomux; - if (pin_function == 0x00) { - DL_GPIO_initPeripheralAnalogFunction(pin_cm); - } else { - DL_GPIO_initPeripheralFunction(pin_cm, - (iomux | pin_function)); - } - } - - return 0; -} diff --git a/drivers/pinctrl/pinctrl_npcx.c b/drivers/pinctrl/pinctrl_npcx.c index 158dc87c9a447..373a7158cfc8a 100644 --- a/drivers/pinctrl/pinctrl_npcx.c +++ b/drivers/pinctrl/pinctrl_npcx.c @@ -139,24 +139,11 @@ static void npcx_psl_input_detection_configure(const pinctrl_soc_pin_t *pin) } /* Configure detection mode of PSL input pads */ -#if defined(CONFIG_PINCTRL_NPCX_EX) - if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) { - inst_glue->PSL_CTS3 |= BIT(psl_in->port); - } else { - inst_glue->PSL_CTS3 &= ~BIT(psl_in->port); - } - - /* Clear event bits */ - inst_glue->PSL_CTS |= BIT(psl_in->port); - inst_glue->PSL_IN_POS |= BIT(psl_in->port); - inst_glue->PSL_IN_NEG |= BIT(psl_in->port); -#else if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) { inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(psl_in->port); } else { inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(psl_in->port); } -#endif /* CONFIG_PINCTRL_NPCX_EX */ } static void npcx_device_control_configure(const pinctrl_soc_pin_t *pin) diff --git a/drivers/pinctrl/pinctrl_rpi_pico.c b/drivers/pinctrl/pinctrl_rpi_pico.c index b15ccdecf3035..037213ea52d76 100644 --- a/drivers/pinctrl/pinctrl_rpi_pico.c +++ b/drivers/pinctrl/pinctrl_rpi_pico.c @@ -20,9 +20,6 @@ static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) gpio_set_input_hysteresis_enabled(pin->pin_num, pin->schmitt_enable); gpio_set_input_enabled(pin->pin_num, pin->input_enable); gpio_set_oeover(pin->pin_num, pin->oe_override); - gpio_set_outover(pin->pin_num, pin->out_override); - gpio_set_inover(pin->pin_num, pin->in_override); - gpio_set_irqover(pin->pin_num, pin->irq_override); } int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, diff --git a/drivers/pinctrl/pinctrl_wch_00x_afio.c b/drivers/pinctrl/pinctrl_wch_00x_afio.c deleted file mode 100644 index 76fb682e4ca48..0000000000000 --- a/drivers/pinctrl/pinctrl_wch_00x_afio.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2025 Michael Hope - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT wch_00x_afio - -#include -#include -#include - -#include - -static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = { - (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)), - (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiob)), - (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)), - (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)), -}; - -int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) -{ - int i; - - for (i = 0; i < pin_cnt; i++, pins++) { - uint8_t port = FIELD_GET(CH32V00X_PINCTRL_PORT_MASK, pins->config); - uint8_t pin = FIELD_GET(CH32V00X_PINCTRL_PIN_MASK, pins->config); - uint8_t bit0 = FIELD_GET(CH32V00X_PINCTRL_BASE_MASK, pins->config); - uint8_t remap = FIELD_GET(CH32V00X_PINCTRL_RM_MASK, pins->config); - GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; - uint8_t cfg = 0; - - if (pins->output_high || pins->output_low) { - cfg |= BIT(0); - if (pins->drive_open_drain) { - cfg |= BIT(2); - } - /* Select the alternate function */ - cfg |= BIT(3); - } else { - if (pins->bias_pull_up || pins->bias_pull_down) { - cfg |= BIT(3); - } - } - regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4)); - - if (pins->output_high) { - regs->OUTDR |= BIT(pin); - regs->BSHR |= BIT(pin); - } else if (pins->output_low) { - regs->OUTDR |= BIT(pin); - /* Reset the pin. */ - regs->BSHR |= BIT(pin + 16); - } else { - regs->OUTDR &= ~(1 << pin); - if (pins->bias_pull_up) { - regs->BSHR = BIT(pin); - } - if (pins->bias_pull_down) { - regs->BCR = BIT(pin); - } - } - - AFIO->PCFR1 |= remap << bit0; - } - - return 0; -} - -static int pinctrl_clock_init(void) -{ - const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); - uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); - - return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); -} - -SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c index b72d9aaf0108b..ae22af8b648d3 100644 --- a/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c +++ b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c @@ -4,9 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT wch_20x_30x_afio - -#include #include #include @@ -33,6 +30,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp uint8_t pcfr_id = FIELD_GET(CH32V20X_V30X_PINCTRL_PCFR_ID_MASK, pins->config); uint8_t remap = FIELD_GET(CH32V20X_V30X_PINCTRL_RM_MASK, pins->config); GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; + uint32_t pcfr = pcfr_id == 0 ? AFIO->PCFR1 : AFIO->PCFR2; uint8_t cfg = 0; if (pins->output_high || pins->output_low) { @@ -71,33 +69,21 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp } } - if (remap != 0) { - RCC->APB2PCENR |= RCC_AFIOEN; + pcfr |= remap << bit0; - if (pcfr_id == 0 && bit0 == CH32V20X_V30X_PINMUX_USART1_RM) { - AFIO->PCFR1 |= ((uint32_t)((remap >> 0) & 1) - << (CH32V20X_V30X_PINMUX_USART1_RM & 0x1F)); - AFIO->PCFR2 |= ((uint32_t)((remap >> 1) & 1) - << (CH32V20X_V30X_PINMUX_USART1_RM1 & 0x1F)); - } else { - if (pcfr_id == 0) { - AFIO->PCFR1 |= (uint32_t)remap << bit0; - } else { - AFIO->PCFR2 |= (uint32_t)remap << bit0; - } - } + if (pcfr_id == 0) { + AFIO->PCFR1 = pcfr; + } else { + AFIO->PCFR2 = pcfr; + } + + if (bit0 == CH32V20X_V30X_PINMUX_USART1_RM) { + pcfr = AFIO->PCFR2; + pcfr |= ((uint32_t)((remap >> 1) & 1) + << (CH32V20X_V30X_PINMUX_USART1_RM1 & 0x1F)); + AFIO->PCFR2 = pcfr; } } return 0; } - -static int pinctrl_clock_init(void) -{ - const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); - uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); - - return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); -} - -SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/drivers/pinctrl/pinctrl_wch_afio.c b/drivers/pinctrl/pinctrl_wch_afio.c index a89e37a418c25..4a56787d56503 100644 --- a/drivers/pinctrl/pinctrl_wch_afio.c +++ b/drivers/pinctrl/pinctrl_wch_afio.c @@ -4,9 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT wch_afio - -#include #include #include @@ -28,8 +25,13 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp uint8_t bit0 = (pins->config >> CH32V003_PINCTRL_RM_BASE_SHIFT) & 0x1F; uint8_t remap = (pins->config >> CH32V003_PINCTRL_RM_SHIFT) & 0x3; GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; + uint32_t pcfr1 = AFIO->PCFR1; uint8_t cfg = 0; + if (remap != 0) { + RCC->APB2PCENR |= RCC_AFIOEN; + } + if (pins->output_high || pins->output_low) { cfg |= (pins->slew_rate + 1); if (pins->drive_open_drain) { @@ -61,34 +63,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp } } - if (remap != 0) { - RCC->APB2PCENR |= RCC_AFIOEN; - - if (bit0 == CH32V003_PINMUX_I2C1_RM) { - AFIO->PCFR1 |= ((uint32_t)((remap >> 0) & 1) - << CH32V003_PINMUX_I2C1_RM) | - ((uint32_t)((remap >> 1) & 1) - << CH32V003_PINMUX_I2C1_RM1); - } else if (bit0 == CH32V003_PINMUX_USART1_RM) { - AFIO->PCFR1 |= ((uint32_t)((remap >> 0) & 1) - << CH32V003_PINMUX_USART1_RM) | - ((uint32_t)((remap >> 1) & 1) - << CH32V003_PINMUX_USART1_RM1); - } else { - AFIO->PCFR1 |= (uint32_t)remap << bit0; - } + if (bit0 == CH32V003_PINMUX_I2C1_RM) { + pcfr1 |= ((remap & 1) << CH32V003_PINMUX_I2C1_RM) | + (((remap >> 1) & 1) << CH32V003_PINMUX_I2C1_RM1); + } else if (bit0 == CH32V003_PINMUX_USART1_RM) { + pcfr1 |= ((remap & 1) << CH32V003_PINMUX_USART1_RM) | + (((remap >> 1) & 1) << CH32V003_PINMUX_USART1_RM1); + } else { + pcfr1 |= remap << bit0; } + AFIO->PCFR1 = pcfr1; } return 0; } - -static int pinctrl_clock_init(void) -{ - const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); - uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); - - return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); -} - -SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt index 25bb624acc1c3..0382b0be2534e 100644 --- a/drivers/pinctrl/renesas/CMakeLists.txt +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -3,7 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RX rx/pinctrl_renesas_rx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c) diff --git a/drivers/pinctrl/renesas/rx/Kconfig b/drivers/pinctrl/renesas/rx/Kconfig deleted file mode 100644 index 1bd9c4ff16d54..0000000000000 --- a/drivers/pinctrl/renesas/rx/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2024 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config PINCTRL_RENESAS_RX - bool "Renesas RX series pin controller driver" - default y - depends on DT_HAS_RENESAS_RX_PINCTRL_ENABLED - select USE_RX_RDP_MPC - select USE_RX_RDP_GPIO - help - Enable Renesas RX series pin controller driver. diff --git a/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c b/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c deleted file mode 100644 index f6a2fcadec557..0000000000000 --- a/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/* Renesas FIT module for iodefine.h data structures */ -#include "platform.h" -#include "r_gpio_rx_if.h" -#include "r_mpc_rx_if.h" - -#define PORT_POS (8) - -extern const uint8_t g_gpio_open_drain_n_support[]; -extern const uint8_t g_gpio_pull_up_support[]; -extern const uint8_t g_gpio_dscr_support[]; - -static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number, - uint8_t pin_number) -{ - if ((check_array[port_number] & (1 << pin_number)) != 0) { - return true; - } else { - return false; - } -} - -static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value) -{ - gpio_port_pin_t port_pin; - bool pin_check; - int ret = 0; - - port_pin = (pin->port_num << PORT_POS) | pin->pin_num; - pin_check = gpio_pin_function_check(g_gpio_pull_up_support, pin->port_num, pin->pin_num); - - if (pin_check) { - ret = R_GPIO_PinControl(port_pin, (value ? GPIO_CMD_IN_PULL_UP_ENABLE - : GPIO_CMD_IN_PULL_UP_DISABLE)); - } - - return ret; -} - -static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value) -{ - gpio_port_pin_t port_pin; - bool pin_check; - int ret = 0; - - port_pin = (pin->port_num << PORT_POS) | pin->pin_num; - pin_check = gpio_pin_function_check(g_gpio_dscr_support, pin->port_num, pin->pin_num); - - if (pin_check) { - ret = R_GPIO_PinControl(port_pin, - (value ? GPIO_CMD_DSCR_ENABLE : GPIO_CMD_DSCR_DISABLE)); - } - - return ret; -} - -static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value) -{ - gpio_port_pin_t port_pin; - bool pin_check; - int ret = 0; - - port_pin = (pin->port_num << PORT_POS) | pin->pin_num; - pin_check = - gpio_pin_function_check(g_gpio_open_drain_n_support, pin->port_num, pin->pin_num); - - if (pin_check) { - ret = R_GPIO_PinControl( - port_pin, (value ? GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN : GPIO_CMD_OUT_CMOS)); - } - - return ret; -} - -int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) -{ - gpio_port_pin_t port_pin; - mpc_config_t pconfig = { - .pin_function = 0x0, - .irq_enable = false, - .analog_enable = false, - }; - int ret; - - for (uint8_t i = 0U; i < pin_cnt; i++) { - const pinctrl_soc_pin_t *pin = &pins[i]; - - port_pin = (pin->port_num << PORT_POS) | pin->pin_num; - - /* Set PMR register to 0 before setting pin control register */ - ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_GPIO); - if (ret != 0) { - return -EINVAL; - } - - /* Set output high */ - if (pin->cfg.output_high) { - R_GPIO_PinWrite(port_pin, GPIO_LEVEL_HIGH); - } - - /* Set port direction */ - if (pin->cfg.output_enable) { - R_GPIO_PinDirectionSet(port_pin, GPIO_DIRECTION_OUTPUT); - } - - /* Set pull-up */ - ret = pinctrl_configure_pullup(pin, pin->cfg.bias_pull_up); - - if (ret != 0) { - return -EINVAL; - } - - /* Set open-drain */ - ret = pinctrl_configure_opendrain(pin, pin->cfg.drive_open_drain); - - if (ret != 0) { - return -EINVAL; - } - - /* Set drive-strength */ - ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength); - - if (ret != 0) { - return -EINVAL; - } - - /* Set pin function */ - pconfig.analog_enable = pin->cfg.analog_enable; - pconfig.pin_function = pin->cfg.psels; - ret = R_MPC_Write(port_pin, &pconfig); - if (ret != 0) { - return -EINVAL; - } - - /* Set MODE */ - if (pin->cfg.pin_mode) { - ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_PERIPHERAL); - if (ret != 0) { - return -EINVAL; - } - } - } - - return 0; -} diff --git a/drivers/ptp_clock/CMakeLists.txt b/drivers/ptp_clock/CMakeLists.txt index c80575787898c..3dfde253e0901 100644 --- a/drivers/ptp_clock/CMakeLists.txt +++ b/drivers/ptp_clock/CMakeLists.txt @@ -5,5 +5,4 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/ptp_clock.h) zephyr_library() zephyr_library_sources_ifdef(CONFIG_PTP_CLOCK ptp_clock.c) -zephyr_library_sources_ifdef(CONFIG_PTP_CLOCK_SHELL ptp_clock_shell.c) zephyr_library_sources_ifdef(CONFIG_PTP_CLOCK_NXP_ENET ptp_clock_nxp_enet.c) diff --git a/drivers/ptp_clock/Kconfig b/drivers/ptp_clock/Kconfig index 9b87301495f17..f6479b65aab53 100644 --- a/drivers/ptp_clock/Kconfig +++ b/drivers/ptp_clock/Kconfig @@ -16,12 +16,4 @@ config PTP_CLOCK_INIT_PRIORITY help PTP Clock device driver initialization priority -config PTP_CLOCK_SHELL - bool "PTP Clock Shell" - depends on SHELL - help - Enable PTP Clock Shell. - - The PTP clock shell currently supports clock operations. - endif # PTP_CLOCK diff --git a/drivers/ptp_clock/ptp_clock_nxp_enet.c b/drivers/ptp_clock/ptp_clock_nxp_enet.c index f80d25bf8e18b..83129fbd1953c 100644 --- a/drivers/ptp_clock/ptp_clock_nxp_enet.c +++ b/drivers/ptp_clock/ptp_clock_nxp_enet.c @@ -29,7 +29,8 @@ struct ptp_clock_nxp_enet_config { struct ptp_clock_nxp_enet_data { ENET_Type *base; - enet_handle_t *enet_handle; + double clock_ratio; + enet_handle_t enet_handle; struct k_mutex ptp_mutex; }; @@ -42,7 +43,7 @@ static int ptp_clock_nxp_enet_set(const struct device *dev, enet_time.second = tm->second; enet_time.nanosecond = tm->nanosecond; - ENET_Ptp1588SetTimer(data->base, data->enet_handle, &enet_time); + ENET_Ptp1588SetTimer(data->base, &data->enet_handle, &enet_time); return 0; } @@ -53,7 +54,7 @@ static int ptp_clock_nxp_enet_get(const struct device *dev, struct ptp_clock_nxp_enet_data *data = dev->data; enet_ptp_time_t enet_time; - ENET_Ptp1588GetTimer(data->base, data->enet_handle, &enet_time); + ENET_Ptp1588GetTimer(data->base, &data->enet_handle, &enet_time); tm->second = enet_time.second; tm->nanosecond = enet_time.nanosecond; @@ -109,12 +110,17 @@ static int ptp_clock_nxp_enet_rate_adjust(const struct device *dev, return 0; } + ratio *= data->clock_ratio; + /* Limit possible ratio. */ if ((ratio > 1.0 + 1.0/(2 * hw_inc)) || (ratio < 1.0 - 1.0/(2 * hw_inc))) { return -EINVAL; } + /* Save new ratio. */ + data->clock_ratio = ratio; + if (ratio < 1.0) { corr = hw_inc - 1; val = 1.0 / (hw_inc * (1.0 - ratio)); @@ -150,11 +156,6 @@ void nxp_enet_ptp_clock_callback(const struct device *dev, { const struct ptp_clock_nxp_enet_config *config = dev->config; struct ptp_clock_nxp_enet_data *data = dev->data; - struct nxp_enet_ptp_data *ptp_data; - - __ASSERT(cb_data != NULL, "ptp data is NULL"); - - ptp_data = (struct nxp_enet_ptp_data *)cb_data; if (event == NXP_ENET_MODULE_RESET) { enet_ptp_config_t ptp_config; @@ -171,16 +172,17 @@ void nxp_enet_ptp_clock_callback(const struct device *dev, /* only for ERRATA_2579 */ ptp_config.channel = kENET_PtpTimerChannel3; ptp_config.ptp1588ClockSrc_Hz = enet_ref_pll_rate; - - /* Share the mutex with mac driver */ - ptp_data->ptp_mutex = &data->ptp_mutex; - /* Get enet handle from mac driver */ - data->enet_handle = ptp_data->enet; + data->clock_ratio = 1.0; ENET_Ptp1588SetChannelMode(data->base, kENET_PtpTimerChannel3, kENET_PtpChannelPulseHighonCompare, true); - ENET_Ptp1588StartTimer(data->base, ptp_config.ptp1588ClockSrc_Hz); - ENET_EnableInterrupts(data->base, ENET_TS_INTERRUPT); + ENET_Ptp1588Configure(data->base, &data->enet_handle, + &ptp_config); + } + + if (cb_data != NULL) { + /* Share the mutex with mac driver */ + *(uintptr_t *)cb_data = (uintptr_t)&data->ptp_mutex; } } @@ -218,7 +220,7 @@ static void ptp_clock_nxp_enet_isr(const struct device *dev) } } - ENET_TimeStampIRQHandler(data->base, data->enet_handle); + ENET_TimeStampIRQHandler(data->base, &data->enet_handle); irq_unlock(irq_lock_key); } diff --git a/drivers/ptp_clock/ptp_clock_shell.c b/drivers/ptp_clock/ptp_clock_shell.c deleted file mode 100644 index c8bc0735ce756..0000000000000 --- a/drivers/ptp_clock/ptp_clock_shell.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#include -LOG_MODULE_REGISTER(ptp_clock_shell, CONFIG_LOG_DEFAULT_LEVEL); - -static bool device_is_ptp_clock(const struct device *dev) -{ - return DEVICE_API_IS(ptp_clock, dev); -} - -static void device_name_get(size_t idx, struct shell_static_entry *entry) -{ - const struct device *dev = shell_device_filter(idx, device_is_ptp_clock); - - entry->syntax = (dev != NULL) ? dev->name : NULL; - entry->handler = NULL; - entry->help = NULL; - entry->subcmd = NULL; -} - -SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get); - -static int parse_device_arg(const struct shell *sh, char **argv, const struct device **dev) -{ - *dev = shell_device_get_binding(argv[1]); - if (!*dev) { - shell_error(sh, "device %s not found", argv[1]); - return -ENODEV; - } - return 0; -} - -/* ptp_clock get */ -static int cmd_ptp_clock_get(const struct shell *sh, size_t argc, char **argv) -{ - struct net_ptp_time tm = {0}; - const struct device *dev; - int ret; - - ret = parse_device_arg(sh, argv, &dev); - if (ret < 0) { - return ret; - } - - ret = ptp_clock_get(dev, &tm); - if (ret < 0) { - return ret; - } - - shell_print(sh, "%"PRIu64".%09u", tm.second, tm.nanosecond); - - return 0; -} - -/* ptp_clock set */ -static int cmd_ptp_clock_set(const struct shell *sh, size_t argc, char **argv) -{ - struct net_ptp_time tm = {0}; - const struct device *dev; - int ret; - - ret = parse_device_arg(sh, argv, &dev); - if (ret < 0) { - return ret; - } - - tm.second = shell_strtoull(argv[2], 10, &ret); - if (ret < 0) { - return ret; - } - - ret = ptp_clock_set(dev, &tm); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* ptp_clock adj */ -static int cmd_ptp_clock_adj(const struct shell *sh, size_t argc, char **argv) -{ - const struct device *dev; - int adj; - int ret; - - ret = parse_device_arg(sh, argv, &dev); - if (ret < 0) { - return ret; - } - - adj = shell_strtol(argv[2], 10, &ret); - if (ret < 0) { - return ret; - } - - ret = ptp_clock_adjust(dev, adj); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* ptp_clock freq */ -static int cmd_ptp_clock_freq(const struct shell *sh, size_t argc, char **argv) -{ - const struct device *dev; - int ppb; - int ret; - - ret = parse_device_arg(sh, argv, &dev); - if (ret < 0) { - return ret; - } - - ppb = shell_strtol(argv[2], 10, &ret); - if (ret < 0) { - return ret; - } - - ret = ptp_clock_rate_adjust(dev, 1.0 + ((double)ppb / 1000000000.0)); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* ptp_clock selftest